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authorTony Lindgren <tony@atomide.com>2011-02-17 12:48:24 -0500
committerTony Lindgren <tony@atomide.com>2011-02-17 12:48:24 -0500
commitd9e45731debd83e2b249be349993595907dddeae (patch)
treeb6e90906227c1e1146df7a0ea92df0f52c4b53c0
parent9238b6d8e800f01f5cb42cc8e3e7b850ca49e83e (diff)
parent5844c4ead25f53a1fa92a4a8f0e363f9b6b87aea (diff)
Merge branch 'for_2.6.39/omap4_hwmod_data' of git://gitorious.org/omap-pm/linux into omap-for-linus
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c3119
1 files changed, 3072 insertions, 47 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c2806bd11fbf..84e795cf0648 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Hardware modules present on the OMAP44xx chips 2 * Hardware modules present on the OMAP44xx chips
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley 7 * Paul Walmsley
@@ -40,10 +40,15 @@
40#define OMAP44XX_DMA_REQ_START 1 40#define OMAP44XX_DMA_REQ_START 1
41 41
42/* Backward references (IPs with Bus Master capability) */ 42/* Backward references (IPs with Bus Master capability) */
43static struct omap_hwmod omap44xx_aess_hwmod;
43static struct omap_hwmod omap44xx_dma_system_hwmod; 44static struct omap_hwmod omap44xx_dma_system_hwmod;
44static struct omap_hwmod omap44xx_dmm_hwmod; 45static struct omap_hwmod omap44xx_dmm_hwmod;
45static struct omap_hwmod omap44xx_dsp_hwmod; 46static struct omap_hwmod omap44xx_dsp_hwmod;
47static struct omap_hwmod omap44xx_dss_hwmod;
46static struct omap_hwmod omap44xx_emif_fw_hwmod; 48static struct omap_hwmod omap44xx_emif_fw_hwmod;
49static struct omap_hwmod omap44xx_hsi_hwmod;
50static struct omap_hwmod omap44xx_ipu_hwmod;
51static struct omap_hwmod omap44xx_iss_hwmod;
47static struct omap_hwmod omap44xx_iva_hwmod; 52static struct omap_hwmod omap44xx_iva_hwmod;
48static struct omap_hwmod omap44xx_l3_instr_hwmod; 53static struct omap_hwmod omap44xx_l3_instr_hwmod;
49static struct omap_hwmod omap44xx_l3_main_1_hwmod; 54static struct omap_hwmod omap44xx_l3_main_1_hwmod;
@@ -53,8 +58,11 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod;
53static struct omap_hwmod omap44xx_l4_cfg_hwmod; 58static struct omap_hwmod omap44xx_l4_cfg_hwmod;
54static struct omap_hwmod omap44xx_l4_per_hwmod; 59static struct omap_hwmod omap44xx_l4_per_hwmod;
55static struct omap_hwmod omap44xx_l4_wkup_hwmod; 60static struct omap_hwmod omap44xx_l4_wkup_hwmod;
61static struct omap_hwmod omap44xx_mmc1_hwmod;
62static struct omap_hwmod omap44xx_mmc2_hwmod;
56static struct omap_hwmod omap44xx_mpu_hwmod; 63static struct omap_hwmod omap44xx_mpu_hwmod;
57static struct omap_hwmod omap44xx_mpu_private_hwmod; 64static struct omap_hwmod omap44xx_mpu_private_hwmod;
65static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
58 66
59/* 67/*
60 * Interconnects omap_hwmod structures 68 * Interconnects omap_hwmod structures
@@ -213,6 +221,14 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
213 .user = OCP_USER_MPU | OCP_USER_SDMA, 221 .user = OCP_USER_MPU | OCP_USER_SDMA,
214}; 222};
215 223
224/* dss -> l3_main_1 */
225static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
226 .master = &omap44xx_dss_hwmod,
227 .slave = &omap44xx_l3_main_1_hwmod,
228 .clk = "l3_div_ck",
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
230};
231
216/* l3_main_2 -> l3_main_1 */ 232/* l3_main_2 -> l3_main_1 */
217static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { 233static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
218 .master = &omap44xx_l3_main_2_hwmod, 234 .master = &omap44xx_l3_main_2_hwmod,
@@ -229,6 +245,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
229 .user = OCP_USER_MPU | OCP_USER_SDMA, 245 .user = OCP_USER_MPU | OCP_USER_SDMA,
230}; 246};
231 247
248/* mmc1 -> l3_main_1 */
249static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
250 .master = &omap44xx_mmc1_hwmod,
251 .slave = &omap44xx_l3_main_1_hwmod,
252 .clk = "l3_div_ck",
253 .user = OCP_USER_MPU | OCP_USER_SDMA,
254};
255
256/* mmc2 -> l3_main_1 */
257static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
258 .master = &omap44xx_mmc2_hwmod,
259 .slave = &omap44xx_l3_main_1_hwmod,
260 .clk = "l3_div_ck",
261 .user = OCP_USER_MPU | OCP_USER_SDMA,
262};
263
232/* mpu -> l3_main_1 */ 264/* mpu -> l3_main_1 */
233static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { 265static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
234 .master = &omap44xx_mpu_hwmod, 266 .master = &omap44xx_mpu_hwmod,
@@ -240,8 +272,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
240/* l3_main_1 slave ports */ 272/* l3_main_1 slave ports */
241static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { 273static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
242 &omap44xx_dsp__l3_main_1, 274 &omap44xx_dsp__l3_main_1,
275 &omap44xx_dss__l3_main_1,
243 &omap44xx_l3_main_2__l3_main_1, 276 &omap44xx_l3_main_2__l3_main_1,
244 &omap44xx_l4_cfg__l3_main_1, 277 &omap44xx_l4_cfg__l3_main_1,
278 &omap44xx_mmc1__l3_main_1,
279 &omap44xx_mmc2__l3_main_1,
245 &omap44xx_mpu__l3_main_1, 280 &omap44xx_mpu__l3_main_1,
246}; 281};
247 282
@@ -262,6 +297,30 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
262 .user = OCP_USER_MPU | OCP_USER_SDMA, 297 .user = OCP_USER_MPU | OCP_USER_SDMA,
263}; 298};
264 299
300/* hsi -> l3_main_2 */
301static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
302 .master = &omap44xx_hsi_hwmod,
303 .slave = &omap44xx_l3_main_2_hwmod,
304 .clk = "l3_div_ck",
305 .user = OCP_USER_MPU | OCP_USER_SDMA,
306};
307
308/* ipu -> l3_main_2 */
309static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
310 .master = &omap44xx_ipu_hwmod,
311 .slave = &omap44xx_l3_main_2_hwmod,
312 .clk = "l3_div_ck",
313 .user = OCP_USER_MPU | OCP_USER_SDMA,
314};
315
316/* iss -> l3_main_2 */
317static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
318 .master = &omap44xx_iss_hwmod,
319 .slave = &omap44xx_l3_main_2_hwmod,
320 .clk = "l3_div_ck",
321 .user = OCP_USER_MPU | OCP_USER_SDMA,
322};
323
265/* iva -> l3_main_2 */ 324/* iva -> l3_main_2 */
266static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { 325static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
267 .master = &omap44xx_iva_hwmod, 326 .master = &omap44xx_iva_hwmod,
@@ -286,12 +345,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
286 .user = OCP_USER_MPU | OCP_USER_SDMA, 345 .user = OCP_USER_MPU | OCP_USER_SDMA,
287}; 346};
288 347
348/* usb_otg_hs -> l3_main_2 */
349static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
350 .master = &omap44xx_usb_otg_hs_hwmod,
351 .slave = &omap44xx_l3_main_2_hwmod,
352 .clk = "l3_div_ck",
353 .user = OCP_USER_MPU | OCP_USER_SDMA,
354};
355
289/* l3_main_2 slave ports */ 356/* l3_main_2 slave ports */
290static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { 357static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
291 &omap44xx_dma_system__l3_main_2, 358 &omap44xx_dma_system__l3_main_2,
359 &omap44xx_hsi__l3_main_2,
360 &omap44xx_ipu__l3_main_2,
361 &omap44xx_iss__l3_main_2,
292 &omap44xx_iva__l3_main_2, 362 &omap44xx_iva__l3_main_2,
293 &omap44xx_l3_main_1__l3_main_2, 363 &omap44xx_l3_main_1__l3_main_2,
294 &omap44xx_l4_cfg__l3_main_2, 364 &omap44xx_l4_cfg__l3_main_2,
365 &omap44xx_usb_otg_hs__l3_main_2,
295}; 366};
296 367
297static struct omap_hwmod omap44xx_l3_main_2_hwmod = { 368static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
@@ -351,6 +422,14 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
351}; 422};
352 423
353/* l4_abe interface data */ 424/* l4_abe interface data */
425/* aess -> l4_abe */
426static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
427 .master = &omap44xx_aess_hwmod,
428 .slave = &omap44xx_l4_abe_hwmod,
429 .clk = "ocp_abe_iclk",
430 .user = OCP_USER_MPU | OCP_USER_SDMA,
431};
432
354/* dsp -> l4_abe */ 433/* dsp -> l4_abe */
355static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { 434static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
356 .master = &omap44xx_dsp_hwmod, 435 .master = &omap44xx_dsp_hwmod,
@@ -377,6 +456,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
377 456
378/* l4_abe slave ports */ 457/* l4_abe slave ports */
379static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { 458static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
459 &omap44xx_aess__l4_abe,
380 &omap44xx_dsp__l4_abe, 460 &omap44xx_dsp__l4_abe,
381 &omap44xx_l3_main_1__l4_abe, 461 &omap44xx_l3_main_1__l4_abe,
382 &omap44xx_mpu__l4_abe, 462 &omap44xx_mpu__l4_abe,
@@ -494,26 +574,15 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
494 * - They still need to be validated with the driver 574 * - They still need to be validated with the driver
495 * properly adapted to omap_hwmod / omap_device 575 * properly adapted to omap_hwmod / omap_device
496 * 576 *
497 * aess
498 * bandgap
499 * c2c 577 * c2c
500 * c2c_target_fw 578 * c2c_target_fw
501 * cm_core 579 * cm_core
502 * cm_core_aon 580 * cm_core_aon
503 * counter_32k
504 * ctrl_module_core 581 * ctrl_module_core
505 * ctrl_module_pad_core 582 * ctrl_module_pad_core
506 * ctrl_module_pad_wkup 583 * ctrl_module_pad_wkup
507 * ctrl_module_wkup 584 * ctrl_module_wkup
508 * debugss 585 * debugss
509 * dmic
510 * dss
511 * dss_dispc
512 * dss_dsi1
513 * dss_dsi2
514 * dss_hdmi
515 * dss_rfbi
516 * dss_venc
517 * efuse_ctrl_cust 586 * efuse_ctrl_cust
518 * efuse_ctrl_std 587 * efuse_ctrl_std
519 * elm 588 * elm
@@ -524,58 +593,211 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
524 * gpu 593 * gpu
525 * hdq1w 594 * hdq1w
526 * hsi 595 * hsi
527 * ipu
528 * iss
529 * kbd
530 * mailbox
531 * mcasp
532 * mcbsp1
533 * mcbsp2
534 * mcbsp3
535 * mcbsp4
536 * mcpdm
537 * mcspi1
538 * mcspi2
539 * mcspi3
540 * mcspi4
541 * mmc1
542 * mmc2
543 * mmc3
544 * mmc4
545 * mmc5
546 * mpu_c0
547 * mpu_c1
548 * ocmc_ram 596 * ocmc_ram
549 * ocp2scp_usb_phy 597 * ocp2scp_usb_phy
550 * ocp_wp_noc 598 * ocp_wp_noc
551 * prcm
552 * prcm_mpu 599 * prcm_mpu
553 * prm 600 * prm
554 * scrm 601 * scrm
555 * sl2if 602 * sl2if
556 * slimbus1 603 * slimbus1
557 * slimbus2 604 * slimbus2
558 * spinlock
559 * timer1
560 * timer10
561 * timer11
562 * timer2
563 * timer3
564 * timer4
565 * timer5
566 * timer6
567 * timer7
568 * timer8
569 * timer9
570 * usb_host_fs 605 * usb_host_fs
571 * usb_host_hs 606 * usb_host_hs
572 * usb_otg_hs
573 * usb_phy_cm 607 * usb_phy_cm
574 * usb_tll_hs 608 * usb_tll_hs
575 * usim 609 * usim
576 */ 610 */
577 611
578/* 612/*
613 * 'aess' class
614 * audio engine sub system
615 */
616
617static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
618 .rev_offs = 0x0000,
619 .sysc_offs = 0x0010,
620 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
621 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
622 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
623 .sysc_fields = &omap_hwmod_sysc_type2,
624};
625
626static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
627 .name = "aess",
628 .sysc = &omap44xx_aess_sysc,
629};
630
631/* aess */
632static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
633 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
634};
635
636static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
637 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
638 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
639 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
640 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
641 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
642 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
643 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
644 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
645};
646
647/* aess master ports */
648static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
649 &omap44xx_aess__l4_abe,
650};
651
652static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
653 {
654 .pa_start = 0x401f1000,
655 .pa_end = 0x401f13ff,
656 .flags = ADDR_TYPE_RT
657 },
658};
659
660/* l4_abe -> aess */
661static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
662 .master = &omap44xx_l4_abe_hwmod,
663 .slave = &omap44xx_aess_hwmod,
664 .clk = "ocp_abe_iclk",
665 .addr = omap44xx_aess_addrs,
666 .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
667 .user = OCP_USER_MPU,
668};
669
670static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
671 {
672 .pa_start = 0x490f1000,
673 .pa_end = 0x490f13ff,
674 .flags = ADDR_TYPE_RT
675 },
676};
677
678/* l4_abe -> aess (dma) */
679static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
680 .master = &omap44xx_l4_abe_hwmod,
681 .slave = &omap44xx_aess_hwmod,
682 .clk = "ocp_abe_iclk",
683 .addr = omap44xx_aess_dma_addrs,
684 .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
685 .user = OCP_USER_SDMA,
686};
687
688/* aess slave ports */
689static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
690 &omap44xx_l4_abe__aess,
691 &omap44xx_l4_abe__aess_dma,
692};
693
694static struct omap_hwmod omap44xx_aess_hwmod = {
695 .name = "aess",
696 .class = &omap44xx_aess_hwmod_class,
697 .mpu_irqs = omap44xx_aess_irqs,
698 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
699 .sdma_reqs = omap44xx_aess_sdma_reqs,
700 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
701 .main_clk = "aess_fck",
702 .prcm = {
703 .omap4 = {
704 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
705 },
706 },
707 .slaves = omap44xx_aess_slaves,
708 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
709 .masters = omap44xx_aess_masters,
710 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
711 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
712};
713
714/*
715 * 'bandgap' class
716 * bangap reference for ldo regulators
717 */
718
719static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
720 .name = "bandgap",
721};
722
723/* bandgap */
724static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
725 { .role = "fclk", .clk = "bandgap_fclk" },
726};
727
728static struct omap_hwmod omap44xx_bandgap_hwmod = {
729 .name = "bandgap",
730 .class = &omap44xx_bandgap_hwmod_class,
731 .prcm = {
732 .omap4 = {
733 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
734 },
735 },
736 .opt_clks = bandgap_opt_clks,
737 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
738 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
739};
740
741/*
742 * 'counter' class
743 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
744 */
745
746static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
747 .rev_offs = 0x0000,
748 .sysc_offs = 0x0004,
749 .sysc_flags = SYSC_HAS_SIDLEMODE,
750 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
751 SIDLE_SMART_WKUP),
752 .sysc_fields = &omap_hwmod_sysc_type1,
753};
754
755static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
756 .name = "counter",
757 .sysc = &omap44xx_counter_sysc,
758};
759
760/* counter_32k */
761static struct omap_hwmod omap44xx_counter_32k_hwmod;
762static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
763 {
764 .pa_start = 0x4a304000,
765 .pa_end = 0x4a30401f,
766 .flags = ADDR_TYPE_RT
767 },
768};
769
770/* l4_wkup -> counter_32k */
771static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
772 .master = &omap44xx_l4_wkup_hwmod,
773 .slave = &omap44xx_counter_32k_hwmod,
774 .clk = "l4_wkup_clk_mux_ck",
775 .addr = omap44xx_counter_32k_addrs,
776 .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
777 .user = OCP_USER_MPU | OCP_USER_SDMA,
778};
779
780/* counter_32k slave ports */
781static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
782 &omap44xx_l4_wkup__counter_32k,
783};
784
785static struct omap_hwmod omap44xx_counter_32k_hwmod = {
786 .name = "counter_32k",
787 .class = &omap44xx_counter_hwmod_class,
788 .flags = HWMOD_SWSUP_SIDLE,
789 .main_clk = "sys_32k_ck",
790 .prcm = {
791 .omap4 = {
792 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
793 },
794 },
795 .slaves = omap44xx_counter_32k_slaves,
796 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
797 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
798};
799
800/*
579 * 'dma' class 801 * 'dma' class
580 * dma controller for data exchange between memory to memory (i.e. internal or 802 * dma controller for data exchange between memory to memory (i.e. internal or
581 * external memory) and gp peripherals to memory or memory to gp peripherals 803 * external memory) and gp peripherals to memory or memory to gp peripherals
@@ -662,6 +884,96 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
662}; 884};
663 885
664/* 886/*
887 * 'dmic' class
888 * digital microphone controller
889 */
890
891static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
892 .rev_offs = 0x0000,
893 .sysc_offs = 0x0010,
894 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
895 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
896 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
897 SIDLE_SMART_WKUP),
898 .sysc_fields = &omap_hwmod_sysc_type2,
899};
900
901static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
902 .name = "dmic",
903 .sysc = &omap44xx_dmic_sysc,
904};
905
906/* dmic */
907static struct omap_hwmod omap44xx_dmic_hwmod;
908static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
909 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
910};
911
912static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
913 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
914};
915
916static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
917 {
918 .pa_start = 0x4012e000,
919 .pa_end = 0x4012e07f,
920 .flags = ADDR_TYPE_RT
921 },
922};
923
924/* l4_abe -> dmic */
925static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
926 .master = &omap44xx_l4_abe_hwmod,
927 .slave = &omap44xx_dmic_hwmod,
928 .clk = "ocp_abe_iclk",
929 .addr = omap44xx_dmic_addrs,
930 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
931 .user = OCP_USER_MPU,
932};
933
934static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
935 {
936 .pa_start = 0x4902e000,
937 .pa_end = 0x4902e07f,
938 .flags = ADDR_TYPE_RT
939 },
940};
941
942/* l4_abe -> dmic (dma) */
943static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
944 .master = &omap44xx_l4_abe_hwmod,
945 .slave = &omap44xx_dmic_hwmod,
946 .clk = "ocp_abe_iclk",
947 .addr = omap44xx_dmic_dma_addrs,
948 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
949 .user = OCP_USER_SDMA,
950};
951
952/* dmic slave ports */
953static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
954 &omap44xx_l4_abe__dmic,
955 &omap44xx_l4_abe__dmic_dma,
956};
957
958static struct omap_hwmod omap44xx_dmic_hwmod = {
959 .name = "dmic",
960 .class = &omap44xx_dmic_hwmod_class,
961 .mpu_irqs = omap44xx_dmic_irqs,
962 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
963 .sdma_reqs = omap44xx_dmic_sdma_reqs,
964 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
965 .main_clk = "dmic_fck",
966 .prcm = {
967 .omap4 = {
968 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
969 },
970 },
971 .slaves = omap44xx_dmic_slaves,
972 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
973 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
974};
975
976/*
665 * 'dsp' class 977 * 'dsp' class
666 * dsp sub-system 978 * dsp sub-system
667 */ 979 */
@@ -747,6 +1059,590 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
747}; 1059};
748 1060
749/* 1061/*
1062 * 'dss' class
1063 * display sub-system
1064 */
1065
1066static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1067 .rev_offs = 0x0000,
1068 .syss_offs = 0x0014,
1069 .sysc_flags = SYSS_HAS_RESET_STATUS,
1070};
1071
1072static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1073 .name = "dss",
1074 .sysc = &omap44xx_dss_sysc,
1075};
1076
1077/* dss */
1078/* dss master ports */
1079static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1080 &omap44xx_dss__l3_main_1,
1081};
1082
1083static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1084 {
1085 .pa_start = 0x58000000,
1086 .pa_end = 0x5800007f,
1087 .flags = ADDR_TYPE_RT
1088 },
1089};
1090
1091/* l3_main_2 -> dss */
1092static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1093 .master = &omap44xx_l3_main_2_hwmod,
1094 .slave = &omap44xx_dss_hwmod,
1095 .clk = "l3_div_ck",
1096 .addr = omap44xx_dss_dma_addrs,
1097 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1098 .user = OCP_USER_SDMA,
1099};
1100
1101static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1102 {
1103 .pa_start = 0x48040000,
1104 .pa_end = 0x4804007f,
1105 .flags = ADDR_TYPE_RT
1106 },
1107};
1108
1109/* l4_per -> dss */
1110static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1111 .master = &omap44xx_l4_per_hwmod,
1112 .slave = &omap44xx_dss_hwmod,
1113 .clk = "l4_div_ck",
1114 .addr = omap44xx_dss_addrs,
1115 .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
1116 .user = OCP_USER_MPU,
1117};
1118
1119/* dss slave ports */
1120static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1121 &omap44xx_l3_main_2__dss,
1122 &omap44xx_l4_per__dss,
1123};
1124
1125static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1126 { .role = "sys_clk", .clk = "dss_sys_clk" },
1127 { .role = "tv_clk", .clk = "dss_tv_clk" },
1128 { .role = "dss_clk", .clk = "dss_dss_clk" },
1129 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1130};
1131
1132static struct omap_hwmod omap44xx_dss_hwmod = {
1133 .name = "dss_core",
1134 .class = &omap44xx_dss_hwmod_class,
1135 .main_clk = "dss_fck",
1136 .prcm = {
1137 .omap4 = {
1138 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1139 },
1140 },
1141 .opt_clks = dss_opt_clks,
1142 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1143 .slaves = omap44xx_dss_slaves,
1144 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1145 .masters = omap44xx_dss_masters,
1146 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1147 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1148};
1149
1150/*
1151 * 'dispc' class
1152 * display controller
1153 */
1154
1155static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1156 .rev_offs = 0x0000,
1157 .sysc_offs = 0x0010,
1158 .syss_offs = 0x0014,
1159 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1160 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1161 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1162 SYSS_HAS_RESET_STATUS),
1163 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1164 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1165 .sysc_fields = &omap_hwmod_sysc_type1,
1166};
1167
1168static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1169 .name = "dispc",
1170 .sysc = &omap44xx_dispc_sysc,
1171};
1172
1173/* dss_dispc */
1174static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1175static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1176 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1177};
1178
1179static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1180 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1181};
1182
1183static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1184 {
1185 .pa_start = 0x58001000,
1186 .pa_end = 0x58001fff,
1187 .flags = ADDR_TYPE_RT
1188 },
1189};
1190
1191/* l3_main_2 -> dss_dispc */
1192static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1193 .master = &omap44xx_l3_main_2_hwmod,
1194 .slave = &omap44xx_dss_dispc_hwmod,
1195 .clk = "l3_div_ck",
1196 .addr = omap44xx_dss_dispc_dma_addrs,
1197 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1198 .user = OCP_USER_SDMA,
1199};
1200
1201static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1202 {
1203 .pa_start = 0x48041000,
1204 .pa_end = 0x48041fff,
1205 .flags = ADDR_TYPE_RT
1206 },
1207};
1208
1209/* l4_per -> dss_dispc */
1210static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1211 .master = &omap44xx_l4_per_hwmod,
1212 .slave = &omap44xx_dss_dispc_hwmod,
1213 .clk = "l4_div_ck",
1214 .addr = omap44xx_dss_dispc_addrs,
1215 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1216 .user = OCP_USER_MPU,
1217};
1218
1219/* dss_dispc slave ports */
1220static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1221 &omap44xx_l3_main_2__dss_dispc,
1222 &omap44xx_l4_per__dss_dispc,
1223};
1224
1225static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1226 .name = "dss_dispc",
1227 .class = &omap44xx_dispc_hwmod_class,
1228 .mpu_irqs = omap44xx_dss_dispc_irqs,
1229 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1230 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1231 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1232 .main_clk = "dss_fck",
1233 .prcm = {
1234 .omap4 = {
1235 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1236 },
1237 },
1238 .slaves = omap44xx_dss_dispc_slaves,
1239 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1240 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1241};
1242
1243/*
1244 * 'dsi' class
1245 * display serial interface controller
1246 */
1247
1248static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1249 .rev_offs = 0x0000,
1250 .sysc_offs = 0x0010,
1251 .syss_offs = 0x0014,
1252 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1253 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1254 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1255 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1256 .sysc_fields = &omap_hwmod_sysc_type1,
1257};
1258
1259static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1260 .name = "dsi",
1261 .sysc = &omap44xx_dsi_sysc,
1262};
1263
1264/* dss_dsi1 */
1265static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1266static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1267 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1268};
1269
1270static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1271 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1272};
1273
1274static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1275 {
1276 .pa_start = 0x58004000,
1277 .pa_end = 0x580041ff,
1278 .flags = ADDR_TYPE_RT
1279 },
1280};
1281
1282/* l3_main_2 -> dss_dsi1 */
1283static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1284 .master = &omap44xx_l3_main_2_hwmod,
1285 .slave = &omap44xx_dss_dsi1_hwmod,
1286 .clk = "l3_div_ck",
1287 .addr = omap44xx_dss_dsi1_dma_addrs,
1288 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1289 .user = OCP_USER_SDMA,
1290};
1291
1292static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1293 {
1294 .pa_start = 0x48044000,
1295 .pa_end = 0x480441ff,
1296 .flags = ADDR_TYPE_RT
1297 },
1298};
1299
1300/* l4_per -> dss_dsi1 */
1301static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1302 .master = &omap44xx_l4_per_hwmod,
1303 .slave = &omap44xx_dss_dsi1_hwmod,
1304 .clk = "l4_div_ck",
1305 .addr = omap44xx_dss_dsi1_addrs,
1306 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1307 .user = OCP_USER_MPU,
1308};
1309
1310/* dss_dsi1 slave ports */
1311static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1312 &omap44xx_l3_main_2__dss_dsi1,
1313 &omap44xx_l4_per__dss_dsi1,
1314};
1315
1316static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1317 .name = "dss_dsi1",
1318 .class = &omap44xx_dsi_hwmod_class,
1319 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1320 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1321 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1322 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1323 .main_clk = "dss_fck",
1324 .prcm = {
1325 .omap4 = {
1326 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1327 },
1328 },
1329 .slaves = omap44xx_dss_dsi1_slaves,
1330 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1331 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1332};
1333
1334/* dss_dsi2 */
1335static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1336static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1337 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1338};
1339
1340static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1341 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1342};
1343
1344static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1345 {
1346 .pa_start = 0x58005000,
1347 .pa_end = 0x580051ff,
1348 .flags = ADDR_TYPE_RT
1349 },
1350};
1351
1352/* l3_main_2 -> dss_dsi2 */
1353static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1354 .master = &omap44xx_l3_main_2_hwmod,
1355 .slave = &omap44xx_dss_dsi2_hwmod,
1356 .clk = "l3_div_ck",
1357 .addr = omap44xx_dss_dsi2_dma_addrs,
1358 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1359 .user = OCP_USER_SDMA,
1360};
1361
1362static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1363 {
1364 .pa_start = 0x48045000,
1365 .pa_end = 0x480451ff,
1366 .flags = ADDR_TYPE_RT
1367 },
1368};
1369
1370/* l4_per -> dss_dsi2 */
1371static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1372 .master = &omap44xx_l4_per_hwmod,
1373 .slave = &omap44xx_dss_dsi2_hwmod,
1374 .clk = "l4_div_ck",
1375 .addr = omap44xx_dss_dsi2_addrs,
1376 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1377 .user = OCP_USER_MPU,
1378};
1379
1380/* dss_dsi2 slave ports */
1381static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1382 &omap44xx_l3_main_2__dss_dsi2,
1383 &omap44xx_l4_per__dss_dsi2,
1384};
1385
1386static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1387 .name = "dss_dsi2",
1388 .class = &omap44xx_dsi_hwmod_class,
1389 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1390 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1391 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1392 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1393 .main_clk = "dss_fck",
1394 .prcm = {
1395 .omap4 = {
1396 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1397 },
1398 },
1399 .slaves = omap44xx_dss_dsi2_slaves,
1400 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1401 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1402};
1403
1404/*
1405 * 'hdmi' class
1406 * hdmi controller
1407 */
1408
1409static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1410 .rev_offs = 0x0000,
1411 .sysc_offs = 0x0010,
1412 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1413 SYSC_HAS_SOFTRESET),
1414 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1415 SIDLE_SMART_WKUP),
1416 .sysc_fields = &omap_hwmod_sysc_type2,
1417};
1418
1419static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1420 .name = "hdmi",
1421 .sysc = &omap44xx_hdmi_sysc,
1422};
1423
1424/* dss_hdmi */
1425static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1426static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1427 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1428};
1429
1430static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1431 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1432};
1433
1434static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1435 {
1436 .pa_start = 0x58006000,
1437 .pa_end = 0x58006fff,
1438 .flags = ADDR_TYPE_RT
1439 },
1440};
1441
1442/* l3_main_2 -> dss_hdmi */
1443static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1444 .master = &omap44xx_l3_main_2_hwmod,
1445 .slave = &omap44xx_dss_hdmi_hwmod,
1446 .clk = "l3_div_ck",
1447 .addr = omap44xx_dss_hdmi_dma_addrs,
1448 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1449 .user = OCP_USER_SDMA,
1450};
1451
1452static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1453 {
1454 .pa_start = 0x48046000,
1455 .pa_end = 0x48046fff,
1456 .flags = ADDR_TYPE_RT
1457 },
1458};
1459
1460/* l4_per -> dss_hdmi */
1461static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1462 .master = &omap44xx_l4_per_hwmod,
1463 .slave = &omap44xx_dss_hdmi_hwmod,
1464 .clk = "l4_div_ck",
1465 .addr = omap44xx_dss_hdmi_addrs,
1466 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1467 .user = OCP_USER_MPU,
1468};
1469
1470/* dss_hdmi slave ports */
1471static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1472 &omap44xx_l3_main_2__dss_hdmi,
1473 &omap44xx_l4_per__dss_hdmi,
1474};
1475
1476static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1477 .name = "dss_hdmi",
1478 .class = &omap44xx_hdmi_hwmod_class,
1479 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1480 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1481 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1482 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1483 .main_clk = "dss_fck",
1484 .prcm = {
1485 .omap4 = {
1486 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1487 },
1488 },
1489 .slaves = omap44xx_dss_hdmi_slaves,
1490 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1491 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1492};
1493
1494/*
1495 * 'rfbi' class
1496 * remote frame buffer interface
1497 */
1498
1499static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1500 .rev_offs = 0x0000,
1501 .sysc_offs = 0x0010,
1502 .syss_offs = 0x0014,
1503 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1504 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1505 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1506 .sysc_fields = &omap_hwmod_sysc_type1,
1507};
1508
1509static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1510 .name = "rfbi",
1511 .sysc = &omap44xx_rfbi_sysc,
1512};
1513
1514/* dss_rfbi */
1515static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1516static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1517 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1518};
1519
1520static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1521 {
1522 .pa_start = 0x58002000,
1523 .pa_end = 0x580020ff,
1524 .flags = ADDR_TYPE_RT
1525 },
1526};
1527
1528/* l3_main_2 -> dss_rfbi */
1529static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1530 .master = &omap44xx_l3_main_2_hwmod,
1531 .slave = &omap44xx_dss_rfbi_hwmod,
1532 .clk = "l3_div_ck",
1533 .addr = omap44xx_dss_rfbi_dma_addrs,
1534 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1535 .user = OCP_USER_SDMA,
1536};
1537
1538static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1539 {
1540 .pa_start = 0x48042000,
1541 .pa_end = 0x480420ff,
1542 .flags = ADDR_TYPE_RT
1543 },
1544};
1545
1546/* l4_per -> dss_rfbi */
1547static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1548 .master = &omap44xx_l4_per_hwmod,
1549 .slave = &omap44xx_dss_rfbi_hwmod,
1550 .clk = "l4_div_ck",
1551 .addr = omap44xx_dss_rfbi_addrs,
1552 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1553 .user = OCP_USER_MPU,
1554};
1555
1556/* dss_rfbi slave ports */
1557static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1558 &omap44xx_l3_main_2__dss_rfbi,
1559 &omap44xx_l4_per__dss_rfbi,
1560};
1561
1562static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1563 .name = "dss_rfbi",
1564 .class = &omap44xx_rfbi_hwmod_class,
1565 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1566 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1567 .main_clk = "dss_fck",
1568 .prcm = {
1569 .omap4 = {
1570 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1571 },
1572 },
1573 .slaves = omap44xx_dss_rfbi_slaves,
1574 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1575 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1576};
1577
1578/*
1579 * 'venc' class
1580 * video encoder
1581 */
1582
1583static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1584 .name = "venc",
1585};
1586
1587/* dss_venc */
1588static struct omap_hwmod omap44xx_dss_venc_hwmod;
1589static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1590 {
1591 .pa_start = 0x58003000,
1592 .pa_end = 0x580030ff,
1593 .flags = ADDR_TYPE_RT
1594 },
1595};
1596
1597/* l3_main_2 -> dss_venc */
1598static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1599 .master = &omap44xx_l3_main_2_hwmod,
1600 .slave = &omap44xx_dss_venc_hwmod,
1601 .clk = "l3_div_ck",
1602 .addr = omap44xx_dss_venc_dma_addrs,
1603 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1604 .user = OCP_USER_SDMA,
1605};
1606
1607static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1608 {
1609 .pa_start = 0x48043000,
1610 .pa_end = 0x480430ff,
1611 .flags = ADDR_TYPE_RT
1612 },
1613};
1614
1615/* l4_per -> dss_venc */
1616static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1617 .master = &omap44xx_l4_per_hwmod,
1618 .slave = &omap44xx_dss_venc_hwmod,
1619 .clk = "l4_div_ck",
1620 .addr = omap44xx_dss_venc_addrs,
1621 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1622 .user = OCP_USER_MPU,
1623};
1624
1625/* dss_venc slave ports */
1626static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1627 &omap44xx_l3_main_2__dss_venc,
1628 &omap44xx_l4_per__dss_venc,
1629};
1630
1631static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1632 .name = "dss_venc",
1633 .class = &omap44xx_venc_hwmod_class,
1634 .main_clk = "dss_fck",
1635 .prcm = {
1636 .omap4 = {
1637 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1638 },
1639 },
1640 .slaves = omap44xx_dss_venc_slaves,
1641 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1642 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1643};
1644
1645/*
750 * 'gpio' class 1646 * 'gpio' class
751 * general purpose io module 1647 * general purpose io module
752 */ 1648 */
@@ -1093,6 +1989,83 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
1093}; 1989};
1094 1990
1095/* 1991/*
1992 * 'hsi' class
1993 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1994 * serial if)
1995 */
1996
1997static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1998 .rev_offs = 0x0000,
1999 .sysc_offs = 0x0010,
2000 .syss_offs = 0x0014,
2001 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2002 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2003 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2005 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2006 MSTANDBY_SMART),
2007 .sysc_fields = &omap_hwmod_sysc_type1,
2008};
2009
2010static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2011 .name = "hsi",
2012 .sysc = &omap44xx_hsi_sysc,
2013};
2014
2015/* hsi */
2016static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2017 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2018 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2019 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2020};
2021
2022/* hsi master ports */
2023static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2024 &omap44xx_hsi__l3_main_2,
2025};
2026
2027static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2028 {
2029 .pa_start = 0x4a058000,
2030 .pa_end = 0x4a05bfff,
2031 .flags = ADDR_TYPE_RT
2032 },
2033};
2034
2035/* l4_cfg -> hsi */
2036static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2037 .master = &omap44xx_l4_cfg_hwmod,
2038 .slave = &omap44xx_hsi_hwmod,
2039 .clk = "l4_div_ck",
2040 .addr = omap44xx_hsi_addrs,
2041 .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
2042 .user = OCP_USER_MPU | OCP_USER_SDMA,
2043};
2044
2045/* hsi slave ports */
2046static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2047 &omap44xx_l4_cfg__hsi,
2048};
2049
2050static struct omap_hwmod omap44xx_hsi_hwmod = {
2051 .name = "hsi",
2052 .class = &omap44xx_hsi_hwmod_class,
2053 .mpu_irqs = omap44xx_hsi_irqs,
2054 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
2055 .main_clk = "hsi_fck",
2056 .prcm = {
2057 .omap4 = {
2058 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2059 },
2060 },
2061 .slaves = omap44xx_hsi_slaves,
2062 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2063 .masters = omap44xx_hsi_masters,
2064 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2065 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2066};
2067
2068/*
1096 * 'i2c' class 2069 * 'i2c' class
1097 * multimaster high-speed i2c controller 2070 * multimaster high-speed i2c controller
1098 */ 2071 */
@@ -1326,6 +2299,188 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
1326}; 2299};
1327 2300
1328/* 2301/*
2302 * 'ipu' class
2303 * imaging processor unit
2304 */
2305
2306static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2307 .name = "ipu",
2308};
2309
2310/* ipu */
2311static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2312 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2313};
2314
2315static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2316 { .name = "cpu0", .rst_shift = 0 },
2317};
2318
2319static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2320 { .name = "cpu1", .rst_shift = 1 },
2321};
2322
2323static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2324 { .name = "mmu_cache", .rst_shift = 2 },
2325};
2326
2327/* ipu master ports */
2328static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2329 &omap44xx_ipu__l3_main_2,
2330};
2331
2332/* l3_main_2 -> ipu */
2333static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2334 .master = &omap44xx_l3_main_2_hwmod,
2335 .slave = &omap44xx_ipu_hwmod,
2336 .clk = "l3_div_ck",
2337 .user = OCP_USER_MPU | OCP_USER_SDMA,
2338};
2339
2340/* ipu slave ports */
2341static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2342 &omap44xx_l3_main_2__ipu,
2343};
2344
2345/* Pseudo hwmod for reset control purpose only */
2346static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2347 .name = "ipu_c0",
2348 .class = &omap44xx_ipu_hwmod_class,
2349 .flags = HWMOD_INIT_NO_RESET,
2350 .rst_lines = omap44xx_ipu_c0_resets,
2351 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2352 .prcm = {
2353 .omap4 = {
2354 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2355 },
2356 },
2357 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2358};
2359
2360/* Pseudo hwmod for reset control purpose only */
2361static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2362 .name = "ipu_c1",
2363 .class = &omap44xx_ipu_hwmod_class,
2364 .flags = HWMOD_INIT_NO_RESET,
2365 .rst_lines = omap44xx_ipu_c1_resets,
2366 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2367 .prcm = {
2368 .omap4 = {
2369 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2370 },
2371 },
2372 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2373};
2374
2375static struct omap_hwmod omap44xx_ipu_hwmod = {
2376 .name = "ipu",
2377 .class = &omap44xx_ipu_hwmod_class,
2378 .mpu_irqs = omap44xx_ipu_irqs,
2379 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
2380 .rst_lines = omap44xx_ipu_resets,
2381 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2382 .main_clk = "ipu_fck",
2383 .prcm = {
2384 .omap4 = {
2385 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2386 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2387 },
2388 },
2389 .slaves = omap44xx_ipu_slaves,
2390 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2391 .masters = omap44xx_ipu_masters,
2392 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2393 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2394};
2395
2396/*
2397 * 'iss' class
2398 * external images sensor pixel data processor
2399 */
2400
2401static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2402 .rev_offs = 0x0000,
2403 .sysc_offs = 0x0010,
2404 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2405 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2406 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2407 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2408 MSTANDBY_SMART),
2409 .sysc_fields = &omap_hwmod_sysc_type2,
2410};
2411
2412static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2413 .name = "iss",
2414 .sysc = &omap44xx_iss_sysc,
2415};
2416
2417/* iss */
2418static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2419 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2420};
2421
2422static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2423 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2424 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2425 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2426 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2427};
2428
2429/* iss master ports */
2430static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2431 &omap44xx_iss__l3_main_2,
2432};
2433
2434static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2435 {
2436 .pa_start = 0x52000000,
2437 .pa_end = 0x520000ff,
2438 .flags = ADDR_TYPE_RT
2439 },
2440};
2441
2442/* l3_main_2 -> iss */
2443static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2444 .master = &omap44xx_l3_main_2_hwmod,
2445 .slave = &omap44xx_iss_hwmod,
2446 .clk = "l3_div_ck",
2447 .addr = omap44xx_iss_addrs,
2448 .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
2449 .user = OCP_USER_MPU | OCP_USER_SDMA,
2450};
2451
2452/* iss slave ports */
2453static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2454 &omap44xx_l3_main_2__iss,
2455};
2456
2457static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2458 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2459};
2460
2461static struct omap_hwmod omap44xx_iss_hwmod = {
2462 .name = "iss",
2463 .class = &omap44xx_iss_hwmod_class,
2464 .mpu_irqs = omap44xx_iss_irqs,
2465 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
2466 .sdma_reqs = omap44xx_iss_sdma_reqs,
2467 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2468 .main_clk = "iss_fck",
2469 .prcm = {
2470 .omap4 = {
2471 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2472 },
2473 },
2474 .opt_clks = iss_opt_clks,
2475 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2476 .slaves = omap44xx_iss_slaves,
2477 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2478 .masters = omap44xx_iss_masters,
2479 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2480 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2481};
2482
2483/*
1329 * 'iva' class 2484 * 'iva' class
1330 * multi-standard video encoder/decoder hardware accelerator 2485 * multi-standard video encoder/decoder hardware accelerator
1331 */ 2486 */
@@ -1435,6 +2590,1045 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
1435}; 2590};
1436 2591
1437/* 2592/*
2593 * 'kbd' class
2594 * keyboard controller
2595 */
2596
2597static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2598 .rev_offs = 0x0000,
2599 .sysc_offs = 0x0010,
2600 .syss_offs = 0x0014,
2601 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2602 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2603 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2604 SYSS_HAS_RESET_STATUS),
2605 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2606 .sysc_fields = &omap_hwmod_sysc_type1,
2607};
2608
2609static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2610 .name = "kbd",
2611 .sysc = &omap44xx_kbd_sysc,
2612};
2613
2614/* kbd */
2615static struct omap_hwmod omap44xx_kbd_hwmod;
2616static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2617 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2618};
2619
2620static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2621 {
2622 .pa_start = 0x4a31c000,
2623 .pa_end = 0x4a31c07f,
2624 .flags = ADDR_TYPE_RT
2625 },
2626};
2627
2628/* l4_wkup -> kbd */
2629static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2630 .master = &omap44xx_l4_wkup_hwmod,
2631 .slave = &omap44xx_kbd_hwmod,
2632 .clk = "l4_wkup_clk_mux_ck",
2633 .addr = omap44xx_kbd_addrs,
2634 .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
2635 .user = OCP_USER_MPU | OCP_USER_SDMA,
2636};
2637
2638/* kbd slave ports */
2639static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2640 &omap44xx_l4_wkup__kbd,
2641};
2642
2643static struct omap_hwmod omap44xx_kbd_hwmod = {
2644 .name = "kbd",
2645 .class = &omap44xx_kbd_hwmod_class,
2646 .mpu_irqs = omap44xx_kbd_irqs,
2647 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
2648 .main_clk = "kbd_fck",
2649 .prcm = {
2650 .omap4 = {
2651 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2652 },
2653 },
2654 .slaves = omap44xx_kbd_slaves,
2655 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2656 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2657};
2658
2659/*
2660 * 'mailbox' class
2661 * mailbox module allowing communication between the on-chip processors using a
2662 * queued mailbox-interrupt mechanism.
2663 */
2664
2665static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2666 .rev_offs = 0x0000,
2667 .sysc_offs = 0x0010,
2668 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2669 SYSC_HAS_SOFTRESET),
2670 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2671 .sysc_fields = &omap_hwmod_sysc_type2,
2672};
2673
2674static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2675 .name = "mailbox",
2676 .sysc = &omap44xx_mailbox_sysc,
2677};
2678
2679/* mailbox */
2680static struct omap_hwmod omap44xx_mailbox_hwmod;
2681static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2682 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2683};
2684
2685static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2686 {
2687 .pa_start = 0x4a0f4000,
2688 .pa_end = 0x4a0f41ff,
2689 .flags = ADDR_TYPE_RT
2690 },
2691};
2692
2693/* l4_cfg -> mailbox */
2694static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2695 .master = &omap44xx_l4_cfg_hwmod,
2696 .slave = &omap44xx_mailbox_hwmod,
2697 .clk = "l4_div_ck",
2698 .addr = omap44xx_mailbox_addrs,
2699 .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
2700 .user = OCP_USER_MPU | OCP_USER_SDMA,
2701};
2702
2703/* mailbox slave ports */
2704static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2705 &omap44xx_l4_cfg__mailbox,
2706};
2707
2708static struct omap_hwmod omap44xx_mailbox_hwmod = {
2709 .name = "mailbox",
2710 .class = &omap44xx_mailbox_hwmod_class,
2711 .mpu_irqs = omap44xx_mailbox_irqs,
2712 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
2713 .prcm = {
2714 .omap4 = {
2715 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2716 },
2717 },
2718 .slaves = omap44xx_mailbox_slaves,
2719 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2720 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2721};
2722
2723/*
2724 * 'mcbsp' class
2725 * multi channel buffered serial port controller
2726 */
2727
2728static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2729 .sysc_offs = 0x008c,
2730 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2731 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2732 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2733 .sysc_fields = &omap_hwmod_sysc_type1,
2734};
2735
2736static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2737 .name = "mcbsp",
2738 .sysc = &omap44xx_mcbsp_sysc,
2739};
2740
2741/* mcbsp1 */
2742static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2743static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2744 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2745};
2746
2747static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2748 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2749 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2750};
2751
2752static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2753 {
2754 .pa_start = 0x40122000,
2755 .pa_end = 0x401220ff,
2756 .flags = ADDR_TYPE_RT
2757 },
2758};
2759
2760/* l4_abe -> mcbsp1 */
2761static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2762 .master = &omap44xx_l4_abe_hwmod,
2763 .slave = &omap44xx_mcbsp1_hwmod,
2764 .clk = "ocp_abe_iclk",
2765 .addr = omap44xx_mcbsp1_addrs,
2766 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2767 .user = OCP_USER_MPU,
2768};
2769
2770static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2771 {
2772 .pa_start = 0x49022000,
2773 .pa_end = 0x490220ff,
2774 .flags = ADDR_TYPE_RT
2775 },
2776};
2777
2778/* l4_abe -> mcbsp1 (dma) */
2779static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2780 .master = &omap44xx_l4_abe_hwmod,
2781 .slave = &omap44xx_mcbsp1_hwmod,
2782 .clk = "ocp_abe_iclk",
2783 .addr = omap44xx_mcbsp1_dma_addrs,
2784 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2785 .user = OCP_USER_SDMA,
2786};
2787
2788/* mcbsp1 slave ports */
2789static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2790 &omap44xx_l4_abe__mcbsp1,
2791 &omap44xx_l4_abe__mcbsp1_dma,
2792};
2793
2794static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2795 .name = "mcbsp1",
2796 .class = &omap44xx_mcbsp_hwmod_class,
2797 .mpu_irqs = omap44xx_mcbsp1_irqs,
2798 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2799 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
2800 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2801 .main_clk = "mcbsp1_fck",
2802 .prcm = {
2803 .omap4 = {
2804 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2805 },
2806 },
2807 .slaves = omap44xx_mcbsp1_slaves,
2808 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2810};
2811
2812/* mcbsp2 */
2813static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2814static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2815 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2816};
2817
2818static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2819 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2820 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2821};
2822
2823static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2824 {
2825 .pa_start = 0x40124000,
2826 .pa_end = 0x401240ff,
2827 .flags = ADDR_TYPE_RT
2828 },
2829};
2830
2831/* l4_abe -> mcbsp2 */
2832static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2833 .master = &omap44xx_l4_abe_hwmod,
2834 .slave = &omap44xx_mcbsp2_hwmod,
2835 .clk = "ocp_abe_iclk",
2836 .addr = omap44xx_mcbsp2_addrs,
2837 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2838 .user = OCP_USER_MPU,
2839};
2840
2841static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2842 {
2843 .pa_start = 0x49024000,
2844 .pa_end = 0x490240ff,
2845 .flags = ADDR_TYPE_RT
2846 },
2847};
2848
2849/* l4_abe -> mcbsp2 (dma) */
2850static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2851 .master = &omap44xx_l4_abe_hwmod,
2852 .slave = &omap44xx_mcbsp2_hwmod,
2853 .clk = "ocp_abe_iclk",
2854 .addr = omap44xx_mcbsp2_dma_addrs,
2855 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2856 .user = OCP_USER_SDMA,
2857};
2858
2859/* mcbsp2 slave ports */
2860static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2861 &omap44xx_l4_abe__mcbsp2,
2862 &omap44xx_l4_abe__mcbsp2_dma,
2863};
2864
2865static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2866 .name = "mcbsp2",
2867 .class = &omap44xx_mcbsp_hwmod_class,
2868 .mpu_irqs = omap44xx_mcbsp2_irqs,
2869 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2870 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2871 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2872 .main_clk = "mcbsp2_fck",
2873 .prcm = {
2874 .omap4 = {
2875 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2876 },
2877 },
2878 .slaves = omap44xx_mcbsp2_slaves,
2879 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2880 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2881};
2882
2883/* mcbsp3 */
2884static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2885static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2886 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2887};
2888
2889static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2890 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2891 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2892};
2893
2894static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2895 {
2896 .pa_start = 0x40126000,
2897 .pa_end = 0x401260ff,
2898 .flags = ADDR_TYPE_RT
2899 },
2900};
2901
2902/* l4_abe -> mcbsp3 */
2903static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2904 .master = &omap44xx_l4_abe_hwmod,
2905 .slave = &omap44xx_mcbsp3_hwmod,
2906 .clk = "ocp_abe_iclk",
2907 .addr = omap44xx_mcbsp3_addrs,
2908 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2909 .user = OCP_USER_MPU,
2910};
2911
2912static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2913 {
2914 .pa_start = 0x49026000,
2915 .pa_end = 0x490260ff,
2916 .flags = ADDR_TYPE_RT
2917 },
2918};
2919
2920/* l4_abe -> mcbsp3 (dma) */
2921static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2922 .master = &omap44xx_l4_abe_hwmod,
2923 .slave = &omap44xx_mcbsp3_hwmod,
2924 .clk = "ocp_abe_iclk",
2925 .addr = omap44xx_mcbsp3_dma_addrs,
2926 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2927 .user = OCP_USER_SDMA,
2928};
2929
2930/* mcbsp3 slave ports */
2931static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2932 &omap44xx_l4_abe__mcbsp3,
2933 &omap44xx_l4_abe__mcbsp3_dma,
2934};
2935
2936static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2937 .name = "mcbsp3",
2938 .class = &omap44xx_mcbsp_hwmod_class,
2939 .mpu_irqs = omap44xx_mcbsp3_irqs,
2940 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2941 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2942 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2943 .main_clk = "mcbsp3_fck",
2944 .prcm = {
2945 .omap4 = {
2946 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2947 },
2948 },
2949 .slaves = omap44xx_mcbsp3_slaves,
2950 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
2951 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2952};
2953
2954/* mcbsp4 */
2955static struct omap_hwmod omap44xx_mcbsp4_hwmod;
2956static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2957 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2958};
2959
2960static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2961 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2962 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2963};
2964
2965static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
2966 {
2967 .pa_start = 0x48096000,
2968 .pa_end = 0x480960ff,
2969 .flags = ADDR_TYPE_RT
2970 },
2971};
2972
2973/* l4_per -> mcbsp4 */
2974static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
2975 .master = &omap44xx_l4_per_hwmod,
2976 .slave = &omap44xx_mcbsp4_hwmod,
2977 .clk = "l4_div_ck",
2978 .addr = omap44xx_mcbsp4_addrs,
2979 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
2980 .user = OCP_USER_MPU | OCP_USER_SDMA,
2981};
2982
2983/* mcbsp4 slave ports */
2984static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
2985 &omap44xx_l4_per__mcbsp4,
2986};
2987
2988static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2989 .name = "mcbsp4",
2990 .class = &omap44xx_mcbsp_hwmod_class,
2991 .mpu_irqs = omap44xx_mcbsp4_irqs,
2992 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
2993 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2994 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
2995 .main_clk = "mcbsp4_fck",
2996 .prcm = {
2997 .omap4 = {
2998 .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2999 },
3000 },
3001 .slaves = omap44xx_mcbsp4_slaves,
3002 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3003 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3004};
3005
3006/*
3007 * 'mcpdm' class
3008 * multi channel pdm controller (proprietary interface with phoenix power
3009 * ic)
3010 */
3011
3012static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3013 .rev_offs = 0x0000,
3014 .sysc_offs = 0x0010,
3015 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3016 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3017 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3018 SIDLE_SMART_WKUP),
3019 .sysc_fields = &omap_hwmod_sysc_type2,
3020};
3021
3022static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3023 .name = "mcpdm",
3024 .sysc = &omap44xx_mcpdm_sysc,
3025};
3026
3027/* mcpdm */
3028static struct omap_hwmod omap44xx_mcpdm_hwmod;
3029static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3030 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3031};
3032
3033static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3034 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3035 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3036};
3037
3038static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3039 {
3040 .pa_start = 0x40132000,
3041 .pa_end = 0x4013207f,
3042 .flags = ADDR_TYPE_RT
3043 },
3044};
3045
3046/* l4_abe -> mcpdm */
3047static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3048 .master = &omap44xx_l4_abe_hwmod,
3049 .slave = &omap44xx_mcpdm_hwmod,
3050 .clk = "ocp_abe_iclk",
3051 .addr = omap44xx_mcpdm_addrs,
3052 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3053 .user = OCP_USER_MPU,
3054};
3055
3056static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3057 {
3058 .pa_start = 0x49032000,
3059 .pa_end = 0x4903207f,
3060 .flags = ADDR_TYPE_RT
3061 },
3062};
3063
3064/* l4_abe -> mcpdm (dma) */
3065static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3066 .master = &omap44xx_l4_abe_hwmod,
3067 .slave = &omap44xx_mcpdm_hwmod,
3068 .clk = "ocp_abe_iclk",
3069 .addr = omap44xx_mcpdm_dma_addrs,
3070 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3071 .user = OCP_USER_SDMA,
3072};
3073
3074/* mcpdm slave ports */
3075static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3076 &omap44xx_l4_abe__mcpdm,
3077 &omap44xx_l4_abe__mcpdm_dma,
3078};
3079
3080static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3081 .name = "mcpdm",
3082 .class = &omap44xx_mcpdm_hwmod_class,
3083 .mpu_irqs = omap44xx_mcpdm_irqs,
3084 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3085 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3086 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3087 .main_clk = "mcpdm_fck",
3088 .prcm = {
3089 .omap4 = {
3090 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3091 },
3092 },
3093 .slaves = omap44xx_mcpdm_slaves,
3094 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3095 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3096};
3097
3098/*
3099 * 'mcspi' class
3100 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3101 * bus
3102 */
3103
3104static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3105 .rev_offs = 0x0000,
3106 .sysc_offs = 0x0010,
3107 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3108 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3109 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3110 SIDLE_SMART_WKUP),
3111 .sysc_fields = &omap_hwmod_sysc_type2,
3112};
3113
3114static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3115 .name = "mcspi",
3116 .sysc = &omap44xx_mcspi_sysc,
3117};
3118
3119/* mcspi1 */
3120static struct omap_hwmod omap44xx_mcspi1_hwmod;
3121static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3122 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3123};
3124
3125static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3126 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3127 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3128 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3129 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3130 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3131 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3132 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3133 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3134};
3135
3136static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3137 {
3138 .pa_start = 0x48098000,
3139 .pa_end = 0x480981ff,
3140 .flags = ADDR_TYPE_RT
3141 },
3142};
3143
3144/* l4_per -> mcspi1 */
3145static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3146 .master = &omap44xx_l4_per_hwmod,
3147 .slave = &omap44xx_mcspi1_hwmod,
3148 .clk = "l4_div_ck",
3149 .addr = omap44xx_mcspi1_addrs,
3150 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3151 .user = OCP_USER_MPU | OCP_USER_SDMA,
3152};
3153
3154/* mcspi1 slave ports */
3155static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3156 &omap44xx_l4_per__mcspi1,
3157};
3158
3159static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3160 .name = "mcspi1",
3161 .class = &omap44xx_mcspi_hwmod_class,
3162 .mpu_irqs = omap44xx_mcspi1_irqs,
3163 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3164 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3165 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3166 .main_clk = "mcspi1_fck",
3167 .prcm = {
3168 .omap4 = {
3169 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3170 },
3171 },
3172 .slaves = omap44xx_mcspi1_slaves,
3173 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3175};
3176
3177/* mcspi2 */
3178static struct omap_hwmod omap44xx_mcspi2_hwmod;
3179static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3180 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3181};
3182
3183static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3184 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3185 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3186 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3187 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3188};
3189
3190static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3191 {
3192 .pa_start = 0x4809a000,
3193 .pa_end = 0x4809a1ff,
3194 .flags = ADDR_TYPE_RT
3195 },
3196};
3197
3198/* l4_per -> mcspi2 */
3199static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3200 .master = &omap44xx_l4_per_hwmod,
3201 .slave = &omap44xx_mcspi2_hwmod,
3202 .clk = "l4_div_ck",
3203 .addr = omap44xx_mcspi2_addrs,
3204 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3205 .user = OCP_USER_MPU | OCP_USER_SDMA,
3206};
3207
3208/* mcspi2 slave ports */
3209static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3210 &omap44xx_l4_per__mcspi2,
3211};
3212
3213static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3214 .name = "mcspi2",
3215 .class = &omap44xx_mcspi_hwmod_class,
3216 .mpu_irqs = omap44xx_mcspi2_irqs,
3217 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3218 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3219 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3220 .main_clk = "mcspi2_fck",
3221 .prcm = {
3222 .omap4 = {
3223 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3224 },
3225 },
3226 .slaves = omap44xx_mcspi2_slaves,
3227 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3229};
3230
3231/* mcspi3 */
3232static struct omap_hwmod omap44xx_mcspi3_hwmod;
3233static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3234 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3235};
3236
3237static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3238 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3239 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3240 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3241 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3242};
3243
3244static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3245 {
3246 .pa_start = 0x480b8000,
3247 .pa_end = 0x480b81ff,
3248 .flags = ADDR_TYPE_RT
3249 },
3250};
3251
3252/* l4_per -> mcspi3 */
3253static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3254 .master = &omap44xx_l4_per_hwmod,
3255 .slave = &omap44xx_mcspi3_hwmod,
3256 .clk = "l4_div_ck",
3257 .addr = omap44xx_mcspi3_addrs,
3258 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3259 .user = OCP_USER_MPU | OCP_USER_SDMA,
3260};
3261
3262/* mcspi3 slave ports */
3263static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3264 &omap44xx_l4_per__mcspi3,
3265};
3266
3267static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3268 .name = "mcspi3",
3269 .class = &omap44xx_mcspi_hwmod_class,
3270 .mpu_irqs = omap44xx_mcspi3_irqs,
3271 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3272 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3273 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3274 .main_clk = "mcspi3_fck",
3275 .prcm = {
3276 .omap4 = {
3277 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3278 },
3279 },
3280 .slaves = omap44xx_mcspi3_slaves,
3281 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3282 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3283};
3284
3285/* mcspi4 */
3286static struct omap_hwmod omap44xx_mcspi4_hwmod;
3287static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3288 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3289};
3290
3291static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3292 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3293 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3294};
3295
3296static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3297 {
3298 .pa_start = 0x480ba000,
3299 .pa_end = 0x480ba1ff,
3300 .flags = ADDR_TYPE_RT
3301 },
3302};
3303
3304/* l4_per -> mcspi4 */
3305static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3306 .master = &omap44xx_l4_per_hwmod,
3307 .slave = &omap44xx_mcspi4_hwmod,
3308 .clk = "l4_div_ck",
3309 .addr = omap44xx_mcspi4_addrs,
3310 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
3312};
3313
3314/* mcspi4 slave ports */
3315static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3316 &omap44xx_l4_per__mcspi4,
3317};
3318
3319static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3320 .name = "mcspi4",
3321 .class = &omap44xx_mcspi_hwmod_class,
3322 .mpu_irqs = omap44xx_mcspi4_irqs,
3323 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3324 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3325 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3326 .main_clk = "mcspi4_fck",
3327 .prcm = {
3328 .omap4 = {
3329 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3330 },
3331 },
3332 .slaves = omap44xx_mcspi4_slaves,
3333 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3334 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3335};
3336
3337/*
3338 * 'mmc' class
3339 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3340 */
3341
3342static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3343 .rev_offs = 0x0000,
3344 .sysc_offs = 0x0010,
3345 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3346 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3347 SYSC_HAS_SOFTRESET),
3348 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3349 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3350 MSTANDBY_SMART),
3351 .sysc_fields = &omap_hwmod_sysc_type2,
3352};
3353
3354static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3355 .name = "mmc",
3356 .sysc = &omap44xx_mmc_sysc,
3357};
3358
3359/* mmc1 */
3360static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3361 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3362};
3363
3364static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3365 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3366 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3367};
3368
3369/* mmc1 master ports */
3370static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3371 &omap44xx_mmc1__l3_main_1,
3372};
3373
3374static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3375 {
3376 .pa_start = 0x4809c000,
3377 .pa_end = 0x4809c3ff,
3378 .flags = ADDR_TYPE_RT
3379 },
3380};
3381
3382/* l4_per -> mmc1 */
3383static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3384 .master = &omap44xx_l4_per_hwmod,
3385 .slave = &omap44xx_mmc1_hwmod,
3386 .clk = "l4_div_ck",
3387 .addr = omap44xx_mmc1_addrs,
3388 .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
3389 .user = OCP_USER_MPU | OCP_USER_SDMA,
3390};
3391
3392/* mmc1 slave ports */
3393static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3394 &omap44xx_l4_per__mmc1,
3395};
3396
3397static struct omap_hwmod omap44xx_mmc1_hwmod = {
3398 .name = "mmc1",
3399 .class = &omap44xx_mmc_hwmod_class,
3400 .mpu_irqs = omap44xx_mmc1_irqs,
3401 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
3402 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3403 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3404 .main_clk = "mmc1_fck",
3405 .prcm = {
3406 .omap4 = {
3407 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3408 },
3409 },
3410 .slaves = omap44xx_mmc1_slaves,
3411 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3412 .masters = omap44xx_mmc1_masters,
3413 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3414 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3415};
3416
3417/* mmc2 */
3418static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3419 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3420};
3421
3422static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3423 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3424 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3425};
3426
3427/* mmc2 master ports */
3428static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3429 &omap44xx_mmc2__l3_main_1,
3430};
3431
3432static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3433 {
3434 .pa_start = 0x480b4000,
3435 .pa_end = 0x480b43ff,
3436 .flags = ADDR_TYPE_RT
3437 },
3438};
3439
3440/* l4_per -> mmc2 */
3441static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3442 .master = &omap44xx_l4_per_hwmod,
3443 .slave = &omap44xx_mmc2_hwmod,
3444 .clk = "l4_div_ck",
3445 .addr = omap44xx_mmc2_addrs,
3446 .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
3447 .user = OCP_USER_MPU | OCP_USER_SDMA,
3448};
3449
3450/* mmc2 slave ports */
3451static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3452 &omap44xx_l4_per__mmc2,
3453};
3454
3455static struct omap_hwmod omap44xx_mmc2_hwmod = {
3456 .name = "mmc2",
3457 .class = &omap44xx_mmc_hwmod_class,
3458 .mpu_irqs = omap44xx_mmc2_irqs,
3459 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
3460 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3461 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3462 .main_clk = "mmc2_fck",
3463 .prcm = {
3464 .omap4 = {
3465 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3466 },
3467 },
3468 .slaves = omap44xx_mmc2_slaves,
3469 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3470 .masters = omap44xx_mmc2_masters,
3471 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3472 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3473};
3474
3475/* mmc3 */
3476static struct omap_hwmod omap44xx_mmc3_hwmod;
3477static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3478 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3479};
3480
3481static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3482 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3483 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3484};
3485
3486static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3487 {
3488 .pa_start = 0x480ad000,
3489 .pa_end = 0x480ad3ff,
3490 .flags = ADDR_TYPE_RT
3491 },
3492};
3493
3494/* l4_per -> mmc3 */
3495static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3496 .master = &omap44xx_l4_per_hwmod,
3497 .slave = &omap44xx_mmc3_hwmod,
3498 .clk = "l4_div_ck",
3499 .addr = omap44xx_mmc3_addrs,
3500 .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
3501 .user = OCP_USER_MPU | OCP_USER_SDMA,
3502};
3503
3504/* mmc3 slave ports */
3505static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3506 &omap44xx_l4_per__mmc3,
3507};
3508
3509static struct omap_hwmod omap44xx_mmc3_hwmod = {
3510 .name = "mmc3",
3511 .class = &omap44xx_mmc_hwmod_class,
3512 .mpu_irqs = omap44xx_mmc3_irqs,
3513 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
3514 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3515 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3516 .main_clk = "mmc3_fck",
3517 .prcm = {
3518 .omap4 = {
3519 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3520 },
3521 },
3522 .slaves = omap44xx_mmc3_slaves,
3523 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3524 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3525};
3526
3527/* mmc4 */
3528static struct omap_hwmod omap44xx_mmc4_hwmod;
3529static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3530 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3531};
3532
3533static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3534 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3535 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3536};
3537
3538static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3539 {
3540 .pa_start = 0x480d1000,
3541 .pa_end = 0x480d13ff,
3542 .flags = ADDR_TYPE_RT
3543 },
3544};
3545
3546/* l4_per -> mmc4 */
3547static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3548 .master = &omap44xx_l4_per_hwmod,
3549 .slave = &omap44xx_mmc4_hwmod,
3550 .clk = "l4_div_ck",
3551 .addr = omap44xx_mmc4_addrs,
3552 .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
3553 .user = OCP_USER_MPU | OCP_USER_SDMA,
3554};
3555
3556/* mmc4 slave ports */
3557static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3558 &omap44xx_l4_per__mmc4,
3559};
3560
3561static struct omap_hwmod omap44xx_mmc4_hwmod = {
3562 .name = "mmc4",
3563 .class = &omap44xx_mmc_hwmod_class,
3564 .mpu_irqs = omap44xx_mmc4_irqs,
3565 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
3566 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3567 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3568 .main_clk = "mmc4_fck",
3569 .prcm = {
3570 .omap4 = {
3571 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3572 },
3573 },
3574 .slaves = omap44xx_mmc4_slaves,
3575 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3577};
3578
3579/* mmc5 */
3580static struct omap_hwmod omap44xx_mmc5_hwmod;
3581static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3582 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3583};
3584
3585static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3586 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3587 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3588};
3589
3590static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3591 {
3592 .pa_start = 0x480d5000,
3593 .pa_end = 0x480d53ff,
3594 .flags = ADDR_TYPE_RT
3595 },
3596};
3597
3598/* l4_per -> mmc5 */
3599static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3600 .master = &omap44xx_l4_per_hwmod,
3601 .slave = &omap44xx_mmc5_hwmod,
3602 .clk = "l4_div_ck",
3603 .addr = omap44xx_mmc5_addrs,
3604 .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
3605 .user = OCP_USER_MPU | OCP_USER_SDMA,
3606};
3607
3608/* mmc5 slave ports */
3609static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3610 &omap44xx_l4_per__mmc5,
3611};
3612
3613static struct omap_hwmod omap44xx_mmc5_hwmod = {
3614 .name = "mmc5",
3615 .class = &omap44xx_mmc_hwmod_class,
3616 .mpu_irqs = omap44xx_mmc5_irqs,
3617 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
3618 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3619 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3620 .main_clk = "mmc5_fck",
3621 .prcm = {
3622 .omap4 = {
3623 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3624 },
3625 },
3626 .slaves = omap44xx_mmc5_slaves,
3627 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3628 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3629};
3630
3631/*
1438 * 'mpu' class 3632 * 'mpu' class
1439 * mpu sub-system 3633 * mpu sub-system
1440 */ 3634 */
@@ -1639,6 +3833,676 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1639}; 3833};
1640 3834
1641/* 3835/*
3836 * 'spinlock' class
3837 * spinlock provides hardware assistance for synchronizing the processes
3838 * running on multiple processors
3839 */
3840
3841static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3842 .rev_offs = 0x0000,
3843 .sysc_offs = 0x0010,
3844 .syss_offs = 0x0014,
3845 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3846 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3847 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3848 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3849 SIDLE_SMART_WKUP),
3850 .sysc_fields = &omap_hwmod_sysc_type1,
3851};
3852
3853static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3854 .name = "spinlock",
3855 .sysc = &omap44xx_spinlock_sysc,
3856};
3857
3858/* spinlock */
3859static struct omap_hwmod omap44xx_spinlock_hwmod;
3860static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3861 {
3862 .pa_start = 0x4a0f6000,
3863 .pa_end = 0x4a0f6fff,
3864 .flags = ADDR_TYPE_RT
3865 },
3866};
3867
3868/* l4_cfg -> spinlock */
3869static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3870 .master = &omap44xx_l4_cfg_hwmod,
3871 .slave = &omap44xx_spinlock_hwmod,
3872 .clk = "l4_div_ck",
3873 .addr = omap44xx_spinlock_addrs,
3874 .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
3875 .user = OCP_USER_MPU | OCP_USER_SDMA,
3876};
3877
3878/* spinlock slave ports */
3879static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3880 &omap44xx_l4_cfg__spinlock,
3881};
3882
3883static struct omap_hwmod omap44xx_spinlock_hwmod = {
3884 .name = "spinlock",
3885 .class = &omap44xx_spinlock_hwmod_class,
3886 .prcm = {
3887 .omap4 = {
3888 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3889 },
3890 },
3891 .slaves = omap44xx_spinlock_slaves,
3892 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
3893 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3894};
3895
3896/*
3897 * 'timer' class
3898 * general purpose timer module with accurate 1ms tick
3899 * This class contains several variants: ['timer_1ms', 'timer']
3900 */
3901
3902static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3903 .rev_offs = 0x0000,
3904 .sysc_offs = 0x0010,
3905 .syss_offs = 0x0014,
3906 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3907 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3908 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3909 SYSS_HAS_RESET_STATUS),
3910 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3911 .sysc_fields = &omap_hwmod_sysc_type1,
3912};
3913
3914static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3915 .name = "timer",
3916 .sysc = &omap44xx_timer_1ms_sysc,
3917};
3918
3919static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3920 .rev_offs = 0x0000,
3921 .sysc_offs = 0x0010,
3922 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3923 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3924 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3925 SIDLE_SMART_WKUP),
3926 .sysc_fields = &omap_hwmod_sysc_type2,
3927};
3928
3929static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3930 .name = "timer",
3931 .sysc = &omap44xx_timer_sysc,
3932};
3933
3934/* timer1 */
3935static struct omap_hwmod omap44xx_timer1_hwmod;
3936static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3937 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3938};
3939
3940static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
3941 {
3942 .pa_start = 0x4a318000,
3943 .pa_end = 0x4a31807f,
3944 .flags = ADDR_TYPE_RT
3945 },
3946};
3947
3948/* l4_wkup -> timer1 */
3949static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3950 .master = &omap44xx_l4_wkup_hwmod,
3951 .slave = &omap44xx_timer1_hwmod,
3952 .clk = "l4_wkup_clk_mux_ck",
3953 .addr = omap44xx_timer1_addrs,
3954 .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
3955 .user = OCP_USER_MPU | OCP_USER_SDMA,
3956};
3957
3958/* timer1 slave ports */
3959static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
3960 &omap44xx_l4_wkup__timer1,
3961};
3962
3963static struct omap_hwmod omap44xx_timer1_hwmod = {
3964 .name = "timer1",
3965 .class = &omap44xx_timer_1ms_hwmod_class,
3966 .mpu_irqs = omap44xx_timer1_irqs,
3967 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
3968 .main_clk = "timer1_fck",
3969 .prcm = {
3970 .omap4 = {
3971 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
3972 },
3973 },
3974 .slaves = omap44xx_timer1_slaves,
3975 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
3976 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3977};
3978
3979/* timer2 */
3980static struct omap_hwmod omap44xx_timer2_hwmod;
3981static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3982 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3983};
3984
3985static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
3986 {
3987 .pa_start = 0x48032000,
3988 .pa_end = 0x4803207f,
3989 .flags = ADDR_TYPE_RT
3990 },
3991};
3992
3993/* l4_per -> timer2 */
3994static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
3995 .master = &omap44xx_l4_per_hwmod,
3996 .slave = &omap44xx_timer2_hwmod,
3997 .clk = "l4_div_ck",
3998 .addr = omap44xx_timer2_addrs,
3999 .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
4000 .user = OCP_USER_MPU | OCP_USER_SDMA,
4001};
4002
4003/* timer2 slave ports */
4004static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4005 &omap44xx_l4_per__timer2,
4006};
4007
4008static struct omap_hwmod omap44xx_timer2_hwmod = {
4009 .name = "timer2",
4010 .class = &omap44xx_timer_1ms_hwmod_class,
4011 .mpu_irqs = omap44xx_timer2_irqs,
4012 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
4013 .main_clk = "timer2_fck",
4014 .prcm = {
4015 .omap4 = {
4016 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4017 },
4018 },
4019 .slaves = omap44xx_timer2_slaves,
4020 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4022};
4023
4024/* timer3 */
4025static struct omap_hwmod omap44xx_timer3_hwmod;
4026static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4027 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4028};
4029
4030static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4031 {
4032 .pa_start = 0x48034000,
4033 .pa_end = 0x4803407f,
4034 .flags = ADDR_TYPE_RT
4035 },
4036};
4037
4038/* l4_per -> timer3 */
4039static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4040 .master = &omap44xx_l4_per_hwmod,
4041 .slave = &omap44xx_timer3_hwmod,
4042 .clk = "l4_div_ck",
4043 .addr = omap44xx_timer3_addrs,
4044 .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
4045 .user = OCP_USER_MPU | OCP_USER_SDMA,
4046};
4047
4048/* timer3 slave ports */
4049static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4050 &omap44xx_l4_per__timer3,
4051};
4052
4053static struct omap_hwmod omap44xx_timer3_hwmod = {
4054 .name = "timer3",
4055 .class = &omap44xx_timer_hwmod_class,
4056 .mpu_irqs = omap44xx_timer3_irqs,
4057 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
4058 .main_clk = "timer3_fck",
4059 .prcm = {
4060 .omap4 = {
4061 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4062 },
4063 },
4064 .slaves = omap44xx_timer3_slaves,
4065 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4066 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4067};
4068
4069/* timer4 */
4070static struct omap_hwmod omap44xx_timer4_hwmod;
4071static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4072 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4073};
4074
4075static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4076 {
4077 .pa_start = 0x48036000,
4078 .pa_end = 0x4803607f,
4079 .flags = ADDR_TYPE_RT
4080 },
4081};
4082
4083/* l4_per -> timer4 */
4084static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4085 .master = &omap44xx_l4_per_hwmod,
4086 .slave = &omap44xx_timer4_hwmod,
4087 .clk = "l4_div_ck",
4088 .addr = omap44xx_timer4_addrs,
4089 .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
4090 .user = OCP_USER_MPU | OCP_USER_SDMA,
4091};
4092
4093/* timer4 slave ports */
4094static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4095 &omap44xx_l4_per__timer4,
4096};
4097
4098static struct omap_hwmod omap44xx_timer4_hwmod = {
4099 .name = "timer4",
4100 .class = &omap44xx_timer_hwmod_class,
4101 .mpu_irqs = omap44xx_timer4_irqs,
4102 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
4103 .main_clk = "timer4_fck",
4104 .prcm = {
4105 .omap4 = {
4106 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4107 },
4108 },
4109 .slaves = omap44xx_timer4_slaves,
4110 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4112};
4113
4114/* timer5 */
4115static struct omap_hwmod omap44xx_timer5_hwmod;
4116static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4117 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4118};
4119
4120static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4121 {
4122 .pa_start = 0x40138000,
4123 .pa_end = 0x4013807f,
4124 .flags = ADDR_TYPE_RT
4125 },
4126};
4127
4128/* l4_abe -> timer5 */
4129static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4130 .master = &omap44xx_l4_abe_hwmod,
4131 .slave = &omap44xx_timer5_hwmod,
4132 .clk = "ocp_abe_iclk",
4133 .addr = omap44xx_timer5_addrs,
4134 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
4135 .user = OCP_USER_MPU,
4136};
4137
4138static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4139 {
4140 .pa_start = 0x49038000,
4141 .pa_end = 0x4903807f,
4142 .flags = ADDR_TYPE_RT
4143 },
4144};
4145
4146/* l4_abe -> timer5 (dma) */
4147static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4148 .master = &omap44xx_l4_abe_hwmod,
4149 .slave = &omap44xx_timer5_hwmod,
4150 .clk = "ocp_abe_iclk",
4151 .addr = omap44xx_timer5_dma_addrs,
4152 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4153 .user = OCP_USER_SDMA,
4154};
4155
4156/* timer5 slave ports */
4157static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4158 &omap44xx_l4_abe__timer5,
4159 &omap44xx_l4_abe__timer5_dma,
4160};
4161
4162static struct omap_hwmod omap44xx_timer5_hwmod = {
4163 .name = "timer5",
4164 .class = &omap44xx_timer_hwmod_class,
4165 .mpu_irqs = omap44xx_timer5_irqs,
4166 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
4167 .main_clk = "timer5_fck",
4168 .prcm = {
4169 .omap4 = {
4170 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4171 },
4172 },
4173 .slaves = omap44xx_timer5_slaves,
4174 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4175 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4176};
4177
4178/* timer6 */
4179static struct omap_hwmod omap44xx_timer6_hwmod;
4180static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4181 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4182};
4183
4184static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4185 {
4186 .pa_start = 0x4013a000,
4187 .pa_end = 0x4013a07f,
4188 .flags = ADDR_TYPE_RT
4189 },
4190};
4191
4192/* l4_abe -> timer6 */
4193static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4194 .master = &omap44xx_l4_abe_hwmod,
4195 .slave = &omap44xx_timer6_hwmod,
4196 .clk = "ocp_abe_iclk",
4197 .addr = omap44xx_timer6_addrs,
4198 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
4199 .user = OCP_USER_MPU,
4200};
4201
4202static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4203 {
4204 .pa_start = 0x4903a000,
4205 .pa_end = 0x4903a07f,
4206 .flags = ADDR_TYPE_RT
4207 },
4208};
4209
4210/* l4_abe -> timer6 (dma) */
4211static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4212 .master = &omap44xx_l4_abe_hwmod,
4213 .slave = &omap44xx_timer6_hwmod,
4214 .clk = "ocp_abe_iclk",
4215 .addr = omap44xx_timer6_dma_addrs,
4216 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4217 .user = OCP_USER_SDMA,
4218};
4219
4220/* timer6 slave ports */
4221static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4222 &omap44xx_l4_abe__timer6,
4223 &omap44xx_l4_abe__timer6_dma,
4224};
4225
4226static struct omap_hwmod omap44xx_timer6_hwmod = {
4227 .name = "timer6",
4228 .class = &omap44xx_timer_hwmod_class,
4229 .mpu_irqs = omap44xx_timer6_irqs,
4230 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
4231 .main_clk = "timer6_fck",
4232 .prcm = {
4233 .omap4 = {
4234 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4235 },
4236 },
4237 .slaves = omap44xx_timer6_slaves,
4238 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4240};
4241
4242/* timer7 */
4243static struct omap_hwmod omap44xx_timer7_hwmod;
4244static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4245 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4246};
4247
4248static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4249 {
4250 .pa_start = 0x4013c000,
4251 .pa_end = 0x4013c07f,
4252 .flags = ADDR_TYPE_RT
4253 },
4254};
4255
4256/* l4_abe -> timer7 */
4257static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4258 .master = &omap44xx_l4_abe_hwmod,
4259 .slave = &omap44xx_timer7_hwmod,
4260 .clk = "ocp_abe_iclk",
4261 .addr = omap44xx_timer7_addrs,
4262 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
4263 .user = OCP_USER_MPU,
4264};
4265
4266static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4267 {
4268 .pa_start = 0x4903c000,
4269 .pa_end = 0x4903c07f,
4270 .flags = ADDR_TYPE_RT
4271 },
4272};
4273
4274/* l4_abe -> timer7 (dma) */
4275static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4276 .master = &omap44xx_l4_abe_hwmod,
4277 .slave = &omap44xx_timer7_hwmod,
4278 .clk = "ocp_abe_iclk",
4279 .addr = omap44xx_timer7_dma_addrs,
4280 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4281 .user = OCP_USER_SDMA,
4282};
4283
4284/* timer7 slave ports */
4285static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4286 &omap44xx_l4_abe__timer7,
4287 &omap44xx_l4_abe__timer7_dma,
4288};
4289
4290static struct omap_hwmod omap44xx_timer7_hwmod = {
4291 .name = "timer7",
4292 .class = &omap44xx_timer_hwmod_class,
4293 .mpu_irqs = omap44xx_timer7_irqs,
4294 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
4295 .main_clk = "timer7_fck",
4296 .prcm = {
4297 .omap4 = {
4298 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4299 },
4300 },
4301 .slaves = omap44xx_timer7_slaves,
4302 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4303 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4304};
4305
4306/* timer8 */
4307static struct omap_hwmod omap44xx_timer8_hwmod;
4308static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4309 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4310};
4311
4312static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4313 {
4314 .pa_start = 0x4013e000,
4315 .pa_end = 0x4013e07f,
4316 .flags = ADDR_TYPE_RT
4317 },
4318};
4319
4320/* l4_abe -> timer8 */
4321static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4322 .master = &omap44xx_l4_abe_hwmod,
4323 .slave = &omap44xx_timer8_hwmod,
4324 .clk = "ocp_abe_iclk",
4325 .addr = omap44xx_timer8_addrs,
4326 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
4327 .user = OCP_USER_MPU,
4328};
4329
4330static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4331 {
4332 .pa_start = 0x4903e000,
4333 .pa_end = 0x4903e07f,
4334 .flags = ADDR_TYPE_RT
4335 },
4336};
4337
4338/* l4_abe -> timer8 (dma) */
4339static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4340 .master = &omap44xx_l4_abe_hwmod,
4341 .slave = &omap44xx_timer8_hwmod,
4342 .clk = "ocp_abe_iclk",
4343 .addr = omap44xx_timer8_dma_addrs,
4344 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4345 .user = OCP_USER_SDMA,
4346};
4347
4348/* timer8 slave ports */
4349static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4350 &omap44xx_l4_abe__timer8,
4351 &omap44xx_l4_abe__timer8_dma,
4352};
4353
4354static struct omap_hwmod omap44xx_timer8_hwmod = {
4355 .name = "timer8",
4356 .class = &omap44xx_timer_hwmod_class,
4357 .mpu_irqs = omap44xx_timer8_irqs,
4358 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
4359 .main_clk = "timer8_fck",
4360 .prcm = {
4361 .omap4 = {
4362 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4363 },
4364 },
4365 .slaves = omap44xx_timer8_slaves,
4366 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4367 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4368};
4369
4370/* timer9 */
4371static struct omap_hwmod omap44xx_timer9_hwmod;
4372static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4373 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4374};
4375
4376static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4377 {
4378 .pa_start = 0x4803e000,
4379 .pa_end = 0x4803e07f,
4380 .flags = ADDR_TYPE_RT
4381 },
4382};
4383
4384/* l4_per -> timer9 */
4385static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4386 .master = &omap44xx_l4_per_hwmod,
4387 .slave = &omap44xx_timer9_hwmod,
4388 .clk = "l4_div_ck",
4389 .addr = omap44xx_timer9_addrs,
4390 .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
4391 .user = OCP_USER_MPU | OCP_USER_SDMA,
4392};
4393
4394/* timer9 slave ports */
4395static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4396 &omap44xx_l4_per__timer9,
4397};
4398
4399static struct omap_hwmod omap44xx_timer9_hwmod = {
4400 .name = "timer9",
4401 .class = &omap44xx_timer_hwmod_class,
4402 .mpu_irqs = omap44xx_timer9_irqs,
4403 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
4404 .main_clk = "timer9_fck",
4405 .prcm = {
4406 .omap4 = {
4407 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4408 },
4409 },
4410 .slaves = omap44xx_timer9_slaves,
4411 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4413};
4414
4415/* timer10 */
4416static struct omap_hwmod omap44xx_timer10_hwmod;
4417static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4418 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4419};
4420
4421static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4422 {
4423 .pa_start = 0x48086000,
4424 .pa_end = 0x4808607f,
4425 .flags = ADDR_TYPE_RT
4426 },
4427};
4428
4429/* l4_per -> timer10 */
4430static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4431 .master = &omap44xx_l4_per_hwmod,
4432 .slave = &omap44xx_timer10_hwmod,
4433 .clk = "l4_div_ck",
4434 .addr = omap44xx_timer10_addrs,
4435 .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
4436 .user = OCP_USER_MPU | OCP_USER_SDMA,
4437};
4438
4439/* timer10 slave ports */
4440static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4441 &omap44xx_l4_per__timer10,
4442};
4443
4444static struct omap_hwmod omap44xx_timer10_hwmod = {
4445 .name = "timer10",
4446 .class = &omap44xx_timer_1ms_hwmod_class,
4447 .mpu_irqs = omap44xx_timer10_irqs,
4448 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
4449 .main_clk = "timer10_fck",
4450 .prcm = {
4451 .omap4 = {
4452 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4453 },
4454 },
4455 .slaves = omap44xx_timer10_slaves,
4456 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4457 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4458};
4459
4460/* timer11 */
4461static struct omap_hwmod omap44xx_timer11_hwmod;
4462static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4463 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4464};
4465
4466static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4467 {
4468 .pa_start = 0x48088000,
4469 .pa_end = 0x4808807f,
4470 .flags = ADDR_TYPE_RT
4471 },
4472};
4473
4474/* l4_per -> timer11 */
4475static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4476 .master = &omap44xx_l4_per_hwmod,
4477 .slave = &omap44xx_timer11_hwmod,
4478 .clk = "l4_div_ck",
4479 .addr = omap44xx_timer11_addrs,
4480 .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
4481 .user = OCP_USER_MPU | OCP_USER_SDMA,
4482};
4483
4484/* timer11 slave ports */
4485static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4486 &omap44xx_l4_per__timer11,
4487};
4488
4489static struct omap_hwmod omap44xx_timer11_hwmod = {
4490 .name = "timer11",
4491 .class = &omap44xx_timer_hwmod_class,
4492 .mpu_irqs = omap44xx_timer11_irqs,
4493 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
4494 .main_clk = "timer11_fck",
4495 .prcm = {
4496 .omap4 = {
4497 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4498 },
4499 },
4500 .slaves = omap44xx_timer11_slaves,
4501 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4502 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4503};
4504
4505/*
1642 * 'uart' class 4506 * 'uart' class
1643 * universal asynchronous receiver/transmitter (uart) 4507 * universal asynchronous receiver/transmitter (uart)
1644 */ 4508 */
@@ -1870,6 +4734,88 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
1870}; 4734};
1871 4735
1872/* 4736/*
4737 * 'usb_otg_hs' class
4738 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4739 */
4740
4741static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4742 .rev_offs = 0x0400,
4743 .sysc_offs = 0x0404,
4744 .syss_offs = 0x0408,
4745 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4746 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4747 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4748 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4749 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4750 MSTANDBY_SMART),
4751 .sysc_fields = &omap_hwmod_sysc_type1,
4752};
4753
4754static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4755 .name = "usb_otg_hs",
4756 .sysc = &omap44xx_usb_otg_hs_sysc,
4757};
4758
4759/* usb_otg_hs */
4760static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4761 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4762 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4763};
4764
4765/* usb_otg_hs master ports */
4766static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4767 &omap44xx_usb_otg_hs__l3_main_2,
4768};
4769
4770static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4771 {
4772 .pa_start = 0x4a0ab000,
4773 .pa_end = 0x4a0ab003,
4774 .flags = ADDR_TYPE_RT
4775 },
4776};
4777
4778/* l4_cfg -> usb_otg_hs */
4779static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4780 .master = &omap44xx_l4_cfg_hwmod,
4781 .slave = &omap44xx_usb_otg_hs_hwmod,
4782 .clk = "l4_div_ck",
4783 .addr = omap44xx_usb_otg_hs_addrs,
4784 .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4785 .user = OCP_USER_MPU | OCP_USER_SDMA,
4786};
4787
4788/* usb_otg_hs slave ports */
4789static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4790 &omap44xx_l4_cfg__usb_otg_hs,
4791};
4792
4793static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4794 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4795};
4796
4797static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4798 .name = "usb_otg_hs",
4799 .class = &omap44xx_usb_otg_hs_hwmod_class,
4800 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4801 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
4802 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4803 .main_clk = "usb_otg_hs_ick",
4804 .prcm = {
4805 .omap4 = {
4806 .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4807 },
4808 },
4809 .opt_clks = usb_otg_hs_opt_clks,
4810 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4811 .slaves = omap44xx_usb_otg_hs_slaves,
4812 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4813 .masters = omap44xx_usb_otg_hs_masters,
4814 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4815 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4816};
4817
4818/*
1873 * 'wd_timer' class 4819 * 'wd_timer' class
1874 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 4820 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1875 * overflow condition 4821 * overflow condition
@@ -2024,13 +4970,34 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2024 /* mpu_bus class */ 4970 /* mpu_bus class */
2025 &omap44xx_mpu_private_hwmod, 4971 &omap44xx_mpu_private_hwmod,
2026 4972
4973 /* aess class */
4974/* &omap44xx_aess_hwmod, */
4975
4976 /* bandgap class */
4977 &omap44xx_bandgap_hwmod,
4978
4979 /* counter class */
4980/* &omap44xx_counter_32k_hwmod, */
4981
2027 /* dma class */ 4982 /* dma class */
2028 &omap44xx_dma_system_hwmod, 4983 &omap44xx_dma_system_hwmod,
2029 4984
4985 /* dmic class */
4986 &omap44xx_dmic_hwmod,
4987
2030 /* dsp class */ 4988 /* dsp class */
2031 &omap44xx_dsp_hwmod, 4989 &omap44xx_dsp_hwmod,
2032 &omap44xx_dsp_c0_hwmod, 4990 &omap44xx_dsp_c0_hwmod,
2033 4991
4992 /* dss class */
4993 &omap44xx_dss_hwmod,
4994 &omap44xx_dss_dispc_hwmod,
4995 &omap44xx_dss_dsi1_hwmod,
4996 &omap44xx_dss_dsi2_hwmod,
4997 &omap44xx_dss_hdmi_hwmod,
4998 &omap44xx_dss_rfbi_hwmod,
4999 &omap44xx_dss_venc_hwmod,
5000
2034 /* gpio class */ 5001 /* gpio class */
2035 &omap44xx_gpio1_hwmod, 5002 &omap44xx_gpio1_hwmod,
2036 &omap44xx_gpio2_hwmod, 5003 &omap44xx_gpio2_hwmod,
@@ -2039,17 +5006,56 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2039 &omap44xx_gpio5_hwmod, 5006 &omap44xx_gpio5_hwmod,
2040 &omap44xx_gpio6_hwmod, 5007 &omap44xx_gpio6_hwmod,
2041 5008
5009 /* hsi class */
5010/* &omap44xx_hsi_hwmod, */
5011
2042 /* i2c class */ 5012 /* i2c class */
2043 &omap44xx_i2c1_hwmod, 5013 &omap44xx_i2c1_hwmod,
2044 &omap44xx_i2c2_hwmod, 5014 &omap44xx_i2c2_hwmod,
2045 &omap44xx_i2c3_hwmod, 5015 &omap44xx_i2c3_hwmod,
2046 &omap44xx_i2c4_hwmod, 5016 &omap44xx_i2c4_hwmod,
2047 5017
5018 /* ipu class */
5019 &omap44xx_ipu_hwmod,
5020 &omap44xx_ipu_c0_hwmod,
5021 &omap44xx_ipu_c1_hwmod,
5022
5023 /* iss class */
5024/* &omap44xx_iss_hwmod, */
5025
2048 /* iva class */ 5026 /* iva class */
2049 &omap44xx_iva_hwmod, 5027 &omap44xx_iva_hwmod,
2050 &omap44xx_iva_seq0_hwmod, 5028 &omap44xx_iva_seq0_hwmod,
2051 &omap44xx_iva_seq1_hwmod, 5029 &omap44xx_iva_seq1_hwmod,
2052 5030
5031 /* kbd class */
5032/* &omap44xx_kbd_hwmod, */
5033
5034 /* mailbox class */
5035 &omap44xx_mailbox_hwmod,
5036
5037 /* mcbsp class */
5038 &omap44xx_mcbsp1_hwmod,
5039 &omap44xx_mcbsp2_hwmod,
5040 &omap44xx_mcbsp3_hwmod,
5041 &omap44xx_mcbsp4_hwmod,
5042
5043 /* mcpdm class */
5044/* &omap44xx_mcpdm_hwmod, */
5045
5046 /* mcspi class */
5047 &omap44xx_mcspi1_hwmod,
5048 &omap44xx_mcspi2_hwmod,
5049 &omap44xx_mcspi3_hwmod,
5050 &omap44xx_mcspi4_hwmod,
5051
5052 /* mmc class */
5053/* &omap44xx_mmc1_hwmod, */
5054/* &omap44xx_mmc2_hwmod, */
5055/* &omap44xx_mmc3_hwmod, */
5056/* &omap44xx_mmc4_hwmod, */
5057/* &omap44xx_mmc5_hwmod, */
5058
2053 /* mpu class */ 5059 /* mpu class */
2054 &omap44xx_mpu_hwmod, 5060 &omap44xx_mpu_hwmod,
2055 5061
@@ -2058,12 +5064,31 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2058 &omap44xx_smartreflex_iva_hwmod, 5064 &omap44xx_smartreflex_iva_hwmod,
2059 &omap44xx_smartreflex_mpu_hwmod, 5065 &omap44xx_smartreflex_mpu_hwmod,
2060 5066
5067 /* spinlock class */
5068 &omap44xx_spinlock_hwmod,
5069
5070 /* timer class */
5071 &omap44xx_timer1_hwmod,
5072 &omap44xx_timer2_hwmod,
5073 &omap44xx_timer3_hwmod,
5074 &omap44xx_timer4_hwmod,
5075 &omap44xx_timer5_hwmod,
5076 &omap44xx_timer6_hwmod,
5077 &omap44xx_timer7_hwmod,
5078 &omap44xx_timer8_hwmod,
5079 &omap44xx_timer9_hwmod,
5080 &omap44xx_timer10_hwmod,
5081 &omap44xx_timer11_hwmod,
5082
2061 /* uart class */ 5083 /* uart class */
2062 &omap44xx_uart1_hwmod, 5084 &omap44xx_uart1_hwmod,
2063 &omap44xx_uart2_hwmod, 5085 &omap44xx_uart2_hwmod,
2064 &omap44xx_uart3_hwmod, 5086 &omap44xx_uart3_hwmod,
2065 &omap44xx_uart4_hwmod, 5087 &omap44xx_uart4_hwmod,
2066 5088
5089 /* usb_otg_hs class */
5090 &omap44xx_usb_otg_hs_hwmod,
5091
2067 /* wd_timer class */ 5092 /* wd_timer class */
2068 &omap44xx_wd_timer2_hwmod, 5093 &omap44xx_wd_timer2_hwmod,
2069 &omap44xx_wd_timer3_hwmod, 5094 &omap44xx_wd_timer3_hwmod,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 17:05:31 -0500