aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLennert Buytenhek <buytenh@wantstofly.org>2006-09-18 18:24:52 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-25 05:25:50 -0400
commitc680b77efe4542830bb170e1cc40db1c47c569bc (patch)
treeed79bf5cb4bab39e694690747c34cee8798c6d02
parent7412b10f7967ef4210ed6f793004d23642dc5140 (diff)
[ARM] 3830/1: iop3xx: board support file cleanup
Revamp the iop3xx board support: move the support code for each iop board type into its own file, start using platform serial and platform physmap flash devices, switch to a per-board time tick rate, and get rid of the ARCH_EP80219 and STEPD config options by doing the relevant checks at run time. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/configs/ep80219_defconfig7
-rw-r--r--arch/arm/configs/iq31244_defconfig7
-rw-r--r--arch/arm/configs/iq80321_defconfig5
-rw-r--r--arch/arm/configs/iq80331_defconfig10
-rw-r--r--arch/arm/configs/iq80332_defconfig10
-rw-r--r--arch/arm/mach-iop32x/Kconfig7
-rw-r--r--arch/arm/mach-iop32x/Makefile6
-rw-r--r--arch/arm/mach-iop32x/common.c67
-rw-r--r--arch/arm/mach-iop32x/iq31244-mm.c46
-rw-r--r--arch/arm/mach-iop32x/iq31244-pci.c90
-rw-r--r--arch/arm/mach-iop32x/iq31244.c293
-rw-r--r--arch/arm/mach-iop32x/iq80321-mm.c46
-rw-r--r--arch/arm/mach-iop32x/iq80321-pci.c84
-rw-r--r--arch/arm/mach-iop32x/iq80321.c193
-rw-r--r--arch/arm/mach-iop32x/setup.c111
-rw-r--r--arch/arm/mach-iop33x/Kconfig6
-rw-r--r--arch/arm/mach-iop33x/Makefile6
-rw-r--r--arch/arm/mach-iop33x/iq80331-pci.c80
-rw-r--r--arch/arm/mach-iop33x/iq80331.c148
-rw-r--r--arch/arm/mach-iop33x/iq80332-pci.c86
-rw-r--r--arch/arm/mach-iop33x/iq80332.c148
-rw-r--r--arch/arm/mach-iop33x/setup.c162
-rw-r--r--arch/arm/mach-iop33x/uart.c106
-rw-r--r--include/asm-arm/arch-iop32x/iop321.h12
-rw-r--r--include/asm-arm/arch-iop32x/iq31244.h7
-rw-r--r--include/asm-arm/arch-iop32x/iq80321.h7
-rw-r--r--include/asm-arm/arch-iop32x/irqs.h38
-rw-r--r--include/asm-arm/arch-iop33x/hardware.h5
-rw-r--r--include/asm-arm/arch-iop33x/iop331.h10
-rw-r--r--include/asm-arm/arch-iop33x/iq80331.h7
-rw-r--r--include/asm-arm/arch-iop33x/iq80332.h7
-rw-r--r--include/asm-arm/arch-iop33x/irqs.h38
32 files changed, 911 insertions, 944 deletions
diff --git a/arch/arm/configs/ep80219_defconfig b/arch/arm/configs/ep80219_defconfig
index f91cf8ff359d..c10f3a8afb59 100644
--- a/arch/arm/configs/ep80219_defconfig
+++ b/arch/arm/configs/ep80219_defconfig
@@ -93,7 +93,6 @@ CONFIG_ARCH_IOP32X=y
93CONFIG_ARCH_IQ31244=y 93CONFIG_ARCH_IQ31244=y
94# CONFIG_ARCH_IQ80331 is not set 94# CONFIG_ARCH_IQ80331 is not set
95# CONFIG_MACH_IQ80332 is not set 95# CONFIG_MACH_IQ80332 is not set
96CONFIG_ARCH_EP80219=y
97 96
98# 97#
99# IOP3xx Chipset Features 98# IOP3xx Chipset Features
@@ -231,9 +230,9 @@ CONFIG_MTD_CFI_UTIL=y
231# 230#
232# CONFIG_MTD_COMPLEX_MAPPINGS is not set 231# CONFIG_MTD_COMPLEX_MAPPINGS is not set
233CONFIG_MTD_PHYSMAP=y 232CONFIG_MTD_PHYSMAP=y
234CONFIG_MTD_PHYSMAP_START=0xf0000000 233CONFIG_MTD_PHYSMAP_START=0x0
235CONFIG_MTD_PHYSMAP_LEN=0x00800000 234CONFIG_MTD_PHYSMAP_LEN=0x0
236CONFIG_MTD_PHYSMAP_BANKWIDTH=2 235CONFIG_MTD_PHYSMAP_BANKWIDTH=1
237# CONFIG_MTD_ARM_INTEGRATOR is not set 236# CONFIG_MTD_ARM_INTEGRATOR is not set
238# CONFIG_MTD_EDB7312 is not set 237# CONFIG_MTD_EDB7312 is not set
239 238
diff --git a/arch/arm/configs/iq31244_defconfig b/arch/arm/configs/iq31244_defconfig
index ce1b1f20b763..0955577243de 100644
--- a/arch/arm/configs/iq31244_defconfig
+++ b/arch/arm/configs/iq31244_defconfig
@@ -94,7 +94,6 @@ CONFIG_ARCH_IOP32X=y
94CONFIG_ARCH_IQ31244=y 94CONFIG_ARCH_IQ31244=y
95# CONFIG_ARCH_IQ80331 is not set 95# CONFIG_ARCH_IQ80331 is not set
96# CONFIG_MACH_IQ80332 is not set 96# CONFIG_MACH_IQ80332 is not set
97# CONFIG_ARCH_EP80219 is not set
98 97
99# 98#
100# IOP3xx Chipset Features 99# IOP3xx Chipset Features
@@ -232,9 +231,9 @@ CONFIG_MTD_CFI_UTIL=y
232# 231#
233# CONFIG_MTD_COMPLEX_MAPPINGS is not set 232# CONFIG_MTD_COMPLEX_MAPPINGS is not set
234CONFIG_MTD_PHYSMAP=y 233CONFIG_MTD_PHYSMAP=y
235CONFIG_MTD_PHYSMAP_START=0xf0000000 234CONFIG_MTD_PHYSMAP_START=0x0
236CONFIG_MTD_PHYSMAP_LEN=0x00800000 235CONFIG_MTD_PHYSMAP_LEN=0x0
237CONFIG_MTD_PHYSMAP_BANKWIDTH=2 236CONFIG_MTD_PHYSMAP_BANKWIDTH=1
238# CONFIG_MTD_ARM_INTEGRATOR is not set 237# CONFIG_MTD_ARM_INTEGRATOR is not set
239# CONFIG_MTD_EDB7312 is not set 238# CONFIG_MTD_EDB7312 is not set
240 239
diff --git a/arch/arm/configs/iq80321_defconfig b/arch/arm/configs/iq80321_defconfig
index f00b0d2159dd..96be4c058546 100644
--- a/arch/arm/configs/iq80321_defconfig
+++ b/arch/arm/configs/iq80321_defconfig
@@ -93,7 +93,6 @@ CONFIG_ARCH_IQ80321=y
93# CONFIG_ARCH_IQ31244 is not set 93# CONFIG_ARCH_IQ31244 is not set
94# CONFIG_ARCH_IQ80331 is not set 94# CONFIG_ARCH_IQ80331 is not set
95# CONFIG_MACH_IQ80332 is not set 95# CONFIG_MACH_IQ80332 is not set
96# CONFIG_ARCH_EP80219 is not set
97 96
98# 97#
99# IOP3xx Chipset Features 98# IOP3xx Chipset Features
@@ -231,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y
231# 230#
232# CONFIG_MTD_COMPLEX_MAPPINGS is not set 231# CONFIG_MTD_COMPLEX_MAPPINGS is not set
233CONFIG_MTD_PHYSMAP=y 232CONFIG_MTD_PHYSMAP=y
234CONFIG_MTD_PHYSMAP_START=0xf0000000 233CONFIG_MTD_PHYSMAP_START=0x0
235CONFIG_MTD_PHYSMAP_LEN=0x00800000 234CONFIG_MTD_PHYSMAP_LEN=0x0
236CONFIG_MTD_PHYSMAP_BANKWIDTH=1 235CONFIG_MTD_PHYSMAP_BANKWIDTH=1
237# CONFIG_MTD_ARM_INTEGRATOR is not set 236# CONFIG_MTD_ARM_INTEGRATOR is not set
238# CONFIG_MTD_EDB7312 is not set 237# CONFIG_MTD_EDB7312 is not set
diff --git a/arch/arm/configs/iq80331_defconfig b/arch/arm/configs/iq80331_defconfig
index af3a87e469d5..874872ab6bdd 100644
--- a/arch/arm/configs/iq80331_defconfig
+++ b/arch/arm/configs/iq80331_defconfig
@@ -93,12 +93,6 @@ CONFIG_ARCH_IOP33X=y
93# CONFIG_ARCH_IQ31244 is not set 93# CONFIG_ARCH_IQ31244 is not set
94CONFIG_ARCH_IQ80331=y 94CONFIG_ARCH_IQ80331=y
95# CONFIG_MACH_IQ80332 is not set 95# CONFIG_MACH_IQ80332 is not set
96# CONFIG_ARCH_EP80219 is not set
97
98#
99# IOP3xx Chipset Features
100#
101CONFIG_IOP331_STEPD=y
102 96
103# 97#
104# Processor Type 98# Processor Type
@@ -236,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y
236# 230#
237# CONFIG_MTD_COMPLEX_MAPPINGS is not set 231# CONFIG_MTD_COMPLEX_MAPPINGS is not set
238CONFIG_MTD_PHYSMAP=y 232CONFIG_MTD_PHYSMAP=y
239CONFIG_MTD_PHYSMAP_START=0xc0000000 233CONFIG_MTD_PHYSMAP_START=0x0
240CONFIG_MTD_PHYSMAP_LEN=0x00800000 234CONFIG_MTD_PHYSMAP_LEN=0x0
241CONFIG_MTD_PHYSMAP_BANKWIDTH=1 235CONFIG_MTD_PHYSMAP_BANKWIDTH=1
242# CONFIG_MTD_ARM_INTEGRATOR is not set 236# CONFIG_MTD_ARM_INTEGRATOR is not set
243# CONFIG_MTD_EDB7312 is not set 237# CONFIG_MTD_EDB7312 is not set
diff --git a/arch/arm/configs/iq80332_defconfig b/arch/arm/configs/iq80332_defconfig
index 931c78755a30..a79895316535 100644
--- a/arch/arm/configs/iq80332_defconfig
+++ b/arch/arm/configs/iq80332_defconfig
@@ -93,12 +93,6 @@ CONFIG_ARCH_IOP33X=y
93# CONFIG_ARCH_IQ31244 is not set 93# CONFIG_ARCH_IQ31244 is not set
94# CONFIG_ARCH_IQ80331 is not set 94# CONFIG_ARCH_IQ80331 is not set
95CONFIG_MACH_IQ80332=y 95CONFIG_MACH_IQ80332=y
96# CONFIG_ARCH_EP80219 is not set
97
98#
99# IOP3xx Chipset Features
100#
101# CONFIG_IOP331_STEPD is not set
102 96
103# 97#
104# Processor Type 98# Processor Type
@@ -236,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y
236# 230#
237# CONFIG_MTD_COMPLEX_MAPPINGS is not set 231# CONFIG_MTD_COMPLEX_MAPPINGS is not set
238CONFIG_MTD_PHYSMAP=y 232CONFIG_MTD_PHYSMAP=y
239CONFIG_MTD_PHYSMAP_START=0xc0000000 233CONFIG_MTD_PHYSMAP_START=0x0
240CONFIG_MTD_PHYSMAP_LEN=0x00800000 234CONFIG_MTD_PHYSMAP_LEN=0x0
241CONFIG_MTD_PHYSMAP_BANKWIDTH=1 235CONFIG_MTD_PHYSMAP_BANKWIDTH=1
242# CONFIG_MTD_ARM_INTEGRATOR is not set 236# CONFIG_MTD_ARM_INTEGRATOR is not set
243# CONFIG_MTD_EDB7312 is not set 237# CONFIG_MTD_EDB7312 is not set
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index 21e3e8c8c2ad..ff8a77a8866e 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -16,13 +16,6 @@ config ARCH_IQ31244
16 Say Y here if you want to run your kernel on the Intel IQ31244 16 Say Y here if you want to run your kernel on the Intel IQ31244
17 evaluation kit for the IOP321 chipset. 17 evaluation kit for the IOP321 chipset.
18 18
19config ARCH_EP80219
20 bool "Enable support for EP80219"
21 select ARCH_IQ31244
22 help
23 Say Y here if you want to run your kernel on the Intel EP80219
24 evaluation kit for the Intel 80219 chipset (a IOP321 variant).
25
26endmenu 19endmenu
27 20
28endif 21endif
diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile
index ef561db20c9b..af1747ae392d 100644
--- a/arch/arm/mach-iop32x/Makefile
+++ b/arch/arm/mach-iop32x/Makefile
@@ -2,10 +2,10 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := common.o setup.o irq.o 5obj-y := irq.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o 10obj-$(CONFIG_ARCH_IQ80321) += iq80321.o
11obj-$(CONFIG_ARCH_IQ31244) += iq31244-mm.o iq31244-pci.o 11obj-$(CONFIG_ARCH_IQ31244) += iq31244.o
diff --git a/arch/arm/mach-iop32x/common.c b/arch/arm/mach-iop32x/common.c
deleted file mode 100644
index 9a17a081327d..000000000000
--- a/arch/arm/mach-iop32x/common.c
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/common.c
3 *
4 * Common routines shared across all IOP3xx implementations
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2003 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/delay.h>
16#include <asm/hardware.h>
17#include <asm/hardware/iop3xx.h>
18
19#ifdef CONFIG_ARCH_EP80219
20#include <linux/kernel.h>
21/*
22 * Default power-off for EP80219
23 */
24
25static inline void ep80219_send_to_pic(__u8 c) {
26}
27
28void ep80219_power_off(void)
29{
30 /*
31 * This function will send a SHUTDOWN_COMPLETE message to the PIC controller
32 * over I2C. We are not using the i2c subsystem since we are going to power
33 * off and it may be removed
34 */
35
36 /* Send the Address byte w/ the start condition */
37 *IOP3XX_IDBR1 = 0x60;
38 *IOP3XX_ICR1 = 0xE9;
39 mdelay(1);
40
41 /* Send the START_MSG byte w/ no start or stop condition */
42 *IOP3XX_IDBR1 = 0x0F;
43 *IOP3XX_ICR1 = 0xE8;
44 mdelay(1);
45
46 /* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or stop condition */
47 *IOP3XX_IDBR1 = 0x03;
48 *IOP3XX_ICR1 = 0xE8;
49 mdelay(1);
50
51 /* Send an ignored byte w/ stop condition */
52 *IOP3XX_IDBR1 = 0x00;
53 *IOP3XX_ICR1 = 0xEA;
54
55 while (1) ;
56}
57
58#include <linux/init.h>
59#include <linux/pm.h>
60
61static int __init ep80219_init(void)
62{
63 pm_power_off = ep80219_power_off;
64 return 0;
65}
66arch_initcall(ep80219_init);
67#endif
diff --git a/arch/arm/mach-iop32x/iq31244-mm.c b/arch/arm/mach-iop32x/iq31244-mm.c
deleted file mode 100644
index fba22d5d908f..000000000000
--- a/arch/arm/mach-iop32x/iq31244-mm.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop32x/iq31244-mm.c
3 *
4 * Low level memory initialization for iq80321 platform
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/page.h>
22
23#include <asm/mach/map.h>
24#include <asm/hardware/iop3xx.h>
25
26
27/*
28 * IQ80321 specific IO mappings
29 *
30 * We use RedBoot's setup for the onboard devices.
31 */
32static struct map_desc iq31244_io_desc[] __initdata = {
33 { /* on-board devices */
34 .virtual = IQ31244_UART,
35 .pfn = __phys_to_pfn(IQ31244_UART),
36 .length = 0x00100000,
37 .type = MT_DEVICE
38 }
39};
40
41void __init iq31244_map_io(void)
42{
43 iop3xx_map_io();
44
45 iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
46}
diff --git a/arch/arm/mach-iop32x/iq31244-pci.c b/arch/arm/mach-iop32x/iq31244-pci.c
deleted file mode 100644
index 605b79553747..000000000000
--- a/arch/arm/mach-iop32x/iq31244-pci.c
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/iq31244-pci.c
3 *
4 * PCI support for the Intel IQ31244 reference board
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/string.h>
18#include <linux/slab.h>
19
20#include <asm/hardware.h>
21#include <asm/irq.h>
22#include <asm/mach/pci.h>
23#include <asm/mach-types.h>
24
25/*
26 * The following macro is used to lookup irqs in a standard table
27 * format for those systems that do not already have PCI
28 * interrupts properly routed. We assume 1 <= pin <= 4
29 */
30#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
31({ int _ctl_ = -1; \
32 unsigned int _idsel = idsel - minid; \
33 if (_idsel <= maxid) \
34 _ctl_ = pci_irq_table[_idsel][pin-1]; \
35 _ctl_; })
36
37#define INTA IRQ_IQ31244_INTA
38#define INTB IRQ_IQ31244_INTB
39#define INTC IRQ_IQ31244_INTC
40#define INTD IRQ_IQ31244_INTD
41
42#define INTE IRQ_IQ31244_I82546
43
44static inline int __init
45iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
46{
47 static int pci_irq_table[][4] = {
48 /*
49 * PCI IDSEL/INTPIN->INTLINE
50 * A B C D
51 */
52#ifdef CONFIG_ARCH_EP80219
53 {INTB, INTB, INTB, INTB}, /* CFlash */
54 {INTE, INTE, INTE, INTE}, /* 82551 Pro 100 */
55 {INTD, INTD, INTD, INTD}, /* PCI-X Slot */
56 {INTC, INTC, INTC, INTC}, /* SATA */
57#else
58 {INTB, INTB, INTB, INTB}, /* CFlash */
59 {INTC, INTC, INTC, INTC}, /* SATA */
60 {INTD, INTD, INTD, INTD}, /* PCI-X Slot */
61 {INTE, INTE, INTE, INTE}, /* 82546 GigE */
62#endif // CONFIG_ARCH_EP80219
63 };
64
65 BUG_ON(pin < 1 || pin > 4);
66
67 return PCI_IRQ_TABLE_LOOKUP(0, 7);
68}
69
70static struct hw_pci iq31244_pci __initdata = {
71 .swizzle = pci_std_swizzle,
72 .nr_controllers = 1,
73 .setup = iop3xx_pci_setup,
74 .scan = iop3xx_pci_scan_bus,
75 .preinit = iop3xx_pci_preinit,
76 .map_irq = iq31244_map_irq
77};
78
79static int __init iq31244_pci_init(void)
80{
81 if (machine_is_iq31244())
82 pci_common_init(&iq31244_pci);
83 return 0;
84}
85
86subsys_initcall(iq31244_pci_init);
87
88
89
90
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
new file mode 100644
index 000000000000..88b77d32b0ac
--- /dev/null
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -0,0 +1,293 @@
1/*
2 * arch/arm/mach-iop32x/iq31244.c
3 *
4 * Board support code for the Intel EP80219 and IQ31244 platforms.
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright 2003 (c) MontaVista, Software, Inc.
9 * Copyright (C) 2004 Intel Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/pm.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/serial_core.h>
26#include <linux/serial_8250.h>
27#include <linux/mtd/physmap.h>
28#include <linux/platform_device.h>
29#include <asm/hardware.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34#include <asm/mach/pci.h>
35#include <asm/mach/time.h>
36#include <asm/mach-types.h>
37#include <asm/page.h>
38#include <asm/pgtable.h>
39
40
41/*
42 * The EP80219 and IQ31244 use the same machine ID. To find out
43 * which of the two we're running on, we look at the processor ID.
44 */
45static int is_80219(void)
46{
47 extern int processor_id;
48 return !!((processor_id & 0xffffffe0) == 0x69052e20);
49}
50
51
52/*
53 * EP80219/IQ31244 timer tick configuration.
54 */
55static void __init iq31244_timer_init(void)
56{
57 if (is_80219()) {
58 /* 33.333 MHz crystal. */
59 iop3xx_init_time(200000000);
60 } else {
61 /* 33.000 MHz crystal. */
62 iop3xx_init_time(198000000);
63 }
64}
65
66static struct sys_timer iq31244_timer = {
67 .init = iq31244_timer_init,
68 .offset = iop3xx_gettimeoffset,
69};
70
71
72/*
73 * IQ31244 I/O.
74 */
75static struct map_desc iq31244_io_desc[] __initdata = {
76 { /* on-board devices */
77 .virtual = IQ31244_UART,
78 .pfn = __phys_to_pfn(IQ31244_UART),
79 .length = 0x00100000,
80 .type = MT_DEVICE,
81 },
82};
83
84void __init iq31244_map_io(void)
85{
86 iop3xx_map_io();
87 iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
88}
89
90
91/*
92 * EP80219/IQ31244 PCI.
93 */
94static inline int __init
95ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
96{
97 int irq;
98
99 if (slot == 0) {
100 /* CFlash */
101 irq = IRQ_IOP321_XINT1;
102 } else if (slot == 1) {
103 /* 82551 Pro 100 */
104 irq = IRQ_IOP321_XINT0;
105 } else if (slot == 2) {
106 /* PCI-X Slot */
107 irq = IRQ_IOP321_XINT3;
108 } else if (slot == 3) {
109 /* SATA */
110 irq = IRQ_IOP321_XINT2;
111 } else {
112 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
113 "device PCI:%d:%d:%d\n", dev->bus->number,
114 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
115 irq = -1;
116 }
117
118 return irq;
119}
120
121static struct hw_pci ep80219_pci __initdata = {
122 .swizzle = pci_std_swizzle,
123 .nr_controllers = 1,
124 .setup = iop3xx_pci_setup,
125 .preinit = iop3xx_pci_preinit,
126 .scan = iop3xx_pci_scan_bus,
127 .map_irq = ep80219_pci_map_irq,
128};
129
130static inline int __init
131iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
132{
133 int irq;
134
135 if (slot == 0) {
136 /* CFlash */
137 irq = IRQ_IOP321_XINT1;
138 } else if (slot == 1) {
139 /* SATA */
140 irq = IRQ_IOP321_XINT2;
141 } else if (slot == 2) {
142 /* PCI-X Slot */
143 irq = IRQ_IOP321_XINT3;
144 } else if (slot == 3) {
145 /* 82546 GigE */
146 irq = IRQ_IOP321_XINT0;
147 } else {
148 printk(KERN_ERR "iq31244_pci_map_irq() called for unknown "
149 "device PCI:%d:%d:%d\n", dev->bus->number,
150 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
151 irq = -1;
152 }
153
154 return irq;
155}
156
157static struct hw_pci iq31244_pci __initdata = {
158 .swizzle = pci_std_swizzle,
159 .nr_controllers = 1,
160 .setup = iop3xx_pci_setup,
161 .preinit = iop3xx_pci_preinit,
162 .scan = iop3xx_pci_scan_bus,
163 .map_irq = iq31244_pci_map_irq,
164};
165
166static int __init iq31244_pci_init(void)
167{
168 if (machine_is_iq31244()) {
169 if (is_80219()) {
170 pci_common_init(&ep80219_pci);
171 } else {
172 pci_common_init(&iq31244_pci);
173 }
174 }
175
176 return 0;
177}
178
179subsys_initcall(iq31244_pci_init);
180
181
182/*
183 * IQ31244 machine initialisation.
184 */
185static struct physmap_flash_data iq31244_flash_data = {
186 .width = 2,
187};
188
189static struct resource iq31244_flash_resource = {
190 .start = 0xf0000000,
191 .end = 0xf07fffff,
192 .flags = IORESOURCE_MEM,
193};
194
195static struct platform_device iq31244_flash_device = {
196 .name = "physmap-flash",
197 .id = 0,
198 .dev = {
199 .platform_data = &iq31244_flash_data,
200 },
201 .num_resources = 1,
202 .resource = &iq31244_flash_resource,
203};
204
205static struct plat_serial8250_port iq31244_serial_port[] = {
206 {
207 .mapbase = IQ31244_UART,
208 .membase = (char *)IQ31244_UART,
209 .irq = IRQ_IOP321_XINT1,
210 .flags = UPF_SKIP_TEST,
211 .iotype = UPIO_MEM,
212 .regshift = 0,
213 .uartclk = 1843200,
214 },
215 { },
216};
217
218static struct resource iq31244_uart_resource = {
219 .start = IQ31244_UART,
220 .end = IQ31244_UART + 7,
221 .flags = IORESOURCE_MEM,
222};
223
224static struct platform_device iq31244_serial_device = {
225 .name = "serial8250",
226 .id = PLAT8250_DEV_PLATFORM,
227 .dev = {
228 .platform_data = iq31244_serial_port,
229 },
230 .num_resources = 1,
231 .resource = &iq31244_uart_resource,
232};
233
234/*
235 * This function will send a SHUTDOWN_COMPLETE message to the PIC
236 * controller over I2C. We are not using the i2c subsystem since
237 * we are going to power off and it may be removed
238 */
239void ep80219_power_off(void)
240{
241 /*
242 * Send the Address byte w/ the start condition
243 */
244 *IOP3XX_IDBR1 = 0x60;
245 *IOP3XX_ICR1 = 0xE9;
246 mdelay(1);
247
248 /*
249 * Send the START_MSG byte w/ no start or stop condition
250 */
251 *IOP3XX_IDBR1 = 0x0F;
252 *IOP3XX_ICR1 = 0xE8;
253 mdelay(1);
254
255 /*
256 * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
257 * stop condition
258 */
259 *IOP3XX_IDBR1 = 0x03;
260 *IOP3XX_ICR1 = 0xE8;
261 mdelay(1);
262
263 /*
264 * Send an ignored byte w/ stop condition
265 */
266 *IOP3XX_IDBR1 = 0x00;
267 *IOP3XX_ICR1 = 0xEA;
268
269 while (1)
270 ;
271}
272
273static void __init iq31244_init_machine(void)
274{
275 platform_device_register(&iop3xx_i2c0_device);
276 platform_device_register(&iop3xx_i2c1_device);
277 platform_device_register(&iq31244_flash_device);
278 platform_device_register(&iq31244_serial_device);
279
280 if (is_80219())
281 pm_power_off = ep80219_power_off;
282}
283
284MACHINE_START(IQ31244, "Intel IQ31244")
285 /* Maintainer: Intel Corp. */
286 .phys_io = IQ31244_UART,
287 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
288 .boot_params = 0xa0000100,
289 .map_io = iq31244_map_io,
290 .init_irq = iop321_init_irq,
291 .timer = &iq31244_timer,
292 .init_machine = iq31244_init_machine,
293MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq80321-mm.c b/arch/arm/mach-iop32x/iq80321-mm.c
deleted file mode 100644
index b6a3079ad29e..000000000000
--- a/arch/arm/mach-iop32x/iq80321-mm.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop32x/iq80321-mm.c
3 *
4 * Low level memory initialization for iq80321 platform
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/page.h>
22
23#include <asm/mach/map.h>
24#include <asm/hardware/iop3xx.h>
25
26
27/*
28 * IQ80321 specific IO mappings
29 *
30 * We use RedBoot's setup for the onboard devices.
31 */
32static struct map_desc iq80321_io_desc[] __initdata = {
33 { /* on-board devices */
34 .virtual = IQ80321_UART,
35 .pfn = __phys_to_pfn(IQ80321_UART),
36 .length = 0x00100000,
37 .type = MT_DEVICE
38 }
39};
40
41void __init iq80321_map_io(void)
42{
43 iop3xx_map_io();
44
45 iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
46}
diff --git a/arch/arm/mach-iop32x/iq80321-pci.c b/arch/arm/mach-iop32x/iq80321-pci.c
deleted file mode 100644
index cedc37b968b7..000000000000
--- a/arch/arm/mach-iop32x/iq80321-pci.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/iq80321-pci.c
3 *
4 * PCI support for the Intel IQ80321 reference board
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/string.h>
18#include <linux/slab.h>
19
20#include <asm/hardware.h>
21#include <asm/irq.h>
22#include <asm/mach/pci.h>
23#include <asm/mach-types.h>
24
25/*
26 * The following macro is used to lookup irqs in a standard table
27 * format for those systems that do not already have PCI
28 * interrupts properly routed. We assume 1 <= pin <= 4
29 */
30#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
31({ int _ctl_ = -1; \
32 unsigned int _idsel = idsel - minid; \
33 if (_idsel <= maxid) \
34 _ctl_ = pci_irq_table[_idsel][pin-1]; \
35 _ctl_; })
36
37#define INTA IRQ_IQ80321_INTA
38#define INTB IRQ_IQ80321_INTB
39#define INTC IRQ_IQ80321_INTC
40#define INTD IRQ_IQ80321_INTD
41
42#define INTE IRQ_IQ80321_I82544
43
44static inline int __init
45iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
46{
47 static int pci_irq_table[][4] = {
48 /*
49 * PCI IDSEL/INTPIN->INTLINE
50 * A B C D
51 */
52 {INTE, INTE, INTE, INTE}, /* Gig-E */
53 {-1, -1, -1, -1}, /* Unused */
54 {INTC, INTD, INTA, INTB}, /* PCI-X Slot */
55 {-1, -1, -1, -1},
56 };
57
58 BUG_ON(pin < 1 || pin > 4);
59
60// return PCI_IRQ_TABLE_LOOKUP(4, 7);
61 return pci_irq_table[idsel%4][pin-1];
62}
63
64static struct hw_pci iq80321_pci __initdata = {
65 .swizzle = pci_std_swizzle,
66 .nr_controllers = 1,
67 .setup = iop3xx_pci_setup,
68 .scan = iop3xx_pci_scan_bus,
69 .preinit = iop3xx_pci_preinit,
70 .map_irq = iq80321_map_irq
71};
72
73static int __init iq80321_pci_init(void)
74{
75 if (machine_is_iq80321())
76 pci_common_init(&iq80321_pci);
77 return 0;
78}
79
80subsys_initcall(iq80321_pci_init);
81
82
83
84
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
new file mode 100644
index 000000000000..3c9b86271759
--- /dev/null
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -0,0 +1,193 @@
1/*
2 * arch/arm/mach-iop32x/iq80321.c
3 *
4 * Board support code for the Intel IQ80321 platform.
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/string.h>
21#include <linux/slab.h>
22#include <linux/serial_core.h>
23#include <linux/serial_8250.h>
24#include <linux/mtd/physmap.h>
25#include <linux/platform_device.h>
26#include <asm/hardware.h>
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/pci.h>
32#include <asm/mach/time.h>
33#include <asm/mach-types.h>
34#include <asm/page.h>
35#include <asm/pgtable.h>
36
37/*
38 * IQ80321 timer tick configuration.
39 */
40static void __init iq80321_timer_init(void)
41{
42 /* 33.333 MHz crystal. */
43 iop3xx_init_time(200000000);
44}
45
46static struct sys_timer iq80321_timer = {
47 .init = iq80321_timer_init,
48 .offset = iop3xx_gettimeoffset,
49};
50
51
52/*
53 * IQ80321 I/O.
54 */
55static struct map_desc iq80321_io_desc[] __initdata = {
56 { /* on-board devices */
57 .virtual = IQ80321_UART,
58 .pfn = __phys_to_pfn(IQ80321_UART),
59 .length = 0x00100000,
60 .type = MT_DEVICE,
61 },
62};
63
64void __init iq80321_map_io(void)
65{
66 iop3xx_map_io();
67 iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
68}
69
70
71/*
72 * IQ80321 PCI.
73 */
74static inline int __init
75iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
76{
77 int irq;
78
79 if ((slot == 2 || slot == 6) && pin == 1) {
80 /* PCI-X Slot INTA */
81 irq = IRQ_IOP321_XINT2;
82 } else if ((slot == 2 || slot == 6) && pin == 2) {
83 /* PCI-X Slot INTA */
84 irq = IRQ_IOP321_XINT3;
85 } else if ((slot == 2 || slot == 6) && pin == 3) {
86 /* PCI-X Slot INTA */
87 irq = IRQ_IOP321_XINT0;
88 } else if ((slot == 2 || slot == 6) && pin == 4) {
89 /* PCI-X Slot INTA */
90 irq = IRQ_IOP321_XINT1;
91 } else if (slot == 4 || slot == 8) {
92 /* Gig-E */
93 irq = IRQ_IOP321_XINT0;
94 } else {
95 printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
96 "device PCI:%d:%d:%d\n", dev->bus->number,
97 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
98 irq = -1;
99 }
100
101 return irq;
102}
103
104static struct hw_pci iq80321_pci __initdata = {
105 .swizzle = pci_std_swizzle,
106 .nr_controllers = 1,
107 .setup = iop3xx_pci_setup,
108 .preinit = iop3xx_pci_preinit,
109 .scan = iop3xx_pci_scan_bus,
110 .map_irq = iq80321_pci_map_irq,
111};
112
113static int __init iq80321_pci_init(void)
114{
115 if (machine_is_iq80321())
116 pci_common_init(&iq80321_pci);
117
118 return 0;
119}
120
121subsys_initcall(iq80321_pci_init);
122
123
124/*
125 * IQ80321 machine initialisation.
126 */
127static struct physmap_flash_data iq80321_flash_data = {
128 .width = 1,
129};
130
131static struct resource iq80321_flash_resource = {
132 .start = 0xf0000000,
133 .end = 0xf07fffff,
134 .flags = IORESOURCE_MEM,
135};
136
137static struct platform_device iq80321_flash_device = {
138 .name = "physmap-flash",
139 .id = 0,
140 .dev = {
141 .platform_data = &iq80321_flash_data,
142 },
143 .num_resources = 1,
144 .resource = &iq80321_flash_resource,
145};
146
147static struct plat_serial8250_port iq80321_serial_port[] = {
148 {
149 .mapbase = IQ80321_UART,
150 .membase = (char *)IQ80321_UART,
151 .irq = IRQ_IOP321_XINT1,
152 .flags = UPF_SKIP_TEST,
153 .iotype = UPIO_MEM,
154 .regshift = 0,
155 .uartclk = 1843200,
156 },
157 { },
158};
159
160static struct resource iq80321_uart_resource = {
161 .start = IQ80321_UART,
162 .end = IQ80321_UART + 7,
163 .flags = IORESOURCE_MEM,
164};
165
166static struct platform_device iq80321_serial_device = {
167 .name = "serial8250",
168 .id = PLAT8250_DEV_PLATFORM,
169 .dev = {
170 .platform_data = iq80321_serial_port,
171 },
172 .num_resources = 1,
173 .resource = &iq80321_uart_resource,
174};
175
176static void __init iq80321_init_machine(void)
177{
178 platform_device_register(&iop3xx_i2c0_device);
179 platform_device_register(&iop3xx_i2c1_device);
180 platform_device_register(&iq80321_flash_device);
181 platform_device_register(&iq80321_serial_device);
182}
183
184MACHINE_START(IQ80321, "Intel IQ80321")
185 /* Maintainer: Intel Corp. */
186 .phys_io = IQ80321_UART,
187 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
188 .boot_params = 0xa0000100,
189 .map_io = iq80321_map_io,
190 .init_irq = iop321_init_irq,
191 .timer = &iq80321_timer,
192 .init_machine = iq80321_init_machine,
193MACHINE_END
diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c
deleted file mode 100644
index 68de247a4cca..000000000000
--- a/arch/arm/mach-iop32x/setup.c
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop32x/setup.c
3 *
4 * Author: Nicolas Pitre <nico@cam.org>
5 * Copyright (C) 2001 MontaVista Software, Inc.
6 * Copyright (C) 2004 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#include <linux/mm.h>
14#include <linux/init.h>
15#include <linux/major.h>
16#include <linux/fs.h>
17#include <linux/platform_device.h>
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21
22#include <asm/io.h>
23#include <asm/pgtable.h>
24#include <asm/page.h>
25#include <asm/mach/map.h>
26#include <asm/setup.h>
27#include <asm/system.h>
28#include <asm/memory.h>
29#include <asm/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/hardware/iop3xx.h>
34
35#define IOP321_UART_XTAL 1843200
36
37#ifdef CONFIG_ARCH_IQ80321
38#define UARTBASE IQ80321_UART
39#define IRQ_UART IRQ_IQ80321_UART
40#endif
41
42#ifdef CONFIG_ARCH_IQ31244
43#define UARTBASE IQ31244_UART
44#define IRQ_UART IRQ_IQ31244_UART
45#endif
46
47static struct uart_port iop321_serial_ports[] = {
48 {
49 .membase = (char*)(UARTBASE),
50 .mapbase = (UARTBASE),
51 .irq = IRQ_UART,
52 .flags = UPF_SKIP_TEST,
53 .iotype = UPIO_MEM,
54 .regshift = 0,
55 .uartclk = IOP321_UART_XTAL,
56 .line = 0,
57 .type = PORT_16550A,
58 .fifosize = 16
59 }
60};
61
62void __init iop32x_init(void)
63{
64 platform_device_register(&iop3xx_i2c0_device);
65 platform_device_register(&iop3xx_i2c1_device);
66 early_serial_setup(&iop321_serial_ports[0]);
67}
68
69#ifdef CONFIG_ARCH_IQ80321
70extern void iq80321_map_io(void);
71#endif
72
73#ifdef CONFIG_ARCH_IQ31244
74extern void iq31244_map_io(void);
75#endif
76
77static void __init iop3xx_timer_init(void)
78{
79 iop3xx_init_time(IOP321_TICK_RATE);
80}
81
82struct sys_timer iop321_timer = {
83 .init = iop3xx_timer_init,
84 .offset = iop3xx_gettimeoffset,
85};
86
87#if defined(CONFIG_ARCH_IQ80321)
88MACHINE_START(IQ80321, "Intel IQ80321")
89 /* Maintainer: Intel Corporation */
90 .phys_io = IQ80321_UART,
91 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
92 .map_io = iq80321_map_io,
93 .init_irq = iop321_init_irq,
94 .timer = &iop321_timer,
95 .boot_params = 0xa0000100,
96 .init_machine = iop32x_init,
97MACHINE_END
98#elif defined(CONFIG_ARCH_IQ31244)
99MACHINE_START(IQ31244, "Intel IQ31244")
100 /* Maintainer: Intel Corp. */
101 .phys_io = IQ31244_UART,
102 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
103 .map_io = iq31244_map_io,
104 .init_irq = iop321_init_irq,
105 .timer = &iop321_timer,
106 .boot_params = 0xa0000100,
107 .init_machine = iop32x_init,
108MACHINE_END
109#else
110#error No machine descriptor defined for this IOP3XX implementation
111#endif
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig
index 410df546e954..9aa016bb18f9 100644
--- a/arch/arm/mach-iop33x/Kconfig
+++ b/arch/arm/mach-iop33x/Kconfig
@@ -16,12 +16,6 @@ config MACH_IQ80332
16 Say Y here if you want to run your kernel on the Intel IQ80332 16 Say Y here if you want to run your kernel on the Intel IQ80332
17 evaluation kit for the IOP332 chipset. 17 evaluation kit for the IOP332 chipset.
18 18
19config IOP331_STEPD
20 bool "Chip stepping D of the IOP80331 processor or IOP80333"
21 help
22 Say Y here if you have StepD of the IOP80331 or IOP8033
23 based platforms.
24
25endmenu 19endmenu
26 20
27endif 21endif
diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile
index f825cee57d9f..90081d8c9d16 100644
--- a/arch/arm/mach-iop33x/Makefile
+++ b/arch/arm/mach-iop33x/Makefile
@@ -2,10 +2,10 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := setup.o irq.o 5obj-y := irq.o uart.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_ARCH_IQ80331) += iq80331-pci.o 10obj-$(CONFIG_ARCH_IQ80331) += iq80331.o
11obj-$(CONFIG_MACH_IQ80332) += iq80332-pci.o 11obj-$(CONFIG_MACH_IQ80332) += iq80332.o
diff --git a/arch/arm/mach-iop33x/iq80331-pci.c b/arch/arm/mach-iop33x/iq80331-pci.c
deleted file mode 100644
index 8b0bed5e2f91..000000000000
--- a/arch/arm/mach-iop33x/iq80331-pci.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * arch/arm/mach-iop33x/iq80331-pci.c
3 *
4 * PCI support for the Intel IQ80331 reference board
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/string.h>
17#include <linux/slab.h>
18
19#include <asm/hardware.h>
20#include <asm/irq.h>
21#include <asm/mach/pci.h>
22#include <asm/mach-types.h>
23
24/*
25 * The following macro is used to lookup irqs in a standard table
26 * format for those systems that do not already have PCI
27 * interrupts properly routed. We assume 1 <= pin <= 4
28 */
29#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
30({ int _ctl_ = -1; \
31 unsigned int _idsel = idsel - minid; \
32 if (_idsel <= maxid) \
33 _ctl_ = pci_irq_table[_idsel][pin-1]; \
34 _ctl_; })
35
36#define INTA IRQ_IQ80331_INTA
37#define INTB IRQ_IQ80331_INTB
38#define INTC IRQ_IQ80331_INTC
39#define INTD IRQ_IQ80331_INTD
40
41//#define INTE IRQ_IQ80331_I82544
42
43static inline int __init
44iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
45{
46 static int pci_irq_table[][4] = {
47 /*
48 * PCI IDSEL/INTPIN->INTLINE
49 * A B C D
50 */
51 {INTB, INTC, INTD, INTA}, /* PCI-X Slot */
52 {INTC, INTC, INTC, INTC}, /* GigE */
53 };
54
55 BUG_ON(pin < 1 || pin > 4);
56
57 return PCI_IRQ_TABLE_LOOKUP(1, 7);
58}
59
60static struct hw_pci iq80331_pci __initdata = {
61 .swizzle = pci_std_swizzle,
62 .nr_controllers = 1,
63 .setup = iop3xx_pci_setup,
64 .scan = iop3xx_pci_scan_bus,
65 .preinit = iop3xx_pci_preinit,
66 .map_irq = iq80331_map_irq
67};
68
69static int __init iq80331_pci_init(void)
70{
71 if (machine_is_iq80331())
72 pci_common_init(&iq80331_pci);
73 return 0;
74}
75
76subsys_initcall(iq80331_pci_init);
77
78
79
80
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
new file mode 100644
index 000000000000..6b8475da3df6
--- /dev/null
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -0,0 +1,148 @@
1/*
2 * arch/arm/mach-iop33x/iq80331.c
3 *
4 * Board support code for the Intel IQ80331 platform.
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/mm.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/string.h>
20#include <linux/slab.h>
21#include <linux/serial_core.h>
22#include <linux/serial_8250.h>
23#include <linux/mtd/physmap.h>
24#include <linux/platform_device.h>
25#include <asm/hardware.h>
26#include <asm/io.h>
27#include <asm/irq.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/pci.h>
31#include <asm/mach/time.h>
32#include <asm/mach-types.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35
36/*
37 * IQ80331 timer tick configuration.
38 */
39static void __init iq80331_timer_init(void)
40{
41 /* D-Step parts run at a higher internal bus frequency */
42 if (*IOP3XX_ATURID >= 0xa)
43 iop3xx_init_time(333000000);
44 else
45 iop3xx_init_time(266000000);
46}
47
48static struct sys_timer iq80331_timer = {
49 .init = iq80331_timer_init,
50 .offset = iop3xx_gettimeoffset,
51};
52
53
54/*
55 * IQ80331 PCI.
56 */
57static inline int __init
58iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
59{
60 int irq;
61
62 if (slot == 1 && pin == 1) {
63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP331_XINT1;
65 } else if (slot == 1 && pin == 2) {
66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP331_XINT2;
68 } else if (slot == 1 && pin == 3) {
69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP331_XINT3;
71 } else if (slot == 1 && pin == 4) {
72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP331_XINT0;
74 } else if (slot == 2) {
75 /* GigE */
76 irq = IRQ_IOP331_XINT2;
77 } else {
78 printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number,
80 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
81 irq = -1;
82 }
83
84 return irq;
85}
86
87static struct hw_pci iq80331_pci __initdata = {
88 .swizzle = pci_std_swizzle,
89 .nr_controllers = 1,
90 .setup = iop3xx_pci_setup,
91 .preinit = iop3xx_pci_preinit,
92 .scan = iop3xx_pci_scan_bus,
93 .map_irq = iq80331_pci_map_irq,
94};
95
96static int __init iq80331_pci_init(void)
97{
98 if (machine_is_iq80331())
99 pci_common_init(&iq80331_pci);
100
101 return 0;
102}
103
104subsys_initcall(iq80331_pci_init);
105
106
107/*
108 * IQ80331 machine initialisation.
109 */
110static struct physmap_flash_data iq80331_flash_data = {
111 .width = 1,
112};
113
114static struct resource iq80331_flash_resource = {
115 .start = 0xc0000000,
116 .end = 0xc07fffff,
117 .flags = IORESOURCE_MEM,
118};
119
120static struct platform_device iq80331_flash_device = {
121 .name = "physmap-flash",
122 .id = 0,
123 .dev = {
124 .platform_data = &iq80331_flash_data,
125 },
126 .num_resources = 1,
127 .resource = &iq80331_flash_resource,
128};
129
130static void __init iq80331_init_machine(void)
131{
132 platform_device_register(&iop3xx_i2c0_device);
133 platform_device_register(&iop3xx_i2c1_device);
134 platform_device_register(&iop33x_uart0_device);
135 platform_device_register(&iop33x_uart1_device);
136 platform_device_register(&iq80331_flash_device);
137}
138
139MACHINE_START(IQ80331, "Intel IQ80331")
140 /* Maintainer: Intel Corp. */
141 .phys_io = 0xfefff000,
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io,
145 .init_irq = iop331_init_irq,
146 .timer = &iq80331_timer,
147 .init_machine = iq80331_init_machine,
148MACHINE_END
diff --git a/arch/arm/mach-iop33x/iq80332-pci.c b/arch/arm/mach-iop33x/iq80332-pci.c
deleted file mode 100644
index 0de8aa748dd8..000000000000
--- a/arch/arm/mach-iop33x/iq80332-pci.c
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * arch/arm/mach-iop33x/iq80332-pci.c
3 *
4 * PCI support for the Intel IQ80332 reference board
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/string.h>
17#include <linux/slab.h>
18
19#include <asm/hardware.h>
20#include <asm/irq.h>
21#include <asm/mach/pci.h>
22#include <asm/mach-types.h>
23
24/*
25 * The following macro is used to lookup irqs in a standard table
26 * format for those systems that do not already have PCI
27 * interrupts properly routed. We assume 1 <= pin <= 4
28 */
29#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
30({ int _ctl_ = -1; \
31 unsigned int _idsel = idsel - minid; \
32 if (_idsel <= maxid) \
33 _ctl_ = pci_irq_table[_idsel][pin-1]; \
34 _ctl_; })
35
36#define INTA IRQ_IQ80332_INTA
37#define INTB IRQ_IQ80332_INTB
38#define INTC IRQ_IQ80332_INTC
39#define INTD IRQ_IQ80332_INTD
40
41//#define INTE IRQ_IQ80332_I82544
42
43static inline int __init
44iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
45{
46 static int pci_irq_table[][8] = {
47 /*
48 * PCI IDSEL/INTPIN->INTLINE
49 * A B C D
50 */
51 {-1, -1, -1, -1},
52 {-1, -1, -1, -1},
53 {-1, -1, -1, -1},
54 {INTA, INTB, INTC, INTD}, /* PCI-X Slot */
55 {-1, -1, -1, -1},
56 {INTC, INTC, INTC, INTC}, /* GigE */
57 {-1, -1, -1, -1},
58 {-1, -1, -1, -1},
59 };
60
61 BUG_ON(pin < 1 || pin > 4);
62
63 return PCI_IRQ_TABLE_LOOKUP(1, 7);
64}
65
66static struct hw_pci iq80332_pci __initdata = {
67 .swizzle = pci_std_swizzle,
68 .nr_controllers = 1,
69 .setup = iop3xx_pci_setup,
70 .scan = iop3xx_pci_scan_bus,
71 .preinit = iop3xx_pci_preinit,
72 .map_irq = iq80332_map_irq
73};
74
75static int __init iq80332_pci_init(void)
76{
77 if (machine_is_iq80332())
78 pci_common_init(&iq80332_pci);
79 return 0;
80}
81
82subsys_initcall(iq80332_pci_init);
83
84
85
86
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
new file mode 100644
index 000000000000..150f3fd5de0b
--- /dev/null
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -0,0 +1,148 @@
1/*
2 * arch/arm/mach-iop33x/iq80332.c
3 *
4 * Board support code for the Intel IQ80332 platform.
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/mm.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/string.h>
20#include <linux/slab.h>
21#include <linux/serial_core.h>
22#include <linux/serial_8250.h>
23#include <linux/mtd/physmap.h>
24#include <linux/platform_device.h>
25#include <asm/hardware.h>
26#include <asm/io.h>
27#include <asm/irq.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/pci.h>
31#include <asm/mach/time.h>
32#include <asm/mach-types.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35
36/*
37 * IQ80332 timer tick configuration.
38 */
39static void __init iq80332_timer_init(void)
40{
41 /* D-Step parts and the iop333 run at a higher internal bus frequency */
42 if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374)
43 iop3xx_init_time(333000000);
44 else
45 iop3xx_init_time(266000000);
46}
47
48static struct sys_timer iq80332_timer = {
49 .init = iq80332_timer_init,
50 .offset = iop3xx_gettimeoffset,
51};
52
53
54/*
55 * IQ80332 PCI.
56 */
57static inline int __init
58iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
59{
60 int irq;
61
62 if (slot == 4 && pin == 1) {
63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP331_XINT0;
65 } else if (slot == 4 && pin == 2) {
66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP331_XINT1;
68 } else if (slot == 4 && pin == 3) {
69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP331_XINT2;
71 } else if (slot == 4 && pin == 4) {
72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP331_XINT3;
74 } else if (slot == 6) {
75 /* GigE */
76 irq = IRQ_IOP331_XINT2;
77 } else {
78 printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number,
80 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
81 irq = -1;
82 }
83
84 return irq;
85}
86
87static struct hw_pci iq80332_pci __initdata = {
88 .swizzle = pci_std_swizzle,
89 .nr_controllers = 1,
90 .setup = iop3xx_pci_setup,
91 .preinit = iop3xx_pci_preinit,
92 .scan = iop3xx_pci_scan_bus,
93 .map_irq = iq80332_pci_map_irq,
94};
95
96static int __init iq80332_pci_init(void)
97{
98 if (machine_is_iq80332())
99 pci_common_init(&iq80332_pci);
100
101 return 0;
102}
103
104subsys_initcall(iq80332_pci_init);
105
106
107/*
108 * IQ80332 machine initialisation.
109 */
110static struct physmap_flash_data iq80332_flash_data = {
111 .width = 1,
112};
113
114static struct resource iq80332_flash_resource = {
115 .start = 0xc0000000,
116 .end = 0xc07fffff,
117 .flags = IORESOURCE_MEM,
118};
119
120static struct platform_device iq80332_flash_device = {
121 .name = "physmap-flash",
122 .id = 0,
123 .dev = {
124 .platform_data = &iq80332_flash_data,
125 },
126 .num_resources = 1,
127 .resource = &iq80332_flash_resource,
128};
129
130static void __init iq80332_init_machine(void)
131{
132 platform_device_register(&iop3xx_i2c0_device);
133 platform_device_register(&iop3xx_i2c1_device);
134 platform_device_register(&iop33x_uart0_device);
135 platform_device_register(&iop33x_uart1_device);
136 platform_device_register(&iq80332_flash_device);
137}
138
139MACHINE_START(IQ80332, "Intel IQ80332")
140 /* Maintainer: Intel Corp. */
141 .phys_io = 0xfefff000,
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io,
145 .init_irq = iop331_init_irq,
146 .timer = &iq80332_timer,
147 .init_machine = iq80332_init_machine,
148MACHINE_END
diff --git a/arch/arm/mach-iop33x/setup.c b/arch/arm/mach-iop33x/setup.c
deleted file mode 100644
index 7cf5015436f3..000000000000
--- a/arch/arm/mach-iop33x/setup.c
+++ /dev/null
@@ -1,162 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop33x/setup.c
3 *
4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright (C) 2004 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#include <linux/mm.h>
13#include <linux/init.h>
14#include <linux/major.h>
15#include <linux/fs.h>
16#include <linux/platform_device.h>
17#include <linux/serial.h>
18#include <linux/tty.h>
19#include <linux/serial_8250.h>
20
21#include <asm/io.h>
22#include <asm/pgtable.h>
23#include <asm/page.h>
24#include <asm/mach/map.h>
25#include <asm/setup.h>
26#include <asm/system.h>
27#include <asm/memory.h>
28#include <asm/hardware.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/time.h>
32#include <asm/hardware/iop3xx.h>
33
34#define IOP331_UART_XTAL 33334000
35
36static struct resource iop33x_uart0_resources[] = {
37 [0] = {
38 .start = IOP331_UART0_PHYS,
39 .end = IOP331_UART0_PHYS + 0x3f,
40 .flags = IORESOURCE_MEM,
41 },
42 [1] = {
43 .start = IRQ_IOP331_UART0,
44 .end = IRQ_IOP331_UART0,
45 .flags = IORESOURCE_IRQ
46 }
47};
48
49static struct resource iop33x_uart1_resources[] = {
50 [0] = {
51 .start = IOP331_UART1_PHYS,
52 .end = IOP331_UART1_PHYS + 0x3f,
53 .flags = IORESOURCE_MEM,
54 },
55 [1] = {
56 .start = IRQ_IOP331_UART1,
57 .end = IRQ_IOP331_UART1,
58 .flags = IORESOURCE_IRQ
59 }
60};
61
62static struct plat_serial8250_port iop33x_uart0_data[] = {
63 {
64 .membase = (char*)(IOP331_UART0_VIRT),
65 .mapbase = (IOP331_UART0_PHYS),
66 .irq = IRQ_IOP331_UART0,
67 .uartclk = IOP331_UART_XTAL,
68 .regshift = 2,
69 .iotype = UPIO_MEM,
70 .flags = UPF_SKIP_TEST,
71 },
72 { },
73};
74
75static struct plat_serial8250_port iop33x_uart1_data[] = {
76 {
77 .membase = (char*)(IOP331_UART1_VIRT),
78 .mapbase = (IOP331_UART1_PHYS),
79 .irq = IRQ_IOP331_UART1,
80 .uartclk = IOP331_UART_XTAL,
81 .regshift = 2,
82 .iotype = UPIO_MEM,
83 .flags = UPF_SKIP_TEST,
84 },
85 { },
86};
87
88static struct platform_device iop33x_uart0 = {
89 .name = "serial8250",
90 .id = PLAT8250_DEV_PLATFORM,
91 .dev.platform_data = iop33x_uart0_data,
92 .num_resources = 2,
93 .resource = iop33x_uart0_resources,
94};
95
96static struct platform_device iop33x_uart1 = {
97 .name = "serial8250",
98 .id = PLAT8250_DEV_PLATFORM1,
99 .dev.platform_data = iop33x_uart1_data,
100 .num_resources = 2,
101 .resource = iop33x_uart1_resources,
102};
103
104static struct platform_device *iop33x_devices[] __initdata = {
105 &iop33x_uart0,
106 &iop33x_uart1,
107};
108
109void __init iop33x_init(void)
110{
111 if(iop_is_331())
112 {
113 platform_add_devices(iop33x_devices,
114 ARRAY_SIZE(iop33x_devices));
115 }
116 platform_device_register(&iop3xx_i2c0_device);
117 platform_device_register(&iop3xx_i2c1_device);
118}
119
120#ifdef CONFIG_ARCH_IOP33X
121extern void iop331_init_irq(void);
122#endif
123
124static void __init iop3xx_timer_init(void)
125{
126 iop3xx_init_time(IOP331_TICK_RATE);
127}
128
129struct sys_timer iop331_timer = {
130 .init = iop3xx_timer_init,
131 .offset = iop3xx_gettimeoffset,
132};
133
134#if defined(CONFIG_ARCH_IQ80331)
135MACHINE_START(IQ80331, "Intel IQ80331")
136 /* Maintainer: Intel Corp. */
137 .phys_io = 0xfefff000,
138 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical
139 .map_io = iop3xx_map_io,
140 .init_irq = iop331_init_irq,
141 .timer = &iop331_timer,
142 .boot_params = 0x0100,
143 .init_machine = iop33x_init,
144MACHINE_END
145
146#elif defined(CONFIG_MACH_IQ80332)
147MACHINE_START(IQ80332, "Intel IQ80332")
148 /* Maintainer: Intel Corp. */
149 .phys_io = 0xfefff000,
150 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical
151 .map_io = iop3xx_map_io,
152 .init_irq = iop331_init_irq,
153 .timer = &iop331_timer,
154 .boot_params = 0x0100,
155 .init_machine = iop33x_init,
156MACHINE_END
157
158#else
159#error No machine descriptor defined for this IOP3XX implementation
160#endif
161
162
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
new file mode 100644
index 000000000000..d221d4abaa87
--- /dev/null
+++ b/arch/arm/mach-iop33x/uart.c
@@ -0,0 +1,106 @@
1/*
2 * linux/arch/arm/mach-iop33x/uart.c
3 *
4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright (C) 2004 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/mm.h>
13#include <linux/init.h>
14#include <linux/major.h>
15#include <linux/fs.h>
16#include <linux/platform_device.h>
17#include <linux/serial.h>
18#include <linux/tty.h>
19#include <linux/serial_8250.h>
20
21#include <asm/io.h>
22#include <asm/pgtable.h>
23#include <asm/page.h>
24#include <asm/mach/map.h>
25#include <asm/setup.h>
26#include <asm/system.h>
27#include <asm/memory.h>
28#include <asm/hardware.h>
29#include <asm/hardware/iop3xx.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#define IOP331_UART_XTAL 33334000
34
35static struct plat_serial8250_port iop33x_uart0_data[] = {
36 {
37 .membase = (char *)IOP331_UART0_VIRT,
38 .mapbase = IOP331_UART0_PHYS,
39 .irq = IRQ_IOP331_UART0,
40 .uartclk = IOP331_UART_XTAL,
41 .regshift = 2,
42 .iotype = UPIO_MEM,
43 .flags = UPF_SKIP_TEST,
44 },
45 { },
46};
47
48static struct resource iop33x_uart0_resources[] = {
49 [0] = {
50 .start = IOP331_UART0_PHYS,
51 .end = IOP331_UART0_PHYS + 0x3f,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = {
55 .start = IRQ_IOP331_UART0,
56 .end = IRQ_IOP331_UART0,
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61struct platform_device iop33x_uart0_device = {
62 .name = "serial8250",
63 .id = PLAT8250_DEV_PLATFORM,
64 .dev = {
65 .platform_data = iop33x_uart0_data,
66 },
67 .num_resources = 2,
68 .resource = iop33x_uart0_resources,
69};
70
71
72static struct resource iop33x_uart1_resources[] = {
73 [0] = {
74 .start = IOP331_UART1_PHYS,
75 .end = IOP331_UART1_PHYS + 0x3f,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = IRQ_IOP331_UART1,
80 .end = IRQ_IOP331_UART1,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct plat_serial8250_port iop33x_uart1_data[] = {
86 {
87 .membase = (char *)IOP331_UART1_VIRT,
88 .mapbase = IOP331_UART1_PHYS,
89 .irq = IRQ_IOP331_UART1,
90 .uartclk = IOP331_UART_XTAL,
91 .regshift = 2,
92 .iotype = UPIO_MEM,
93 .flags = UPF_SKIP_TEST,
94 },
95 { },
96};
97
98struct platform_device iop33x_uart1_device = {
99 .name = "serial8250",
100 .id = PLAT8250_DEV_PLATFORM1,
101 .dev = {
102 .platform_data = iop33x_uart1_data,
103 },
104 .num_resources = 2,
105 .resource = iop33x_uart1_resources,
106};
diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h
index 1e57e0094767..8042946327ed 100644
--- a/include/asm-arm/arch-iop32x/iop321.h
+++ b/include/asm-arm/arch-iop32x/iop321.h
@@ -150,18 +150,6 @@
150#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8) 150#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
151#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) 151#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
152 152
153/* Timers */
154#ifdef CONFIG_ARCH_IQ80321
155#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */
156#elif defined(CONFIG_ARCH_IQ31244)
157#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */
158#endif
159
160#ifdef CONFIG_ARCH_EP80219
161#undef IOP321_TICK_RATE
162#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
163#endif
164
165/* Application accelerator unit 0x00000800 - 0x000008FF */ 153/* Application accelerator unit 0x00000800 - 0x000008FF */
166#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800) 154#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
167#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804) 155#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
diff --git a/include/asm-arm/arch-iop32x/iq31244.h b/include/asm-arm/arch-iop32x/iq31244.h
index f490063d2156..cf2d2343398d 100644
--- a/include/asm-arm/arch-iop32x/iq31244.h
+++ b/include/asm-arm/arch-iop32x/iq31244.h
@@ -7,18 +7,11 @@
7#ifndef _IQ31244_H_ 7#ifndef _IQ31244_H_
8#define _IQ31244_H_ 8#define _IQ31244_H_
9 9
10#define IQ31244_FLASHBASE 0xf0000000 /* Flash */
11#define IQ31244_FLASHSIZE 0x00800000
12#define IQ31244_FLASHWIDTH 2
13
14#define IQ31244_UART 0xfe800000 /* UART #1 */ 10#define IQ31244_UART 0xfe800000 /* UART #1 */
15#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ 11#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
16#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ 12#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
17#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ 13#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
18#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ 14#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
19 15
20#ifndef __ASSEMBLY__
21extern void iq31244_map_io(void);
22#endif
23 16
24#endif // _IQ31244_H_ 17#endif // _IQ31244_H_
diff --git a/include/asm-arm/arch-iop32x/iq80321.h b/include/asm-arm/arch-iop32x/iq80321.h
index 7015a605ab64..55d70f49b7fd 100644
--- a/include/asm-arm/arch-iop32x/iq80321.h
+++ b/include/asm-arm/arch-iop32x/iq80321.h
@@ -7,18 +7,11 @@
7#ifndef _IQ80321_H_ 7#ifndef _IQ80321_H_
8#define _IQ80321_H_ 8#define _IQ80321_H_
9 9
10#define IQ80321_FLASHBASE 0xf0000000 /* Flash */
11#define IQ80321_FLASHSIZE 0x00800000
12#define IQ80321_FLASHWIDTH 1
13
14#define IQ80321_UART 0xfe800000 /* UART #1 */ 10#define IQ80321_UART 0xfe800000 /* UART #1 */
15#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ 11#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
16#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ 12#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
17#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ 13#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
18#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ 14#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
19 15
20#ifndef __ASSEMBLY__
21extern void iq80321_map_io(void);
22#endif
23 16
24#endif // _IQ80321_H_ 17#endif // _IQ80321_H_
diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h
index 9fefcf3372b1..a48327ced92e 100644
--- a/include/asm-arm/arch-iop32x/irqs.h
+++ b/include/asm-arm/arch-iop32x/irqs.h
@@ -47,42 +47,4 @@
47#define NR_IRQS 32 47#define NR_IRQS 32
48 48
49 49
50/*
51 * Interrupts available on the IQ80321 board
52 */
53
54/*
55 * On board devices
56 */
57#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0
58#define IRQ_IQ80321_UART IRQ_IOP321_XINT1
59
60/*
61 * PCI interrupts
62 */
63#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0
64#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1
65#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2
66#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3
67
68/*
69 * Interrupts on the IQ31244 board
70 */
71
72/*
73 * On board devices
74 */
75#define IRQ_IQ31244_UART IRQ_IOP321_XINT1
76#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0
77#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2
78#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3
79
80/*
81 * PCI interrupts
82 */
83#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0
84#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1
85#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2
86#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3
87
88#endif // _IRQ_H_ 50#endif // _IRQ_H_
diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h
index 5e3cb32af020..3ebfdc6fea99 100644
--- a/include/asm-arm/arch-iop33x/hardware.h
+++ b/include/asm-arm/arch-iop33x/hardware.h
@@ -22,6 +22,11 @@
22#define PCIBIOS_MIN_IO 0x00000000 22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000 23#define PCIBIOS_MIN_MEM 0x00000000
24 24
25#ifndef __ASSEMBLY__
26extern struct platform_device iop33x_uart0_device;
27extern struct platform_device iop33x_uart1_device;
28#endif
29
25 30
26/* 31/*
27 * Generic chipset bits 32 * Generic chipset bits
diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h
index d12a95aa967a..a21872abd877 100644
--- a/include/asm-arm/arch-iop33x/iop331.h
+++ b/include/asm-arm/arch-iop33x/iop331.h
@@ -136,16 +136,6 @@
136#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC) 136#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
137 137
138 138
139/* Timers */
140#if defined(CONFIG_ARCH_IOP33X)
141#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */
142#endif
143
144#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333)
145#undef IOP331_TICK_RATE
146#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */
147#endif
148
149/* Application accelerator unit 0x00000800 - 0x000008FF */ 139/* Application accelerator unit 0x00000800 - 0x000008FF */
150#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800) 140#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800)
151#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804) 141#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804)
diff --git a/include/asm-arm/arch-iop33x/iq80331.h b/include/asm-arm/arch-iop33x/iq80331.h
index bda7ab6d55cf..186762bf8944 100644
--- a/include/asm-arm/arch-iop33x/iq80331.h
+++ b/include/asm-arm/arch-iop33x/iq80331.h
@@ -7,17 +7,10 @@
7#ifndef _IQ80331_H_ 7#ifndef _IQ80331_H_
8#define _IQ80331_H_ 8#define _IQ80331_H_
9 9
10#define IQ80331_FLASHBASE 0xc0000000 /* Flash */
11#define IQ80331_FLASHSIZE 0x00800000
12#define IQ80331_FLASHWIDTH 1
13
14#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ 10#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
15#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ 11#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
16#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ 12#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
17#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ 13#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
18 14
19#ifndef __ASSEMBLY__
20extern void iq80331_map_io(void);
21#endif
22 15
23#endif // _IQ80331_H_ 16#endif // _IQ80331_H_
diff --git a/include/asm-arm/arch-iop33x/iq80332.h b/include/asm-arm/arch-iop33x/iq80332.h
index f728e04378ab..2a5d4ee01df9 100644
--- a/include/asm-arm/arch-iop33x/iq80332.h
+++ b/include/asm-arm/arch-iop33x/iq80332.h
@@ -7,17 +7,10 @@
7#ifndef _IQ80332_H_ 7#ifndef _IQ80332_H_
8#define _IQ80332_H_ 8#define _IQ80332_H_
9 9
10#define IQ80332_FLASHBASE 0xc0000000 /* Flash */
11#define IQ80332_FLASHSIZE 0x00800000
12#define IQ80332_FLASHWIDTH 1
13
14#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ 10#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
15#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ 11#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
16#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ 12#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
17#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ 13#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
18 14
19#ifndef __ASSEMBLY__
20extern void iq80332_map_io(void);
21#endif
22 15
23#endif // _IQ80332_H_ 16#endif // _IQ80332_H_
diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h
index 2e3ade3b5ff9..a875404a07fc 100644
--- a/include/asm-arm/arch-iop33x/irqs.h
+++ b/include/asm-arm/arch-iop33x/irqs.h
@@ -57,42 +57,4 @@
57#define NR_IRQS 64 57#define NR_IRQS 64
58 58
59 59
60/*
61 * Interrupts available on the IQ80331 board
62 */
63
64/*
65 * On board devices
66 */
67#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0
68#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0
69#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1
70
71/*
72 * PCI interrupts
73 */
74#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0
75#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1
76#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2
77#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3
78
79/*
80 * Interrupts available on the IQ80332 board
81 */
82
83/*
84 * On board devices
85 */
86#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0
87#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0
88#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1
89
90/*
91 * PCI interrupts
92 */
93#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0
94#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1
95#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2
96#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3
97
98#endif // _IRQ_H_ 60#endif // _IRQ_H_
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 04:39:26 -0500