aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAndrew Victor <andrew@sanpeople.com>2007-02-08 03:42:40 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-08 09:55:24 -0500
commitb2c6561605da4802886cafe96432b8e2968e9edc (patch)
tree46991d838d08e6b7ed4ec3942a1bc7ea70b8280f
parentd0760b3bc8ff9b34e3e2e166e2102548a24751b4 (diff)
[ARM] 4145/2: AT91: Add support for AT91SAM9263 processor
Add support for the Atmel AT91SAM9263 processor. It is similar to the AT91SAM9260 but with more integrated peripherals, 5 GPIO banks, etc. Original patch from Nicolas Ferre. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mach-at91/Kconfig3
-rw-r--r--arch/arm/mach-at91/Makefile1
-rw-r--r--arch/arm/mach-at91/at91sam9263.c313
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c818
-rw-r--r--arch/arm/mach-at91/clock.c2
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/pm.c2
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--drivers/usb/gadget/at91_udc.c4
-rw-r--r--include/asm-arm/arch-at91/at91sam9263.h131
-rw-r--r--include/asm-arm/arch-at91/at91sam9263_matrix.h129
-rw-r--r--include/asm-arm/arch-at91/at91sam926x_mc.h7
-rw-r--r--include/asm-arm/arch-at91/cpu.h7
-rw-r--r--include/asm-arm/arch-at91/hardware.h2
-rw-r--r--include/asm-arm/arch-at91/timex.h5
15 files changed, 1425 insertions, 5 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 9f11db8af233..2499385e22da 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -14,6 +14,9 @@ config ARCH_AT91SAM9260
14config ARCH_AT91SAM9261 14config ARCH_AT91SAM9261
15 bool "AT91SAM9261" 15 bool "AT91SAM9261"
16 16
17config ARCH_AT91SAM9263
18 bool "AT91SAM9263"
19
17endchoice 20endchoice
18 21
19# ---------------------------------------------------------- 22# ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index cf777007847a..2fd4cd4a57f8 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PM) += pm.o
13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o 13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o 14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o 15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
16 17
17# AT91RM9200 board-specific support 18# AT91RM9200 board-specific support
18obj-$(CONFIG_MACH_ONEARM) += board-1arm.o 19obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
new file mode 100644
index 000000000000..fae6a821a61b
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -0,0 +1,313 @@
1/*
2 * arch/arm/mach-at91/at91sam9263.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <asm/arch/at91sam9263.h>
18#include <asm/arch/at91_pmc.h>
19#include <asm/arch/at91_rstc.h>
20
21#include "generic.h"
22#include "clock.h"
23
24static struct map_desc at91sam9263_io_desc[] __initdata = {
25 {
26 .virtual = AT91_VA_BASE_SYS,
27 .pfn = __phys_to_pfn(AT91_BASE_SYS),
28 .length = SZ_16K,
29 .type = MT_DEVICE,
30 }, {
31 .virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
32 .pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
33 .length = AT91SAM9263_SRAM0_SIZE,
34 .type = MT_DEVICE,
35 }, {
36 .virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
37 .pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
38 .length = AT91SAM9263_SRAM1_SIZE,
39 .type = MT_DEVICE,
40 },
41};
42
43/* --------------------------------------------------------------------
44 * Clocks
45 * -------------------------------------------------------------------- */
46
47/*
48 * The peripheral clocks.
49 */
50static struct clk pioA_clk = {
51 .name = "pioA_clk",
52 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
53 .type = CLK_TYPE_PERIPHERAL,
54};
55static struct clk pioB_clk = {
56 .name = "pioB_clk",
57 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
58 .type = CLK_TYPE_PERIPHERAL,
59};
60static struct clk pioCDE_clk = {
61 .name = "pioCDE_clk",
62 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
63 .type = CLK_TYPE_PERIPHERAL,
64};
65static struct clk usart0_clk = {
66 .name = "usart0_clk",
67 .pmc_mask = 1 << AT91SAM9263_ID_US0,
68 .type = CLK_TYPE_PERIPHERAL,
69};
70static struct clk usart1_clk = {
71 .name = "usart1_clk",
72 .pmc_mask = 1 << AT91SAM9263_ID_US1,
73 .type = CLK_TYPE_PERIPHERAL,
74};
75static struct clk usart2_clk = {
76 .name = "usart2_clk",
77 .pmc_mask = 1 << AT91SAM9263_ID_US2,
78 .type = CLK_TYPE_PERIPHERAL,
79};
80static struct clk mmc0_clk = {
81 .name = "mci0_clk",
82 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
83 .type = CLK_TYPE_PERIPHERAL,
84};
85static struct clk mmc1_clk = {
86 .name = "mci1_clk",
87 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
88 .type = CLK_TYPE_PERIPHERAL,
89};
90static struct clk twi_clk = {
91 .name = "twi_clk",
92 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
93 .type = CLK_TYPE_PERIPHERAL,
94};
95static struct clk spi0_clk = {
96 .name = "spi0_clk",
97 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
98 .type = CLK_TYPE_PERIPHERAL,
99};
100static struct clk spi1_clk = {
101 .name = "spi1_clk",
102 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
103 .type = CLK_TYPE_PERIPHERAL,
104};
105static struct clk tcb_clk = {
106 .name = "tcb_clk",
107 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
108 .type = CLK_TYPE_PERIPHERAL,
109};
110static struct clk ether_clk = {
111 .name = "ether_clk",
112 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
113 .type = CLK_TYPE_PERIPHERAL,
114};
115static struct clk udc_clk = {
116 .name = "udc_clk",
117 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
118 .type = CLK_TYPE_PERIPHERAL,
119};
120static struct clk isi_clk = {
121 .name = "isi_clk",
122 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
123 .type = CLK_TYPE_PERIPHERAL,
124};
125static struct clk lcdc_clk = {
126 .name = "lcdc_clk",
127 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
128 .type = CLK_TYPE_PERIPHERAL,
129};
130static struct clk ohci_clk = {
131 .name = "ohci_clk",
132 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
133 .type = CLK_TYPE_PERIPHERAL,
134};
135
136static struct clk *periph_clocks[] __initdata = {
137 &pioA_clk,
138 &pioB_clk,
139 &pioCDE_clk,
140 &usart0_clk,
141 &usart1_clk,
142 &usart2_clk,
143 &mmc0_clk,
144 &mmc1_clk,
145 // can
146 &twi_clk,
147 &spi0_clk,
148 &spi1_clk,
149 // ssc0 .. ssc1
150 // ac97
151 &tcb_clk,
152 // pwmc
153 &ether_clk,
154 // 2dge
155 &udc_clk,
156 &isi_clk,
157 &lcdc_clk,
158 // dma
159 &ohci_clk,
160 // irq0 .. irq1
161};
162
163/*
164 * The four programmable clocks.
165 * You must configure pin multiplexing to bring these signals out.
166 */
167static struct clk pck0 = {
168 .name = "pck0",
169 .pmc_mask = AT91_PMC_PCK0,
170 .type = CLK_TYPE_PROGRAMMABLE,
171 .id = 0,
172};
173static struct clk pck1 = {
174 .name = "pck1",
175 .pmc_mask = AT91_PMC_PCK1,
176 .type = CLK_TYPE_PROGRAMMABLE,
177 .id = 1,
178};
179static struct clk pck2 = {
180 .name = "pck2",
181 .pmc_mask = AT91_PMC_PCK2,
182 .type = CLK_TYPE_PROGRAMMABLE,
183 .id = 2,
184};
185static struct clk pck3 = {
186 .name = "pck3",
187 .pmc_mask = AT91_PMC_PCK3,
188 .type = CLK_TYPE_PROGRAMMABLE,
189 .id = 3,
190};
191
192static void __init at91sam9263_register_clocks(void)
193{
194 int i;
195
196 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
197 clk_register(periph_clocks[i]);
198
199 clk_register(&pck0);
200 clk_register(&pck1);
201 clk_register(&pck2);
202 clk_register(&pck3);
203}
204
205/* --------------------------------------------------------------------
206 * GPIO
207 * -------------------------------------------------------------------- */
208
209static struct at91_gpio_bank at91sam9263_gpio[] = {
210 {
211 .id = AT91SAM9263_ID_PIOA,
212 .offset = AT91_PIOA,
213 .clock = &pioA_clk,
214 }, {
215 .id = AT91SAM9263_ID_PIOB,
216 .offset = AT91_PIOB,
217 .clock = &pioB_clk,
218 }, {
219 .id = AT91SAM9263_ID_PIOCDE,
220 .offset = AT91_PIOC,
221 .clock = &pioCDE_clk,
222 }, {
223 .id = AT91SAM9263_ID_PIOCDE,
224 .offset = AT91_PIOD,
225 .clock = &pioCDE_clk,
226 }, {
227 .id = AT91SAM9263_ID_PIOCDE,
228 .offset = AT91_PIOE,
229 .clock = &pioCDE_clk,
230 }
231};
232
233static void at91sam9263_reset(void)
234{
235 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
236}
237
238
239/* --------------------------------------------------------------------
240 * AT91SAM9263 processor initialization
241 * -------------------------------------------------------------------- */
242
243void __init at91sam9263_initialize(unsigned long main_clock)
244{
245 /* Map peripherals */
246 iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
247
248 at91_arch_reset = at91sam9263_reset;
249 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
250
251 /* Init clock subsystem */
252 at91_clock_init(main_clock);
253
254 /* Register the processor-specific clocks */
255 at91sam9263_register_clocks();
256
257 /* Register GPIO subsystem */
258 at91_gpio_init(at91sam9263_gpio, 5);
259}
260
261/* --------------------------------------------------------------------
262 * Interrupt initialization
263 * -------------------------------------------------------------------- */
264
265/*
266 * The default interrupt priority levels (0 = lowest, 7 = highest).
267 */
268static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
269 7, /* Advanced Interrupt Controller (FIQ) */
270 7, /* System Peripherals */
271 0, /* Parallel IO Controller A */
272 0, /* Parallel IO Controller B */
273 0, /* Parallel IO Controller C, D and E */
274 0,
275 0,
276 6, /* USART 0 */
277 6, /* USART 1 */
278 6, /* USART 2 */
279 0, /* Multimedia Card Interface 0 */
280 0, /* Multimedia Card Interface 1 */
281 4, /* CAN */
282 0, /* Two-Wire Interface */
283 6, /* Serial Peripheral Interface 0 */
284 6, /* Serial Peripheral Interface 1 */
285 5, /* Serial Synchronous Controller 0 */
286 5, /* Serial Synchronous Controller 1 */
287 6, /* AC97 Controller */
288 0, /* Timer Counter 0, 1 and 2 */
289 0, /* Pulse Width Modulation Controller */
290 3, /* Ethernet */
291 0,
292 0, /* 2D Graphic Engine */
293 3, /* USB Device Port */
294 0, /* Image Sensor Interface */
295 3, /* LDC Controller */
296 0, /* DMA Controller */
297 0,
298 3, /* USB Host port */
299 0, /* Advanced Interrupt Controller (IRQ0) */
300 0, /* Advanced Interrupt Controller (IRQ1) */
301};
302
303void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
304{
305 if (!priority)
306 priority = at91sam9263_default_irq_priority;
307
308 /* Initialize the AIC interrupt controller */
309 at91_aic_init(priority);
310
311 /* Enable GPIO interrupts */
312 at91_gpio_irq_setup();
313}
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
new file mode 100644
index 000000000000..d9af7ca58bce
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -0,0 +1,818 @@
1/*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/platform_device.h>
16
17#include <asm/arch/board.h>
18#include <asm/arch/gpio.h>
19#include <asm/arch/at91sam9263.h>
20#include <asm/arch/at91sam926x_mc.h>
21#include <asm/arch/at91sam9263_matrix.h>
22
23#include "generic.h"
24
25#define SZ_512 0x00000200
26#define SZ_256 0x00000100
27#define SZ_16 0x00000010
28
29/* --------------------------------------------------------------------
30 * USB Host
31 * -------------------------------------------------------------------- */
32
33#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
34static u64 ohci_dmamask = 0xffffffffUL;
35static struct at91_usbh_data usbh_data;
36
37static struct resource usbh_resources[] = {
38 [0] = {
39 .start = AT91SAM9263_UHP_BASE,
40 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
41 .flags = IORESOURCE_MEM,
42 },
43 [1] = {
44 .start = AT91SAM9263_ID_UHP,
45 .end = AT91SAM9263_ID_UHP,
46 .flags = IORESOURCE_IRQ,
47 },
48};
49
50static struct platform_device at91_usbh_device = {
51 .name = "at91_ohci",
52 .id = -1,
53 .dev = {
54 .dma_mask = &ohci_dmamask,
55 .coherent_dma_mask = 0xffffffff,
56 .platform_data = &usbh_data,
57 },
58 .resource = usbh_resources,
59 .num_resources = ARRAY_SIZE(usbh_resources),
60};
61
62void __init at91_add_device_usbh(struct at91_usbh_data *data)
63{
64 int i;
65
66 if (!data)
67 return;
68
69 /* Enable VBus control for UHP ports */
70 for (i = 0; i < data->ports; i++) {
71 if (data->vbus_pin[i])
72 at91_set_gpio_output(data->vbus_pin[i], 0);
73 }
74
75 usbh_data = *data;
76 platform_device_register(&at91_usbh_device);
77}
78#else
79void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
80#endif
81
82
83/* --------------------------------------------------------------------
84 * USB Device (Gadget)
85 * -------------------------------------------------------------------- */
86
87#ifdef CONFIG_USB_GADGET_AT91
88static struct at91_udc_data udc_data;
89
90static struct resource udc_resources[] = {
91 [0] = {
92 .start = AT91SAM9263_BASE_UDP,
93 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = AT91SAM9263_ID_UDP,
98 .end = AT91SAM9263_ID_UDP,
99 .flags = IORESOURCE_IRQ,
100 },
101};
102
103static struct platform_device at91_udc_device = {
104 .name = "at91_udc",
105 .id = -1,
106 .dev = {
107 .platform_data = &udc_data,
108 },
109 .resource = udc_resources,
110 .num_resources = ARRAY_SIZE(udc_resources),
111};
112
113void __init at91_add_device_udc(struct at91_udc_data *data)
114{
115 if (!data)
116 return;
117
118 if (data->vbus_pin) {
119 at91_set_gpio_input(data->vbus_pin, 0);
120 at91_set_deglitch(data->vbus_pin, 1);
121 }
122
123 /* Pullup pin is handled internally by USB device peripheral */
124
125 udc_data = *data;
126 platform_device_register(&at91_udc_device);
127}
128#else
129void __init at91_add_device_udc(struct at91_udc_data *data) {}
130#endif
131
132
133/* --------------------------------------------------------------------
134 * Ethernet
135 * -------------------------------------------------------------------- */
136
137#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
138static u64 eth_dmamask = 0xffffffffUL;
139static struct at91_eth_data eth_data;
140
141static struct resource eth_resources[] = {
142 [0] = {
143 .start = AT91SAM9263_BASE_EMAC,
144 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
145 .flags = IORESOURCE_MEM,
146 },
147 [1] = {
148 .start = AT91SAM9263_ID_EMAC,
149 .end = AT91SAM9263_ID_EMAC,
150 .flags = IORESOURCE_IRQ,
151 },
152};
153
154static struct platform_device at91sam9263_eth_device = {
155 .name = "macb",
156 .id = -1,
157 .dev = {
158 .dma_mask = &eth_dmamask,
159 .coherent_dma_mask = 0xffffffff,
160 .platform_data = &eth_data,
161 },
162 .resource = eth_resources,
163 .num_resources = ARRAY_SIZE(eth_resources),
164};
165
166void __init at91_add_device_eth(struct at91_eth_data *data)
167{
168 if (!data)
169 return;
170
171 if (data->phy_irq_pin) {
172 at91_set_gpio_input(data->phy_irq_pin, 0);
173 at91_set_deglitch(data->phy_irq_pin, 1);
174 }
175
176 /* Pins used for MII and RMII */
177 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
178 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
179 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
180 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
181 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
182 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
183 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
184 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
185 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
186 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
187
188 if (!data->is_rmii) {
189 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
190 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
191 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
192 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
193 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
194 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
195 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
196 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
197 }
198
199 eth_data = *data;
200 platform_device_register(&at91sam9263_eth_device);
201}
202#else
203void __init at91_add_device_eth(struct at91_eth_data *data) {}
204#endif
205
206
207/* --------------------------------------------------------------------
208 * MMC / SD
209 * -------------------------------------------------------------------- */
210
211#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
212static u64 mmc_dmamask = 0xffffffffUL;
213static struct at91_mmc_data mmc0_data, mmc1_data;
214
215static struct resource mmc0_resources[] = {
216 [0] = {
217 .start = AT91SAM9263_BASE_MCI0,
218 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 [1] = {
222 .start = AT91SAM9263_ID_MCI0,
223 .end = AT91SAM9263_ID_MCI0,
224 .flags = IORESOURCE_IRQ,
225 },
226};
227
228static struct platform_device at91sam9263_mmc0_device = {
229 .name = "at91_mci",
230 .id = 0,
231 .dev = {
232 .dma_mask = &mmc_dmamask,
233 .coherent_dma_mask = 0xffffffff,
234 .platform_data = &mmc0_data,
235 },
236 .resource = mmc0_resources,
237 .num_resources = ARRAY_SIZE(mmc0_resources),
238};
239
240static struct resource mmc1_resources[] = {
241 [0] = {
242 .start = AT91SAM9263_BASE_MCI1,
243 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
244 .flags = IORESOURCE_MEM,
245 },
246 [1] = {
247 .start = AT91SAM9263_ID_MCI1,
248 .end = AT91SAM9263_ID_MCI1,
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct platform_device at91sam9263_mmc1_device = {
254 .name = "at91_mci",
255 .id = 1,
256 .dev = {
257 .dma_mask = &mmc_dmamask,
258 .coherent_dma_mask = 0xffffffff,
259 .platform_data = &mmc1_data,
260 },
261 .resource = mmc1_resources,
262 .num_resources = ARRAY_SIZE(mmc1_resources),
263};
264
265void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
266{
267 if (!data)
268 return;
269
270 /* input/irq */
271 if (data->det_pin) {
272 at91_set_gpio_input(data->det_pin, 1);
273 at91_set_deglitch(data->det_pin, 1);
274 }
275 if (data->wp_pin)
276 at91_set_gpio_input(data->wp_pin, 1);
277 if (data->vcc_pin)
278 at91_set_gpio_output(data->vcc_pin, 0);
279
280 if (mmc_id == 0) { /* MCI0 */
281 /* CLK */
282 at91_set_A_periph(AT91_PIN_PA12, 0);
283
284 if (data->slot_b) {
285 /* CMD */
286 at91_set_A_periph(AT91_PIN_PA16, 1);
287
288 /* DAT0, maybe DAT1..DAT3 */
289 at91_set_A_periph(AT91_PIN_PA17, 1);
290 if (data->wire4) {
291 at91_set_A_periph(AT91_PIN_PA18, 1);
292 at91_set_A_periph(AT91_PIN_PA19, 1);
293 at91_set_A_periph(AT91_PIN_PA20, 1);
294 }
295 } else {
296 /* CMD */
297 at91_set_A_periph(AT91_PIN_PA1, 1);
298
299 /* DAT0, maybe DAT1..DAT3 */
300 at91_set_A_periph(AT91_PIN_PA0, 1);
301 if (data->wire4) {
302 at91_set_A_periph(AT91_PIN_PA3, 1);
303 at91_set_A_periph(AT91_PIN_PA4, 1);
304 at91_set_A_periph(AT91_PIN_PA5, 1);
305 }
306 }
307
308 mmc0_data = *data;
309 at91_clock_associate("mci0_clk", &at91sam9263_mmc1_device.dev, "mci_clk");
310 platform_device_register(&at91sam9263_mmc0_device);
311 } else { /* MCI1 */
312 /* CLK */
313 at91_set_A_periph(AT91_PIN_PA6, 0);
314
315 if (data->slot_b) {
316 /* CMD */
317 at91_set_A_periph(AT91_PIN_PA21, 1);
318
319 /* DAT0, maybe DAT1..DAT3 */
320 at91_set_A_periph(AT91_PIN_PA22, 1);
321 if (data->wire4) {
322 at91_set_A_periph(AT91_PIN_PA23, 1);
323 at91_set_A_periph(AT91_PIN_PA24, 1);
324 at91_set_A_periph(AT91_PIN_PA25, 1);
325 }
326 } else {
327 /* CMD */
328 at91_set_A_periph(AT91_PIN_PA7, 1);
329
330 /* DAT0, maybe DAT1..DAT3 */
331 at91_set_A_periph(AT91_PIN_PA8, 1);
332 if (data->wire4) {
333 at91_set_A_periph(AT91_PIN_PA9, 1);
334 at91_set_A_periph(AT91_PIN_PA10, 1);
335 at91_set_A_periph(AT91_PIN_PA11, 1);
336 }
337 }
338
339 mmc1_data = *data;
340 at91_clock_associate("mci1_clk", &at91sam9263_mmc1_device.dev, "mci_clk");
341 platform_device_register(&at91sam9263_mmc1_device);
342 }
343}
344#else
345void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
346#endif
347
348
349/* --------------------------------------------------------------------
350 * NAND / SmartMedia
351 * -------------------------------------------------------------------- */
352
353#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
354static struct at91_nand_data nand_data;
355
356#define NAND_BASE AT91_CHIPSELECT_3
357
358static struct resource nand_resources[] = {
359 {
360 .start = NAND_BASE,
361 .end = NAND_BASE + SZ_256M - 1,
362 .flags = IORESOURCE_MEM,
363 }
364};
365
366static struct platform_device at91sam9263_nand_device = {
367 .name = "at91_nand",
368 .id = -1,
369 .dev = {
370 .platform_data = &nand_data,
371 },
372 .resource = nand_resources,
373 .num_resources = ARRAY_SIZE(nand_resources),
374};
375
376void __init at91_add_device_nand(struct at91_nand_data *data)
377{
378 unsigned long csa, mode;
379
380 if (!data)
381 return;
382
383 csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
384 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC);
385
386 /* set the bus interface characteristics */
387 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
388 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
389
390 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
391 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
392
393 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
394
395 if (data->bus_width_16)
396 mode = AT91_SMC_DBW_16;
397 else
398 mode = AT91_SMC_DBW_8;
399 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
400
401 /* enable pin */
402 if (data->enable_pin)
403 at91_set_gpio_output(data->enable_pin, 1);
404
405 /* ready/busy pin */
406 if (data->rdy_pin)
407 at91_set_gpio_input(data->rdy_pin, 1);
408
409 /* card detect pin */
410 if (data->det_pin)
411 at91_set_gpio_input(data->det_pin, 1);
412
413 nand_data = *data;
414 platform_device_register(&at91sam9263_nand_device);
415}
416#else
417void __init at91_add_device_nand(struct at91_nand_data *data) {}
418#endif
419
420
421/* --------------------------------------------------------------------
422 * TWI (i2c)
423 * -------------------------------------------------------------------- */
424
425#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
426
427static struct resource twi_resources[] = {
428 [0] = {
429 .start = AT91SAM9263_BASE_TWI,
430 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
431 .flags = IORESOURCE_MEM,
432 },
433 [1] = {
434 .start = AT91SAM9263_ID_TWI,
435 .end = AT91SAM9263_ID_TWI,
436 .flags = IORESOURCE_IRQ,
437 },
438};
439
440static struct platform_device at91sam9263_twi_device = {
441 .name = "at91_i2c",
442 .id = -1,
443 .resource = twi_resources,
444 .num_resources = ARRAY_SIZE(twi_resources),
445};
446
447void __init at91_add_device_i2c(void)
448{
449 /* pins used for TWI interface */
450 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
451 at91_set_multi_drive(AT91_PIN_PB4, 1);
452
453 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
454 at91_set_multi_drive(AT91_PIN_PB5, 1);
455
456 platform_device_register(&at91sam9263_twi_device);
457}
458#else
459void __init at91_add_device_i2c(void) {}
460#endif
461
462
463/* --------------------------------------------------------------------
464 * SPI
465 * -------------------------------------------------------------------- */
466
467#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
468static u64 spi_dmamask = 0xffffffffUL;
469
470static struct resource spi0_resources[] = {
471 [0] = {
472 .start = AT91SAM9263_BASE_SPI0,
473 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
474 .flags = IORESOURCE_MEM,
475 },
476 [1] = {
477 .start = AT91SAM9263_ID_SPI0,
478 .end = AT91SAM9263_ID_SPI0,
479 .flags = IORESOURCE_IRQ,
480 },
481};
482
483static struct platform_device at91sam9263_spi0_device = {
484 .name = "atmel_spi",
485 .id = 0,
486 .dev = {
487 .dma_mask = &spi_dmamask,
488 .coherent_dma_mask = 0xffffffff,
489 },
490 .resource = spi0_resources,
491 .num_resources = ARRAY_SIZE(spi0_resources),
492};
493
494static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
495
496static struct resource spi1_resources[] = {
497 [0] = {
498 .start = AT91SAM9263_BASE_SPI1,
499 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
500 .flags = IORESOURCE_MEM,
501 },
502 [1] = {
503 .start = AT91SAM9263_ID_SPI1,
504 .end = AT91SAM9263_ID_SPI1,
505 .flags = IORESOURCE_IRQ,
506 },
507};
508
509static struct platform_device at91sam9263_spi1_device = {
510 .name = "atmel_spi",
511 .id = 1,
512 .dev = {
513 .dma_mask = &spi_dmamask,
514 .coherent_dma_mask = 0xffffffff,
515 },
516 .resource = spi1_resources,
517 .num_resources = ARRAY_SIZE(spi1_resources),
518};
519
520static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
521
522void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
523{
524 int i;
525 unsigned long cs_pin;
526 short enable_spi0 = 0;
527 short enable_spi1 = 0;
528
529 /* Choose SPI chip-selects */
530 for (i = 0; i < nr_devices; i++) {
531 if (devices[i].controller_data)
532 cs_pin = (unsigned long) devices[i].controller_data;
533 else if (devices[i].bus_num == 0)
534 cs_pin = spi0_standard_cs[devices[i].chip_select];
535 else
536 cs_pin = spi1_standard_cs[devices[i].chip_select];
537
538 if (devices[i].bus_num == 0)
539 enable_spi0 = 1;
540 else
541 enable_spi1 = 1;
542
543 /* enable chip-select pin */
544 at91_set_gpio_output(cs_pin, 1);
545
546 /* pass chip-select pin to driver */
547 devices[i].controller_data = (void *) cs_pin;
548 }
549
550 spi_register_board_info(devices, nr_devices);
551
552 /* Configure SPI bus(es) */
553 if (enable_spi0) {
554 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
555 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
556 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
557
558 at91_clock_associate("spi0_clk", &at91sam9263_spi0_device.dev, "spi_clk");
559 platform_device_register(&at91sam9263_spi0_device);
560 }
561 if (enable_spi1) {
562 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
563 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
564 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
565
566 at91_clock_associate("spi1_clk", &at91sam9263_spi1_device.dev, "spi_clk");
567 platform_device_register(&at91sam9263_spi1_device);
568 }
569}
570#else
571void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
572#endif
573
574
575/* --------------------------------------------------------------------
576 * LEDs
577 * -------------------------------------------------------------------- */
578
579#if defined(CONFIG_LEDS)
580u8 at91_leds_cpu;
581u8 at91_leds_timer;
582
583void __init at91_init_leds(u8 cpu_led, u8 timer_led)
584{
585 /* Enable GPIO to access the LEDs */
586 at91_set_gpio_output(cpu_led, 1);
587 at91_set_gpio_output(timer_led, 1);
588
589 at91_leds_cpu = cpu_led;
590 at91_leds_timer = timer_led;
591}
592#else
593void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
594#endif
595
596
597/* --------------------------------------------------------------------
598 * UART
599 * -------------------------------------------------------------------- */
600
601#if defined(CONFIG_SERIAL_ATMEL)
602
603static struct resource dbgu_resources[] = {
604 [0] = {
605 .start = AT91_VA_BASE_SYS + AT91_DBGU,
606 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
607 .flags = IORESOURCE_MEM,
608 },
609 [1] = {
610 .start = AT91_ID_SYS,
611 .end = AT91_ID_SYS,
612 .flags = IORESOURCE_IRQ,
613 },
614};
615
616static struct atmel_uart_data dbgu_data = {
617 .use_dma_tx = 0,
618 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
619 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
620};
621
622static struct platform_device at91sam9263_dbgu_device = {
623 .name = "atmel_usart",
624 .id = 0,
625 .dev = {
626 .platform_data = &dbgu_data,
627 .coherent_dma_mask = 0xffffffff,
628 },
629 .resource = dbgu_resources,
630 .num_resources = ARRAY_SIZE(dbgu_resources),
631};
632
633static inline void configure_dbgu_pins(void)
634{
635 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
636 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
637}
638
639static struct resource uart0_resources[] = {
640 [0] = {
641 .start = AT91SAM9263_BASE_US0,
642 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
643 .flags = IORESOURCE_MEM,
644 },
645 [1] = {
646 .start = AT91SAM9263_ID_US0,
647 .end = AT91SAM9263_ID_US0,
648 .flags = IORESOURCE_IRQ,
649 },
650};
651
652static struct atmel_uart_data uart0_data = {
653 .use_dma_tx = 1,
654 .use_dma_rx = 1,
655};
656
657static struct platform_device at91sam9263_uart0_device = {
658 .name = "atmel_usart",
659 .id = 1,
660 .dev = {
661 .platform_data = &uart0_data,
662 .coherent_dma_mask = 0xffffffff,
663 },
664 .resource = uart0_resources,
665 .num_resources = ARRAY_SIZE(uart0_resources),
666};
667
668static inline void configure_usart0_pins(void)
669{
670 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
671 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
672 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
673 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
674}
675
676static struct resource uart1_resources[] = {
677 [0] = {
678 .start = AT91SAM9263_BASE_US1,
679 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
680 .flags = IORESOURCE_MEM,
681 },
682 [1] = {
683 .start = AT91SAM9263_ID_US1,
684 .end = AT91SAM9263_ID_US1,
685 .flags = IORESOURCE_IRQ,
686 },
687};
688
689static struct atmel_uart_data uart1_data = {
690 .use_dma_tx = 1,
691 .use_dma_rx = 1,
692};
693
694static struct platform_device at91sam9263_uart1_device = {
695 .name = "atmel_usart",
696 .id = 2,
697 .dev = {
698 .platform_data = &uart1_data,
699 .coherent_dma_mask = 0xffffffff,
700 },
701 .resource = uart1_resources,
702 .num_resources = ARRAY_SIZE(uart1_resources),
703};
704
705static inline void configure_usart1_pins(void)
706{
707 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
708 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
709 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
710 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
711}
712
713static struct resource uart2_resources[] = {
714 [0] = {
715 .start = AT91SAM9263_BASE_US2,
716 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
717 .flags = IORESOURCE_MEM,
718 },
719 [1] = {
720 .start = AT91SAM9263_ID_US2,
721 .end = AT91SAM9263_ID_US2,
722 .flags = IORESOURCE_IRQ,
723 },
724};
725
726static struct atmel_uart_data uart2_data = {
727 .use_dma_tx = 1,
728 .use_dma_rx = 1,
729};
730
731static struct platform_device at91sam9263_uart2_device = {
732 .name = "atmel_usart",
733 .id = 3,
734 .dev = {
735 .platform_data = &uart2_data,
736 .coherent_dma_mask = 0xffffffff,
737 },
738 .resource = uart2_resources,
739 .num_resources = ARRAY_SIZE(uart2_resources),
740};
741
742static inline void configure_usart2_pins(void)
743{
744 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
745 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
746 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
747 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
748}
749
750struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
751struct platform_device *atmel_default_console_device; /* the serial console device */
752
753void __init at91_init_serial(struct at91_uart_config *config)
754{
755 int i;
756
757 /* Fill in list of supported UARTs */
758 for (i = 0; i < config->nr_tty; i++) {
759 switch (config->tty_map[i]) {
760 case 0:
761 configure_usart0_pins();
762 at91_uarts[i] = &at91sam9263_uart0_device;
763 at91_clock_associate("usart0_clk", &at91sam9263_uart0_device.dev, "usart");
764 break;
765 case 1:
766 configure_usart1_pins();
767 at91_uarts[i] = &at91sam9263_uart1_device;
768 at91_clock_associate("usart1_clk", &at91sam9263_uart1_device.dev, "usart");
769 break;
770 case 2:
771 configure_usart2_pins();
772 at91_uarts[i] = &at91sam9263_uart2_device;
773 at91_clock_associate("usart2_clk", &at91sam9263_uart2_device.dev, "usart");
774 break;
775 case 3:
776 configure_dbgu_pins();
777 at91_uarts[i] = &at91sam9263_dbgu_device;
778 at91_clock_associate("mck", &at91sam9263_dbgu_device.dev, "usart");
779 break;
780 default:
781 continue;
782 }
783 at91_uarts[i]->id = i; /* update ID number to mapped ID */
784 }
785
786 /* Set serial console device */
787 if (config->console_tty < ATMEL_MAX_UART)
788 atmel_default_console_device = at91_uarts[config->console_tty];
789 if (!atmel_default_console_device)
790 printk(KERN_INFO "AT91: No default serial console defined.\n");
791}
792
793void __init at91_add_device_serial(void)
794{
795 int i;
796
797 for (i = 0; i < ATMEL_MAX_UART; i++) {
798 if (at91_uarts[i])
799 platform_device_register(at91_uarts[i]);
800 }
801}
802#else
803void __init at91_init_serial(struct at91_uart_config *config) {}
804void __init at91_add_device_serial(void) {}
805#endif
806
807
808/* -------------------------------------------------------------------- */
809/*
810 * These devices are always present and don't need any board-specific
811 * setup.
812 */
813static int __init at91_add_standard_devices(void)
814{
815 return 0;
816}
817
818arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index baab095f6e32..27e7279b5b39 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -598,7 +598,7 @@ int __init at91_clock_init(unsigned long main_clock)
598 udpck.pmc_mask = AT91RM9200_PMC_UDP; 598 udpck.pmc_mask = AT91RM9200_PMC_UDP;
599 at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP); 599 at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP);
600 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); 600 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
601 } else if (cpu_is_at91sam9260()) { 601 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
602 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 602 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
603 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 603 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
604 at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP); 604 at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP);
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 10ee37bf6d4d..bda26221c522 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -12,11 +12,13 @@
12extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks); 12extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
13extern void __init at91sam9260_initialize(unsigned long main_clock); 13extern void __init at91sam9260_initialize(unsigned long main_clock);
14extern void __init at91sam9261_initialize(unsigned long main_clock); 14extern void __init at91sam9261_initialize(unsigned long main_clock);
15extern void __init at91sam9263_initialize(unsigned long main_clock);
15 16
16 /* Interrupts */ 17 /* Interrupts */
17extern void __init at91rm9200_init_interrupts(unsigned int priority[]); 18extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
18extern void __init at91sam9260_init_interrupts(unsigned int priority[]); 19extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
19extern void __init at91sam9261_init_interrupts(unsigned int priority[]); 20extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
21extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
20extern void __init at91_aic_init(unsigned int priority[]); 22extern void __init at91_aic_init(unsigned int priority[]);
21 23
22 /* Timer */ 24 /* Timer */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index e095b1fe8d8a..b49bfda53d7f 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -80,6 +80,8 @@ static int at91_pm_verify_clocks(void)
80#warning "Check SAM9260 USB clocks" 80#warning "Check SAM9260 USB clocks"
81 } else if (cpu_is_at91sam9261()) { 81 } else if (cpu_is_at91sam9261()) {
82#warning "Check SAM9261 USB clocks" 82#warning "Check SAM9261 USB clocks"
83 } else if (cpu_is_at91sam9263()) {
84#warning "Check SAM9263 USB clocks"
83 } 85 }
84 86
85#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS 87#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index aade2f72c920..b305cbda8b87 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -171,8 +171,8 @@ config CPU_ARM925T
171# ARM926T 171# ARM926T
172config CPU_ARM926T 172config CPU_ARM926T
173 bool "Support ARM926T processor" 173 bool "Support ARM926T processor"
174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263
175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263
176 select CPU_32v5 176 select CPU_32v5
177 select CPU_ABRT_EV5TJ 177 select CPU_ABRT_EV5TJ
178 select CPU_CACHE_VIVT 178 select CPU_CACHE_VIVT
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 812c733ba8ce..8afecb8a98ee 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -913,7 +913,7 @@ static void pullup(struct at91_udc *udc, int is_on)
913 at91_udp_write(udc, AT91_UDP_TXVC, 0); 913 at91_udp_write(udc, AT91_UDP_TXVC, 0);
914 if (cpu_is_at91rm9200()) 914 if (cpu_is_at91rm9200())
915 at91_set_gpio_value(udc->board.pullup_pin, 1); 915 at91_set_gpio_value(udc->board.pullup_pin, 1);
916 else if (cpu_is_at91sam9260()) { 916 else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
917 u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); 917 u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC);
918 918
919 txvc |= AT91_UDP_TXVC_PUON; 919 txvc |= AT91_UDP_TXVC_PUON;
@@ -930,7 +930,7 @@ static void pullup(struct at91_udc *udc, int is_on)
930 at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); 930 at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
931 if (cpu_is_at91rm9200()) 931 if (cpu_is_at91rm9200())
932 at91_set_gpio_value(udc->board.pullup_pin, 0); 932 at91_set_gpio_value(udc->board.pullup_pin, 0);
933 else if (cpu_is_at91sam9260()) { 933 else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
934 u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); 934 u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC);
935 935
936 txvc &= ~AT91_UDP_TXVC_PUON; 936 txvc &= ~AT91_UDP_TXVC_PUON;
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
new file mode 100644
index 000000000000..f4af68ae0ea9
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -0,0 +1,131 @@
1/*
2 * include/asm-arm/arch-at91/at91sam9263.h
3 *
4 * (C) 2007 Atmel Corporation.
5 *
6 * Common definitions.
7 * Based on AT91SAM9263 datasheet revision B (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9263_H
16#define AT91SAM9263_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Peripherals */
23#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
24#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
25#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
26#define AT91SAM9263_ID_US0 7 /* USART 0 */
27#define AT91SAM9263_ID_US1 8 /* USART 1 */
28#define AT91SAM9263_ID_US2 9 /* USART 2 */
29#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
30#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
31#define AT91SAM9263_ID_CAN 12 /* CAN */
32#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
33#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
34#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
35#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
36#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
37#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
38#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
39#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
40#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
41#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
42#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
43#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
44#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
45#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
46#define AT91SAM9263_ID_UHP 29 /* USB Host port */
47#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
48#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
49
50
51/*
52 * User Peripheral physical base addresses.
53 */
54#define AT91SAM9263_BASE_UDP 0xfff78000
55#define AT91SAM9263_BASE_TCB0 0xfff7c000
56#define AT91SAM9263_BASE_TC0 0xfff7c000
57#define AT91SAM9263_BASE_TC1 0xfff7c040
58#define AT91SAM9263_BASE_TC2 0xfff7c080
59#define AT91SAM9263_BASE_MCI0 0xfff80000
60#define AT91SAM9263_BASE_MCI1 0xfff84000
61#define AT91SAM9263_BASE_TWI 0xfff88000
62#define AT91SAM9263_BASE_US0 0xfff8c000
63#define AT91SAM9263_BASE_US1 0xfff90000
64#define AT91SAM9263_BASE_US2 0xfff94000
65#define AT91SAM9263_BASE_SSC0 0xfff98000
66#define AT91SAM9263_BASE_SSC1 0xfff9c000
67#define AT91SAM9263_BASE_AC97C 0xfffa0000
68#define AT91SAM9263_BASE_SPI0 0xfffa4000
69#define AT91SAM9263_BASE_SPI1 0xfffa8000
70#define AT91SAM9263_BASE_CAN 0xfffac000
71#define AT91SAM9263_BASE_PWMC 0xfffb8000
72#define AT91SAM9263_BASE_EMAC 0xfffbc000
73#define AT91SAM9263_BASE_ISI 0xfffc4000
74#define AT91SAM9263_BASE_2DGE 0xfffc8000
75#define AT91_BASE_SYS 0xffffe000
76
77/*
78 * System Peripherals (offset from AT91_BASE_SYS)
79 */
80#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
81#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
82#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
83#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
84#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
85#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
86#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
87#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
88#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
89#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
90#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
91#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
92#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
93#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
94#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
95#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
96#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
97#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
98#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
99#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
100#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
101#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
102#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
103
104#define AT91_SMC AT91_SMC0
105
106/*
107 * Internal Memory.
108 */
109#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
110#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
111
112#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
113#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
114
115#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
116#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
117
118#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
119#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
120#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
121
122#if 0
123/*
124 * PIO pin definitions (peripheral A/B multiplexing).
125 */
126
127// TODO: Add
128
129#endif
130
131#endif
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h
new file mode 100644
index 000000000000..6fc6e4be624e
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9263_matrix.h
@@ -0,0 +1,129 @@
1/*
2 * include/asm-arm/arch-at91/at91sam9263_matrix.h
3 *
4 * Copyright (C) 2006 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9263 datasheet revision B (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9263_MATRIX_H
16#define AT91SAM9263_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
28#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
29#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
30#define AT91_MATRIX_ULBT_FOUR (2 << 0)
31#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
33
34#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
35#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
36#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
37#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
38#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
39#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
40#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
41#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
45#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
46#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
47#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
48#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
51
52#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
53#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
54#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
55#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
56#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
57#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
58#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
59#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
60#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
61#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
62#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
63#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
64#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
65#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
66#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
67#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
71#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
72#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
73#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
74#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
77
78#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
81#define AT91_MATRIX_RCB2 (1 << 2)
82#define AT91_MATRIX_RCB3 (1 << 3)
83#define AT91_MATRIX_RCB4 (1 << 4)
84#define AT91_MATRIX_RCB5 (1 << 5)
85#define AT91_MATRIX_RCB6 (1 << 6)
86#define AT91_MATRIX_RCB7 (1 << 7)
87#define AT91_MATRIX_RCB8 (1 << 8)
88
89#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
91#define AT91_MATRIX_ITCM_0 (0 << 0)
92#define AT91_MATRIX_ITCM_16 (5 << 0)
93#define AT91_MATRIX_ITCM_32 (6 << 0)
94#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
95#define AT91_MATRIX_DTCM_0 (0 << 4)
96#define AT91_MATRIX_DTCM_16 (5 << 4)
97#define AT91_MATRIX_DTCM_32 (6 << 4)
98
99#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
103#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
104#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
105#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
106#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
107#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
108#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
109#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
110#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
111#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
112#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
113#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
116
117#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
121#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
122#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
123#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
124#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
125#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
126#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
127#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
128
129#endif
diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam926x_mc.h
index 355eee67ebca..d82631c251f1 100644
--- a/include/asm-arm/arch-at91/at91sam926x_mc.h
+++ b/include/asm-arm/arch-at91/at91sam926x_mc.h
@@ -131,4 +131,11 @@
131#define AT91_SMC_PS_16 (2 << 28) 131#define AT91_SMC_PS_16 (2 << 28)
132#define AT91_SMC_PS_32 (3 << 28) 132#define AT91_SMC_PS_32 (3 << 28)
133 133
134#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
135#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
136#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
137#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
138#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
139#endif
140
134#endif 141#endif
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 762eb41aa675..9efde0dad249 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -20,6 +20,7 @@
20#define ARCH_ID_AT91RM9200 0x09290780 20#define ARCH_ID_AT91RM9200 0x09290780
21#define ARCH_ID_AT91SAM9260 0x019803a0 21#define ARCH_ID_AT91SAM9260 0x019803a0
22#define ARCH_ID_AT91SAM9261 0x019703a0 22#define ARCH_ID_AT91SAM9261 0x019703a0
23#define ARCH_ID_AT91SAM9263 0x019607a0
23 24
24 25
25static inline unsigned long at91_cpu_identify(void) 26static inline unsigned long at91_cpu_identify(void)
@@ -46,4 +47,10 @@ static inline unsigned long at91_cpu_identify(void)
46#define cpu_is_at91sam9261() (0) 47#define cpu_is_at91sam9261() (0)
47#endif 48#endif
48 49
50#ifdef CONFIG_ARCH_AT91SAM9263
51#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
52#else
53#define cpu_is_at91sam9263() (0)
54#endif
55
49#endif 56#endif
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 1637fc4a0d8f..eaaf1c12b753 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -22,6 +22,8 @@
22#include <asm/arch/at91sam9260.h> 22#include <asm/arch/at91sam9260.h>
23#elif defined(CONFIG_ARCH_AT91SAM9261) 23#elif defined(CONFIG_ARCH_AT91SAM9261)
24#include <asm/arch/at91sam9261.h> 24#include <asm/arch/at91sam9261.h>
25#elif defined(CONFIG_ARCH_AT91SAM9263)
26#include <asm/arch/at91sam9263.h>
25#else 27#else
26#error "Unsupported AT91 processor" 28#error "Unsupported AT91 processor"
27#endif 29#endif
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index b24e364997e1..f41636d607a2 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -32,6 +32,11 @@
32#define AT91SAM9_MASTER_CLOCK 99300000 32#define AT91SAM9_MASTER_CLOCK 99300000
33#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 33#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
34 34
35#elif defined(CONFIG_ARCH_AT91SAM9263)
36
37#define AT91SAM9_MASTER_CLOCK 99959500
38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
39
35#endif 40#endif
36 41
37#endif 42#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 09:06:20 -0500