[ARM] pxa: cpufreq-pxa2xx: sdram_rows detection support

This patch implements Eric Miao's idea to detect the correct value of
sdram_rows by inspecting the MDCNFG register settings.
It is only tested on two pxa27x devices with 64MB RAM (magician and
hx4700) so far.

Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>

2 files changed, 27 insertions, 3 deletions

diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 6bb678db537c..771dd4eac935 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -64,7 +64,7 @@ typedef struct {
 
 /* Define the refresh period in mSec for the SDRAM and the number of rows */
 #define SDRAM_TREF      64      /* standard 64ms SDRAM */
-#define SDRAM_ROWS      4096    /* 64MB=8192 32MB=4096 */
+static unsigned int sdram_rows;
 
 #define CCLKCFG_TURBO           0x1
 #define CCLKCFG_FCS             0x2
@@ -73,6 +73,9 @@ typedef struct {
 #define MDREFR_DB2_MASK         (MDREFR_K2DB2 | MDREFR_K1DB2)
 #define MDREFR_DRI_MASK         0xFFF
 
+#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
+#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
+
 /*
  * PXA255 definitions
  */
@@ -192,14 +195,28 @@ static void pxa27x_guess_max_freq(void)
         }
 }
 
+static void init_sdram_rows(void)
+{
+        uint32_t mdcnfg = MDCNFG;
+        unsigned int drac2 = 0, drac0 = 0;
+
+        if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
+                drac2 = MDCNFG_DRAC2(mdcnfg);
+
+        if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
+                drac0 = MDCNFG_DRAC0(mdcnfg);
+
+        sdram_rows = 1 << (11 + max(drac0, drac2));
+}
+
 static u32 mdrefr_dri(unsigned int freq)
 {
         u32 dri = 0;
 
         if (cpu_is_pxa25x())
-                dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32));
+                dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
         if (cpu_is_pxa27x())
-                dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32;
+                dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
         return dri;
 }
 
@@ -334,6 +351,8 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
         if (cpu_is_pxa27x())
                 pxa27x_guess_max_freq();
 
+        init_sdram_rows();
+
         /* set default policy and cpuinfo */
         policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
         policy->cur = get_clk_frequency_khz(0);    /* current freq */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 2b71d87c898f..77102d695cc7 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -49,6 +49,11 @@
 #define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
 #define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
 
+#define MDCNFG_DE0      (1 << 0)        /* SDRAM Bank 0 Enable */
+#define MDCNFG_DE1      (1 << 1)        /* SDRAM Bank 1 Enable */
+#define MDCNFG_DE2      (1 << 16)       /* SDRAM Bank 2 Enable */
+#define MDCNFG_DE3      (1 << 17)       /* SDRAM Bank 3 Enable */
+
 #define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
 #define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
 #define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */