diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-13 18:52:48 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-13 18:52:48 -0400 |
commit | 95a17a23a2189512bc76e7a5901521129d7ae9c1 (patch) | |
tree | 90c7596ee675f2551bea3d4f3b1e62f9f82c679d | |
parent | 28db837693c84bc64e20d84aad00e2c0f206468a (diff) | |
parent | c640e8ca172c6a5c45abe8e2e8353900a84427fa (diff) |
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm/radeon: fix page flipping hangs on r300/r400
drm/radeon: add pageflip hooks for fusion
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 3 |
3 files changed, 5 insertions, 18 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 93fa735c8c1a..79de991e1ea3 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -70,23 +70,6 @@ MODULE_FIRMWARE(FIRMWARE_R520); | |||
70 | 70 | ||
71 | void r100_pre_page_flip(struct radeon_device *rdev, int crtc) | 71 | void r100_pre_page_flip(struct radeon_device *rdev, int crtc) |
72 | { | 72 | { |
73 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc]; | ||
74 | u32 tmp; | ||
75 | |||
76 | /* make sure flip is at vb rather than hb */ | ||
77 | tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset); | ||
78 | tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; | ||
79 | /* make sure pending bit is asserted */ | ||
80 | tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; | ||
81 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp); | ||
82 | |||
83 | /* set pageflip to happen as late as possible in the vblank interval. | ||
84 | * same field for crtc1/2 | ||
85 | */ | ||
86 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); | ||
87 | tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK; | ||
88 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); | ||
89 | |||
90 | /* enable the pflip int */ | 73 | /* enable the pflip int */ |
91 | radeon_irq_kms_pflip_irq_get(rdev, crtc); | 74 | radeon_irq_kms_pflip_irq_get(rdev, crtc); |
92 | } | 75 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index e75d63b8e21d..793c5e6026ad 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -834,6 +834,9 @@ static struct radeon_asic sumo_asic = { | |||
834 | .pm_finish = &evergreen_pm_finish, | 834 | .pm_finish = &evergreen_pm_finish, |
835 | .pm_init_profile = &rs780_pm_init_profile, | 835 | .pm_init_profile = &rs780_pm_init_profile, |
836 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | 836 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
837 | .pre_page_flip = &evergreen_pre_page_flip, | ||
838 | .page_flip = &evergreen_page_flip, | ||
839 | .post_page_flip = &evergreen_post_page_flip, | ||
837 | }; | 840 | }; |
838 | 841 | ||
839 | static struct radeon_asic btc_asic = { | 842 | static struct radeon_asic btc_asic = { |
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index cf0638c3b7c7..78968b738e88 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c | |||
@@ -443,7 +443,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, | |||
443 | (target_fb->bits_per_pixel * 8)); | 443 | (target_fb->bits_per_pixel * 8)); |
444 | crtc_pitch |= crtc_pitch << 16; | 444 | crtc_pitch |= crtc_pitch << 16; |
445 | 445 | ||
446 | 446 | crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; | |
447 | if (tiling_flags & RADEON_TILING_MACRO) { | 447 | if (tiling_flags & RADEON_TILING_MACRO) { |
448 | if (ASIC_IS_R300(rdev)) | 448 | if (ASIC_IS_R300(rdev)) |
449 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | | 449 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
@@ -502,6 +502,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, | |||
502 | gen_cntl_val = RREG32(gen_cntl_reg); | 502 | gen_cntl_val = RREG32(gen_cntl_reg); |
503 | gen_cntl_val &= ~(0xf << 8); | 503 | gen_cntl_val &= ~(0xf << 8); |
504 | gen_cntl_val |= (format << 8); | 504 | gen_cntl_val |= (format << 8); |
505 | gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; | ||
505 | WREG32(gen_cntl_reg, gen_cntl_val); | 506 | WREG32(gen_cntl_reg, gen_cntl_val); |
506 | 507 | ||
507 | crtc_offset = (u32)base; | 508 | crtc_offset = (u32)base; |