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authorLennert Buytenhek <buytenh@wantstofly.org>2006-09-18 18:17:36 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-25 05:25:41 -0400
commit7e9740b11529a0a69789fbe92d324f293e6266f6 (patch)
tree7ea94f603608744270756b56c668d658174a5b9b
parent0cb015f9dea8a40d82d170be1a4f39ff909890bf (diff)
[ARM] 3821/1: iop3xx: switch iop32x/iop33x over to shared pci code
Switch the iop32x and iop33x code over to the common PCI implementation, and remove the (nearly identical) iop32x and iop33x PCI implementations. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mach-iop32x/Makefile2
-rw-r--r--arch/arm/mach-iop32x/common.c6
-rw-r--r--arch/arm/mach-iop32x/iq31244-pci.c45
-rw-r--r--arch/arm/mach-iop32x/iq80321-pci.c45
-rw-r--r--arch/arm/mach-iop32x/irq.c2
-rw-r--r--arch/arm/mach-iop32x/pci.c220
-rw-r--r--arch/arm/mach-iop33x/Makefile2
-rw-r--r--arch/arm/mach-iop33x/common.c22
-rw-r--r--arch/arm/mach-iop33x/iq80331-pci.c45
-rw-r--r--arch/arm/mach-iop33x/iq80332-pci.c45
-rw-r--r--arch/arm/mach-iop33x/irq.c2
-rw-r--r--arch/arm/mach-iop33x/pci.c222
-rw-r--r--include/asm-arm/arch-iop32x/hardware.h20
-rw-r--r--include/asm-arm/arch-iop32x/iop321.h86
-rw-r--r--include/asm-arm/arch-iop32x/memory.h4
-rw-r--r--include/asm-arm/arch-iop32x/system.h2
-rw-r--r--include/asm-arm/arch-iop33x/hardware.h20
-rw-r--r--include/asm-arm/arch-iop33x/iop331.h96
-rw-r--r--include/asm-arm/arch-iop33x/memory.h4
-rw-r--r--include/asm-arm/arch-iop33x/system.h2
-rw-r--r--include/asm-arm/mach/pci.h8
21 files changed, 30 insertions, 870 deletions
diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile
index 94144f7efa6c..7266224ab6d7 100644
--- a/arch/arm/mach-iop32x/Makefile
+++ b/arch/arm/mach-iop32x/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := common.o setup.o irq.o pci.o time.o 5obj-y := common.o setup.o irq.o time.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/mach-iop32x/common.c b/arch/arm/mach-iop32x/common.c
index 17e7d650fecb..9a17a081327d 100644
--- a/arch/arm/mach-iop32x/common.c
+++ b/arch/arm/mach-iop32x/common.c
@@ -16,12 +16,6 @@
16#include <asm/hardware.h> 16#include <asm/hardware.h>
17#include <asm/hardware/iop3xx.h> 17#include <asm/hardware/iop3xx.h>
18 18
19/*
20 * Shared variables
21 */
22unsigned long iop3xx_pcibios_min_io = 0;
23unsigned long iop3xx_pcibios_min_mem = 0;
24
25#ifdef CONFIG_ARCH_EP80219 19#ifdef CONFIG_ARCH_EP80219
26#include <linux/kernel.h> 20#include <linux/kernel.h>
27/* 21/*
diff --git a/arch/arm/mach-iop32x/iq31244-pci.c b/arch/arm/mach-iop32x/iq31244-pci.c
index e447c8103ecd..605b79553747 100644
--- a/arch/arm/mach-iop32x/iq31244-pci.c
+++ b/arch/arm/mach-iop32x/iq31244-pci.c
@@ -67,51 +67,12 @@ iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
67 return PCI_IRQ_TABLE_LOOKUP(0, 7); 67 return PCI_IRQ_TABLE_LOOKUP(0, 7);
68} 68}
69 69
70static int iq31244_setup(int nr, struct pci_sys_data *sys)
71{
72 struct resource *res;
73
74 if(nr != 0)
75 return 0;
76
77 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
78 if (!res)
79 panic("PCI: unable to alloc resources");
80
81 res[0].start = IOP321_PCI_LOWER_IO_VA;
82 res[0].end = IOP321_PCI_UPPER_IO_VA;
83 res[0].name = "IQ31244 PCI I/O Space";
84 res[0].flags = IORESOURCE_IO;
85
86 res[1].start = IOP321_PCI_LOWER_MEM_PA;
87 res[1].end = IOP321_PCI_UPPER_MEM_PA;
88 res[1].name = "IQ31244 PCI Memory Space";
89 res[1].flags = IORESOURCE_MEM;
90
91 request_resource(&ioport_resource, &res[0]);
92 request_resource(&iomem_resource, &res[1]);
93
94 sys->mem_offset = IOP321_PCI_MEM_OFFSET;
95 sys->io_offset = IOP321_PCI_IO_OFFSET;
96
97 sys->resource[0] = &res[0];
98 sys->resource[1] = &res[1];
99 sys->resource[2] = NULL;
100
101 return 1;
102}
103
104static void iq31244_preinit(void)
105{
106 iop321_init();
107}
108
109static struct hw_pci iq31244_pci __initdata = { 70static struct hw_pci iq31244_pci __initdata = {
110 .swizzle = pci_std_swizzle, 71 .swizzle = pci_std_swizzle,
111 .nr_controllers = 1, 72 .nr_controllers = 1,
112 .setup = iq31244_setup, 73 .setup = iop3xx_pci_setup,
113 .scan = iop321_scan_bus, 74 .scan = iop3xx_pci_scan_bus,
114 .preinit = iq31244_preinit, 75 .preinit = iop3xx_pci_preinit,
115 .map_irq = iq31244_map_irq 76 .map_irq = iq31244_map_irq
116}; 77};
117 78
diff --git a/arch/arm/mach-iop32x/iq80321-pci.c b/arch/arm/mach-iop32x/iq80321-pci.c
index 8767950e131f..cedc37b968b7 100644
--- a/arch/arm/mach-iop32x/iq80321-pci.c
+++ b/arch/arm/mach-iop32x/iq80321-pci.c
@@ -61,51 +61,12 @@ iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
61 return pci_irq_table[idsel%4][pin-1]; 61 return pci_irq_table[idsel%4][pin-1];
62} 62}
63 63
64static int iq80321_setup(int nr, struct pci_sys_data *sys)
65{
66 struct resource *res;
67
68 if(nr != 0)
69 return 0;
70
71 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
72 if (!res)
73 panic("PCI: unable to alloc resources");
74
75 res[0].start = IOP321_PCI_LOWER_IO_VA;
76 res[0].end = IOP321_PCI_UPPER_IO_VA;
77 res[0].name = "IQ80321 PCI I/O Space";
78 res[0].flags = IORESOURCE_IO;
79
80 res[1].start = IOP321_PCI_LOWER_MEM_PA;
81 res[1].end = IOP321_PCI_UPPER_MEM_PA;
82 res[1].name = "IQ80321 PCI Memory Space";
83 res[1].flags = IORESOURCE_MEM;
84
85 request_resource(&ioport_resource, &res[0]);
86 request_resource(&iomem_resource, &res[1]);
87
88 sys->mem_offset = IOP321_PCI_MEM_OFFSET;
89 sys->io_offset = IOP321_PCI_IO_OFFSET;
90
91 sys->resource[0] = &res[0];
92 sys->resource[1] = &res[1];
93 sys->resource[2] = NULL;
94
95 return 1;
96}
97
98static void iq80321_preinit(void)
99{
100 iop321_init();
101}
102
103static struct hw_pci iq80321_pci __initdata = { 64static struct hw_pci iq80321_pci __initdata = {
104 .swizzle = pci_std_swizzle, 65 .swizzle = pci_std_swizzle,
105 .nr_controllers = 1, 66 .nr_controllers = 1,
106 .setup = iq80321_setup, 67 .setup = iop3xx_pci_setup,
107 .scan = iop321_scan_bus, 68 .scan = iop3xx_pci_scan_bus,
108 .preinit = iq80321_preinit, 69 .preinit = iop3xx_pci_preinit,
109 .map_irq = iq80321_map_irq 70 .map_irq = iq80321_map_irq
110}; 71};
111 72
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index c5f633d2d632..76f2d561dbc1 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -84,7 +84,7 @@ void __init iop321_init_irq(void)
84 intstr_write(0); // treat all as IRQ 84 intstr_write(0); // treat all as IRQ
85 if(machine_is_iq80321() || 85 if(machine_is_iq80321() ||
86 machine_is_iq31244()) // all interrupts are inputs to chip 86 machine_is_iq31244()) // all interrupts are inputs to chip
87 *IOP321_PCIIRSR = 0x0f; 87 *IOP3XX_PCIIRSR = 0x0f;
88 88
89 for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++) 89 for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++)
90 { 90 {
diff --git a/arch/arm/mach-iop32x/pci.c b/arch/arm/mach-iop32x/pci.c
deleted file mode 100644
index 1a7c683673f2..000000000000
--- a/arch/arm/mach-iop32x/pci.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/pci.c
3 *
4 * PCI support for the Intel IOP321 chipset
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20
21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/system.h>
24#include <asm/hardware.h>
25#include <asm/mach/pci.h>
26
27#include <asm/arch/iop321.h>
28
29// #define DEBUG
30
31#ifdef DEBUG
32#define DBG(x...) printk(x)
33#else
34#define DBG(x...) do { } while (0)
35#endif
36
37/*
38 * This routine builds either a type0 or type1 configuration command. If the
39 * bus is on the 80321 then a type0 made, else a type1 is created.
40 */
41static u32 iop321_cfg_address(struct pci_bus *bus, int devfn, int where)
42{
43 struct pci_sys_data *sys = bus->sysdata;
44 u32 addr;
45
46 if (sys->busnr == bus->number)
47 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
48 else
49 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
50
51 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
52
53 return addr;
54}
55
56/*
57 * This routine checks the status of the last configuration cycle. If an error
58 * was detected it returns a 1, else it returns a 0. The errors being checked
59 * are parity, master abort, target abort (master and target). These types of
60 * errors occure during a config cycle where there is no device, like during
61 * the discovery stage.
62 */
63static int iop321_pci_status(void)
64{
65 unsigned int status;
66 int ret = 0;
67
68 /*
69 * Check the status registers.
70 */
71 status = *IOP321_ATUSR;
72 if (status & 0xf900)
73 {
74 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
75 *IOP321_ATUSR = status & 0xf900;
76 ret = 1;
77 }
78 status = *IOP321_ATUISR;
79 if (status & 0x679f)
80 {
81 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
82 *IOP321_ATUISR = status & 0x679f;
83 ret = 1;
84 }
85 return ret;
86}
87
88/*
89 * Simply write the address register and read the configuration
90 * data. Note that the 4 nop's ensure that we are able to handle
91 * a delayed abort (in theory.)
92 */
93static inline u32 iop321_read(unsigned long addr)
94{
95 u32 val;
96
97 __asm__ __volatile__(
98 "str %1, [%2]\n\t"
99 "ldr %0, [%3]\n\t"
100 "nop\n\t"
101 "nop\n\t"
102 "nop\n\t"
103 "nop\n\t"
104 : "=r" (val)
105 : "r" (addr), "r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
106
107 return val;
108}
109
110/*
111 * The read routines must check the error status of the last configuration
112 * cycle. If there was an error, the routine returns all hex f's.
113 */
114static int
115iop321_read_config(struct pci_bus *bus, unsigned int devfn, int where,
116 int size, u32 *value)
117{
118 unsigned long addr = iop321_cfg_address(bus, devfn, where);
119 u32 val = iop321_read(addr) >> ((where & 3) * 8);
120
121 if( iop321_pci_status() )
122 val = 0xffffffff;
123
124 *value = val;
125
126 return PCIBIOS_SUCCESSFUL;
127}
128
129static int
130iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where,
131 int size, u32 value)
132{
133 unsigned long addr = iop321_cfg_address(bus, devfn, where);
134 u32 val;
135
136 if (size != 4) {
137 val = iop321_read(addr);
138 if (!iop321_pci_status() == 0)
139 return PCIBIOS_SUCCESSFUL;
140
141 where = (where & 3) * 8;
142
143 if (size == 1)
144 val &= ~(0xff << where);
145 else
146 val &= ~(0xffff << where);
147
148 *IOP321_OCCDR = val | value << where;
149 } else {
150 asm volatile(
151 "str %1, [%2]\n\t"
152 "str %0, [%3]\n\t"
153 "nop\n\t"
154 "nop\n\t"
155 "nop\n\t"
156 "nop\n\t"
157 :
158 : "r" (value), "r" (addr),
159 "r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
160 }
161
162 return PCIBIOS_SUCCESSFUL;
163}
164
165static struct pci_ops iop321_ops = {
166 .read = iop321_read_config,
167 .write = iop321_write_config,
168};
169
170/*
171 * When a PCI device does not exist during config cycles, the 80200 gets a
172 * bus error instead of returning 0xffffffff. This handler simply returns.
173 */
174int
175iop321_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
176{
177 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
178 addr, fsr, regs->ARM_pc, regs->ARM_lr);
179
180 /*
181 * If it was an imprecise abort, then we need to correct the
182 * return address to be _after_ the instruction.
183 */
184 if (fsr & (1 << 10))
185 regs->ARM_pc += 4;
186
187 return 0;
188}
189
190/*
191 * Scan an IOP321 PCI bus. sys->bus defines which bus we scan.
192 */
193struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys)
194{
195 return pci_scan_bus(sys->busnr, &iop321_ops, sys);
196}
197
198void iop321_init(void)
199{
200 DBG("PCI: Intel 80321 PCI init code.\n");
201 DBG("ATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD);
202 DBG("ATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n",
203 *IOP321_OMWTVR0,
204 *IOP321_OIOWTVR);
205 DBG("ATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR);
206 DBG("ATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n",
207 *IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0);
208 DBG("ATU: IOP321_OMWTVR0=0x%08x\n", *IOP321_OMWTVR0);
209 DBG("ATU: IOP321_IABAR1=0x%08x IOP321_IALR1=0x%08x\n",
210 *IOP321_IABAR1, *IOP321_IALR1);
211 DBG("ATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n",
212 *IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR);
213 DBG("ATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n",
214 *IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2);
215 DBG("ATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n",
216 *IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3);
217
218 hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort");
219}
220
diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile
index 7865923b0a60..6c74f13b1139 100644
--- a/arch/arm/mach-iop33x/Makefile
+++ b/arch/arm/mach-iop33x/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := common.o setup.o irq.o pci.o time.o 5obj-y := setup.o irq.o time.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/mach-iop33x/common.c b/arch/arm/mach-iop33x/common.c
deleted file mode 100644
index dd75f2b8e74f..000000000000
--- a/arch/arm/mach-iop33x/common.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * arch/arm/mach-iop33x/common.c
3 *
4 * Common routines shared across all IOP3xx implementations
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2003 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/delay.h>
16#include <asm/hardware.h>
17
18/*
19 * Shared variables
20 */
21unsigned long iop3xx_pcibios_min_io = 0;
22unsigned long iop3xx_pcibios_min_mem = 0;
diff --git a/arch/arm/mach-iop33x/iq80331-pci.c b/arch/arm/mach-iop33x/iq80331-pci.c
index 71adb12a9421..8b0bed5e2f91 100644
--- a/arch/arm/mach-iop33x/iq80331-pci.c
+++ b/arch/arm/mach-iop33x/iq80331-pci.c
@@ -57,51 +57,12 @@ iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
57 return PCI_IRQ_TABLE_LOOKUP(1, 7); 57 return PCI_IRQ_TABLE_LOOKUP(1, 7);
58} 58}
59 59
60static int iq80331_setup(int nr, struct pci_sys_data *sys)
61{
62 struct resource *res;
63
64 if(nr != 0)
65 return 0;
66
67 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
68 if (!res)
69 panic("PCI: unable to alloc resources");
70
71 res[0].start = IOP331_PCI_LOWER_IO_VA;
72 res[0].end = IOP331_PCI_UPPER_IO_VA;
73 res[0].name = "IQ80331 PCI I/O Space";
74 res[0].flags = IORESOURCE_IO;
75
76 res[1].start = IOP331_PCI_LOWER_MEM_PA;
77 res[1].end = IOP331_PCI_UPPER_MEM_PA;
78 res[1].name = "IQ80331 PCI Memory Space";
79 res[1].flags = IORESOURCE_MEM;
80
81 request_resource(&ioport_resource, &res[0]);
82 request_resource(&iomem_resource, &res[1]);
83
84 sys->mem_offset = IOP331_PCI_MEM_OFFSET;
85 sys->io_offset = IOP331_PCI_IO_OFFSET;
86
87 sys->resource[0] = &res[0];
88 sys->resource[1] = &res[1];
89 sys->resource[2] = NULL;
90
91 return 1;
92}
93
94static void iq80331_preinit(void)
95{
96 iop331_init();
97}
98
99static struct hw_pci iq80331_pci __initdata = { 60static struct hw_pci iq80331_pci __initdata = {
100 .swizzle = pci_std_swizzle, 61 .swizzle = pci_std_swizzle,
101 .nr_controllers = 1, 62 .nr_controllers = 1,
102 .setup = iq80331_setup, 63 .setup = iop3xx_pci_setup,
103 .scan = iop331_scan_bus, 64 .scan = iop3xx_pci_scan_bus,
104 .preinit = iq80331_preinit, 65 .preinit = iop3xx_pci_preinit,
105 .map_irq = iq80331_map_irq 66 .map_irq = iq80331_map_irq
106}; 67};
107 68
diff --git a/arch/arm/mach-iop33x/iq80332-pci.c b/arch/arm/mach-iop33x/iq80332-pci.c
index f3010f85b1a2..0de8aa748dd8 100644
--- a/arch/arm/mach-iop33x/iq80332-pci.c
+++ b/arch/arm/mach-iop33x/iq80332-pci.c
@@ -63,51 +63,12 @@ iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
63 return PCI_IRQ_TABLE_LOOKUP(1, 7); 63 return PCI_IRQ_TABLE_LOOKUP(1, 7);
64} 64}
65 65
66static int iq80332_setup(int nr, struct pci_sys_data *sys)
67{
68 struct resource *res;
69
70 if(nr != 0)
71 return 0;
72
73 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
74 if (!res)
75 panic("PCI: unable to alloc resources");
76
77 res[0].start = IOP331_PCI_LOWER_IO_VA;
78 res[0].end = IOP331_PCI_UPPER_IO_VA;
79 res[0].name = "IQ80332 PCI I/O Space";
80 res[0].flags = IORESOURCE_IO;
81
82 res[1].start = IOP331_PCI_LOWER_MEM_PA;
83 res[1].end = IOP331_PCI_UPPER_MEM_PA;
84 res[1].name = "IQ80332 PCI Memory Space";
85 res[1].flags = IORESOURCE_MEM;
86
87 request_resource(&ioport_resource, &res[0]);
88 request_resource(&iomem_resource, &res[1]);
89
90 sys->mem_offset = IOP331_PCI_MEM_OFFSET;
91 sys->io_offset = IOP331_PCI_IO_OFFSET;
92
93 sys->resource[0] = &res[0];
94 sys->resource[1] = &res[1];
95 sys->resource[2] = NULL;
96
97 return 1;
98}
99
100static void iq80332_preinit(void)
101{
102 iop331_init();
103}
104
105static struct hw_pci iq80332_pci __initdata = { 66static struct hw_pci iq80332_pci __initdata = {
106 .swizzle = pci_std_swizzle, 67 .swizzle = pci_std_swizzle,
107 .nr_controllers = 1, 68 .nr_controllers = 1,
108 .setup = iq80332_setup, 69 .setup = iop3xx_pci_setup,
109 .scan = iop331_scan_bus, 70 .scan = iop3xx_pci_scan_bus,
110 .preinit = iq80332_preinit, 71 .preinit = iop3xx_pci_preinit,
111 .map_irq = iq80332_map_irq 72 .map_irq = iq80332_map_irq
112}; 73};
113 74
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 029fa78876a5..bcffc33a5be8 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -117,7 +117,7 @@ void __init iop331_init_irq(void)
117 intstr_write0(0); // treat all as IRQ 117 intstr_write0(0); // treat all as IRQ
118 intstr_write1(0); 118 intstr_write1(0);
119 if(machine_is_iq80331()) // all interrupts are inputs to chip 119 if(machine_is_iq80331()) // all interrupts are inputs to chip
120 *IOP331_PCIIRSR = 0x0f; 120 *IOP3XX_PCIIRSR = 0x0f;
121 121
122 for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++) 122 for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++)
123 { 123 {
diff --git a/arch/arm/mach-iop33x/pci.c b/arch/arm/mach-iop33x/pci.c
deleted file mode 100644
index bf6aba91b47d..000000000000
--- a/arch/arm/mach-iop33x/pci.c
+++ /dev/null
@@ -1,222 +0,0 @@
1/*
2 * arch/arm/mach-iop33x/pci.c
3 *
4 * PCI support for the Intel IOP331 chipset
5 *
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20
21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/system.h>
24#include <asm/hardware.h>
25#include <asm/mach/pci.h>
26
27#include <asm/arch/iop331.h>
28
29#undef DEBUG
30#undef DEBUG1
31
32#ifdef DEBUG
33#define DBG(x...) printk(x)
34#else
35#define DBG(x...) do { } while (0)
36#endif
37
38#ifdef DEBUG1
39#define DBG1(x...) printk(x)
40#else
41#define DBG1(x...) do { } while (0)
42#endif
43
44/*
45 * This routine builds either a type0 or type1 configuration command. If the
46 * bus is on the 80331 then a type0 made, else a type1 is created.
47 */
48static u32 iop331_cfg_address(struct pci_bus *bus, int devfn, int where)
49{
50 struct pci_sys_data *sys = bus->sysdata;
51 u32 addr;
52
53 if (sys->busnr == bus->number)
54 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
55 else
56 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
57
58 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
59
60 return addr;
61}
62
63/*
64 * This routine checks the status of the last configuration cycle. If an error
65 * was detected it returns a 1, else it returns a 0. The errors being checked
66 * are parity, master abort, target abort (master and target). These types of
67 * errors occure during a config cycle where there is no device, like during
68 * the discovery stage.
69 */
70static int iop331_pci_status(void)
71{
72 unsigned int status;
73 int ret = 0;
74
75 /*
76 * Check the status registers.
77 */
78 status = *IOP331_ATUSR;
79 if (status & 0xf900)
80 {
81 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
82 *IOP331_ATUSR = status & 0xf900;
83 ret = 1;
84 }
85 status = *IOP331_ATUISR;
86 if (status & 0x679f)
87 {
88 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
89 *IOP331_ATUISR = status & 0x679f;
90 ret = 1;
91 }
92 return ret;
93}
94
95/*
96 * Simply write the address register and read the configuration
97 * data. Note that the 4 nop's ensure that we are able to handle
98 * a delayed abort (in theory.)
99 */
100static inline u32 iop331_read(unsigned long addr)
101{
102 u32 val;
103
104 __asm__ __volatile__(
105 "str %1, [%2]\n\t"
106 "ldr %0, [%3]\n\t"
107 "nop\n\t"
108 "nop\n\t"
109 "nop\n\t"
110 "nop\n\t"
111 : "=r" (val)
112 : "r" (addr), "r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
113
114 return val;
115}
116
117/*
118 * The read routines must check the error status of the last configuration
119 * cycle. If there was an error, the routine returns all hex f's.
120 */
121static int
122iop331_read_config(struct pci_bus *bus, unsigned int devfn, int where,
123 int size, u32 *value)
124{
125 unsigned long addr = iop331_cfg_address(bus, devfn, where);
126 u32 val = iop331_read(addr) >> ((where & 3) * 8);
127
128 if( iop331_pci_status() )
129 val = 0xffffffff;
130
131 *value = val;
132
133 return PCIBIOS_SUCCESSFUL;
134}
135
136static int
137iop331_write_config(struct pci_bus *bus, unsigned int devfn, int where,
138 int size, u32 value)
139{
140 unsigned long addr = iop331_cfg_address(bus, devfn, where);
141 u32 val;
142
143 if (size != 4) {
144 val = iop331_read(addr);
145 if (!iop331_pci_status() == 0)
146 return PCIBIOS_SUCCESSFUL;
147
148 where = (where & 3) * 8;
149
150 if (size == 1)
151 val &= ~(0xff << where);
152 else
153 val &= ~(0xffff << where);
154
155 *IOP331_OCCDR = val | value << where;
156 } else {
157 asm volatile(
158 "str %1, [%2]\n\t"
159 "str %0, [%3]\n\t"
160 "nop\n\t"
161 "nop\n\t"
162 "nop\n\t"
163 "nop\n\t"
164 :
165 : "r" (value), "r" (addr),
166 "r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
167 }
168
169 return PCIBIOS_SUCCESSFUL;
170}
171
172static struct pci_ops iop331_ops = {
173 .read = iop331_read_config,
174 .write = iop331_write_config,
175};
176
177/*
178 * When a PCI device does not exist during config cycles, the XScale gets a
179 * bus error instead of returning 0xffffffff. This handler simply returns.
180 */
181int
182iop331_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
183{
184 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
185 addr, fsr, regs->ARM_pc, regs->ARM_lr);
186
187 /*
188 * If it was an imprecise abort, then we need to correct the
189 * return address to be _after_ the instruction.
190 */
191 if (fsr & (1 << 10))
192 regs->ARM_pc += 4;
193
194 return 0;
195}
196
197/*
198 * Scan an IOP331 PCI bus. sys->bus defines which bus we scan.
199 */
200struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys)
201{
202 return pci_scan_bus(sys->busnr, &iop331_ops, sys);
203}
204
205void iop331_init(void)
206{
207 DBG1("PCI: Intel 80331 PCI init code.\n");
208 DBG1("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD);
209 DBG1("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n",
210 *IOP331_OMWTVR0,
211 *IOP331_OIOWTVR);
212 DBG1("\tATU: IOP331_OMWTVR1=0x%04x\n", *IOP331_OMWTVR1);
213 DBG1("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR);
214 DBG1("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0);
215 DBG1("\tATU: IOP31_IABAR1=0x%08x IOP331_IALR1=0x%08x\n", *IOP331_IABAR1, *IOP331_IALR1);
216 DBG1("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR);
217 DBG1("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2);
218 DBG1("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3);
219
220 hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort");
221}
222
diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h
index 8fb10134a107..16d0630ab252 100644
--- a/include/asm-arm/arch-iop32x/hardware.h
+++ b/include/asm-arm/arch-iop32x/hardware.h
@@ -19,27 +19,11 @@
19 */ 19 */
20 20
21#define pcibios_assign_all_busses() 1 21#define pcibios_assign_all_busses() 1
22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000
22 24
23 25
24/* 26/*
25 * The min PCI I/O and MEM space are dependent on what specific
26 * chipset/platform we are running on, so instead of hardcoding with
27 * #ifdefs, we just fill these in the platform level PCI init code.
28 */
29#ifndef __ASSEMBLY__
30extern unsigned long iop3xx_pcibios_min_io;
31extern unsigned long iop3xx_pcibios_min_mem;
32
33extern unsigned int processor_id;
34#endif
35
36/*
37 * We just set these to zero since they are really bogus anyways
38 */
39#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
40#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
41
42/*
43 * Generic chipset bits 27 * Generic chipset bits
44 * 28 *
45 */ 29 */
diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h
index 1a82dd96bf50..e3c85a05e73a 100644
--- a/include/asm-arm/arch-iop32x/iop321.h
+++ b/include/asm-arm/arch-iop32x/iop321.h
@@ -25,27 +25,6 @@
25#endif 25#endif
26 26
27/* 27/*
28 * IOP321 I/O and Mem space regions for PCI autoconfiguration
29 */
30#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000
31#define IOP321_PCI_LOWER_IO_PA 0x90000000
32#define IOP321_PCI_LOWER_IO_VA 0xfe000000
33#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR)
34#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
35#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
36#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
37#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
38
39/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */
40#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
41#define IOP321_PCI_LOWER_MEM_PA 0x80000000
42#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
43#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
44#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
45#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
46
47
48/*
49 * IOP321 chipset registers 28 * IOP321 chipset registers
50 */ 29 */
51#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ 30#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
@@ -55,69 +34,6 @@
55/* Reserved 0x00000000 through 0x000000FF */ 34/* Reserved 0x00000000 through 0x000000FF */
56 35
57/* Address Translation Unit 0x00000100 through 0x000001FF */ 36/* Address Translation Unit 0x00000100 through 0x000001FF */
58#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100)
59#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102)
60#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104)
61#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106)
62#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108)
63#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109)
64#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C)
65#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D)
66#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E)
67#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F)
68#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110)
69#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114)
70#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118)
71#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C)
72#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120)
73#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124)
74#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C)
75#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E)
76#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130)
77/* Reserved 0x00000134 through 0x0000013B */
78#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C)
79#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D)
80#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E)
81#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F)
82#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140)
83#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144)
84#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148)
85#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C)
86#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150)
87#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154)
88#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158)
89#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C)
90#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160)
91#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164)
92#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168)
93#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C)
94/* Reserved 0x00000170 through 0x00000177*/
95#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178)
96/* Reserved 0x0000017C through 0x0000017F*/
97#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180)
98#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184)
99#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188)
100#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C)
101#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190)
102#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194)
103#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198)
104#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C)
105/* Reserved 0x000001A0 through 0x000001A3*/
106#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4)
107/* Reserved 0x000001A8 through 0x000001AB*/
108#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC)
109/* Reserved 0x000001B0 through 0x000001BB*/
110#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC)
111#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0)
112#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1)
113#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2)
114#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4)
115/* Reserved 0x000001C6 through 0x000001DF */
116#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0)
117#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1)
118#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2)
119#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4)
120#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
121 37
122/* Messaging Unit 0x00000300 through 0x000003FF */ 38/* Messaging Unit 0x00000300 through 0x000003FF */
123 39
@@ -317,6 +233,8 @@
317 233
318/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ 234/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
319 235
236#include <asm/hardware/iop3xx.h>
237
320 238
321#ifndef __ASSEMBLY__ 239#ifndef __ASSEMBLY__
322extern void iop321_init_irq(void); 240extern void iop321_init_irq(void);
diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h
index b4073f15b405..4c64d9e7229b 100644
--- a/include/asm-arm/arch-iop32x/memory.h
+++ b/include/asm-arm/arch-iop32x/memory.h
@@ -20,8 +20,8 @@
20 * to an address that the kernel can use. 20 * to an address that the kernel can use.
21 */ 21 */
22 22
23#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0)) 23#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
24#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2))) 24#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
25 25
26 26
27#endif 27#endif
diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h
index d4c8d691e1b0..1ac207a0d52e 100644
--- a/include/asm-arm/arch-iop32x/system.h
+++ b/include/asm-arm/arch-iop32x/system.h
@@ -16,7 +16,7 @@ static inline void arch_idle(void)
16 16
17static inline void arch_reset(char mode) 17static inline void arch_reset(char mode)
18{ 18{
19 *IOP321_PCSR = 0x30; 19 *IOP3XX_PCSR = 0x30;
20 20
21 if ( 1 && mode == 's') { 21 if ( 1 && mode == 's') {
22 /* Jump into ROM at address 0 */ 22 /* Jump into ROM at address 0 */
diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h
index 4a457084c5c6..5e3cb32af020 100644
--- a/include/asm-arm/arch-iop33x/hardware.h
+++ b/include/asm-arm/arch-iop33x/hardware.h
@@ -19,27 +19,11 @@
19 */ 19 */
20 20
21#define pcibios_assign_all_busses() 1 21#define pcibios_assign_all_busses() 1
22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000
22 24
23 25
24/* 26/*
25 * The min PCI I/O and MEM space are dependent on what specific
26 * chipset/platform we are running on, so instead of hardcoding with
27 * #ifdefs, we just fill these in the platform level PCI init code.
28 */
29#ifndef __ASSEMBLY__
30extern unsigned long iop3xx_pcibios_min_io;
31extern unsigned long iop3xx_pcibios_min_mem;
32
33extern unsigned int processor_id;
34#endif
35
36/*
37 * We just set these to zero since they are really bogus anyways
38 */
39#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
40#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
41
42/*
43 * Generic chipset bits 27 * Generic chipset bits
44 * 28 *
45 */ 29 */
diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h
index a7f47122c5e1..e85e1a2e1a86 100644
--- a/include/asm-arm/arch-iop33x/iop331.h
+++ b/include/asm-arm/arch-iop33x/iop331.h
@@ -24,27 +24,6 @@
24#endif 24#endif
25 25
26/* 26/*
27 * IOP331 I/O and Mem space regions for PCI autoconfiguration
28 */
29#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000
30#define IOP331_PCI_LOWER_IO_PA 0x90000000
31#define IOP331_PCI_LOWER_IO_VA 0xfe000000
32#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR)
33#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
34#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
35#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
36#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
37
38/* this can be 128M if OMWTVR1 is set */
39#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
40/* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */
41#define IOP331_PCI_LOWER_MEM_PA 0x80000000
42#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0)
43#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
44#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
45#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
46
47/*
48 * IOP331 chipset registers 27 * IOP331 chipset registers
49 */ 28 */
50#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ 29#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
@@ -54,79 +33,6 @@
54/* Reserved 0x00000000 through 0x000000FF */ 33/* Reserved 0x00000000 through 0x000000FF */
55 34
56/* Address Translation Unit 0x00000100 through 0x000001FF */ 35/* Address Translation Unit 0x00000100 through 0x000001FF */
57#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100)
58#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102)
59#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104)
60#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106)
61#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108)
62#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109)
63#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C)
64#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D)
65#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E)
66#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F)
67#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110)
68#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114)
69#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118)
70#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
71#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120)
72#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124)
73#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
74#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
75#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130)
76#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
77/* Reserved 0x00000138 through 0x0000013B */
78#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C)
79#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D)
80#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E)
81#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F)
82#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140)
83#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144)
84#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148)
85#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
86#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150)
87#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154)
88#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158)
89#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
90#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160)
91#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164)
92#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168)
93#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
94/* Reserved 0x00000170 through 0x00000177*/
95#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178)
96/* Reserved 0x0000017C through 0x0000017F*/
97#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180)
98#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184)
99#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188)
100#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
101#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190)
102#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194)
103#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198)
104#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
105/* Reserved 0x000001A0 through 0x000001A3*/
106#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
107/* Reserved 0x000001A8 through 0x000001AB*/
108#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
109/* Reserved 0x000001B0 through 0x000001BB*/
110#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
111#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
112#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
113#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
114#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
115#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
116#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
117#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
118/* Reserved 0x000001C6 through 0x000001CF */
119#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
120#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
121#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
122#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
123#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
124#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
125#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
126#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
127#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
128#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
129#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
130 36
131/* Messaging Unit 0x00000300 through 0x000003FF */ 37/* Messaging Unit 0x00000300 through 0x000003FF */
132 38
@@ -332,6 +238,8 @@
332 238
333/* Reserved 0x0000178c through 0x000019ff */ 239/* Reserved 0x0000178c through 0x000019ff */
334 240
241#include <asm/hardware/iop3xx.h>
242
335 243
336#ifndef __ASSEMBLY__ 244#ifndef __ASSEMBLY__
337extern void iop331_init_irq(void); 245extern void iop331_init_irq(void);
diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h
index 5e47164934ce..de208d2cca4e 100644
--- a/include/asm-arm/arch-iop33x/memory.h
+++ b/include/asm-arm/arch-iop33x/memory.h
@@ -19,8 +19,8 @@
19 * bus_to_virt: Used to convert an address for DMA operations 19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use. 20 * to an address that the kernel can use.
21 */ 21 */
22#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0)) 22#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
23#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2))) 23#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
24 24
25 25
26#endif 26#endif
diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h
index 43cc787ea629..8270ad9f86c8 100644
--- a/include/asm-arm/arch-iop33x/system.h
+++ b/include/asm-arm/arch-iop33x/system.h
@@ -16,7 +16,7 @@ static inline void arch_idle(void)
16 16
17static inline void arch_reset(char mode) 17static inline void arch_reset(char mode)
18{ 18{
19 *IOP331_PCSR = 0x30; 19 *IOP3XX_PCSR = 0x30;
20 20
21 if ( 1 && mode == 's') { 21 if ( 1 && mode == 's') {
22 /* Jump into ROM at address 0 */ 22 /* Jump into ROM at address 0 */
diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h
index cb41defad4a1..24621c49a0c7 100644
--- a/include/asm-arm/mach/pci.h
+++ b/include/asm-arm/mach/pci.h
@@ -56,14 +56,6 @@ extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
56extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); 56extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
57extern void iop3xx_pci_preinit(void); 57extern void iop3xx_pci_preinit(void);
58 58
59extern int iop321_setup(int nr, struct pci_sys_data *);
60extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
61extern void iop321_init(void);
62
63extern int iop331_setup(int nr, struct pci_sys_data *);
64extern struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *);
65extern void iop331_init(void);
66
67extern int dc21285_setup(int nr, struct pci_sys_data *); 59extern int dc21285_setup(int nr, struct pci_sys_data *);
68extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); 60extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
69extern void dc21285_preinit(void); 61extern void dc21285_preinit(void);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 06:12:30 -0500