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authorPaul Mundt <lethal@linux-sh.org>2010-02-08 02:36:56 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-02-08 02:36:56 -0500
commit7561f2dd393bd0c6397e6b2a6b021cdb827a2eb1 (patch)
tree71b58308f1383ef54bd6418a8243c047b3434519
parent13fd7aeb9af0a106905757369362137996f3feb0 (diff)
sh: Fix up SH7786 PCI resource definitions.
This adds in some of the missing memory resources for channels 1/2 and gets the code building again for the recent changes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.c112
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.h38
2 files changed, 63 insertions, 87 deletions
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index feac1fef21eb..95d095f26d66 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Low-Level PCI Express Support for the SH7786 2 * Low-Level PCI Express Support for the SH7786
3 * 3 *
4 * Copyright (C) 2009 Paul Mundt 4 * Copyright (C) 2009 - 2010 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -30,60 +30,84 @@ static struct sh7786_pcie_hwops {
30 int (*port_init_hw)(struct sh7786_pcie_port *port); 30 int (*port_init_hw)(struct sh7786_pcie_port *port);
31} *sh7786_pcie_hwops; 31} *sh7786_pcie_hwops;
32 32
33static struct resource sh7786_pci_32bit_mem_resources[] = { 33static struct resource sh7786_pci0_resources[] = {
34 { 34 {
35 .name = "pci0_mem", 35 .name = "PCIe0 IO",
36 .start = SH4A_PCIMEM_BASEA, 36 .start = 0xfd000000,
37 .end = SH4A_PCIMEM_BASEA + SZ_64M - 1, 37 .end = 0xfd000000 + SZ_8M - 1,
38 .flags = IORESOURCE_MEM, 38 .flags = IORESOURCE_IO,
39 }, { 39 }, {
40 .name = "pci1_mem", 40 .name = "PCIe0 MEM 0",
41 .start = SH4A_PCIMEM_BASEA1, 41 .start = 0xc0000000,
42 .end = SH4A_PCIMEM_BASEA1 + SZ_64M - 1, 42 .end = 0xc0000000 + SZ_512M - 1,
43 .flags = IORESOURCE_MEM, 43 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
44 }, { 44 }, {
45 .name = "pci2_mem", 45 .name = "PCIe0 MEM 1",
46 .start = SH4A_PCIMEM_BASEA2, 46 .start = 0x10000000,
47 .end = SH4A_PCIMEM_BASEA2 + SZ_64M - 1, 47 .end = 0x10000000 + SZ_64M - 1,
48 .flags = IORESOURCE_MEM, 48 .flags = IORESOURCE_MEM,
49 }, {
50 .name = "PCIe0 MEM 2",
51 .start = 0xfe100000,
52 .end = 0xfe100000 + SZ_1M - 1,
49 }, 53 },
50}; 54};
51 55
52static struct resource sh7786_pci_29bit_mem_resource = { 56static struct resource sh7786_pci1_resources[] = {
53 .start = SH4A_PCIMEM_BASE, 57 {
54 .end = SH4A_PCIMEM_BASE + SZ_64M - 1, 58 .name = "PCIe1 IO",
55 .flags = IORESOURCE_MEM, 59 .start = 0xfd800000,
60 .end = 0xfd800000 + SZ_8M - 1,
61 .flags = IORESOURCE_IO,
62 }, {
63 .name = "PCIe1 MEM 0",
64 .start = 0xa0000000,
65 .end = 0xa0000000 + SZ_512M - 1,
66 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
67 }, {
68 .name = "PCIe1 MEM 1",
69 .start = 0x30000000,
70 .end = 0x30000000 + SZ_256M - 1,
71 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
72 }, {
73 .name = "PCIe1 MEM 2",
74 .start = 0xfe300000,
75 .end = 0xfe300000 + SZ_1M - 1,
76 },
56}; 77};
57 78
58static struct resource sh7786_pci_io_resources[] = { 79static struct resource sh7786_pci2_resources[] = {
59 { 80 {
60 .name = "pci0_io", 81 .name = "PCIe2 IO",
61 .start = SH4A_PCIIO_BASE, 82 .start = 0xfc800000,
62 .end = SH4A_PCIIO_BASE + SZ_8M - 1, 83 .end = 0xfc800000 + SZ_4M - 1,
63 .flags = IORESOURCE_IO,
64 }, { 84 }, {
65 .name = "pci1_io", 85 .name = "PCIe2 MEM 0",
66 .start = SH4A_PCIIO_BASE1, 86 .start = 0x80000000,
67 .end = SH4A_PCIIO_BASE1 + SZ_8M - 1, 87 .end = 0x80000000 + SZ_512M - 1,
68 .flags = IORESOURCE_IO, 88 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
69 }, { 89 }, {
70 .name = "pci2_io", 90 .name = "PCIe2 MEM 1",
71 .start = SH4A_PCIIO_BASE2, 91 .start = 0x20000000,
72 .end = SH4A_PCIIO_BASE2 + SZ_4M - 1, 92 .end = 0x20000000 + SZ_256M - 1,
73 .flags = IORESOURCE_IO, 93 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
94 }, {
95 .name = "PCIe2 MEM 2",
96 .start = 0xfcd00000,
97 .end = 0xfcd00000 + SZ_1M - 1,
74 }, 98 },
75}; 99};
76 100
77extern struct pci_ops sh7786_pci_ops; 101extern struct pci_ops sh7786_pci_ops;
78 102
79#define DEFINE_CONTROLLER(start, idx) \ 103#define DEFINE_CONTROLLER(start, idx) \
80{ \ 104{ \
81 .pci_ops = &sh7786_pci_ops, \ 105 .pci_ops = &sh7786_pci_ops, \
82 .reg_base = start, \ 106 .resources = sh7786_pci##idx##_resources, \
83 /* mem_resource filled in at probe time */ \ 107 .nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
84 .mem_offset = 0, \ 108 .reg_base = start, \
85 .io_resource = &sh7786_pci_io_resources[idx], \ 109 .mem_offset = 0, \
86 .io_offset = 0, \ 110 .io_offset = 0, \
87} 111}
88 112
89static struct pci_channel sh7786_pci_channels[] = { 113static struct pci_channel sh7786_pci_channels[] = {
@@ -330,17 +354,7 @@ static int __init sh7786_pcie_init(void)
330 354
331 port->index = i; 355 port->index = i;
332 port->hose = sh7786_pci_channels + i; 356 port->hose = sh7786_pci_channels + i;
333 port->hose->io_map_base = port->hose->io_resource->start; 357 port->hose->io_map_base = port->hose->resources[0].start;
334
335 /*
336 * Check if we are booting in 29 or 32-bit mode
337 *
338 * 32-bit mode provides each controller with its own
339 * memory window, while 29-bit mode uses a shared one.
340 */
341 port->hose->mem_resource = test_mode_pin(MODE_PIN10) ?
342 &sh7786_pci_32bit_mem_resources[i] :
343 &sh7786_pci_29bit_mem_resource;
344 358
345 ret |= sh7786_pcie_hwops->port_init_hw(port); 359 ret |= sh7786_pcie_hwops->port_init_hw(port);
346 } 360 }
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
index c655290a7750..6666ea29cba8 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.h
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -30,47 +30,9 @@
30 * for other(Max Payload Size=4096B,PCIIO_SIZE=8M) 30 * for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
31 */ 31 */
32 32
33/* PCI0-0: PCI I/O space */
34#define SH4A_PCIIO_BASE 0xFD000000 /* PCI I/O for controller 0 */
35#define SH4A_PCIIO_BASE1 0xFD800000 /* PCI I/O for controller 1 (Rev1.14)*/
36#define SH4A_PCIIO_BASE2 0xFC800000 /* PCI I/O for controller 2 (Rev1.171)*/
37
38#define SH4A_PCIIO_SIZE64 0x00010000 /* PLX allows only 64K */
39#define SH4A_PCIIO_SIZE 0x00800000 /* 8M */
40#define SH4A_PCIIO_SIZE2 0x00400000 /* 4M (Rev1.171)*/
41
42/* PCI0-1: PCI memory space 29-bit address */
43#define SH4A_PCIMEM_BASE 0x10000000
44#define SH4A_PCIMEM_SIZE 0x04000000 /* 64M */
45
46/* PCI0-2: PCI memory space 32-bit address */
47#define SH4A_PCIMEM_BASEA 0xC0000000 /* for controller 0 */
48#define SH4A_PCIMEM_BASEA1 0xA0000000 /* for controller 1 (Rev1.14)*/
49#define SH4A_PCIMEM_BASEA2 0x80000000 /* for controller 2 (Rev1.171)*/
50#define SH4A_PCIMEM_SIZEA 0x20000000 /* 512M */
51
52/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/ 33/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
53#define SH4A_PCIBMSTR_TRANSLATION 0x20000000 34#define SH4A_PCIBMSTR_TRANSLATION 0x20000000
54 35
55#define SH4A_PCI_DEVICE_ID 0x0002
56#define SH4A_PCI_VENDOR_ID 0x1912
57
58// PCI compatible 000-03f
59#define PCI_CMD 0x004
60#define PCI_RID 0x008
61#define PCI_IBAR 0x010
62#define PCI_MBAR0 0x014
63#define PCI_MBAR1 0x018
64
65/* PCI power management/MSI/capablity 040-0ff */
66/* PCIE extended 100-fff */
67
68/* SH7786 device identification */ // Rev1.171
69#define SH4A_PVR (0xFF000030)
70#define SH4A_PVR_SHX3 (0x10400000)
71#define SH4A_PRR (0xFF000044)
72#define SH4A_PRR_SH7786 (0x00000400) // Rev1.171
73
74/* SPVCR0 */ 36/* SPVCR0 */
75#define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */ 37#define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */
76#define BITS_TOP_MB (24) 38#define BITS_TOP_MB (24)
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 14:24:55 -0400