diff options
author | Stephane Eranian <eranian@hpl.hp.com> | 2006-12-06 20:14:11 -0500 |
---|---|---|
committer | Andi Kleen <andi@basil.nowhere.org> | 2006-12-06 20:14:11 -0500 |
commit | 538f188e03c821c93b355c9fc346806cdd34e286 (patch) | |
tree | 4fa4a37d35444a51a30722a2af8f8f57ea11449d | |
parent | ee58fad51a2a767cb2567706ace967705233d881 (diff) |
[PATCH] i386: i386 add Intel BTS cpufeature bit and detection (take 2)
Here is a small patch for i386 which adds a cpufeature flag and
detection code for Intel's Branch Trace Store (BTS) feature. This
feature can be found on Intel P4 and Core 2 processors among others.
It can also be used by perfmon.
changelog:
- add CPU_FEATURE_BTS
- add Branch Trace Store detection
signed-off-by: stephane eranian <eranian@hpl.hp.com>
Signed-off-by: Andi Kleen <ak@suse.de>
-rw-r--r-- | arch/i386/kernel/cpu/intel.c | 2 | ||||
-rw-r--r-- | include/asm-i386/cpufeature.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c index 3ae795e9056d..56fe26584957 100644 --- a/arch/i386/kernel/cpu/intel.c +++ b/arch/i386/kernel/cpu/intel.c | |||
@@ -199,6 +199,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) | |||
199 | if (cpu_has_ds) { | 199 | if (cpu_has_ds) { |
200 | unsigned int l1; | 200 | unsigned int l1; |
201 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | 201 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); |
202 | if (!(l1 & (1<<11))) | ||
203 | set_bit(X86_FEATURE_BTS, c->x86_capability); | ||
202 | if (!(l1 & (1<<12))) | 204 | if (!(l1 & (1<<12))) |
203 | set_bit(X86_FEATURE_PEBS, c->x86_capability); | 205 | set_bit(X86_FEATURE_PEBS, c->x86_capability); |
204 | } | 206 | } |
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index 4c83e059228f..3f92b94e0d75 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h | |||
@@ -74,6 +74,7 @@ | |||
74 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ | 74 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ |
75 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ | 75 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
76 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ | 76 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
77 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | ||
77 | 78 | ||
78 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 79 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
79 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | 80 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |
@@ -138,6 +139,7 @@ | |||
138 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) | 139 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) |
139 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) | 140 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) |
140 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) | 141 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) |
142 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) | ||
141 | 143 | ||
142 | #endif /* __ASM_I386_CPUFEATURE_H */ | 144 | #endif /* __ASM_I386_CPUFEATURE_H */ |
143 | 145 | ||