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authorJongpill Lee <boyko.lee@samsung.com>2010-08-27 04:53:26 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-08-27 05:29:27 -0400
commit3297c2e6d7c3b1498b28c93141056cbe96444fde (patch)
treed6dd6d0e0208c4571b918de205c33dbac0dedd6a
parent5a847b4af8057f0297356824f793988d311d7aa0 (diff)
ARM: S5PV310: Bug fix on uclk1 and sclk_pwm
This patch fixes on enable and ctrlbit of uclk1 and sclk_pwm. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--arch/arm/mach-s5pv310/clock.c21
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-clock.h2
2 files changed, 15 insertions, 8 deletions
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 165c8bf412b2..26a0f03df8ea 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -30,6 +30,11 @@ static struct clk clk_sclk_hdmi27m = {
30 .rate = 27000000, 30 .rate = 27000000,
31}; 31};
32 32
33static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
34{
35 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
36}
37
33static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) 38static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
34{ 39{
35 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); 40 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
@@ -397,7 +402,7 @@ static struct clksrc_clk clksrcs[] = {
397 .clk = { 402 .clk = {
398 .name = "uclk1", 403 .name = "uclk1",
399 .id = 0, 404 .id = 0,
400 .enable = s5pv310_clk_ip_peril_ctrl, 405 .enable = s5pv310_clksrc_mask_peril0_ctrl,
401 .ctrlbit = (1 << 0), 406 .ctrlbit = (1 << 0),
402 }, 407 },
403 .sources = &clkset_group, 408 .sources = &clkset_group,
@@ -407,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
407 .clk = { 412 .clk = {
408 .name = "uclk1", 413 .name = "uclk1",
409 .id = 1, 414 .id = 1,
410 .enable = s5pv310_clk_ip_peril_ctrl, 415 .enable = s5pv310_clksrc_mask_peril0_ctrl,
411 .ctrlbit = (1 << 1), 416 .ctrlbit = (1 << 4),
412 }, 417 },
413 .sources = &clkset_group, 418 .sources = &clkset_group,
414 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, 419 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@@ -417,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
417 .clk = { 422 .clk = {
418 .name = "uclk1", 423 .name = "uclk1",
419 .id = 2, 424 .id = 2,
420 .enable = s5pv310_clk_ip_peril_ctrl, 425 .enable = s5pv310_clksrc_mask_peril0_ctrl,
421 .ctrlbit = (1 << 2), 426 .ctrlbit = (1 << 8),
422 }, 427 },
423 .sources = &clkset_group, 428 .sources = &clkset_group,
424 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, 429 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@@ -427,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
427 .clk = { 432 .clk = {
428 .name = "uclk1", 433 .name = "uclk1",
429 .id = 3, 434 .id = 3,
430 .enable = s5pv310_clk_ip_peril_ctrl, 435 .enable = s5pv310_clksrc_mask_peril0_ctrl,
431 .ctrlbit = (1 << 3), 436 .ctrlbit = (1 << 12),
432 }, 437 },
433 .sources = &clkset_group, 438 .sources = &clkset_group,
434 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, 439 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@@ -437,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
437 .clk = { 442 .clk = {
438 .name = "sclk_pwm", 443 .name = "sclk_pwm",
439 .id = -1, 444 .id = -1,
440 .enable = s5pv310_clk_ip_peril_ctrl, 445 .enable = s5pv310_clksrc_mask_peril0_ctrl,
441 .ctrlbit = (1 << 24), 446 .ctrlbit = (1 << 24),
442 }, 447 },
443 .sources = &clkset_group, 448 .sources = &clkset_group,
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index 7727b4563a26..4013553cd9be 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -38,6 +38,8 @@
38#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) 38#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
39#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) 39#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
40 40
41#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
42
41#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 43#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
42 44
43#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) 45#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)