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authorJeff Garzik <jeff@garzik.org>2009-04-07 19:18:32 -0400
committerJeff Garzik <jgarzik@redhat.com>2009-09-01 19:47:19 -0400
commit2fc37adba0fb05760b8635c6706773af828ccf3c (patch)
tree821acd350a7e315481b0bf8f2478797dbb946588
parent54c38444fad6a99b4b19512f8f0055d69115e69e (diff)
[libata] sata_sil: disable DMA engine in sil_freeze()
We must disable the DMA engine before accessing taskfile registers. Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
-rw-r--r--drivers/ata/sata_sil.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index 35bd5cc7f285..3cb69d5fb817 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -565,6 +565,19 @@ static void sil_freeze(struct ata_port *ap)
565 tmp |= SIL_MASK_IDE0_INT << ap->port_no; 565 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
566 writel(tmp, mmio_base + SIL_SYSCFG); 566 writel(tmp, mmio_base + SIL_SYSCFG);
567 readl(mmio_base + SIL_SYSCFG); /* flush */ 567 readl(mmio_base + SIL_SYSCFG); /* flush */
568
569 /* Ensure DMA_ENABLE is off.
570 *
571 * This is because the controller will not give us access to the
572 * taskfile registers while a DMA is in progress
573 */
574 iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE,
575 ap->ioaddr.bmdma_addr);
576
577 /* According to ata_bmdma_stop, an HDMA transition requires
578 * on PIO cycle. But we can't read a taskfile register.
579 */
580 ioread8(ap->ioaddr.bmdma_addr);
568} 581}
569 582
570static void sil_thaw(struct ata_port *ap) 583static void sil_thaw(struct ata_port *ap)