[ARM] 3400/1: lpd7a40x: platform headers update

Patch from Marc Singer

Updates to the lpd7a40x platform headers.  Includes support for new
architecture, lpd7a400.

Signed-off-by: Marc Singer <elf@buici.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

10 files changed, 581 insertions, 21 deletions

diff --git a/arch/arm/mach-lh7a40x/common.h b/arch/arm/mach-lh7a40x/common.h
index ea8de7e3ab1b..18e8bb4eb202 100644
--- a/arch/arm/mach-lh7a40x/common.h
+++ b/arch/arm/mach-lh7a40x/common.h
@@ -12,6 +12,7 @@ extern struct sys_timer lh7a40x_timer;
 
 extern void lh7a400_init_irq (void);
 extern void lh7a404_init_irq (void);
+extern void lh7a40x_clcd_init (void);
 extern void lh7a40x_init_board_irq (void);
 
 #define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq), regs)
diff --git a/arch/arm/mach-lh7a40x/lcd-panel.h b/arch/arm/mach-lh7a40x/lcd-panel.h
new file mode 100644
index 000000000000..4fb2efc4950f
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/lcd-panel.h
@@ -0,0 +1,346 @@
+/* lcd-panel.h
+     $Id$
+
+   written by Marc Singer
+   18 Jul 2005
+
+   Copyright (C) 2005 Marc Singer
+
+   -----------
+   DESCRIPTION
+   -----------
+
+   Only one panel may be defined at a time.
+
+   The pixel clock is calculated to be no greater than the target.
+
+   Each timing value is accompanied by a specification comment.
+
+     UNITS/MIN/TYP/MAX
+
+   Most of the units will be in clocks.
+
+   USE_RGB555
+
+     Define this macro to configure the AMBA LCD controller to use an
+     RGB555 encoding for the pels instead of the normal RGB565.
+
+   LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11
+
+     These boards are best approximated by 555 for all panels.  Some
+     can use an extra low-order bit of blue in bit 16 of the color
+     value, but we don't have a way to communicate this non-linear
+     mapping to the kernel.
+
+*/
+
+#if !defined (__LCD_PANEL_H__)
+#    define   __LCD_PANEL_H__
+
+#if defined (MACH_LPD79520)\
+ || defined (MACH_LPD79524)\
+ || defined (MACH_LPD7A400)\
+ || defined (MACH_LPD7A404)
+# define USE_RGB555
+#endif
+
+struct clcd_panel_extra {
+        unsigned int hrmode;
+        unsigned int clsen;
+        unsigned int spsen;
+        unsigned int pcdel;
+        unsigned int revdel;
+        unsigned int lpdel;
+        unsigned int spldel;
+        unsigned int pc2del;
+};
+
+#define NS_TO_CLOCK(ns,c)       ((((ns)*((c)/1000) + (1000000 - 1))/1000000))
+#define CLOCK_TO_DIV(e,c)       (((c) + (e) - 1)/(e))
+
+#if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
+
+        /* Logic Product Development LCD 3.5" QVGA HRTFT -10 */
+        /* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */
+
+#define PIX_CLOCK_TARGET        (6800000)
+#define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
+#define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
+
+static struct clcd_panel lcd_panel = {
+        .mode   = {
+                .name           = "3.5in QVGA (LQ035Q7DB02)",
+                .xres           = 240,
+                .yres           = 320,
+                .pixclock       = PIX_CLOCK,
+                .left_margin    = 16,
+                .right_margin   = 21,
+                .upper_margin   = 8,                    // line/8/8/8
+                .lower_margin   = 5,
+                .hsync_len      = 61,
+                .vsync_len      = NS_TO_CLOCK (60, PIX_CLOCK),
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+        .width          = -1,
+        .height         = -1,
+        .tim2           = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2),
+        .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
+        .bpp            = 16,
+};
+
+#define HAS_LCD_PANEL_EXTRA
+
+static struct clcd_panel_extra lcd_panel_extra = {
+        .hrmode = 1,
+        .clsen = 1,
+        .spsen = 1,
+        .pcdel = 8,
+        .revdel = 7,
+        .lpdel = 13,
+        .spldel = 77,
+        .pc2del = 208,
+};
+
+#endif
+
+#if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02
+
+        /* Logic Product Development LCD 5.7" QVGA -10 */
+        /* Sharp PN LQ057Q3DC02 */
+        /* QVGA mode, V/Q=LOW */
+
+/* From Sharp on 2006.1.3.  I believe some of the values are incorrect
+ * based on the datasheet.
+
+    Timing0     TIMING1         TIMING2         CONTROL
+    0x140A0C4C  0x080504EF      0x013F380D      0x00000829
+    HBP= 20     VBP=  8         BCD=  0
+    HFP= 10     VFP=  5         CPL=319
+    HSW= 12     VSW=  1         IOE=  0
+    PPL= 19     LPP=239         IPC=  1
+                                IHS=  1
+                                IVS=  1
+                                ACB=  0
+                                CSEL= 0
+                                PCD= 13
+
+ */
+
+/* The full horozontal cycle (Th) is clock/360/400/450. */
+/* The full vertical   cycle (Tv) is line/251/262/280. */
+
+#define PIX_CLOCK_TARGET        (6300000) /* -/6.3/7 MHz */
+#define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
+#define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
+
+static struct clcd_panel lcd_panel = {
+        .mode   = {
+                .name           = "5.7in QVGA (LQ057Q3DC02)",
+                .xres           = 320,
+                .yres           = 240,
+                .pixclock       = PIX_CLOCK,
+                .left_margin    = 11,
+                .right_margin   = 400-11-320-2,
+                .upper_margin   = 7,                    // line/7/7/7
+                .lower_margin   = 262-7-240-2,
+                .hsync_len      = 2,                    // clk/2/96/200
+                .vsync_len      = 2,                    // line/2/-/34
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+        .width          = -1,
+        .height         = -1,
+        .tim2           = TIM2_IHS | TIM2_IVS
+                        | (PIX_CLOCK_DIVIDER - 2),
+        .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
+        .bpp            = 16,
+};
+
+#endif
+
+#if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343
+
+        /* Logic Product Development LCD 6.4" VGA -10 */
+        /* Sharp PN LQ64D343 */
+
+/* The full horozontal cycle (Th) is clock/750/800/900. */
+/* The full vertical   cycle (Tv) is line/515/525/560. */
+
+#define PIX_CLOCK_TARGET        (28330000)
+#define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
+#define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
+
+static struct clcd_panel lcd_panel = {
+        .mode   = {
+                .name           = "6.4in QVGA (LQ64D343)",
+                .xres           = 640,
+                .yres           = 480,
+                .pixclock       = PIX_CLOCK,
+                .left_margin    = 32,
+                .right_margin   = 800-32-640-96,
+                .upper_margin   = 32,                   // line/34/34/34
+                .lower_margin   = 540-32-480-2,
+                .hsync_len      = 96,                   // clk/2/96/200
+                .vsync_len      = 2,                    // line/2/-/34
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+        .width          = -1,
+        .height         = -1,
+        .tim2           = TIM2_IHS | TIM2_IVS
+                        | (PIX_CLOCK_DIVIDER - 2),
+        .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
+        .bpp            = 16,
+};
+
+#endif
+
+#if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368
+
+        /* Logic Product Development LCD 10.4" VGA -10 */
+        /* Sharp PN LQ10D368 */
+
+#define PIX_CLOCK_TARGET        (28330000)
+#define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
+#define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
+
+static struct clcd_panel lcd_panel = {
+        .mode   = {
+                .name           = "10.4in VGA (LQ10D368)",
+                .xres           = 640,
+                .yres           = 480,
+                .pixclock       = PIX_CLOCK,
+                .left_margin    = 21,
+                .right_margin   = 15,
+                .upper_margin   = 34,
+                .lower_margin   = 5,
+                .hsync_len      = 96,
+                .vsync_len      = 16,
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+        .width          = -1,
+        .height         = -1,
+        .tim2           = TIM2_IHS | TIM2_IVS
+                        | (PIX_CLOCK_DIVIDER - 2),
+        .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
+        .bpp            = 16,
+};
+
+#endif
+
+#if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41
+
+        /* Logic Product Development LCD 12.1" SVGA -10 */
+        /* Sharp PN LQ121S1DG41, was LQ121S1DG31 */
+
+/* Note that with a 99993900 Hz HCLK, it is not possible to hit the
+ * target clock frequency range of 35MHz to 42MHz. */
+
+/* If the target pixel clock is substantially lower than the panel
+ * spec, this is done to prevent the LCD display from glitching when
+ * the CPU is under load.  A pixel clock higher than 25MHz
+ * (empirically determined) will compete with the CPU for bus cycles
+ * for the Ethernet chip.  However, even a pixel clock of 10MHz
+ * competes with Compact Flash interface during some operations
+ * (fdisk, e2fsck).  And, at that speed the display may have a visible
+ * flicker. */
+
+/* The full horozontal cycle (Th) is clock/832/1056/1395. */
+
+#define PIX_CLOCK_TARGET        (20000000)
+#define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
+#define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
+
+static struct clcd_panel lcd_panel = {
+        .mode   = {
+                .name           = "12.1in SVGA (LQ121S1DG41)",
+                .xres           = 800,
+                .yres           = 600,
+                .pixclock       = PIX_CLOCK,
+                .left_margin    = 89,           // ns/5/-/(1/PIX_CLOCK)-10
+                .right_margin   = 1056-800-89-128,
+                .upper_margin   = 23,           // line/23/23/23
+                .lower_margin   = 44,
+                .hsync_len      = 128,          // clk/2/128/200
+                .vsync_len      = 4,            // line/2/4/6
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+        .width          = -1,
+        .height         = -1,
+        .tim2           = TIM2_IHS | TIM2_IVS
+                        | (PIX_CLOCK_DIVIDER - 2),
+        .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
+        .bpp            = 16,
+};
+
+#endif
+
+#if defined CONFIG_FB_ARMCLCD_HITACHI
+
+        /* Hitachi*/
+        /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
+
+#define PIX_CLOCK_TARGET        (49000000)
+#define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
+#define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
+
+static struct clcd_panel lcd_panel = {
+        .mode   = {
+                .name           = "Hitachi 800x480",
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = PIX_CLOCK,
+                .left_margin    = 88,
+                .right_margin   = 40,
+                .upper_margin   = 32,
+                .lower_margin   = 11,
+                .hsync_len      = 128,
+                .vsync_len      = 2,
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+        .width          = -1,
+        .height         = -1,
+        .tim2           = TIM2_IPC | TIM2_IHS | TIM2_IVS
+                        | (PIX_CLOCK_DIVIDER - 2),
+        .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
+        .bpp            = 16,
+};
+
+#endif
+
+
+#if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE
+
+        /* AU Optotronics  A070VW01 7.0 Wide Screen color Display*/
+        /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
+
+#define PIX_CLOCK_TARGET        (10000000)
+#define PIX_CLOCK_DIVIDER       CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
+#define PIX_CLOCK               (HCLK/PIX_CLOCK_DIVIDER)
+
+static struct clcd_panel lcd_panel = {
+        .mode   = {
+                .name           = "7.0in Wide (A070VW01)",
+                .xres           = 480,
+                .yres           = 234,
+                .pixclock       = PIX_CLOCK,
+                .left_margin    = 30,
+                .right_margin   = 25,
+                .upper_margin   = 14,
+                .lower_margin   = 12,
+                .hsync_len      = 100,
+                .vsync_len      = 1,
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+        .width          = -1,
+        .height         = -1,
+        .tim2           = TIM2_IPC | TIM2_IHS | TIM2_IVS
+                        | (PIX_CLOCK_DIVIDER - 2),
+        .cntl           = CNTL_LCDTFT | CNTL_WATERMARK,
+        .bpp            = 16,
+};
+
+#endif
+
+#undef NS_TO_CLOCK
+#undef CLOCK_TO_DIV
+
+#endif  /* __LCD_PANEL_H__ */
diff --git a/include/asm-arm/arch-lh7a40x/clocks.h b/include/asm-arm/arch-lh7a40x/clocks.h
new file mode 100644
index 000000000000..bee02fd8dab1
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/clocks.h
@@ -0,0 +1,20 @@
+/* include/asm-arm/arch-lh7a40x/clocks.h
+ *
+ *  Copyright (C) 2004 Marc Singer
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/config.h>
+
+#ifndef __ASM_ARCH_CLOCKS_H
+#define __ASM_ARCH_CLOCKS_H
+
+unsigned int fclkfreq_get (void);
+unsigned int hclkfreq_get (void);
+unsigned int pclkfreq_get (void);
+
+#endif  /* _ASM_ARCH_CLOCKS_H */
diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h
index 52c1cb9c39c6..2929e891ee03 100644
--- a/include/asm-arm/arch-lh7a40x/constants.h
+++ b/include/asm-arm/arch-lh7a40x/constants.h
@@ -29,8 +29,7 @@
 
 #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
 
-# define IOBARRIER_PHYS         0xc0000000 /* Start of SDRAM */
-/*# define IOBARRIER_PHYS               0x00000000 */ /* Start of flash */
+# define IOBARRIER_PHYS         0x10000000 /* Second bank, fastest timing */
 # define IOBARRIER_VIRT         0xf0000000
 # define IOBARRIER_SIZE         PAGE_SIZE
 
@@ -53,6 +52,9 @@
 # define CPLD08_PHYS            CPLDX_PHYS (0x08)
 # define CPLD08_VIRT            CPLDX_VIRT (0x08)
 # define CPLD08_SIZE            PAGE_SIZE
+# define CPLD0A_PHYS            CPLDX_PHYS (0x0a)
+# define CPLD0A_VIRT            CPLDX_VIRT (0x0a)
+# define CPLD0A_SIZE            PAGE_SIZE
 # define CPLD0C_PHYS            CPLDX_PHYS (0x0c)
 # define CPLD0C_VIRT            CPLDX_VIRT (0x0c)
 # define CPLD0C_SIZE            PAGE_SIZE
@@ -84,5 +86,7 @@
 #define XTAL_IN                 14745600        /* 14.7456 MHz crystal */
 #define PLL_CLOCK               (XTAL_IN * 21)  /* 309 MHz PLL clock */
 #define MAX_HCLK_KHZ            100000          /* HCLK max limit ~100MHz */
+#define HCLK                    (99993600)
+//#define HCLK                  (119808000)
 
 #endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h
index 15492e3253f6..a8cbd14bbf9d 100644
--- a/include/asm-arm/arch-lh7a40x/dma.h
+++ b/include/asm-arm/arch-lh7a40x/dma.h
@@ -1,9 +1,86 @@
 /* include/asm-arm/arch-lh7a40x/dma.h
  *
- *  Copyright (C) 2003 Coastal Environmental Systems
+ *  Copyright (C) 2005 Marc Singer
  *
  *  This program is free software; you can redistribute it and/or
  *  modify it under the terms of the GNU General Public License
  *  version 2 as published by the Free Software Foundation.
  *
  */
+
+typedef enum {
+        DMA_M2M0        = 0,
+        DMA_M2M1        = 1,
+        DMA_M2P0        = 2,    /* Tx */
+        DMA_M2P1        = 3,    /* Rx */
+        DMA_M2P2        = 4,    /* Tx */
+        DMA_M2P3        = 5,    /* Rx */
+        DMA_M2P4        = 6,    /* Tx - AC97 */
+        DMA_M2P5        = 7,    /* Rx - AC97 */
+        DMA_M2P6        = 8,    /* Tx */
+        DMA_M2P7        = 9,    /* Rx */
+} dma_device_t;
+
+#define DMA_LENGTH_MAX          ((64*1024) - 4) /* bytes */
+
+#define DMAC_GCA                __REG(DMAC_PHYS + 0x2b80)
+#define DMAC_GIR                __REG(DMAC_PHYS + 0x2bc0)
+
+#define DMAC_GIR_MMI1           (1<<11)
+#define DMAC_GIR_MMI0           (1<<10)
+#define DMAC_GIR_MPI8           (1<<9)
+#define DMAC_GIR_MPI9           (1<<8)
+#define DMAC_GIR_MPI6           (1<<7)
+#define DMAC_GIR_MPI7           (1<<6)
+#define DMAC_GIR_MPI4           (1<<5)
+#define DMAC_GIR_MPI5           (1<<4)
+#define DMAC_GIR_MPI2           (1<<3)
+#define DMAC_GIR_MPI3           (1<<2)
+#define DMAC_GIR_MPI0           (1<<1)
+#define DMAC_GIR_MPI1           (1<<0)
+
+#define DMAC_M2P0               0x0000
+#define DMAC_M2P1               0x0040
+#define DMAC_M2P2               0x0080
+#define DMAC_M2P3               0x00c0
+#define DMAC_M2P4               0x0240
+#define DMAC_M2P5               0x0200
+#define DMAC_M2P6               0x02c0
+#define DMAC_M2P7               0x0280
+#define DMAC_M2P8               0x0340
+#define DMAC_M2P9               0x0300
+#define DMAC_M2M0               0x0100
+#define DMAC_M2M1               0x0140
+
+#define DMAC_P_PCONTROL(c)      __REG(DMAC_PHYS + (c) + 0x00)
+#define DMAC_P_PINTERRUPT(c)    __REG(DMAC_PHYS + (c) + 0x04)
+#define DMAC_P_PPALLOC(c)       __REG(DMAC_PHYS + (c) + 0x08)
+#define DMAC_P_PSTATUS(c)       __REG(DMAC_PHYS + (c) + 0x0c)
+#define DMAC_P_REMAIN(c)        __REG(DMAC_PHYS + (c) + 0x14)
+#define DMAC_P_MAXCNT0(c)       __REG(DMAC_PHYS + (c) + 0x20)
+#define DMAC_P_BASE0(c)         __REG(DMAC_PHYS + (c) + 0x24)
+#define DMAC_P_CURRENT0(c)      __REG(DMAC_PHYS + (c) + 0x28)
+#define DMAC_P_MAXCNT1(c)       __REG(DMAC_PHYS + (c) + 0x30)
+#define DMAC_P_BASE1(c)         __REG(DMAC_PHYS + (c) + 0x34)
+#define DMAC_P_CURRENT1(c)      __REG(DMAC_PHYS + (c) + 0x38)
+
+#define DMAC_PCONTROL_ENABLE    (1<<4)
+
+#define DMAC_PORT_USB           0
+#define DMAC_PORT_SDMMC         1
+#define DMAC_PORT_AC97_1        2
+#define DMAC_PORT_AC97_2        3
+#define DMAC_PORT_AC97_3        4
+#define DMAC_PORT_UART1         6
+#define DMAC_PORT_UART2         7
+#define DMAC_PORT_UART3         8
+
+#define DMAC_PSTATUS_CURRSTATE_SHIFT    4
+#define DMAC_PSTATUS_CURRSTATE_MASK     0x3
+
+#define DMAC_PSTATUS_NEXTBUF     (1<<6)
+#define DMAC_PSTATUS_STALLRINT   (1<<0)
+
+#define DMAC_INT_CHE             (1<<3)
+#define DMAC_INT_NFB             (1<<1)
+#define DMAC_INT_STALL           (1<<0)
diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h
index aeb07c162e25..e9ff74fd7939 100644
--- a/include/asm-arm/arch-lh7a40x/hardware.h
+++ b/include/asm-arm/arch-lh7a40x/hardware.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
+#include <asm/sizes.h>          /* Added for the sake of amba-clcd driver */
+
 #define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
 #define io_v2p(x) (             (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
 
@@ -53,6 +55,8 @@ typedef struct { volatile u8 offset[4096]; } __regbase8;
 
 #endif
 
+#define MASK_AND_SET(v,m,s)     (v) = ((v)&~(m))|(s)
+
 #include "registers.h"
 
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h
index f91f3e59f3ab..7e8a217200e9 100644
--- a/include/asm-arm/arch-lh7a40x/irqs.h
+++ b/include/asm-arm/arch-lh7a40x/irqs.h
@@ -154,9 +154,10 @@
 #if !defined (IRQ_GPIO0INTR)
 # define IRQ_GPIO0INTR  IRQ_GPIO0FIQ
 #endif
-#define IRQ_TICK        IRQ_TINTR
+#define IRQ_TICK        IRQ_TINTR
 #define IRQ_PCC1_RDY    IRQ_GPIO6INTR   /* PCCard 1 ready */
 #define IRQ_PCC2_RDY    IRQ_GPIO7INTR   /* PCCard 2 ready */
+#define IRQ_USB         IRQ_USBINTR     /* USB device */
 
 #ifdef CONFIG_MACH_KEV7A400
 # define IRQ_TS         IRQ_GPIOFIQ     /* Touchscreen */
@@ -191,6 +192,10 @@
 # define IRQ_LPD7A400_TS        IRQ_LPD7A40X_CPLD + 1   /* Touch screen */
 #endif
 
+#if defined (CONFIG_MACH_LPD7A400)
+# define IRQ_TOUCH              IRQ_LPD7A400_TS
+#endif
+
 #define NR_IRQS         (NR_IRQ_CPU + NR_IRQ_BOARD)
 
 #endif
diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h
index 2edb22e35450..544307bb87a2 100644
--- a/include/asm-arm/arch-lh7a40x/registers.h
+++ b/include/asm-arm/arch-lh7a40x/registers.h
@@ -18,7 +18,7 @@
 
         /* Physical register base addresses */
 
-#define AC97_PHYS       (0x80000000)    /* AC97 Controller */
+#define AC97C_PHYS      (0x80000000)    /* AC97 Controller */
 #define MMC_PHYS        (0x80000100)    /* Multimedia Card Controller */
 #define USB_PHYS        (0x80000200)    /* USB Client */
 #define SCI_PHYS        (0x80000300)    /* Secure Card Interface */
@@ -35,6 +35,8 @@
 #define RTC_PHYS        (0x80000d00)    /* Real-time Clock */
 #define GPIO_PHYS       (0x80000e00)    /* General Purpose IO */
 #define BMI_PHYS        (0x80000f00)    /* Battery Monitor Interface */
+#define HRTFTC_PHYS     (0x80001000)    /* High-res TFT Controller (LH7A400) */
+#define ALI_PHYS        (0x80001000)    /* Advanced LCD Interface (LH7A404) */
 #define WDT_PHYS        (0x80001400)    /* Watchdog Timer */
 #define SMC_PHYS        (0x80002000)    /* Static Memory Controller */
 #define SDRC_PHYS       (0x80002400)    /* SDRAM Controller */
@@ -43,6 +45,7 @@
 
         /* Physical registers of the LH7A404 */
 
+#define ADC_PHYS        (0x80001300)    /* A/D & Touchscreen Controller */
 #define VIC1_PHYS       (0x80008000)    /* Vectored Interrupt Controller 1 */
 #define USBH_PHYS       (0x80009000)    /* USB OHCI host controller */
 #define VIC2_PHYS       (0x8000a000)    /* Vectored Interrupt Controller 2 */
@@ -53,10 +56,32 @@
 
         /* Clock/State Controller register */
 
+#define CSC_PWRSR       __REG(CSC_PHYS + 0x00) /* Reset register & ID */
 #define CSC_PWRCNT      __REG(CSC_PHYS + 0x04) /* Power control */
+#define CSC_CLKSET      __REG(CSC_PHYS + 0x20) /* Clock speed control */
+#define CSC_USBDRESET   __REG(CSC_PHYS + 0x4c) /* USB Device resets */
 
 #define CSC_PWRCNT_USBH_EN      (1<<28) /* USB Host power enable */
-
+#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
+#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
+#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
+#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
+#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
+#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
+#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
+#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
+#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
+#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
+#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
+#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
+
+#define CSC_PWRSR_CHIPMAN_SHIFT (24)
+#define CSC_PWRSR_CHIPMAN_MASK  (0xff)
+#define CSC_PWRSR_CHIPID_SHIFT  (16)
+#define CSC_PWRSR_CHIPID_MASK   (0xff)
+
+#define CSC_USBDRESET_APBRESETREG       (1<<1)
+#define CSC_USBDRESET_IORESETREG        (1<<0)
 
         /* Interrupt Controller registers */
 
@@ -109,6 +134,13 @@
 #define GPIO_GPIOFEOI   __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
 #define GPIO_GPIOINTEN  __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
 #define GPIO_INTSTATUS  __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
+#define GPIO_PINMUX     __REG(GPIO_PHYS + 0x2c)
+#define GPIO_PADD       __REG(GPIO_PHYS + 0x10)
+#define GPIO_PAD        __REG(GPIO_PHYS + 0x00)
+#define GPIO_PCD        __REG(GPIO_PHYS + 0x08)
+#define GPIO_PCDD       __REG(GPIO_PHYS + 0x18)
+#define GPIO_PEDD       __REG(GPIO_PHYS + 0x24)
+#define GPIO_PED        __REG(GPIO_PHYS + 0x20)
 
 
         /* Static Memory Controller registers */
@@ -138,20 +170,21 @@
 #endif
 
 #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
-# define CPLD_CONTROL           __REG8(CPLD02_PHYS)
-# define CPLD_SPI_DATA          __REG8(CPLD06_PHYS)
-# define CPLD_SPI_CONTROL       __REG8(CPLD08_PHYS)
-# define CPLD_SPI_EEPROM        __REG8(CPLD0A_PHYS)
-# define CPLD_INTERRUPTS        __REG8(CPLD0C_PHYS) /* IRQ mask/status */
-# define CPLD_BOOT_MODE         __REG8(CPLD0E_PHYS)
-# define CPLD_FLASH             __REG8(CPLD10_PHYS)
-# define CPLD_POWER_MGMT        __REG8(CPLD12_PHYS)
-# define CPLD_REVISION          __REG8(CPLD14_PHYS)
-# define CPLD_GPIO_EXT          __REG8(CPLD16_PHYS)
-# define CPLD_GPIO_DATA         __REG8(CPLD18_PHYS)
-# define CPLD_GPIO_DIR          __REG8(CPLD1A_PHYS)
-#endif
 
+# define CPLD_CONTROL           __REG16(CPLD02_PHYS)
+# define CPLD_SPI_DATA          __REG16(CPLD06_PHYS)
+# define CPLD_SPI_CONTROL       __REG16(CPLD08_PHYS)
+# define CPLD_SPI_EEPROM        __REG16(CPLD0A_PHYS)
+# define CPLD_INTERRUPTS        __REG16(CPLD0C_PHYS) /* IRQ mask/status */
+# define CPLD_BOOT_MODE         __REG16(CPLD0E_PHYS)
+# define CPLD_FLASH             __REG16(CPLD10_PHYS)
+# define CPLD_POWER_MGMT        __REG16(CPLD12_PHYS)
+# define CPLD_REVISION          __REG16(CPLD14_PHYS)
+# define CPLD_GPIO_EXT          __REG16(CPLD16_PHYS)
+# define CPLD_GPIO_DATA         __REG16(CPLD18_PHYS)
+# define CPLD_GPIO_DIR          __REG16(CPLD1A_PHYS)
+
+#endif
 
         /* Timer registers */
 
@@ -190,4 +223,3 @@
 
 
 #endif  /* _ASM_ARCH_REGISTERS_H */
-
diff --git a/include/asm-arm/arch-lh7a40x/ssp.h b/include/asm-arm/arch-lh7a40x/ssp.h
new file mode 100644
index 000000000000..132b1c4d5ce6
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/ssp.h
@@ -0,0 +1,71 @@
+/* ssp.h
+     $Id$
+
+   written by Marc Singer
+   6 Dec 2004
+
+   Copyright (C) 2004 Marc Singer
+
+   -----------
+   DESCRIPTION
+   -----------
+
+   This SSP header is available throughout the kernel, for this
+   machine/architecture, because drivers that use it may be dispersed.
+
+   This file was cloned from the 7952x implementation.  It would be
+   better to share them, but we're taking an easier approach for the
+   time being.
+
+*/
+
+#if !defined (__SSP_H__)
+#    define   __SSP_H__
+
+/* ----- Includes */
+
+/* ----- Types */
+
+struct ssp_driver {
+        int  (*init)            (void);
+        void (*exit)            (void);
+        void (*acquire)         (void);
+        void (*release)         (void);
+        int  (*configure)       (int device, int mode, int speed,
+                                 int frame_size_write, int frame_size_read);
+        void (*chip_select)     (int enable);
+        void (*set_callbacks)   (void* handle,
+                                 irqreturn_t (*callback_tx)(void*),
+                                 irqreturn_t (*callback_rx)(void*));
+        void (*enable)          (void);
+        void (*disable)         (void);
+//      int  (*save_state)      (void*);
+//      void (*restore_state)   (void*);
+        int  (*read)            (void);
+        int  (*write)           (u16 data);
+        int  (*write_read)      (u16 data);
+        void (*flush)           (void);
+        void (*write_async)     (void* pv, size_t cb);
+        size_t (*write_pos)     (void);
+};
+
+        /* These modes are only available on the LH79524 */
+#define SSP_MODE_SPI            (1)
+#define SSP_MODE_SSI            (2)
+#define SSP_MODE_MICROWIRE      (3)
+#define SSP_MODE_I2S            (4)
+
+        /* CPLD SPI devices */
+#define DEVICE_EEPROM   0       /* Configuration eeprom */
+#define DEVICE_MAC      1       /* MAC eeprom (LPD79524) */
+#define DEVICE_CODEC    2       /* Audio codec */
+#define DEVICE_TOUCH    3       /* Touch screen (LPD79520) */
+
+/* ----- Globals */
+
+/* ----- Prototypes */
+
+//extern struct ssp_driver lh79520_i2s_driver;
+extern struct ssp_driver lh7a400_cpld_ssp_driver;
+
+#endif  /* __SSP_H__ */
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
index f8053346f608..3d1ce0426a33 100644
--- a/include/asm-arm/arch-lh7a40x/uncompress.h
+++ b/include/asm-arm/arch-lh7a40x/uncompress.h
@@ -16,7 +16,7 @@
 #ifndef UART_R_STATUS
 # define UART_R_STATUS  (0x10)
 #endif
-#define nTxRdy          (0x20)  /* Not TxReady (literally Tx FIFO full) */
+#define nTxRdy          (0x20)  /* Not TxReady (literally Tx FIFO full) */
 
         /* Access UART with physical addresses before MMU is setup */
 #define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))