aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSuresh Siddha <suresh.b.siddha@intel.com>2008-05-07 15:09:52 -0400
committerThomas Gleixner <tglx@linutronix.de>2008-05-10 13:31:45 -0400
commitfd3c3ed5d1e3ceb37635cbe6d220ab94aae0781d (patch)
tree67cc2a950e670e5362173efd88ea6ded708b7e6c
parent0646153921892cc7a81320a6920beaca06b3e9f0 (diff)
x86: fix fpu restore from sig return
If the task never used fpu, initialize the fpu before restoring the FP state from the signal handler context. This will allocate the fpu state, if the task never needed it before. Reported-and-bisected-by: Eric Sesterhenn <snakebyte@gmx.de> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Tested-by: Eric Sesterhenn <snakebyte@gmx.de> Cc: Frederik Deweerdt <deweerdt@free.fr> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-rw-r--r--arch/x86/kernel/i387.c12
-rw-r--r--include/asm-x86/i387.h10
2 files changed, 19 insertions, 3 deletions
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index db6839b53195..e03cc952f233 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -450,7 +450,6 @@ static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf)
450{ 450{
451 struct task_struct *tsk = current; 451 struct task_struct *tsk = current;
452 452
453 clear_fpu(tsk);
454 return __copy_from_user(&tsk->thread.xstate->fsave, buf, 453 return __copy_from_user(&tsk->thread.xstate->fsave, buf,
455 sizeof(struct i387_fsave_struct)); 454 sizeof(struct i387_fsave_struct));
456} 455}
@@ -461,7 +460,6 @@ static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf)
461 struct user_i387_ia32_struct env; 460 struct user_i387_ia32_struct env;
462 int err; 461 int err;
463 462
464 clear_fpu(tsk);
465 err = __copy_from_user(&tsk->thread.xstate->fxsave, &buf->_fxsr_env[0], 463 err = __copy_from_user(&tsk->thread.xstate->fxsave, &buf->_fxsr_env[0],
466 sizeof(struct i387_fxsave_struct)); 464 sizeof(struct i387_fxsave_struct));
467 /* mxcsr reserved bits must be masked to zero for security reasons */ 465 /* mxcsr reserved bits must be masked to zero for security reasons */
@@ -478,6 +476,16 @@ int restore_i387_ia32(struct _fpstate_ia32 __user *buf)
478 int err; 476 int err;
479 477
480 if (HAVE_HWFP) { 478 if (HAVE_HWFP) {
479 struct task_struct *tsk = current;
480
481 clear_fpu(tsk);
482
483 if (!used_math()) {
484 err = init_fpu(tsk);
485 if (err)
486 return err;
487 }
488
481 if (cpu_has_fxsr) 489 if (cpu_has_fxsr)
482 err = restore_i387_fxsave(buf); 490 err = restore_i387_fxsave(buf);
483 else 491 else
diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h
index da2adb45f6e3..6b722d315936 100644
--- a/include/asm-x86/i387.h
+++ b/include/asm-x86/i387.h
@@ -175,7 +175,15 @@ static inline int save_i387(struct _fpstate __user *buf)
175 */ 175 */
176static inline int restore_i387(struct _fpstate __user *buf) 176static inline int restore_i387(struct _fpstate __user *buf)
177{ 177{
178 set_used_math(); 178 struct task_struct *tsk = current;
179 int err;
180
181 if (!used_math()) {
182 err = init_fpu(tsk);
183 if (err)
184 return err;
185 }
186
179 if (!(task_thread_info(current)->status & TS_USEDFPU)) { 187 if (!(task_thread_info(current)->status & TS_USEDFPU)) {
180 clts(); 188 clts();
181 task_thread_info(current)->status |= TS_USEDFPU; 189 task_thread_info(current)->status |= TS_USEDFPU;
l opt">); pci_read_config_word(dev, 0x50, &CIS); return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; } /* * Set the control register to use the 66MHz system * clock for UDMA 3/4/5 mode operation when necessary. * * FIXME: this register is shared by both channels, some locking is needed * * It may also be possible to leave the 66MHz clock on * and readjust the timing parameters. */ static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) { unsigned long clock_reg = hwif->extra_base + 0x01; u8 clock = inb(clock_reg); outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); } static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) { unsigned long clock_reg = hwif->extra_base + 0x01; u8 clock = inb(clock_reg); outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); } static void pdc2026x_init_hwif(ide_hwif_t *hwif) { pdc_old_disable_66MHz_clock(hwif); } static void pdc202xx_dma_start(ide_drive_t *drive) { if (drive->current_speed > XFER_UDMA_2) pdc_old_enable_66MHz_clock(drive->hwif); if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { ide_hwif_t *hwif = drive->hwif; struct request *rq = hwif->rq; unsigned long high_16 = hwif->extra_base - 16; unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); u32 word_count = 0; u8 clock = inb(high_16 + 0x11); outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11); word_count = (blk_rq_sectors(rq) << 8); word_count = (rq_data_dir(rq) == READ) ? word_count | 0x05000000 : word_count | 0x06000000; outl(word_count, atapi_reg); } ide_dma_start(drive); } static int pdc202xx_dma_end(ide_drive_t *drive) { if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { ide_hwif_t *hwif = drive->hwif; unsigned long high_16 = hwif->extra_base - 16; unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); u8 clock = 0; outl(0, atapi_reg); /* zero out extra */ clock = inb(high_16 + 0x11); outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11); } if (drive->current_speed > XFER_UDMA_2) pdc_old_disable_66MHz_clock(drive->hwif); return ide_dma_end(drive); } static int init_chipset_pdc202xx(struct pci_dev *dev) { unsigned long dmabase = pci_resource_start(dev, 4); u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0; if (dmabase == 0) goto out; udma_speed_flag = inb(dmabase | 0x1f); primary_mode = inb(dmabase | 0x1a); secondary_mode = inb(dmabase | 0x1b); printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \ "Primary %s Mode " \ "Secondary %s Mode.\n", pci_name(dev), (udma_speed_flag & 1) ? "EN" : "DIS", (primary_mode & 1) ? "MASTER" : "PCI", (secondary_mode & 1) ? "MASTER" : "PCI" ); if (!(udma_speed_flag & 1)) { printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ", pci_name(dev), udma_speed_flag, (udma_speed_flag|1)); outb(udma_speed_flag | 1, dmabase | 0x1f); printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN"); } out: return 0; } static void pdc202ata4_fixup_irq(struct pci_dev *dev, const char *name) { if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) { u8 irq = 0, irq2 = 0; pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); /* 0xbc */ pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); if (irq != irq2) { pci_write_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */ printk(KERN_INFO "%s %s: PCI config space interrupt " "mirror fixed\n", name, pci_name(dev)); } } } #define IDE_HFLAGS_PDC202XX \ (IDE_HFLAG_ERROR_STOPS_FIFO | \ IDE_HFLAG_OFF_BOARD) static const struct ide_port_ops pdc20246_port_ops = { .set_pio_mode = pdc202xx_set_pio_mode, .set_dma_mode = pdc202xx_set_mode, .test_irq = pdc202xx_test_irq, }; static const struct ide_port_ops pdc2026x_port_ops = { .set_pio_mode = pdc202xx_set_pio_mode, .set_dma_mode = pdc202xx_set_mode, .test_irq = pdc202xx_test_irq, .cable_detect = pdc2026x_cable_detect, }; static const struct ide_dma_ops pdc2026x_dma_ops = { .dma_host_set = ide_dma_host_set, .dma_setup = ide_dma_setup, .dma_start = pdc202xx_dma_start, .dma_end = pdc202xx_dma_end, .dma_test_irq = ide_dma_test_irq, .dma_lost_irq = ide_dma_lost_irq, .dma_timer_expiry = ide_dma_sff_timer_expiry, .dma_sff_read_status = ide_dma_sff_read_status, }; #define DECLARE_PDC2026X_DEV(udma, sectors) \ { \ .name = DRV_NAME, \ .init_chipset = init_chipset_pdc202xx, \ .init_hwif = pdc2026x_init_hwif, \ .port_ops = &pdc2026x_port_ops, \ .dma_ops = &pdc2026x_dma_ops, \ .host_flags = IDE_HFLAGS_PDC202XX, \ .pio_mask = ATA_PIO4, \ .mwdma_mask = ATA_MWDMA2, \ .udma_mask = udma, \ .max_sectors = sectors, \ } static const struct ide_port_info pdc202xx_chipsets[] = { { /* 0: PDC20246 */ .name = DRV_NAME, .init_chipset = init_chipset_pdc202xx, .port_ops = &pdc20246_port_ops, .dma_ops = &sff_dma_ops, .host_flags = IDE_HFLAGS_PDC202XX, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA2, }, /* 1: PDC2026{2,3} */ DECLARE_PDC2026X_DEV(ATA_UDMA4, 0), /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */ DECLARE_PDC2026X_DEV(ATA_UDMA5, 256), }; /** * pdc202xx_init_one - called when a PDC202xx is found * @dev: the pdc202xx device * @id: the matching pci id * * Called when the PCI registration layer (or the IDE initialization) * finds a device matching our IDE device tables. */ static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) { const struct ide_port_info *d; u8 idx = id->driver_data; d = &pdc202xx_chipsets[idx]; if (idx < 2) pdc202ata4_fixup_irq(dev, d->name); if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) { struct pci_dev *bridge = dev->bus->self; if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL && (bridge->device == PCI_DEVICE_ID_INTEL_I960 || bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { printk(KERN_INFO DRV_NAME " %s: skipping Promise " "PDC20265 attached to I2O RAID controller\n", pci_name(dev)); return -ENODEV; } } return ide_pci_init_one(dev, d, NULL); } static const struct pci_device_id pdc202xx_pci_tbl[] = { { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, { 0, }, }; MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl); static struct pci_driver pdc202xx_pci_driver = { .name = "Promise_Old_IDE", .id_table = pdc202xx_pci_tbl, .probe = pdc202xx_init_one, .remove = ide_pci_remove, .suspend = ide_pci_suspend, .resume = ide_pci_resume, }; static int __init pdc202xx_ide_init(void) { return ide_pci_register_driver(&pdc202xx_pci_driver); } static void __exit pdc202xx_ide_exit(void) { pci_unregister_driver(&pdc202xx_pci_driver); } module_init(pdc202xx_ide_init); module_exit(pdc202xx_ide_exit); MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz"); MODULE_DESCRIPTION("PCI driver module for older Promise IDE"); MODULE_LICENSE("GPL");