Blackfin: don't attempt to flush on-chip L1 SRAM regions

Since the on-chip L1 regions are not cacheable, there is no point in
trying to flush/invalidate them.  Plus, older Blackfin parts like to
trigger an exception (like BF533-0.3).

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

1 files changed, 18 insertions, 5 deletions

diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 77135b62818e..9a5b2c572ebf 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -39,8 +39,13 @@ extern void blackfin_invalidate_entire_icache(void);
 
 static inline void flush_icache_range(unsigned start, unsigned end)
 {
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-        blackfin_dcache_flush_range(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
+        if (end <= physical_mem_end)
+                blackfin_dcache_flush_range(start, end);
+#endif
+#if defined(CONFIG_BFIN_L2_WRITEBACK)
+        if (start >= L2_START && end <= L2_START + L2_LENGTH)
+                blackfin_dcache_flush_range(start, end);
 #endif
 
         /* Make sure all write buffers in the data side of the core
@@ -52,9 +57,17 @@ static inline void flush_icache_range(unsigned start, unsigned end)
          * the pipeline.
          */
         SSYNC();
-#if defined(CONFIG_BFIN_ICACHE)
-        blackfin_icache_flush_range(start, end);
-        flush_icache_range_others(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
+        if (end <= physical_mem_end) {
+                blackfin_icache_flush_range(start, end);
+                flush_icache_range_others(start, end);
+        }
+#endif
+#if defined(CONFIG_BFIN_L2_ICACHEABLE)
+        if (start >= L2_START && end <= L2_START + L2_LENGTH) {
+                blackfin_icache_flush_range(start, end);
+                flush_icache_range_others(start, end);
+        }
 #endif
 }