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authorMike Frysinger <vapier@gentoo.org>2011-03-30 02:54:33 -0400
committerMike Frysinger <vapier@gentoo.org>2011-05-25 08:13:42 -0400
commit6adc521e7127732512ebd7fcfd3926d7970a82e1 (patch)
tree1de12c99fde995c82a8cd7487f45c6f6ea0b4ef4
parent6b108049d67090988fbb0b9d9905ffca114b6ff1 (diff)
Blackfin: unify core IRQ definitions
Start a new common IRQ header and move all of the CEC pieces there. This lets the individual part headers worry just about its SIC defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat
-rw-r--r--arch/blackfin/include/mach-common/irq.h57
-rw-r--r--arch/blackfin/mach-bf518/include/mach/irq.h42
-rw-r--r--arch/blackfin/mach-bf527/include/mach/irq.h42
-rw-r--r--arch/blackfin/mach-bf533/include/mach/irq.h61
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h39
-rw-r--r--arch/blackfin/mach-bf538/include/mach/irq.h42
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h43
-rw-r--r--arch/blackfin/mach-bf561/include/mach/irq.h117
8 files changed, 64 insertions, 379 deletions
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
new file mode 100644
index 000000000000..cab14e911dc2
--- /dev/null
+++ b/arch/blackfin/include/mach-common/irq.h
@@ -0,0 +1,57 @@
1/*
2 * Common Blackfin IRQ definitions (i.e. the CEC)
3 *
4 * Copyright 2005-2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later
7 */
8
9#ifndef _MACH_COMMON_IRQ_H_
10#define _MACH_COMMON_IRQ_H_
11
12/*
13 * Core events interrupt source definitions
14 *
15 * Event Source Event Name
16 * Emulation EMU 0 (highest priority)
17 * Reset RST 1
18 * NMI NMI 2
19 * Exception EVX 3
20 * Reserved -- 4
21 * Hardware Error IVHW 5
22 * Core Timer IVTMR 6
23 * Peripherals IVG7 7
24 * Peripherals IVG8 8
25 * Peripherals IVG9 9
26 * Peripherals IVG10 10
27 * Peripherals IVG11 11
28 * Peripherals IVG12 12
29 * Peripherals IVG13 13
30 * Softirq IVG14 14
31 * System Call IVG15 15 (lowest priority)
32 */
33
34/* The ABSTRACT IRQ definitions */
35#define IRQ_EMU 0 /* Emulation */
36#define IRQ_RST 1 /* reset */
37#define IRQ_NMI 2 /* Non Maskable */
38#define IRQ_EVX 3 /* Exception */
39#define IRQ_UNUSED 4 /* - unused interrupt */
40#define IRQ_HWERR 5 /* Hardware Error */
41#define IRQ_CORETMR 6 /* Core timer */
42
43#define BFIN_IRQ(x) ((x) + 7)
44
45#define IVG7 7
46#define IVG8 8
47#define IVG9 9
48#define IVG10 10
49#define IVG11 11
50#define IVG12 12
51#define IVG13 13
52#define IVG14 14
53#define IVG15 15
54
55#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
56
57#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index 435e76e31aaa..daf1fa5bbb00 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -7,39 +7,10 @@
7#ifndef _BF518_IRQ_H_ 7#ifndef _BF518_IRQ_H_
8#define _BF518_IRQ_H_ 8#define _BF518_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions
12 Event Source Core Event Name
13 Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22 .....
23
24 Software Interrupt 1 IVG14 31
25 Software Interrupt 2 --
26 (lowest priority) IVG15 32 *
27*/
28 11
29#define NR_PERI_INTS (2 * 32) 12#define NR_PERI_INTS (2 * 32)
30 13
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /* Emulation */
34#define IRQ_RST 1 /* reset */
35#define IRQ_NMI 2 /* Non Maskable */
36#define IRQ_EVX 3 /* Exception */
37#define IRQ_UNUSED 4 /* - unused interrupt */
38#define IRQ_HWERR 5 /* Hardware Error */
39#define IRQ_CORETMR 6 /* Core timer */
40
41#define BFIN_IRQ(x) ((x) + 7)
42
43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
45#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */ 16#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
@@ -161,17 +132,6 @@
161#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
162 133
163#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
164#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
165
166#define IVG7 7
167#define IVG8 8
168#define IVG9 9
169#define IVG10 10
170#define IVG11 11
171#define IVG12 12
172#define IVG13 13
173#define IVG14 14
174#define IVG15 15
175 135
176/* IAR0 BIT FIELDS */ 136/* IAR0 BIT FIELDS */
177#define IRQ_PLL_WAKEUP_POS 0 137#define IRQ_PLL_WAKEUP_POS 0
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 704d9253e41d..555d42ad08ed 100644
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -7,39 +7,10 @@
7#ifndef _BF527_IRQ_H_ 7#ifndef _BF527_IRQ_H_
8#define _BF527_IRQ_H_ 8#define _BF527_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions
12 Event Source Core Event Name
13 Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22 .....
23
24 Software Interrupt 1 IVG14 31
25 Software Interrupt 2 --
26 (lowest priority) IVG15 32 *
27*/
28 11
29#define NR_PERI_INTS (2 * 32) 12#define NR_PERI_INTS (2 * 32)
30 13
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /* Emulation */
34#define IRQ_RST 1 /* reset */
35#define IRQ_NMI 2 /* Non Maskable */
36#define IRQ_EVX 3 /* Exception */
37#define IRQ_UNUSED 4 /* - unused interrupt */
38#define IRQ_HWERR 5 /* Hardware Error */
39#define IRQ_CORETMR 6 /* Core timer */
40
41#define BFIN_IRQ(x) ((x) + 7)
42
43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
45#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */ 16#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
@@ -161,17 +132,6 @@
161#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
162 133
163#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
164#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
165
166#define IVG7 7
167#define IVG8 8
168#define IVG9 9
169#define IVG10 10
170#define IVG11 11
171#define IVG12 12
172#define IVG13 13
173#define IVG14 14
174#define IVG15 15
175 135
176/* IAR0 BIT FIELDS */ 136/* IAR0 BIT FIELDS */
177#define IRQ_PLL_WAKEUP_POS 0 137#define IRQ_PLL_WAKEUP_POS 0
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index 1f7e9765d954..c4c29fc4ea90 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -7,59 +7,11 @@
7#ifndef _BF533_IRQ_H_ 7#ifndef _BF533_IRQ_H_
8#define _BF533_IRQ_H_ 8#define _BF533_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions
12 Event Source Core Event Name
13Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21 PLL Wakeup Interrupt IVG7 7
22 DMA Error (generic) IVG7 8
23 PPI Error Interrupt IVG7 9
24 SPORT0 Error Interrupt IVG7 10
25 SPORT1 Error Interrupt IVG7 11
26 SPI Error Interrupt IVG7 12
27 UART Error Interrupt IVG7 13
28 RTC Interrupt IVG8 14
29 DMA0 Interrupt (PPI) IVG8 15
30 DMA1 (SPORT0 RX) IVG9 16
31 DMA2 (SPORT0 TX) IVG9 17
32 DMA3 (SPORT1 RX) IVG9 18
33 DMA4 (SPORT1 TX) IVG9 19
34 DMA5 (PPI) IVG10 20
35 DMA6 (UART RX) IVG10 21
36 DMA7 (UART TX) IVG10 22
37 Timer0 IVG11 23
38 Timer1 IVG11 24
39 Timer2 IVG11 25
40 PF Interrupt A IVG12 26
41 PF Interrupt B IVG12 27
42 DMA8/9 Interrupt IVG13 28
43 DMA10/11 Interrupt IVG13 29
44 Watchdog Timer IVG13 30
45 11
46 Softirq IVG14 31
47 System Call --
48 (lowest priority) IVG15 32 *
49 */
50#define SYS_IRQS 31 12#define SYS_IRQS 31
51#define NR_PERI_INTS 24 13#define NR_PERI_INTS 24
52 14
53/* The ABSTRACT IRQ definitions */
54/** the first seven of the following are fixed, the rest you change if you need to **/
55#define IRQ_EMU 0 /*Emulation */
56#define IRQ_RST 1 /*reset */
57#define IRQ_NMI 2 /*Non Maskable */
58#define IRQ_EVX 3 /*Exception */
59#define IRQ_UNUSED 4 /*- unused interrupt*/
60#define IRQ_HWERR 5 /*Hardware Error */
61#define IRQ_CORETMR 6 /*Core timer */
62
63#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ 15#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
64#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ 16#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
65#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */ 17#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
@@ -105,17 +57,6 @@ Core Emulation **
105#define GPIO_IRQ_BASE IRQ_PF0 57#define GPIO_IRQ_BASE IRQ_PF0
106 58
107#define NR_MACH_IRQS (IRQ_PF15 + 1) 59#define NR_MACH_IRQS (IRQ_PF15 + 1)
108#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
109
110#define IVG7 7
111#define IVG8 8
112#define IVG9 9
113#define IVG10 10
114#define IVG11 11
115#define IVG12 12
116#define IVG13 13
117#define IVG14 14
118#define IVG15 15
119 60
120/* IAR0 BIT FIELDS*/ 61/* IAR0 BIT FIELDS*/
121#define RTC_ERROR_POS 28 62#define RTC_ERROR_POS 28
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 1a6d617c5fcf..2a8194eadb4c 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -7,37 +7,11 @@
7#ifndef _BF537_IRQ_H_ 7#ifndef _BF537_IRQ_H_
8#define _BF537_IRQ_H_ 8#define _BF537_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions
12 * Event Source Core Event Name
13 * Core Emulation **
14 * Events (highest priority) EMU 0
15 * Reset RST 1
16 * NMI NMI 2
17 * Exception EVX 3
18 * Reserved -- 4
19 * Hardware Error IVHW 5
20 * Core Timer IVTMR 6
21 * .....
22 *
23 * Softirq IVG14
24 * System Call --
25 * (lowest priority) IVG15
26 */
27 11
28#define SYS_IRQS 39 12#define SYS_IRQS 39
29#define NR_PERI_INTS 32 13#define NR_PERI_INTS 32
30 14
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /*Emulation */
34#define IRQ_RST 1 /*reset */
35#define IRQ_NMI 2 /*Non Maskable */
36#define IRQ_EVX 3 /*Exception */
37#define IRQ_UNUSED 4 /*- unused interrupt*/
38#define IRQ_HWERR 5 /*Hardware Error */
39#define IRQ_CORETMR 6 /*Core timer */
40
41#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ 15#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
42#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ 16#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
43#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */ 17#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
@@ -144,17 +118,6 @@
144#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */ 118#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
145 119
146#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 120#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
147#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
148
149#define IVG7 7
150#define IVG8 8
151#define IVG9 9
152#define IVG10 10
153#define IVG11 11
154#define IVG12 12
155#define IVG13 13
156#define IVG14 14
157#define IVG15 15
158 121
159/* IAR0 BIT FIELDS*/ 122/* IAR0 BIT FIELDS*/
160#define IRQ_PLL_WAKEUP_POS 0 123#define IRQ_PLL_WAKEUP_POS 0
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
index 7a479d224dc7..08d47675d71f 100644
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -7,39 +7,10 @@
7#ifndef _BF538_IRQ_H_ 7#ifndef _BF538_IRQ_H_
8#define _BF538_IRQ_H_ 8#define _BF538_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions
12 Event Source Core Event Name
13 Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22 .....
23
24 Software Interrupt 1 IVG14 31
25 Software Interrupt 2 --
26 (lowest priority) IVG15 32 *
27*/
28 11
29#define NR_PERI_INTS (2 * 32) 12#define NR_PERI_INTS (2 * 32)
30 13
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /* Emulation */
34#define IRQ_RST 1 /* reset */
35#define IRQ_NMI 2 /* Non Maskable */
36#define IRQ_EVX 3 /* Exception */
37#define IRQ_UNUSED 4 /* - unused interrupt */
38#define IRQ_HWERR 5 /* Hardware Error */
39#define IRQ_CORETMR 6 /* Core timer */
40
41#define BFIN_IRQ(x) ((x) + 7)
42
43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
45#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */ 16#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
@@ -111,17 +82,6 @@
111#define GPIO_IRQ_BASE IRQ_PF0 82#define GPIO_IRQ_BASE IRQ_PF0
112 83
113#define NR_MACH_IRQS (IRQ_PF15 + 1) 84#define NR_MACH_IRQS (IRQ_PF15 + 1)
114#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
115
116#define IVG7 7
117#define IVG8 8
118#define IVG9 9
119#define IVG10 10
120#define IVG11 11
121#define IVG12 12
122#define IVG13 13
123#define IVG14 14
124#define IVG15 15
125 85
126/* IAR0 BIT FIELDS */ 86/* IAR0 BIT FIELDS */
127#define IRQ_PLL_WAKEUP_POS 0 87#define IRQ_PLL_WAKEUP_POS 0
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 7f87787e7738..19f209ff4329 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -7,39 +7,10 @@
7#ifndef _BF548_IRQ_H_ 7#ifndef _BF548_IRQ_H_
8#define _BF548_IRQ_H_ 8#define _BF548_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions
12 Event Source Core Event Name
13Core Emulation **
14Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22.....
23
24 Software Interrupt 1 IVG14 31
25 Software Interrupt 2 --
26 (lowest priority) IVG15 32 *
27 */
28 11
29#define NR_PERI_INTS (32 * 3) 12#define NR_PERI_INTS (32 * 3)
30 13
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /* Emulation */
34#define IRQ_RST 1 /* reset */
35#define IRQ_NMI 2 /* Non Maskable */
36#define IRQ_EVX 3 /* Exception */
37#define IRQ_UNUSED 4 /* - unused interrupt*/
38#define IRQ_HWERR 5 /* Hardware Error */
39#define IRQ_CORETMR 6 /* Core timer */
40
41#define BFIN_IRQ(x) ((x) + 7)
42
43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ 15#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
45#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ 16#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
@@ -314,7 +285,6 @@ Events (highest priority) EMU 0
314#define GPIO_IRQ_BASE IRQ_PA0 285#define GPIO_IRQ_BASE IRQ_PA0
315 286
316#define NR_MACH_IRQS (IRQ_PJ15 + 1) 287#define NR_MACH_IRQS (IRQ_PJ15 + 1)
317#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
318 288
319/* For compatibility reasons with existing code */ 289/* For compatibility reasons with existing code */
320 290
@@ -343,17 +313,6 @@ Events (highest priority) EMU 0
343#define IRQ_CAN1_ERR IRQ_CAN1_ERROR 313#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
344#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR 314#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
345 315
346
347#define IVG7 7
348#define IVG8 8
349#define IVG9 9
350#define IVG10 10
351#define IVG11 11
352#define IVG12 12
353#define IVG13 13
354#define IVG14 14
355#define IVG15 15
356
357/* IAR0 BIT FIELDS */ 316/* IAR0 BIT FIELDS */
358#define IRQ_PLL_WAKEUP_POS 0 317#define IRQ_PLL_WAKEUP_POS 0
359#define IRQ_DMAC0_ERR_POS 4 318#define IRQ_DMAC0_ERR_POS 4
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
index c95566ade51b..aa8f5953a1ac 100644
--- a/arch/blackfin/mach-bf561/include/mach/irq.h
+++ b/arch/blackfin/mach-bf561/include/mach/irq.h
@@ -7,115 +7,11 @@
7#ifndef _BF561_IRQ_H_ 7#ifndef _BF561_IRQ_H_
8#define _BF561_IRQ_H_ 8#define _BF561_IRQ_H_
9 9
10/*********************************************************************** 10#include <mach-common/irq.h>
11 * Interrupt source definitions:
12 Event Source Core Event Name IRQ No
13 (highest priority)
14 Emulation Events EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22 PLL Wakeup Interrupt IVG7 7
23 DMA1 Error (generic) IVG7 8
24 DMA2 Error (generic) IVG7 9
25 IMDMA Error (generic) IVG7 10
26 PPI1 Error Interrupt IVG7 11
27 PPI2 Error Interrupt IVG7 12
28 SPORT0 Error Interrupt IVG7 13
29 SPORT1 Error Interrupt IVG7 14
30 SPI Error Interrupt IVG7 15
31 UART Error Interrupt IVG7 16
32 Reserved Interrupt IVG7 17
33
34 DMA1 0 Interrupt(PPI1) IVG8 18
35 DMA1 1 Interrupt(PPI2) IVG8 19
36 DMA1 2 Interrupt IVG8 20
37 DMA1 3 Interrupt IVG8 21
38 DMA1 4 Interrupt IVG8 22
39 DMA1 5 Interrupt IVG8 23
40 DMA1 6 Interrupt IVG8 24
41 DMA1 7 Interrupt IVG8 25
42 DMA1 8 Interrupt IVG8 26
43 DMA1 9 Interrupt IVG8 27
44 DMA1 10 Interrupt IVG8 28
45 DMA1 11 Interrupt IVG8 29
46
47 DMA2 0 (SPORT0 RX) IVG9 30
48 DMA2 1 (SPORT0 TX) IVG9 31
49 DMA2 2 (SPORT1 RX) IVG9 32
50 DMA2 3 (SPORT2 TX) IVG9 33
51 DMA2 4 (SPI) IVG9 34
52 DMA2 5 (UART RX) IVG9 35
53 DMA2 6 (UART TX) IVG9 36
54 DMA2 7 Interrupt IVG9 37
55 DMA2 8 Interrupt IVG9 38
56 DMA2 9 Interrupt IVG9 39
57 DMA2 10 Interrupt IVG9 40
58 DMA2 11 Interrupt IVG9 41
59
60 TIMER 0 Interrupt IVG10 42
61 TIMER 1 Interrupt IVG10 43
62 TIMER 2 Interrupt IVG10 44
63 TIMER 3 Interrupt IVG10 45
64 TIMER 4 Interrupt IVG10 46
65 TIMER 5 Interrupt IVG10 47
66 TIMER 6 Interrupt IVG10 48
67 TIMER 7 Interrupt IVG10 49
68 TIMER 8 Interrupt IVG10 50
69 TIMER 9 Interrupt IVG10 51
70 TIMER 10 Interrupt IVG10 52
71 TIMER 11 Interrupt IVG10 53
72
73 Programmable Flags0 A (8) IVG11 54
74 Programmable Flags0 B (8) IVG11 55
75 Programmable Flags1 A (8) IVG11 56
76 Programmable Flags1 B (8) IVG11 57
77 Programmable Flags2 A (8) IVG11 58
78 Programmable Flags2 B (8) IVG11 59
79
80 MDMA1 0 write/read INT IVG8 60
81 MDMA1 1 write/read INT IVG8 61
82
83 MDMA2 0 write/read INT IVG9 62
84 MDMA2 1 write/read INT IVG9 63
85
86 IMDMA 0 write/read INT IVG12 64
87 IMDMA 1 write/read INT IVG12 65
88
89 Watch Dog Timer IVG13 66
90
91 Reserved interrupt IVG7 67
92 Reserved interrupt IVG7 68
93 Supplemental interrupt 0 IVG7 69
94 supplemental interrupt 1 IVG7 70
95
96 Softirq IVG14
97 System Call --
98 (lowest priority) IVG15
99
100 **********************************************************************/
101 11
102#define SYS_IRQS 71 12#define SYS_IRQS 71
103#define NR_PERI_INTS 64 13#define NR_PERI_INTS 64
104 14
105/*
106 * The ABSTRACT IRQ definitions
107 * the first seven of the following are fixed,
108 * the rest you change if you need to.
109 */
110/* IVG 0-6*/
111#define IRQ_EMU 0 /* Emulation */
112#define IRQ_RST 1 /* Reset */
113#define IRQ_NMI 2 /* Non Maskable Interrupt */
114#define IRQ_EVX 3 /* Exception */
115#define IRQ_UNUSED 4 /* Reserved interrupt */
116#define IRQ_HWERR 5 /* Hardware Error */
117#define IRQ_CORETMR 6 /* Core timer */
118
119#define IVG_BASE 7 15#define IVG_BASE 7
120/* IVG 7 */ 16/* IVG 7 */
121#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ 17#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
@@ -266,17 +162,6 @@
266#define GPIO_IRQ_BASE IRQ_PF0 162#define GPIO_IRQ_BASE IRQ_PF0
267 163
268#define NR_MACH_IRQS (IRQ_PF47 + 1) 164#define NR_MACH_IRQS (IRQ_PF47 + 1)
269#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
270
271#define IVG7 7
272#define IVG8 8
273#define IVG9 9
274#define IVG10 10
275#define IVG11 11
276#define IVG12 12
277#define IVG13 13
278#define IVG14 14
279#define IVG15 15
280 165
281/* 166/*
282 * DEFAULT PRIORITIES: 167 * DEFAULT PRIORITIES:
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 07:59:18 -0500