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authorBruce Allan <bruce.w.allan@intel.com>2011-01-06 09:29:49 -0500
committerDavid S. Miller <davem@davemloft.net>2011-01-10 02:44:07 -0500
commit482fed85e64958f678a138a4b5f8891190d2b169 (patch)
tree5904011346d4659039122c083741d63f48379c54
parentdd93f95e92283498f2497a632a81c167444668b5 (diff)
e1000e: convert calls of ops.[read|write]_reg to e1e_[r|w]phy
Cleans up the code a bit by using the driver-specific e1e_rphy and e1e_wphy macros instead of the full function pointer variants. Fix a couple whitespace issue with two already existing calls to e1e_wphy. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/e1000e/ich8lan.c54
-rw-r--r--drivers/net/e1000e/lib.c3
-rw-r--r--drivers/net/e1000e/phy.c40
3 files changed, 44 insertions, 53 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 754590d79f6d..902e4935f3ee 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -3118,7 +3118,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3118 * Reset the phy after disabling host wakeup to reset the Rx buffer. 3118 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3119 */ 3119 */
3120 if (hw->phy.type == e1000_phy_82578) { 3120 if (hw->phy.type == e1000_phy_82578) {
3121 hw->phy.ops.read_reg(hw, BM_WUC, &i); 3121 e1e_rphy(hw, BM_WUC, &i);
3122 ret_val = e1000_phy_hw_reset_ich8lan(hw); 3122 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3123 if (ret_val) 3123 if (ret_val)
3124 return ret_val; 3124 return ret_val;
@@ -3276,9 +3276,8 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3276 (hw->phy.type == e1000_phy_82577)) { 3276 (hw->phy.type == e1000_phy_82577)) {
3277 ew32(FCRTV_PCH, hw->fc.refresh_time); 3277 ew32(FCRTV_PCH, hw->fc.refresh_time);
3278 3278
3279 ret_val = hw->phy.ops.write_reg(hw, 3279 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3280 PHY_REG(BM_PORT_CTRL_PAGE, 27), 3280 hw->fc.pause_time);
3281 hw->fc.pause_time);
3282 if (ret_val) 3281 if (ret_val)
3283 return ret_val; 3282 return ret_val;
3284 } 3283 }
@@ -3342,8 +3341,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3342 return ret_val; 3341 return ret_val;
3343 break; 3342 break;
3344 case e1000_phy_ife: 3343 case e1000_phy_ife:
3345 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 3344 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3346 &reg_data);
3347 if (ret_val) 3345 if (ret_val)
3348 return ret_val; 3346 return ret_val;
3349 3347
@@ -3361,8 +3359,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3361 reg_data |= IFE_PMC_AUTO_MDIX; 3359 reg_data |= IFE_PMC_AUTO_MDIX;
3362 break; 3360 break;
3363 } 3361 }
3364 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 3362 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3365 reg_data);
3366 if (ret_val) 3363 if (ret_val)
3367 return ret_val; 3364 return ret_val;
3368 break; 3365 break;
@@ -3646,7 +3643,8 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3646{ 3643{
3647 if (hw->phy.type == e1000_phy_ife) 3644 if (hw->phy.type == e1000_phy_ife)
3648 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3645 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3649 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 3646 (IFE_PSCL_PROBE_MODE |
3647 IFE_PSCL_PROBE_LEDS_OFF));
3650 3648
3651 ew32(LEDCTL, hw->mac.ledctl_mode1); 3649 ew32(LEDCTL, hw->mac.ledctl_mode1);
3652 return 0; 3650 return 0;
@@ -3660,8 +3658,7 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3660 **/ 3658 **/
3661static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 3659static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3662{ 3660{
3663 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3661 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3664 (u16)hw->mac.ledctl_mode1);
3665} 3662}
3666 3663
3667/** 3664/**
@@ -3672,8 +3669,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3672 **/ 3669 **/
3673static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 3670static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3674{ 3671{
3675 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3672 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3676 (u16)hw->mac.ledctl_default);
3677} 3673}
3678 3674
3679/** 3675/**
@@ -3704,7 +3700,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3704 } 3700 }
3705 } 3701 }
3706 3702
3707 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 3703 return e1e_wphy(hw, HV_LED_CONFIG, data);
3708} 3704}
3709 3705
3710/** 3706/**
@@ -3735,7 +3731,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3735 } 3731 }
3736 } 3732 }
3737 3733
3738 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 3734 return e1e_wphy(hw, HV_LED_CONFIG, data);
3739} 3735}
3740 3736
3741/** 3737/**
@@ -3844,20 +3840,20 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3844 if ((hw->phy.type == e1000_phy_82578) || 3840 if ((hw->phy.type == e1000_phy_82578) ||
3845 (hw->phy.type == e1000_phy_82579) || 3841 (hw->phy.type == e1000_phy_82579) ||
3846 (hw->phy.type == e1000_phy_82577)) { 3842 (hw->phy.type == e1000_phy_82577)) {
3847 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data); 3843 e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3848 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data); 3844 e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
3849 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data); 3845 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
3850 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data); 3846 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
3851 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data); 3847 e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
3852 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data); 3848 e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
3853 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data); 3849 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
3854 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data); 3850 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
3855 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data); 3851 e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
3856 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data); 3852 e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
3857 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data); 3853 e1e_rphy(hw, HV_DC_UPPER, &phy_data);
3858 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data); 3854 e1e_rphy(hw, HV_DC_LOWER, &phy_data);
3859 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data); 3855 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
3860 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data); 3856 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
3861 } 3857 }
3862} 3858}
3863 3859
diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c
index 7e55170a601e..ff2872153b21 100644
--- a/drivers/net/e1000e/lib.c
+++ b/drivers/net/e1000e/lib.c
@@ -1135,7 +1135,8 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1135 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); 1135 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1136 if (ret_val) 1136 if (ret_val)
1137 return ret_val; 1137 return ret_val;
1138 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); 1138 ret_val =
1139 e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1139 if (ret_val) 1140 if (ret_val)
1140 return ret_val; 1141 return ret_val;
1141 1142
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 1781efeb55e3..a640f1c369ae 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -637,12 +637,11 @@ s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
637 **/ 637 **/
638s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 638s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
639{ 639{
640 struct e1000_phy_info *phy = &hw->phy;
641 s32 ret_val; 640 s32 ret_val;
642 u16 phy_data; 641 u16 phy_data;
643 642
644 /* Enable CRS on TX. This must be set for half-duplex operation. */ 643 /* Enable CRS on TX. This must be set for half-duplex operation. */
645 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); 644 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
646 if (ret_val) 645 if (ret_val)
647 goto out; 646 goto out;
648 647
@@ -651,7 +650,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
651 /* Enable downshift */ 650 /* Enable downshift */
652 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 651 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
653 652
654 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); 653 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
655 654
656out: 655out:
657 return ret_val; 656 return ret_val;
@@ -774,16 +773,14 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
774 } 773 }
775 774
776 if (phy->type == e1000_phy_82578) { 775 if (phy->type == e1000_phy_82578) {
777 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 776 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
778 &phy_data);
779 if (ret_val) 777 if (ret_val)
780 return ret_val; 778 return ret_val;
781 779
782 /* 82578 PHY - set the downshift count to 1x. */ 780 /* 82578 PHY - set the downshift count to 1x. */
783 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 781 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
784 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 782 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
785 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 783 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
786 phy_data);
787 if (ret_val) 784 if (ret_val)
788 return ret_val; 785 return ret_val;
789 } 786 }
@@ -1319,9 +1316,8 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1319 * We didn't get link. 1316 * We didn't get link.
1320 * Reset the DSP and cross our fingers. 1317 * Reset the DSP and cross our fingers.
1321 */ 1318 */
1322 ret_val = e1e_wphy(hw, 1319 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1323 M88E1000_PHY_PAGE_SELECT, 1320 0x001d);
1324 0x001d);
1325 if (ret_val) 1321 if (ret_val)
1326 return ret_val; 1322 return ret_val;
1327 ret_val = e1000e_phy_reset_dsp(hw); 1323 ret_val = e1000e_phy_reset_dsp(hw);
@@ -3071,12 +3067,12 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3071 goto out; 3067 goto out;
3072 3068
3073 /* Do not apply workaround if in PHY loopback bit 14 set */ 3069 /* Do not apply workaround if in PHY loopback bit 14 set */
3074 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3070 e1e_rphy(hw, PHY_CONTROL, &data);
3075 if (data & PHY_CONTROL_LB) 3071 if (data & PHY_CONTROL_LB)
3076 goto out; 3072 goto out;
3077 3073
3078 /* check if link is up and at 1Gbps */ 3074 /* check if link is up and at 1Gbps */
3079 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3075 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3080 if (ret_val) 3076 if (ret_val)
3081 goto out; 3077 goto out;
3082 3078
@@ -3092,14 +3088,12 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3092 mdelay(200); 3088 mdelay(200);
3093 3089
3094 /* flush the packets in the fifo buffer */ 3090 /* flush the packets in the fifo buffer */
3095 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3091 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3096 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3092 HV_MUX_DATA_CTRL_FORCE_SPEED);
3097 HV_MUX_DATA_CTRL_FORCE_SPEED);
3098 if (ret_val) 3093 if (ret_val)
3099 goto out; 3094 goto out;
3100 3095
3101 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3096 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3102 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3103 3097
3104out: 3098out:
3105 return ret_val; 3099 return ret_val;
@@ -3119,7 +3113,7 @@ s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3119 s32 ret_val; 3113 s32 ret_val;
3120 u16 data; 3114 u16 data;
3121 3115
3122 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3116 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3123 3117
3124 if (!ret_val) 3118 if (!ret_val)
3125 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3119 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
@@ -3142,13 +3136,13 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3142 u16 phy_data; 3136 u16 phy_data;
3143 bool link; 3137 bool link;
3144 3138
3145 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3139 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
3146 if (ret_val) 3140 if (ret_val)
3147 goto out; 3141 goto out;
3148 3142
3149 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 3143 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3150 3144
3151 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3145 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
3152 if (ret_val) 3146 if (ret_val)
3153 goto out; 3147 goto out;
3154 3148
@@ -3212,7 +3206,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3212 if (ret_val) 3206 if (ret_val)
3213 goto out; 3207 goto out;
3214 3208
3215 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3209 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3216 if (ret_val) 3210 if (ret_val)
3217 goto out; 3211 goto out;
3218 3212
@@ -3224,7 +3218,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3224 if (ret_val) 3218 if (ret_val)
3225 goto out; 3219 goto out;
3226 3220
3227 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3221 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
3228 if (ret_val) 3222 if (ret_val)
3229 goto out; 3223 goto out;
3230 3224
@@ -3258,7 +3252,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3258 s32 ret_val; 3252 s32 ret_val;
3259 u16 phy_data, length; 3253 u16 phy_data, length;
3260 3254
3261 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3255 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3262 if (ret_val) 3256 if (ret_val)
3263 goto out; 3257 goto out;
3264 3258