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authorStefan Richter <stefanr@s5r6.in-berlin.de>2010-02-19 15:00:31 -0500
committerStefan Richter <stefanr@s5r6.in-berlin.de>2010-02-24 14:36:54 -0500
commitfd6e0c518121d22b50060d26c8aec2b701c6aab7 (patch)
tree187955ecd1f8dd1319ad8fb4ddf1b434548718da
parent137d9ebfdbaa45c01f9f0f6d5121ae6f1eb942bd (diff)
firewire: core: rename an internal function
according to what it really does. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
-rw-r--r--drivers/firewire/core-device.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/firewire/core-device.c b/drivers/firewire/core-device.c
index f61211977d33..014cabd3afda 100644
--- a/drivers/firewire/core-device.c
+++ b/drivers/firewire/core-device.c
@@ -492,29 +492,29 @@ static int read_rom(struct fw_device *device,
492 return rcode; 492 return rcode;
493} 493}
494 494
495#define READ_BIB_ROM_SIZE 256 495#define MAX_CONFIG_ROM_SIZE 256
496 496
497/* 497/*
498 * Read the bus info block, perform a speed probe, and read all of the rest of 498 * Read the bus info block, perform a speed probe, and read all of the rest of
499 * the config ROM. We do all this with a cached bus generation. If the bus 499 * the config ROM. We do all this with a cached bus generation. If the bus
500 * generation changes under us, read_bus_info_block will fail and get retried. 500 * generation changes under us, read_config_rom will fail and get retried.
501 * It's better to start all over in this case because the node from which we 501 * It's better to start all over in this case because the node from which we
502 * are reading the ROM may have changed the ROM during the reset. 502 * are reading the ROM may have changed the ROM during the reset.
503 */ 503 */
504static int read_bus_info_block(struct fw_device *device, int generation) 504static int read_config_rom(struct fw_device *device, int generation)
505{ 505{
506 const u32 *old_rom, *new_rom; 506 const u32 *old_rom, *new_rom;
507 u32 *rom, *stack; 507 u32 *rom, *stack;
508 u32 sp, key; 508 u32 sp, key;
509 int i, end, length, ret = -1; 509 int i, end, length, ret = -1;
510 510
511 rom = kmalloc(sizeof(*rom) * READ_BIB_ROM_SIZE + 511 rom = kmalloc(sizeof(*rom) * MAX_CONFIG_ROM_SIZE +
512 sizeof(*stack) * READ_BIB_ROM_SIZE, GFP_KERNEL); 512 sizeof(*stack) * MAX_CONFIG_ROM_SIZE, GFP_KERNEL);
513 if (rom == NULL) 513 if (rom == NULL)
514 return -ENOMEM; 514 return -ENOMEM;
515 515
516 stack = &rom[READ_BIB_ROM_SIZE]; 516 stack = &rom[MAX_CONFIG_ROM_SIZE];
517 memset(rom, 0, sizeof(*rom) * READ_BIB_ROM_SIZE); 517 memset(rom, 0, sizeof(*rom) * MAX_CONFIG_ROM_SIZE);
518 518
519 device->max_speed = SCODE_100; 519 device->max_speed = SCODE_100;
520 520
@@ -581,14 +581,14 @@ static int read_bus_info_block(struct fw_device *device, int generation)
581 */ 581 */
582 key = stack[--sp]; 582 key = stack[--sp];
583 i = key & 0xffffff; 583 i = key & 0xffffff;
584 if (WARN_ON(i >= READ_BIB_ROM_SIZE)) 584 if (WARN_ON(i >= MAX_CONFIG_ROM_SIZE))
585 goto out; 585 goto out;
586 586
587 /* Read header quadlet for the block to get the length. */ 587 /* Read header quadlet for the block to get the length. */
588 if (read_rom(device, generation, i, &rom[i]) != RCODE_COMPLETE) 588 if (read_rom(device, generation, i, &rom[i]) != RCODE_COMPLETE)
589 goto out; 589 goto out;
590 end = i + (rom[i] >> 16) + 1; 590 end = i + (rom[i] >> 16) + 1;
591 if (end > READ_BIB_ROM_SIZE) { 591 if (end > MAX_CONFIG_ROM_SIZE) {
592 /* 592 /*
593 * This block extends outside the config ROM which is 593 * This block extends outside the config ROM which is
594 * a firmware bug. Ignore this whole block, i.e. 594 * a firmware bug. Ignore this whole block, i.e.
@@ -621,7 +621,7 @@ static int read_bus_info_block(struct fw_device *device, int generation)
621 * fake immediate entry so that later iterators over 621 * fake immediate entry so that later iterators over
622 * the ROM don't have to check offsets all the time. 622 * the ROM don't have to check offsets all the time.
623 */ 623 */
624 if (i + (rom[i] & 0xffffff) >= READ_BIB_ROM_SIZE) { 624 if (i + (rom[i] & 0xffffff) >= MAX_CONFIG_ROM_SIZE) {
625 fw_error("skipped unsupported ROM entry %x at %llx\n", 625 fw_error("skipped unsupported ROM entry %x at %llx\n",
626 rom[i], 626 rom[i],
627 i * 4 | CSR_REGISTER_BASE | CSR_CONFIG_ROM); 627 i * 4 | CSR_REGISTER_BASE | CSR_CONFIG_ROM);
@@ -971,7 +971,7 @@ static void fw_device_init(struct work_struct *work)
971 * device. 971 * device.
972 */ 972 */
973 973
974 if (read_bus_info_block(device, device->generation) < 0) { 974 if (read_config_rom(device, device->generation) < 0) {
975 if (device->config_rom_retries < MAX_RETRIES && 975 if (device->config_rom_retries < MAX_RETRIES &&
976 atomic_read(&device->state) == FW_DEVICE_INITIALIZING) { 976 atomic_read(&device->state) == FW_DEVICE_INITIALIZING) {
977 device->config_rom_retries++; 977 device->config_rom_retries++;
@@ -1088,7 +1088,7 @@ enum {
1088}; 1088};
1089 1089
1090/* Reread and compare bus info block and header of root directory */ 1090/* Reread and compare bus info block and header of root directory */
1091static int reread_bus_info_block(struct fw_device *device, int generation) 1091static int reread_config_rom(struct fw_device *device, int generation)
1092{ 1092{
1093 u32 q; 1093 u32 q;
1094 int i; 1094 int i;
@@ -1114,7 +1114,7 @@ static void fw_device_refresh(struct work_struct *work)
1114 struct fw_card *card = device->card; 1114 struct fw_card *card = device->card;
1115 int node_id = device->node_id; 1115 int node_id = device->node_id;
1116 1116
1117 switch (reread_bus_info_block(device, device->generation)) { 1117 switch (reread_config_rom(device, device->generation)) {
1118 case REREAD_BIB_ERROR: 1118 case REREAD_BIB_ERROR:
1119 if (device->config_rom_retries < MAX_RETRIES / 2 && 1119 if (device->config_rom_retries < MAX_RETRIES / 2 &&
1120 atomic_read(&device->state) == FW_DEVICE_INITIALIZING) { 1120 atomic_read(&device->state) == FW_DEVICE_INITIALIZING) {
@@ -1148,7 +1148,7 @@ static void fw_device_refresh(struct work_struct *work)
1148 */ 1148 */
1149 device_for_each_child(&device->device, NULL, shutdown_unit); 1149 device_for_each_child(&device->device, NULL, shutdown_unit);
1150 1150
1151 if (read_bus_info_block(device, device->generation) < 0) { 1151 if (read_config_rom(device, device->generation) < 0) {
1152 if (device->config_rom_retries < MAX_RETRIES && 1152 if (device->config_rom_retries < MAX_RETRIES &&
1153 atomic_read(&device->state) == FW_DEVICE_INITIALIZING) { 1153 atomic_read(&device->state) == FW_DEVICE_INITIALIZING) {
1154 device->config_rom_retries++; 1154 device->config_rom_retries++;
' href='#n1072'>1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662
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/* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
/*
	Written 2002-2004 by David Dillow <dave@thedillows.org>
	Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
	Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.

	This software may be used and distributed according to the terms of
	the GNU General Public License (GPL), incorporated herein by reference.
	Drivers based on or derived from this code fall under the GPL and must
	retain the authorship, copyright and license notice.  This file is not
	a complete program and may only be used when the entire operating
	system is licensed under the GPL.

	This software is available on a public web site. It may enable
	cryptographic capabilities of the 3Com hardware, and may be
	exported from the United States under License Exception "TSU"
	pursuant to 15 C.F.R. Section 740.13(e).

	This work was funded by the National Library of Medicine under
	the Department of Energy project number 0274DD06D1 and NLM project
	number Y1-LM-2015-01.

	This driver is designed for the 3Com 3CR990 Family of cards with the
	3XP Processor. It has been tested on x86 and sparc64.

	KNOWN ISSUES:
	*) The current firmware always strips the VLAN tag off, even if
		we tell it not to. You should filter VLANs at the switch
		as a workaround (good practice in any event) until we can
		get this fixed.
	*) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
		issue. Hopefully 3Com will fix it.
	*) Waiting for a command response takes 8ms due to non-preemptable
		polling. Only significant for getting stats and creating
		SAs, but an ugly wart never the less.

	TODO:
	*) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
	*) Add more support for ethtool (especially for NIC stats)
	*) Allow disabling of RX checksum offloading
	*) Fix MAC changing to work while the interface is up
		(Need to put commands on the TX ring, which changes
		the locking)
	*) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
		http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
*/

/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
 * Setting to > 1518 effectively disables this feature.
 */
static int rx_copybreak = 200;

/* Should we use MMIO or Port IO?
 * 0: Port IO
 * 1: MMIO
 * 2: Try MMIO, fallback to Port IO
 */
static unsigned int use_mmio = 2;

/* end user-configurable values */

/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
 */
static const int multicast_filter_limit = 32;

/* Operational parameters that are set at compile time. */

/* Keep the ring sizes a power of two for compile efficiency.
 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
 * Making the Tx ring too large decreases the effectiveness of channel
 * bonding and packet priority.
 * There are no ill effects from too-large receive rings.
 *
 * We don't currently use the Hi Tx ring so, don't make it very big.
 *
 * Beware that if we start using the Hi Tx ring, we will need to change
 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
 */
#define TXHI_ENTRIES		2
#define TXLO_ENTRIES		128
#define RX_ENTRIES		32
#define COMMAND_ENTRIES		16
#define RESPONSE_ENTRIES	32

#define COMMAND_RING_SIZE	(COMMAND_ENTRIES * sizeof(struct cmd_desc))
#define RESPONSE_RING_SIZE	(RESPONSE_ENTRIES * sizeof(struct resp_desc))

/* The 3XP will preload and remove 64 entries from the free buffer
 * list, and we need one entry to keep the ring from wrapping, so 
 * to keep this a power of two, we use 128 entries.
 */
#define RXFREE_ENTRIES		128
#define RXENT_ENTRIES		(RXFREE_ENTRIES - 1)

/* Operational parameters that usually are not changed. */

/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT  (2*HZ)

#define PKT_BUF_SZ		1536

#define DRV_MODULE_NAME		"typhoon"
#define DRV_MODULE_VERSION 	"1.5.7"
#define DRV_MODULE_RELDATE	"05/01/07"
#define PFX			DRV_MODULE_NAME ": "
#define ERR_PFX			KERN_ERR PFX

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/bitops.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <linux/in6.h>
#include <asm/checksum.h>
#include <linux/version.h>
#include <linux/dma-mapping.h>

#include "typhoon.h"
#include "typhoon-firmware.h"

static const char version[] __devinitdata =
    "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";

MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
MODULE_VERSION(DRV_MODULE_VERSION);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
			       "the buffer given back to the NIC. Default "
			       "is 200.");
MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
			   "Default is to try MMIO and fallback to PIO.");
module_param(rx_copybreak, int, 0);
module_param(use_mmio, int, 0);

#if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
#warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
#undef NETIF_F_TSO
#endif

#if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
#error TX ring too small!
#endif

struct typhoon_card_info {
	char *name;
	int capabilities;
};

#define TYPHOON_CRYPTO_NONE		0x00
#define TYPHOON_CRYPTO_DES		0x01
#define TYPHOON_CRYPTO_3DES		0x02
#define	TYPHOON_CRYPTO_VARIABLE		0x04
#define TYPHOON_FIBER			0x08
#define TYPHOON_WAKEUP_NEEDS_RESET	0x10

enum typhoon_cards {
	TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
	TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
	TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
	TYPHOON_FXM,
};

/* directly indexed by enum typhoon_cards, above */
static const struct typhoon_card_info typhoon_card_info[] __devinitdata = {
	{ "3Com Typhoon (3C990-TX)",
		TYPHOON_CRYPTO_NONE},
	{ "3Com Typhoon (3CR990-TX-95)",
		TYPHOON_CRYPTO_DES},
	{ "3Com Typhoon (3CR990-TX-97)",
	 	TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
	{ "3Com Typhoon (3C990SVR)",
		TYPHOON_CRYPTO_NONE},
	{ "3Com Typhoon (3CR990SVR95)",
		TYPHOON_CRYPTO_DES},
	{ "3Com Typhoon (3CR990SVR97)",
	 	TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
	{ "3Com Typhoon2 (3C990B-TX-M)",
		TYPHOON_CRYPTO_VARIABLE},
	{ "3Com Typhoon2 (3C990BSVR)",
		TYPHOON_CRYPTO_VARIABLE},
	{ "3Com Typhoon (3CR990-FX-95)",
		TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
	{ "3Com Typhoon (3CR990-FX-97)",
	 	TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
	{ "3Com Typhoon (3CR990-FX-95 Server)",
	 	TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
	{ "3Com Typhoon (3CR990-FX-97 Server)",
	 	TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
	{ "3Com Typhoon2 (3C990B-FX-97)",
		TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
};

/* Notes on the new subsystem numbering scheme:
 * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
 * bit 4 indicates if this card has secured firmware (we don't support it)
 * bit 8 indicates if this is a (0) copper or (1) fiber card
 * bits 12-16 indicate card type: (0) client and (1) server
 */
static struct pci_device_id typhoon_pci_tbl[] = {
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
	  PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
	  PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
	  PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
	  PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
	  PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
	  PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
	  PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);

/* Define the shared memory area
 * Align everything the 3XP will normally be using.
 * We'll need to move/align txHi if we start using that ring.
 */
#define __3xp_aligned	____cacheline_aligned
struct typhoon_shared {
	struct typhoon_interface	iface;
	struct typhoon_indexes		indexes			__3xp_aligned;
	struct tx_desc			txLo[TXLO_ENTRIES] 	__3xp_aligned;
	struct rx_desc			rxLo[RX_ENTRIES]	__3xp_aligned;
	struct rx_desc			rxHi[RX_ENTRIES]	__3xp_aligned;
	struct cmd_desc			cmd[COMMAND_ENTRIES]	__3xp_aligned;
	struct resp_desc		resp[RESPONSE_ENTRIES]	__3xp_aligned;
	struct rx_free			rxBuff[RXFREE_ENTRIES]	__3xp_aligned;
	u32				zeroWord;
	struct tx_desc			txHi[TXHI_ENTRIES];
} __attribute__ ((packed));

struct rxbuff_ent {
	struct sk_buff *skb;
	dma_addr_t	dma_addr;
};

struct typhoon {
	/* Tx cache line section */
	struct transmit_ring 	txLoRing	____cacheline_aligned;	
	struct pci_dev *	tx_pdev;
	void __iomem		*tx_ioaddr;
	u32			txlo_dma_addr;

	/* Irq/Rx cache line section */
	void __iomem		*ioaddr		____cacheline_aligned;
	struct typhoon_indexes *indexes;
	u8			awaiting_resp;
	u8			duplex;
	u8			speed;
	u8			card_state;
	struct basic_ring	rxLoRing;
	struct pci_dev *	pdev;
	struct net_device *	dev;
	spinlock_t		state_lock;
	struct vlan_group *	vlgrp;
	struct basic_ring	rxHiRing;
	struct basic_ring	rxBuffRing;
	struct rxbuff_ent	rxbuffers[RXENT_ENTRIES];

	/* general section */
	spinlock_t		command_lock	____cacheline_aligned;
	struct basic_ring	cmdRing;
	struct basic_ring	respRing;
	struct net_device_stats	stats;
	struct net_device_stats	stats_saved;
	const char *		name;
	struct typhoon_shared *	shared;
	dma_addr_t		shared_dma;
	u16			xcvr_select;
	u16			wol_events;
	u32			offload;

	/* unused stuff (future use) */
	int			capabilities;
	struct transmit_ring 	txHiRing;
};

enum completion_wait_values {
	NoWait = 0, WaitNoSleep, WaitSleep,
};

/* These are the values for the typhoon.card_state variable.
 * These determine where the statistics will come from in get_stats().
 * The sleep image does not support the statistics we need.
 */
enum state_values {
	Sleeping = 0, Running,
};

/* PCI writes are not guaranteed to be posted in order, but outstanding writes
 * cannot pass a read, so this forces current writes to post.
 */
#define typhoon_post_pci_writes(x) \
	do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)

/* We'll wait up to six seconds for a reset, and half a second normally.
 */
#define TYPHOON_UDELAY			50
#define TYPHOON_RESET_TIMEOUT_SLEEP	(6 * HZ)
#define TYPHOON_RESET_TIMEOUT_NOSLEEP	((6 * 1000000) / TYPHOON_UDELAY)
#define TYPHOON_WAIT_TIMEOUT		((1000000 / 2) / TYPHOON_UDELAY)

#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 28)
#define typhoon_synchronize_irq(x) synchronize_irq()
#else
#define typhoon_synchronize_irq(x) synchronize_irq(x)
#endif

#if defined(NETIF_F_TSO)
#define skb_tso_size(x)		(skb_shinfo(x)->tso_size)
#define TSO_NUM_DESCRIPTORS	2
#define TSO_OFFLOAD_ON		TYPHOON_OFFLOAD_TCP_SEGMENT
#else
#define NETIF_F_TSO 		0
#define skb_tso_size(x) 	0
#define TSO_NUM_DESCRIPTORS	0
#define TSO_OFFLOAD_ON		0
#endif

static inline void
typhoon_inc_index(u32 *index, const int count, const int num_entries)
{
	/* Increment a ring index -- we can use this for all rings execept
	 * the Rx rings, as they use different size descriptors
	 * otherwise, everything is the same size as a cmd_desc
	 */
	*index += count * sizeof(struct cmd_desc);
	*index %= num_entries * sizeof(struct cmd_desc);
}

static inline void
typhoon_inc_cmd_index(u32 *index, const int count)
{
	typhoon_inc_index(index, count, COMMAND_ENTRIES);
}

static inline void
typhoon_inc_resp_index(u32 *index, const int count)
{
	typhoon_inc_index(index, count, RESPONSE_ENTRIES);
}

static inline void
typhoon_inc_rxfree_index(u32 *index, const int count)
{
	typhoon_inc_index(index, count, RXFREE_ENTRIES);
}

static inline void
typhoon_inc_tx_index(u32 *index, const int count)
{
	/* if we start using the Hi Tx ring, this needs updateing */
	typhoon_inc_index(index, count, TXLO_ENTRIES);
}

static inline void
typhoon_inc_rx_index(u32 *index, const int count)
{
	/* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
	*index += count * sizeof(struct rx_desc);
	*index %= RX_ENTRIES * sizeof(struct rx_desc);
}

static int
typhoon_reset(void __iomem *ioaddr, int wait_type)
{
	int i, err = 0;
	int timeout;

	if(wait_type == WaitNoSleep)
		timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
	else
		timeout = TYPHOON_RESET_TIMEOUT_SLEEP;

	iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
	iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);

	iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
	typhoon_post_pci_writes(ioaddr);
	udelay(1);
	iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);

	if(wait_type != NoWait) {
		for(i = 0; i < timeout; i++) {
			if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
			   TYPHOON_STATUS_WAITING_FOR_HOST)
				goto out;

			if(wait_type == WaitSleep)
				schedule_timeout_uninterruptible(1);
			else
				udelay(TYPHOON_UDELAY);
		}

		err = -ETIMEDOUT;
	}

out:
	iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
	iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);

	/* The 3XP seems to need a little extra time to complete the load
	 * of the sleep image before we can reliably boot it. Failure to
	 * do this occasionally results in a hung adapter after boot in
	 * typhoon_init_one() while trying to read the MAC address or
	 * putting the card to sleep. 3Com's driver waits 5ms, but
	 * that seems to be overkill. However, if we can sleep, we might
	 * as well give it that much time. Otherwise, we'll give it 500us,
	 * which should be enough (I've see it work well at 100us, but still
	 * saw occasional problems.)
	 */
	if(wait_type == WaitSleep)
		msleep(5);
	else
		udelay(500);
	return err;
}

static int
typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
{
	int i, err = 0;

	for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
		if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
			goto out;
		udelay(TYPHOON_UDELAY);
	}

	err = -ETIMEDOUT;

out:
	return err;
}

static inline void
typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
{
	if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
		netif_carrier_off(dev);
	else
		netif_carrier_on(dev);
}

static inline void
typhoon_hello(struct typhoon *tp)
{
	struct basic_ring *ring = &tp->cmdRing;
	struct cmd_desc *cmd;

	/* We only get a hello request if we've not sent anything to the
	 * card in a long while. If the lock is held, then we're in the
	 * process of issuing a command, so we don't need to respond.
	 */
	if(spin_trylock(&tp->command_lock)) {
		cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
		typhoon_inc_cmd_index(&ring->lastWrite, 1);

		INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
		smp_wmb();
		iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
		spin_unlock(&tp->command_lock);
	}
}

static int
typhoon_process_response(struct typhoon *tp, int resp_size,
				struct resp_desc *resp_save)
{
	struct typhoon_indexes *indexes = tp->indexes;
	struct resp_desc *resp;
	u8 *base = tp->respRing.ringBase;
	int count, len, wrap_len;
	u32 cleared;
	u32 ready;

	cleared = le32_to_cpu(indexes->respCleared);
	ready = le32_to_cpu(indexes->respReady);
	while(cleared != ready) {
		resp = (struct resp_desc *)(base + cleared);
		count = resp->numDesc + 1;
		if(resp_save && resp->seqNo) {
			if(count > resp_size) {
				resp_save->flags = TYPHOON_RESP_ERROR;
				goto cleanup;
			}

			wrap_len = 0;
			len = count * sizeof(*resp);
			if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
				wrap_len = cleared + len - RESPONSE_RING_SIZE;
				len = RESPONSE_RING_SIZE - cleared;
			}

			memcpy(resp_save, resp, len);
			if(unlikely(wrap_len)) {
				resp_save += len / sizeof(*resp);
				memcpy(resp_save, base, wrap_len);
			}

			resp_save = NULL;
		} else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
			typhoon_media_status(tp->dev, resp);
		} else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
			typhoon_hello(tp);
		} else {
			printk(KERN_ERR "%s: dumping unexpected response "
			       "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
			       tp->name, le16_to_cpu(resp->cmd),
			       resp->numDesc, resp->flags,
			       le16_to_cpu(resp->parm1),
			       le32_to_cpu(resp->parm2),
			       le32_to_cpu(resp->parm3));
		}

cleanup:
		typhoon_inc_resp_index(&cleared, count);
	}

	indexes->respCleared = cpu_to_le32(cleared);
	wmb();
	return (resp_save == NULL);
}

static inline int
typhoon_num_free(int lastWrite, int lastRead, int ringSize)
{
	/* this works for all descriptors but rx_desc, as they are a
	 * different size than the cmd_desc -- everyone else is the same
	 */
	lastWrite /= sizeof(struct cmd_desc);
	lastRead /= sizeof(struct cmd_desc);
	return (ringSize + lastRead - lastWrite - 1) % ringSize;
}

static inline int
typhoon_num_free_cmd(struct typhoon *tp)
{
	int lastWrite = tp->cmdRing.lastWrite;
	int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);

	return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
}

static inline int
typhoon_num_free_resp(struct typhoon *tp)
{
	int respReady = le32_to_cpu(tp->indexes->respReady);
	int respCleared = le32_to_cpu(tp->indexes->respCleared);

	return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
}

static inline int
typhoon_num_free_tx(struct transmit_ring *ring)
{
	/* if we start using the Hi Tx ring, this needs updating */
	return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
}

static int
typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
		      int num_resp, struct resp_desc *resp)
{
	struct typhoon_indexes *indexes = tp->indexes;
	struct basic_ring *ring = &tp->cmdRing;
	struct resp_desc local_resp;
	int i, err = 0;
	int got_resp;
	int freeCmd, freeResp;
	int len, wrap_len;

	spin_lock(&tp->command_lock);

	freeCmd = typhoon_num_free_cmd(tp);
	freeResp = typhoon_num_free_resp(tp);

	if(freeCmd < num_cmd || freeResp < num_resp) {
		printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
			"%d (%d) resp\n", tp->name, freeCmd, num_cmd,
			freeResp, num_resp);
		err = -ENOMEM;
		goto out;
	}

	if(cmd->flags & TYPHOON_CMD_RESPOND) {
		/* If we're expecting a response, but the caller hasn't given
		 * us a place to put it, we'll provide one.
		 */
		tp->awaiting_resp = 1;
		if(resp == NULL) {
			resp = &local_resp;
			num_resp = 1;
		}
	}

	wrap_len = 0;
	len = num_cmd * sizeof(*cmd);
	if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
		wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
		len = COMMAND_RING_SIZE - ring->lastWrite;
	}

	memcpy(ring->ringBase + ring->lastWrite, cmd, len);
	if(unlikely(wrap_len)) {
		struct cmd_desc *wrap_ptr = cmd;
		wrap_ptr += len / sizeof(*cmd);
		memcpy(ring->ringBase, wrap_ptr, wrap_len);
	}

	typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);

	/* "I feel a presence... another warrior is on the the mesa."
	 */
	wmb();
	iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
	typhoon_post_pci_writes(tp->ioaddr);

	if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
		goto out;

	/* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
	 * preempt or do anything other than take interrupts. So, don't
	 * wait for a response unless you have to.
	 *
	 * I've thought about trying to sleep here, but we're called
	 * from many contexts that don't allow that. Also, given the way
	 * 3Com has implemented irq coalescing, we would likely timeout --
	 * this has been observed in real life!
	 *
	 * The big killer is we have to wait to get stats from the card,
	 * though we could go to a periodic refresh of those if we don't
	 * mind them getting somewhat stale. The rest of the waiting
	 * commands occur during open/close/suspend/resume, so they aren't
	 * time critical. Creating SAs in the future will also have to
	 * wait here.
	 */
	got_resp = 0;
	for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
		if(indexes->respCleared != indexes->respReady)
			got_resp = typhoon_process_response(tp, num_resp,
								resp);
		udelay(TYPHOON_UDELAY);
	}

	if(!got_resp) {
		err = -ETIMEDOUT;
		goto out;
	}

	/* Collect the error response even if we don't care about the
	 * rest of the response
	 */
	if(resp->flags & TYPHOON_RESP_ERROR)
		err = -EIO;

out:
	if(tp->awaiting_resp) {
		tp->awaiting_resp = 0;
		smp_wmb();

		/* Ugh. If a response was added to the ring between
		 * the call to typhoon_process_response() and the clearing
		 * of tp->awaiting_resp, we could have missed the interrupt
		 * and it could hang in the ring an indeterminate amount of
		 * time. So, check for it, and interrupt ourselves if this
		 * is the case.
		 */
		if(indexes->respCleared != indexes->respReady)
			iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
	}

	spin_unlock(&tp->command_lock);
	return err;
}

static void
typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
{
	struct typhoon *tp = netdev_priv(dev);
	struct cmd_desc xp_cmd;
	int err;

	spin_lock_bh(&tp->state_lock);
	if(!tp->vlgrp != !grp) {
		/* We've either been turned on for the first time, or we've
		 * been turned off. Update the 3XP.
		 */
		if(grp)
			tp->offload |= TYPHOON_OFFLOAD_VLAN;
		else
			tp->offload &= ~TYPHOON_OFFLOAD_VLAN;

		/* If the interface is up, the runtime is running -- and we
		 * must be up for the vlan core to call us.
		 *
		 * Do the command outside of the spin lock, as it is slow.
		 */
		INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
					TYPHOON_CMD_SET_OFFLOAD_TASKS);
		xp_cmd.parm2 = tp->offload;
		xp_cmd.parm3 = tp->offload;
		spin_unlock_bh(&tp->state_lock);
		err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
		if(err < 0)
			printk("%s: vlan offload error %d\n", tp->name, -err);
		spin_lock_bh(&tp->state_lock);
	}

	/* now make the change visible */
	tp->vlgrp = grp;
	spin_unlock_bh(&tp->state_lock);
}

static void
typhoon_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
{
	struct typhoon *tp = netdev_priv(dev);
	spin_lock_bh(&tp->state_lock);
	if(tp->vlgrp)
		tp->vlgrp->vlan_devices[vid] = NULL;
	spin_unlock_bh(&tp->state_lock);
}

static inline void
typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
			u32 ring_dma)
{
	struct tcpopt_desc *tcpd;
	u32 tcpd_offset = ring_dma;

	tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
	tcpd_offset += txRing->lastWrite;
	tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
	typhoon_inc_tx_index(&txRing->lastWrite, 1);

	tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
	tcpd->numDesc = 1;
	tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
	tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
	tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
	tcpd->bytesTx = cpu_to_le32(skb->len);
	tcpd->status = 0;
}

static int
typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
{
	struct typhoon *tp = netdev_priv(dev);
	struct transmit_ring *txRing;
	struct tx_desc *txd, *first_txd;
	dma_addr_t skb_dma;
	int numDesc;

	/* we have two rings to choose from, but we only use txLo for now
	 * If we start using the Hi ring as well, we'll need to update
	 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
	 * and TXHI_ENTRIES to match, as well as update the TSO code below
	 * to get the right DMA address
	 */
	txRing = &tp->txLoRing;

	/* We need one descriptor for each fragment of the sk_buff, plus the
	 * one for the ->data area of it.
	 *
	 * The docs say a maximum of 16 fragment descriptors per TCP option
	 * descriptor, then make a new packet descriptor and option descriptor
	 * for the next 16 fragments. The engineers say just an option
	 * descriptor is needed. I've tested up to 26 fragments with a single
	 * packet descriptor/option descriptor combo, so I use that for now.
	 *
	 * If problems develop with TSO, check this first.
	 */
	numDesc = skb_shinfo(skb)->nr_frags + 1;
	if(skb_tso_size(skb))
		numDesc++;

	/* When checking for free space in the ring, we need to also
	 * account for the initial Tx descriptor, and we always must leave
	 * at least one descriptor unused in the ring so that it doesn't
	 * wrap and look empty.
	 *
	 * The only time we should loop here is when we hit the race
	 * between marking the queue awake and updating the cleared index.
	 * Just loop and it will appear. This comes from the acenic driver.
	 */
	while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
		smp_rmb();

	first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
	typhoon_inc_tx_index(&txRing->lastWrite, 1);

	first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
	first_txd->numDesc = 0;
	first_txd->len = 0;
	first_txd->addr = (u64)((unsigned long) skb) & 0xffffffff;
	first_txd->addrHi = (u64)((unsigned long) skb) >> 32;
	first_txd->processFlags = 0;

	if(skb->ip_summed == CHECKSUM_HW) {
		/* The 3XP will figure out if this is UDP/TCP */
		first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
		first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
		first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
	}

	if(vlan_tx_tag_present(skb)) {
		first_txd->processFlags |=
		    TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
		first_txd->processFlags |=
		    cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
				TYPHOON_TX_PF_VLAN_TAG_SHIFT);
	}

	if(skb_tso_size(skb)) {
		first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
		first_txd->numDesc++;

		typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
	}

	txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
	typhoon_inc_tx_index(&txRing->lastWrite, 1);

	/* No need to worry about padding packet -- the firmware pads
	 * it with zeros to ETH_ZLEN for us.
	 */
	if(skb_shinfo(skb)->nr_frags == 0) {
		skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
				       PCI_DMA_TODEVICE);
		txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
		txd->len = cpu_to_le16(skb->len);
		txd->addr = cpu_to_le32(skb_dma);
		txd->addrHi = 0;
		first_txd->numDesc++;
	} else {
		int i, len;

		len = skb_headlen(skb);
		skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
				         PCI_DMA_TODEVICE);
		txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
		txd->len = cpu_to_le16(len);
		txd->addr = cpu_to_le32(skb_dma);
		txd->addrHi = 0;
		first_txd->numDesc++;

		for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
			skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
			void *frag_addr;

			txd = (struct tx_desc *) (txRing->ringBase +
						txRing->lastWrite);
			typhoon_inc_tx_index(&txRing->lastWrite, 1);

			len = frag->size;
			frag_addr = (void *) page_address(frag->page) +
						frag->page_offset;
			skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
					 PCI_DMA_TODEVICE);
			txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
			txd->len = cpu_to_le16(len);
			txd->addr = cpu_to_le32(skb_dma);
			txd->addrHi = 0;
			first_txd->numDesc++;
		}
	}

	/* Kick the 3XP
	 */
	wmb();
	iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);

	dev->trans_start = jiffies;

	/* If we don't have room to put the worst case packet on the
	 * queue, then we must stop the queue. We need 2 extra
	 * descriptors -- one to prevent ring wrap, and one for the
	 * Tx header.
	 */
	numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;

	if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
		netif_stop_queue(dev);

		/* A Tx complete IRQ could have gotten inbetween, making
		 * the ring free again. Only need to recheck here, since
		 * Tx is serialized.
		 */
		if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
			netif_wake_queue(dev);
	}

	return 0;
}

static void
typhoon_set_rx_mode(struct net_device *dev)
{
	struct typhoon *tp = netdev_priv(dev);
	struct cmd_desc xp_cmd;
	u32 mc_filter[2];
	u16 filter;

	filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
	if(dev->flags & IFF_PROMISC) {
		printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
		       dev->name);
		filter |= TYPHOON_RX_FILTER_PROMISCOUS;
	} else if((dev->mc_count > multicast_filter_limit) ||
		  (dev->flags & IFF_ALLMULTI)) {
		/* Too many to match, or accept all multicasts. */
		filter |= TYPHOON_RX_FILTER_ALL_MCAST;
	} else if(dev->mc_count) {
		struct dev_mc_list *mclist;
		int i;

		memset(mc_filter, 0, sizeof(mc_filter));
		for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
		    i++, mclist = mclist->next) {
			int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
			mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
		}

		INIT_COMMAND_NO_RESPONSE(&xp_cmd,
					 TYPHOON_CMD_SET_MULTICAST_HASH);
		xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
		xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
		xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
		typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);

		filter |= TYPHOON_RX_FILTER_MCAST_HASH;
	}

	INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
	xp_cmd.parm1 = filter;
	typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
}

static int
typhoon_do_get_stats(struct typhoon *tp)
{
	struct net_device_stats *stats = &tp->stats;
	struct net_device_stats *saved = &tp->stats_saved;
	struct cmd_desc xp_cmd;
	struct resp_desc xp_resp[7];
	struct stats_resp *s = (struct stats_resp *) xp_resp;
	int err;

	INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
	err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
	if(err < 0)
		return err;

	/* 3Com's Linux driver uses txMultipleCollisions as it's
	 * collisions value, but there is some other collision info as well...
	 *
	 * The extra status reported would be a good candidate for
	 * ethtool_ops->get_{strings,stats}()
	 */
	stats->tx_packets = le32_to_cpu(s->txPackets);
	stats->tx_bytes = le32_to_cpu(s->txBytes);
	stats->tx_errors = le32_to_cpu(s->txCarrierLost);
	stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
	stats->collisions = le32_to_cpu(s->txMultipleCollisions);
	stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
	stats->rx_bytes = le32_to_cpu(s->rxBytesGood);
	stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
	stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
			le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
	stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
	stats->rx_length_errors = le32_to_cpu(s->rxOversized);
	tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
			SPEED_100 : SPEED_10;
	tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
			DUPLEX_FULL : DUPLEX_HALF;

	/* add in the saved statistics
	 */
	stats->tx_packets += saved->tx_packets;
	stats->tx_bytes += saved->tx_bytes;
	stats->tx_errors += saved->tx_errors;
	stats->collisions += saved->collisions;
	stats->rx_packets += saved->rx_packets;
	stats->rx_bytes += saved->rx_bytes;
	stats->rx_fifo_errors += saved->rx_fifo_errors;
	stats->rx_errors += saved->rx_errors;
	stats->rx_crc_errors += saved->rx_crc_errors;
	stats->rx_length_errors += saved->rx_length_errors;

	return 0;
}

static struct net_device_stats *
typhoon_get_stats(struct net_device *dev)
{
	struct typhoon *tp = netdev_priv(dev);
	struct net_device_stats *stats = &tp->stats;
	struct net_device_stats *saved = &tp->stats_saved;

	smp_rmb();
	if(tp->card_state == Sleeping)
		return saved;

	if(typhoon_do_get_stats(tp) < 0) {
		printk(KERN_ERR "%s: error getting stats\n", dev->name);
		return saved;
	}

	return stats;
}

static int
typhoon_set_mac_address(struct net_device *dev, void *addr)
{
	struct sockaddr *saddr = (struct sockaddr *) addr;

	if(netif_running(dev))
		return -EBUSY;

	memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
	return 0;
}

static void
typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
	struct typhoon *tp = netdev_priv(dev);
	struct pci_dev *pci_dev = tp->pdev;
	struct cmd_desc xp_cmd;
	struct resp_desc xp_resp[3];

	smp_rmb();
	if(tp->card_state == Sleeping) {
		strcpy(info->fw_version, "Sleep image");
	} else {
		INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
		if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
			strcpy(info->fw_version, "Unknown runtime");
		} else {
			u32 sleep_ver = xp_resp[0].parm2;
			snprintf(info->fw_version, 32, "%02x.%03x.%03x",
				 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff, 
				 sleep_ver & 0xfff);
		}
	}

	strcpy(info->driver, DRV_MODULE_NAME);
	strcpy(info->version, DRV_MODULE_VERSION);
	strcpy(info->bus_info, pci_name(pci_dev));
}

static int
typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct typhoon *tp = netdev_priv(dev);

	cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
				SUPPORTED_Autoneg;

	switch (tp->xcvr_select) {
	case TYPHOON_XCVR_10HALF:
		cmd->advertising = ADVERTISED_10baseT_Half;
		break;
	case TYPHOON_XCVR_10FULL:
		cmd->advertising = ADVERTISED_10baseT_Full;
		break;
	case TYPHOON_XCVR_100HALF:
		cmd->advertising = ADVERTISED_100baseT_Half;
		break;
	case TYPHOON_XCVR_100FULL:
		cmd->advertising = ADVERTISED_100baseT_Full;
		break;
	case TYPHOON_XCVR_AUTONEG:
		cmd->advertising = ADVERTISED_10baseT_Half |
					    ADVERTISED_10baseT_Full |
					    ADVERTISED_100baseT_Half |
					    ADVERTISED_100baseT_Full |
					    ADVERTISED_Autoneg;
		break;
	}

	if(tp->capabilities & TYPHOON_FIBER) {
		cmd->supported |= SUPPORTED_FIBRE;
		cmd->advertising |= ADVERTISED_FIBRE;
		cmd->port = PORT_FIBRE;
	} else {
		cmd->supported |= SUPPORTED_10baseT_Half |
		    			SUPPORTED_10baseT_Full |
					SUPPORTED_TP;
		cmd->advertising |= ADVERTISED_TP;
		cmd->port = PORT_TP;
	}

	/* need to get stats to make these link speed/duplex valid */
	typhoon_do_get_stats(tp);
	cmd->speed = tp->speed;
	cmd->duplex = tp->duplex;
	cmd->phy_address = 0;
	cmd->transceiver = XCVR_INTERNAL;
	if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
		cmd->autoneg = AUTONEG_ENABLE;
	else
		cmd->autoneg = AUTONEG_DISABLE;
	cmd->maxtxpkt = 1;
	cmd->maxrxpkt = 1;

	return 0;
}

static int
typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct typhoon *tp = netdev_priv(dev);
	struct cmd_desc xp_cmd;
	int xcvr;
	int err;

	err = -EINVAL;
	if(cmd->autoneg == AUTONEG_ENABLE) {
		xcvr = TYPHOON_XCVR_AUTONEG;
	} else {
		if(cmd->duplex == DUPLEX_HALF) {
			if(cmd->speed == SPEED_10)
				xcvr = TYPHOON_XCVR_10HALF;
			else if(cmd->speed == SPEED_100)
				xcvr = TYPHOON_XCVR_100HALF;
			else
				goto out;
		} else if(cmd->duplex == DUPLEX_FULL) {
			if(cmd->speed == SPEED_10)
				xcvr = TYPHOON_XCVR_10FULL;
			else if(cmd->speed == SPEED_100)
				xcvr = TYPHOON_XCVR_100FULL;
			else
				goto out;
		} else
			goto out;
	}

	INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
	xp_cmd.parm1 = cpu_to_le16(xcvr);
	err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
	if(err < 0)
		goto out;

	tp->xcvr_select = xcvr;
	if(cmd->autoneg == AUTONEG_ENABLE) {
		tp->speed = 0xff;	/* invalid */
		tp->duplex = 0xff;	/* invalid */
	} else {
		tp->speed = cmd->speed;
		tp->duplex = cmd->duplex;
	}

out:
	return err;
}

static void
typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct typhoon *tp = netdev_priv(dev);

	wol->supported = WAKE_PHY | WAKE_MAGIC;
	wol->wolopts = 0;
	if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
		wol->wolopts |= WAKE_PHY;
	if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
		wol->wolopts |= WAKE_MAGIC;
	memset(&wol->sopass, 0, sizeof(wol->sopass));
}

static int
typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct typhoon *tp = netdev_priv(dev);

	if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
		return -EINVAL;

	tp->wol_events = 0;
	if(wol->wolopts & WAKE_PHY)
		tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
	if(wol->wolopts & WAKE_MAGIC)
		tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;

	return 0;
}

static u32
typhoon_get_rx_csum(struct net_device *dev)
{
	/* For now, we don't allow turning off RX checksums.
	 */
	return 1;
}

static void
typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
{
	ering->rx_max_pending = RXENT_ENTRIES;
	ering->rx_mini_max_pending = 0;
	ering->rx_jumbo_max_pending = 0;
	ering->tx_max_pending = TXLO_ENTRIES - 1;

	ering->rx_pending = RXENT_ENTRIES;
	ering->rx_mini_pending = 0;
	ering->rx_jumbo_pending = 0;
	ering->tx_pending = TXLO_ENTRIES - 1;
}

static struct ethtool_ops typhoon_ethtool_ops = {
	.get_settings		= typhoon_get_settings,
	.set_settings		= typhoon_set_settings,
	.get_drvinfo		= typhoon_get_drvinfo,
	.get_wol		= typhoon_get_wol,
	.set_wol		= typhoon_set_wol,
	.get_link		= ethtool_op_get_link,
	.get_rx_csum		= typhoon_get_rx_csum,
	.get_tx_csum		= ethtool_op_get_tx_csum,
	.set_tx_csum		= ethtool_op_set_tx_csum,
	.get_sg			= ethtool_op_get_sg,
	.set_sg			= ethtool_op_set_sg,
	.get_tso		= ethtool_op_get_tso,
	.set_tso		= ethtool_op_set_tso,
	.get_ringparam		= typhoon_get_ringparam,
};

static int
typhoon_wait_interrupt(void __iomem *ioaddr)
{
	int i, err = 0;

	for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
		if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
		   TYPHOON_INTR_BOOTCMD)
			goto out;
		udelay(TYPHOON_UDELAY);
	}

	err = -ETIMEDOUT;

out:
	iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
	return err;
}

#define shared_offset(x)	offsetof(struct typhoon_shared, x)

static void
typhoon_init_interface(struct typhoon *tp)
{
	struct typhoon_interface *iface = &tp->shared->iface;
	dma_addr_t shared_dma;

	memset(tp->shared, 0, sizeof(struct typhoon_shared));

	/* The *Hi members of iface are all init'd to zero by the memset().
	 */
	shared_dma = tp->shared_dma + shared_offset(indexes);
	iface->ringIndex = cpu_to_le32(shared_dma);

	shared_dma = tp->shared_dma + shared_offset(txLo);
	iface->txLoAddr = cpu_to_le32(shared_dma);
	iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));

	shared_dma = tp->shared_dma + shared_offset(txHi);
	iface->txHiAddr = cpu_to_le32(shared_dma);
	iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));

	shared_dma = tp->shared_dma + shared_offset(rxBuff);
	iface->rxBuffAddr = cpu_to_le32(shared_dma);
	iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
					sizeof(struct rx_free));

	shared_dma = tp->shared_dma + shared_offset(rxLo);
	iface->rxLoAddr = cpu_to_le32(shared_dma);
	iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));

	shared_dma = tp->shared_dma + shared_offset(rxHi);
	iface->rxHiAddr = cpu_to_le32(shared_dma);
	iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));

	shared_dma = tp->shared_dma + shared_offset(cmd);
	iface->cmdAddr = cpu_to_le32(shared_dma);
	iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);

	shared_dma = tp->shared_dma + shared_offset(resp);
	iface->respAddr = cpu_to_le32(shared_dma);
	iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);

	shared_dma = tp->shared_dma + shared_offset(zeroWord);
	iface->zeroAddr = cpu_to_le32(shared_dma);

	tp->indexes = &tp->shared->indexes;
	tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
	tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
	tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
	tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
	tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
	tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
	tp->respRing.ringBase = (u8 *) tp->shared->resp;

	tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
	tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;

	tp->txlo_dma_addr = iface->txLoAddr;
	tp->card_state = Sleeping;
	smp_wmb();

	tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
	tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;

	spin_lock_init(&tp->command_lock);
	spin_lock_init(&tp->state_lock);
}

static void
typhoon_init_rings(struct typhoon *tp)
{
	memset(tp->indexes, 0, sizeof(struct typhoon_indexes));

	tp->txLoRing.lastWrite = 0;
	tp->txHiRing.lastWrite = 0;
	tp->rxLoRing.lastWrite = 0;
	tp->rxHiRing.lastWrite = 0;
	tp->rxBuffRing.lastWrite = 0;
	tp->cmdRing.lastWrite = 0;
	tp->cmdRing.lastWrite = 0;

	tp->txLoRing.lastRead = 0;
	tp->txHiRing.lastRead = 0;
}

static int
typhoon_download_firmware(struct typhoon *tp)
{
	void __iomem *ioaddr = tp->ioaddr;
	struct pci_dev *pdev = tp->pdev;
	struct typhoon_file_header *fHdr;
	struct typhoon_section_header *sHdr;
	u8 *image_data;
	void *dpage;
	dma_addr_t dpage_dma;
	unsigned int csum;
	u32 irqEnabled;
	u32 irqMasked;
	u32 numSections;
	u32 section_len;
	u32 len;
	u32 load_addr;
	u32 hmac;
	int i;
	int err;

	err = -EINVAL;
	fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
	image_data = (u8 *) fHdr;

	if(memcmp(fHdr->tag, "TYPHOON", 8)) {
		printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
		goto err_out;
	}

	/* Cannot just map the firmware image using pci_map_single() as
	 * the firmware is part of the kernel/module image, so we allocate
	 * some consistent memory to copy the sections into, as it is simpler,
	 * and short-lived. If we ever split out and require a userland
	 * firmware loader, then we can revisit this.
	 */
	err = -ENOMEM;
	dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
	if(!dpage) {
		printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
		goto err_out;
	}

	irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
	iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
	       ioaddr + TYPHOON_REG_INTR_ENABLE);
	irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
	iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
	       ioaddr + TYPHOON_REG_INTR_MASK);

	err = -ETIMEDOUT;
	if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
		printk(KERN_ERR "%s: card ready timeout\n", tp->name);
		goto err_out_irq;
	}

	numSections = le32_to_cpu(fHdr->numSections);
	load_addr = le32_to_cpu(fHdr->startAddr);

	iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
	iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
	hmac = le32_to_cpu(fHdr->hmacDigest[0]);
	iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
	hmac = le32_to_cpu(fHdr->hmacDigest[1]);
	iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
	hmac = le32_to_cpu(fHdr->hmacDigest[2]);
	iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
	hmac = le32_to_cpu(fHdr->hmacDigest[3]);
	iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
	hmac = le32_to_cpu(fHdr->hmacDigest[4]);
	iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
	typhoon_post_pci_writes(ioaddr);
	iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);

	image_data += sizeof(struct typhoon_file_header);

	/* The ioread32() in typhoon_wait_interrupt() will force the
	 * last write to the command register to post, so
	 * we don't need a typhoon_post_pci_writes() after it.
	 */
	for(i = 0; i < numSections; i++) {
		sHdr = (struct typhoon_section_header *) image_data;
		image_data += sizeof(struct typhoon_section_header);
		load_addr = le32_to_cpu(sHdr->startAddr);
		section_len = le32_to_cpu(sHdr->len);

		while(section_len) {
			len = min_t(u32, section_len, PAGE_SIZE);

			if(typhoon_wait_interrupt(ioaddr) < 0 ||
			   ioread32(ioaddr + TYPHOON_REG_STATUS) !=
			   TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
				printk(KERN_ERR "%s: segment ready timeout\n",
				       tp->name);
				goto err_out_irq;
			}

			/* Do an pseudo IPv4 checksum on the data -- first
			 * need to convert each u16 to cpu order before
			 * summing. Fortunately, due to the properties of
			 * the checksum, we can do this once, at the end.
			 */
			csum = csum_partial_copy_nocheck(image_data, dpage,
							 len, 0);
			csum = csum_fold(csum);
			csum = le16_to_cpu(csum);

			iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
			iowrite32(csum, ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
			iowrite32(load_addr,
					ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
			iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
			iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
			typhoon_post_pci_writes(ioaddr);
			iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
			       ioaddr + TYPHOON_REG_COMMAND);

			image_data += len;
			load_addr += len;
			section_len -= len;
		}
	}

	if(typhoon_wait_interrupt(ioaddr) < 0 ||
	   ioread32(ioaddr + TYPHOON_REG_STATUS) !=
	   TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
		printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
		goto err_out_irq;
	}

	iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);

	if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
		printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
		       tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
		goto err_out_irq;
	}

	err = 0;

err_out_irq:
	iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
	iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);

	pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);

err_out:
	return err;
}

static int
typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
{
	void __iomem *ioaddr = tp->ioaddr;

	if(typhoon_wait_status(ioaddr, initial_status) < 0) {
		printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
		goto out_timeout;
	}

	iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
	iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
	typhoon_post_pci_writes(ioaddr);
	iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
				ioaddr + TYPHOON_REG_COMMAND);

	if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
		printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
		       tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
		goto out_timeout;
	}

	/* Clear the Transmit and Command ready registers
	 */
	iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
	iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
	iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
	typhoon_post_pci_writes(ioaddr);
	iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);

	return 0;

out_timeout:
	return -ETIMEDOUT;
}

static u32
typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
			volatile u32 * index)
{
	u32 lastRead = txRing->lastRead;
	struct tx_desc *tx;
	dma_addr_t skb_dma;
	int dma_len;
	int type;

	while(lastRead != le32_to_cpu(*index)) {
		tx = (struct tx_desc *) (txRing->ringBase + lastRead);
		type = tx->flags & TYPHOON_TYPE_MASK;

		if(type == TYPHOON_TX_DESC) {
			/* This tx_desc describes a packet.
			 */
			unsigned long ptr = tx->addr | ((u64)tx->addrHi << 32);
			struct sk_buff *skb = (struct sk_buff *) ptr;
			dev_kfree_skb_irq(skb);
		} else if(type == TYPHOON_FRAG_DESC) {
			/* This tx_desc describes a memory mapping. Free it.
			 */
			skb_dma = (dma_addr_t) le32_to_cpu(tx->addr);
			dma_len = le16_to_cpu(tx->len);
			pci_unmap_single(tp->pdev, skb_dma, dma_len,
				       PCI_DMA_TODEVICE);
		}

		tx->flags = 0;
		typhoon_inc_tx_index(&lastRead, 1);
	}

	return lastRead;
}

static void
typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
			volatile u32 * index)
{
	u32 lastRead;
	int numDesc = MAX_SKB_FRAGS + 1;

	/* This will need changing if we start to use the Hi Tx ring. */
	lastRead = typhoon_clean_tx(tp, txRing, index);
	if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
				lastRead, TXLO_ENTRIES) > (numDesc + 2))
		netif_wake_queue(tp->dev);

	txRing->lastRead = lastRead;
	smp_wmb();
}

static void
typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
{
	struct typhoon_indexes *indexes = tp->indexes;
	struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
	struct basic_ring *ring = &tp->rxBuffRing;
	struct rx_free *r;

	if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
				indexes->rxBuffCleared) {
		/* no room in ring, just drop the skb
		 */
		dev_kfree_skb_any(rxb->skb);
		rxb->skb = NULL;
		return;
	}

	r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
	typhoon_inc_rxfree_index(&ring->lastWrite, 1);
	r->virtAddr = idx;
	r->physAddr = cpu_to_le32(rxb->dma_addr);

	/* Tell the card about it */
	wmb();
	indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
}

static int
typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
{
	struct typhoon_indexes *indexes = tp->indexes;
	struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
	struct basic_ring *ring = &tp->rxBuffRing;
	struct rx_free *r;
	struct sk_buff *skb;
	dma_addr_t dma_addr;

	rxb->skb = NULL;

	if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
				indexes->rxBuffCleared)
		return -ENOMEM;

	skb = dev_alloc_skb(PKT_BUF_SZ);
	if(!skb)
		return -ENOMEM;

#if 0
	/* Please, 3com, fix the firmware to allow DMA to a unaligned
	 * address! Pretty please?
	 */
	skb_reserve(skb, 2);
#endif

	skb->dev = tp->dev;
	dma_addr = pci_map_single(tp->pdev, skb->data,
				  PKT_BUF_SZ, PCI_DMA_FROMDEVICE);

	/* Since no card does 64 bit DAC, the high bits will never
	 * change from zero.
	 */
	r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
	typhoon_inc_rxfree_index(&ring->lastWrite, 1);
	r->virtAddr = idx;
	r->physAddr = cpu_to_le32(dma_addr);
	rxb->skb = skb;
	rxb->dma_addr = dma_addr;

	/* Tell the card about it */
	wmb();
	indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
	return 0;
}

static int
typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile u32 * ready,
	   volatile u32 * cleared, int budget)
{
	struct rx_desc *rx;
	struct sk_buff *skb, *new_skb;
	struct rxbuff_ent *rxb;
	dma_addr_t dma_addr;
	u32 local_ready;
	u32 rxaddr;
	int pkt_len;
	u32 idx;
	u32 csum_bits;
	int received;

	received = 0;
	local_ready = le32_to_cpu(*ready);
	rxaddr = le32_to_cpu(*cleared);
	while(rxaddr != local_ready && budget > 0) {
		rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
		idx = rx->addr;
		rxb = &tp->rxbuffers[idx];
		skb = rxb->skb;
		dma_addr = rxb->dma_addr;

		typhoon_inc_rx_index(&rxaddr, 1);

		if(rx->flags & TYPHOON_RX_ERROR) {
			typhoon_recycle_rx_skb(tp, idx);
			continue;
		}

		pkt_len = le16_to_cpu(rx->frameLen);

		if(pkt_len < rx_copybreak &&
		   (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
			new_skb->dev = tp->dev;
			skb_reserve(new_skb, 2);
			pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
						    PKT_BUF_SZ,
						    PCI_DMA_FROMDEVICE);
			eth_copy_and_sum(new_skb, skb->data, pkt_len, 0);
			pci_dma_sync_single_for_device(tp->pdev, dma_addr,
						       PKT_BUF_SZ,
						       PCI_DMA_FROMDEVICE);
			skb_put(new_skb, pkt_len);
			typhoon_recycle_rx_skb(tp, idx);
		} else {
			new_skb = skb;
			skb_put(new_skb, pkt_len);
			pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
				       PCI_DMA_FROMDEVICE);
			typhoon_alloc_rx_skb(tp, idx);
		}
		new_skb->protocol = eth_type_trans(new_skb, tp->dev);
		csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
			TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
		if(csum_bits ==
		   (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
		   || csum_bits ==
		   (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
			new_skb->ip_summed = CHECKSUM_UNNECESSARY;
		} else
			new_skb->ip_summed = CHECKSUM_NONE;

		spin_lock(&tp->state_lock);
		if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
			vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
						 ntohl(rx->vlanTag) & 0xffff);
		else
			netif_receive_skb(new_skb);
		spin_unlock(&tp->state_lock);

		tp->dev->last_rx = jiffies;
		received++;
		budget--;
	}
	*cleared = cpu_to_le32(rxaddr);

	return received;
}

static void
typhoon_fill_free_ring(struct typhoon *tp)
{
	u32 i;

	for(i = 0; i < RXENT_ENTRIES; i++) {
		struct rxbuff_ent *rxb = &tp->rxbuffers[i];
		if(rxb->skb)
			continue;
		if(typhoon_alloc_rx_skb(tp, i) < 0)
			break;
	}
}

static int
typhoon_poll(struct net_device *dev, int *total_budget)
{
	struct typhoon *tp = netdev_priv(dev);
	struct typhoon_indexes *indexes = tp->indexes;
	int orig_budget = *total_budget;
	int budget, work_done, done;

	rmb();
	if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
			typhoon_process_response(tp, 0, NULL);

	if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
		typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);

	if(orig_budget > dev->quota)
		orig_budget = dev->quota;

	budget = orig_budget;
	work_done = 0;
	done = 1;

	if(indexes->rxHiCleared != indexes->rxHiReady) {
		work_done = typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
			   		&indexes->rxHiCleared, budget);
		budget -= work_done;
	}

	if(indexes->rxLoCleared != indexes->rxLoReady) {
		work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
			   		&indexes->rxLoCleared, budget);
	}

	if(work_done) {
		*total_budget -= work_done;
		dev->quota -= work_done;

		if(work_done >= orig_budget)
			done = 0;
	}

	if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
		/* rxBuff ring is empty, try to fill it. */
		typhoon_fill_free_ring(tp);
	}

	if(done) {
		netif_rx_complete(dev);
		iowrite32(TYPHOON_INTR_NONE,
				tp->ioaddr + TYPHOON_REG_INTR_MASK);
		typhoon_post_pci_writes(tp->ioaddr);
	}

	return (done ? 0 : 1);
}

static irqreturn_t
typhoon_interrupt(int irq, void *dev_instance, struct pt_regs *rgs)
{
	struct net_device *dev = (struct net_device *) dev_instance;
	struct typhoon *tp = dev->priv;
	void __iomem *ioaddr = tp->ioaddr;
	u32 intr_status;

	intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
	if(!(intr_status & TYPHOON_INTR_HOST_INT))
		return IRQ_NONE;

	iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);

	if(netif_rx_schedule_prep(dev)) {
		iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
		typhoon_post_pci_writes(ioaddr);
		__netif_rx_schedule(dev);
	} else {
		printk(KERN_ERR "%s: Error, poll already scheduled\n",
                       dev->name);
	}
	return IRQ_HANDLED;
}

static void
typhoon_free_rx_rings(struct typhoon *tp)
{
	u32 i;

	for(i = 0; i < RXENT_ENTRIES; i++) {
		struct rxbuff_ent *rxb = &tp->rxbuffers[i];
		if(rxb->skb) {
			pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
				       PCI_DMA_FROMDEVICE);
			dev_kfree_skb(rxb->skb);
			rxb->skb = NULL;
		}
	}
}

static int
typhoon_sleep(struct typhoon *tp, pci_power_t state, u16 events)
{
	struct pci_dev *pdev = tp->pdev;
	void __iomem *ioaddr = tp->ioaddr;
	struct cmd_desc xp_cmd;
	int err;

	INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
	xp_cmd.parm1 = events;
	err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
	if(err < 0) {