[AVR32] Add PIOE device and reserve SDRAM pins

The PIOE device was left out before because it muxes SDRAM pins (and
is therefore a bit dangerous to mess with) and because no existing
drivers had any use for it.

It is needed for CompactFlash, however, and now that we have a way
to protect the SDRAM pins, it can be safely added.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>

4 files changed, 36 insertions, 1 deletions

diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
index 3787d6bfe0d7..bca815ff11f2 100644
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
@@ -19,6 +19,7 @@
 #include <asm/setup.h>
 #include <asm/arch/board.h>
 #include <asm/arch/init.h>
+#include <asm/arch/portmux.h>
 
 
 #define SW2_DEFAULT             /* MMCI and UART_A available */
@@ -102,6 +103,28 @@ void __init setup_board(void)
 
 static int __init atstk1002_init(void)
 {
+        /*
+         * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
+         * SDRAM-specific pins so that nobody messes with them.
+         */
+        at32_reserve_pin(GPIO_PIN_PE(0));       /* DATA[16]     */
+        at32_reserve_pin(GPIO_PIN_PE(1));       /* DATA[17]     */
+        at32_reserve_pin(GPIO_PIN_PE(2));       /* DATA[18]     */
+        at32_reserve_pin(GPIO_PIN_PE(3));       /* DATA[19]     */
+        at32_reserve_pin(GPIO_PIN_PE(4));       /* DATA[20]     */
+        at32_reserve_pin(GPIO_PIN_PE(5));       /* DATA[21]     */
+        at32_reserve_pin(GPIO_PIN_PE(6));       /* DATA[22]     */
+        at32_reserve_pin(GPIO_PIN_PE(7));       /* DATA[23]     */
+        at32_reserve_pin(GPIO_PIN_PE(8));       /* DATA[24]     */
+        at32_reserve_pin(GPIO_PIN_PE(9));       /* DATA[25]     */
+        at32_reserve_pin(GPIO_PIN_PE(10));      /* DATA[26]     */
+        at32_reserve_pin(GPIO_PIN_PE(11));      /* DATA[27]     */
+        at32_reserve_pin(GPIO_PIN_PE(12));      /* DATA[28]     */
+        at32_reserve_pin(GPIO_PIN_PE(13));      /* DATA[29]     */
+        at32_reserve_pin(GPIO_PIN_PE(14));      /* DATA[30]     */
+        at32_reserve_pin(GPIO_PIN_PE(15));      /* DATA[31]     */
+        at32_reserve_pin(GPIO_PIN_PE(26));      /* SDCS         */
+
         at32_add_system_devices();
 
 #ifdef  SW2_DEFAULT
diff --git a/arch/avr32/mach-at32ap/at32ap7000.c b/arch/avr32/mach-at32ap/at32ap7000.c
index 21561ab60471..981d553e471b 100644
--- a/arch/avr32/mach-at32ap/at32ap7000.c
+++ b/arch/avr32/mach-at32ap/at32ap7000.c
@@ -496,6 +496,13 @@ static struct resource pio3_resource[] = {
 DEFINE_DEV(pio, 3);
 DEV_CLK(mck, pio3, pba, 13);
 
+static struct resource pio4_resource[] = {
+        PBMEM(0xffe03800),
+        IRQ(17),
+};
+DEFINE_DEV(pio, 4);
+DEV_CLK(mck, pio4, pba, 14);
+
 void __init at32_add_system_devices(void)
 {
         system_manager.eim_first_irq = EIM_IRQ_BASE;
@@ -509,6 +516,7 @@ void __init at32_add_system_devices(void)
         platform_device_register(&pio1_device);
         platform_device_register(&pio2_device);
         platform_device_register(&pio3_device);
+        platform_device_register(&pio4_device);
 }
 
 /* --------------------------------------------------------------------
@@ -860,6 +868,7 @@ struct clk *at32_clock_list[] = {
         &pio1_mck,
         &pio2_mck,
         &pio3_mck,
+        &pio4_mck,
         &atmel_usart0_usart,
         &atmel_usart1_usart,
         &atmel_usart2_usart,
@@ -880,6 +889,7 @@ void __init at32_portmux_init(void)
         at32_init_pio(&pio1_device);
         at32_init_pio(&pio2_device);
         at32_init_pio(&pio3_device);
+        at32_init_pio(&pio4_device);
 }
 
 void __init at32_clock_init(void)
diff --git a/include/asm-avr32/arch-at32ap/at32ap7000.h b/include/asm-avr32/arch-at32ap/at32ap7000.h
index ba85e04553d4..3914d7b94ff4 100644
--- a/include/asm-avr32/arch-at32ap/at32ap7000.h
+++ b/include/asm-avr32/arch-at32ap/at32ap7000.h
@@ -24,10 +24,12 @@
 #define GPIO_PIOB_BASE  (GPIO_PIOA_BASE + 32)
 #define GPIO_PIOC_BASE  (GPIO_PIOB_BASE + 32)
 #define GPIO_PIOD_BASE  (GPIO_PIOC_BASE + 32)
+#define GPIO_PIOE_BASE  (GPIO_PIOD_BASE + 32)
 
 #define GPIO_PIN_PA(N)  (GPIO_PIOA_BASE + (N))
 #define GPIO_PIN_PB(N)  (GPIO_PIOB_BASE + (N))
 #define GPIO_PIN_PC(N)  (GPIO_PIOC_BASE + (N))
 #define GPIO_PIN_PD(N)  (GPIO_PIOD_BASE + (N))
+#define GPIO_PIN_PE(N)  (GPIO_PIOE_BASE + (N))
 
 #endif /* __ASM_ARCH_AT32AP7000_H__ */
diff --git a/include/asm-avr32/arch-at32ap/irq.h b/include/asm-avr32/arch-at32ap/irq.h
index f8f7f4571e44..5adffab9a577 100644
--- a/include/asm-avr32/arch-at32ap/irq.h
+++ b/include/asm-avr32/arch-at32ap/irq.h
@@ -7,7 +7,7 @@
 #define AT32_EXTINT(n)  (EIM_IRQ_BASE + (n))
 
 #define GPIO_IRQ_BASE   (EIM_IRQ_BASE + NR_EIM_IRQS)
-#define NR_GPIO_IRQS    (4 * 32)
+#define NR_GPIO_IRQS    (5 * 32)
 
 #define NR_IRQS         (GPIO_IRQ_BASE + NR_GPIO_IRQS)