Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "The lion share of this pull request are fixes for clk-related breakage
  caused by other changes during this merge window.  For some platforms
  the fix was as simple as selecting HAVE_CLK, for others like the
  Loongson 2 significant restructuring was required.

  The remainder are changes required to get the Lantiq code to work
  again."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Loongson 2: Sort out clock managment.
  MIPS: Loongson 1: more clk support and add select HAVE_CLK
  MIPS: txx9: Fix redefinition of clk_* by adding select HAVE_CLK
  MIPS: BCM63xx: Fix redefinition of clk_* by adding select HAVE_CLK
  MIPS: AR7: Fix redefinition of clk_* by adding select HAVE_CLK
  MIPS: Lantiq: Platform specific CLK fixup
  MIPS: Lantiq: Add device_tree_init function
  MIPS: Lantiq: Fix interface clock and PCI control register offset

14 files changed, 108 insertions, 72 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e3efc06e6409..331d574df99c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -77,6 +77,7 @@ config AR7
         select SYS_SUPPORTS_ZBOOT_UART16550
         select ARCH_REQUIRE_GPIOLIB
         select VLYNQ
+        select HAVE_CLK
         help
           Support for the Texas Instruments AR7 System-on-a-Chip
           family: TNETD7100, 7200 and 7300.
@@ -124,6 +125,7 @@ config BCM63XX
         select SYS_HAS_EARLY_PRINTK
         select SWAP_IO_SPACE
         select ARCH_REQUIRE_GPIOLIB
+        select HAVE_CLK
         help
          Support for BCM63XX based boards
 
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
index 83894aa7932c..c9456e7a7283 100644
--- a/arch/mips/include/asm/clock.h
+++ b/arch/mips/include/asm/clock.h
@@ -50,15 +50,4 @@ void clk_recalc_rate(struct clk *);
 int clk_register(struct clk *);
 void clk_unregister(struct clk *);
 
-/* the exported API, in addition to clk_set_rate */
-/**
- * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
- * @clk: clock source
- * @rate: desired clock rate in Hz
- * @algo_id: algorithm id to be passed down to ops->set_rate
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
-
 #endif                          /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 06367c37e1b2..5222a007bc21 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -245,7 +245,6 @@ static inline void do_perfcnt_IRQ(void)
 
 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
 #include <linux/cpufreq.h>
-extern void loongson2_cpu_wait(void);
 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
 
 /* Chip Config */
diff --git a/arch/mips/kernel/cpufreq/Makefile b/arch/mips/kernel/cpufreq/Makefile
index c3479a432efe..05a5715ee38c 100644
--- a/arch/mips/kernel/cpufreq/Makefile
+++ b/arch/mips/kernel/cpufreq/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the Linux/MIPS cpufreq.
 #
 
-obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o loongson2_clock.o
+obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o
diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
index ae5db206347c..e7c98e2b78b6 100644
--- a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
+++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
@@ -19,7 +19,7 @@
 
 #include <asm/clock.h>
 
-#include <loongson.h>
+#include <asm/mach-loongson/loongson.h>
 
 static uint nowait;
 
@@ -181,6 +181,25 @@ static struct platform_driver platform_driver = {
         .id_table = platform_device_ids,
 };
 
+/*
+ * This is the simple version of Loongson-2 wait, Maybe we need do this in
+ * interrupt disabled context.
+ */
+
+static DEFINE_SPINLOCK(loongson2_wait_lock);
+
+static void loongson2_cpu_wait(void)
+{
+        unsigned long flags;
+        u32 cpu_freq;
+
+        spin_lock_irqsave(&loongson2_wait_lock, flags);
+        cpu_freq = LOONGSON_CHIPCFG0;
+        LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
+        LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
+        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
+}
+
 static int __init cpufreq_init(void)
 {
         int ret;
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index d3bcc33f4699..ce2f129b081f 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -135,6 +135,11 @@ void clk_deactivate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_deactivate);
 
+struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
+{
+        return NULL;
+}
+
 static inline u32 get_counter_resolution(void)
 {
         u32 res;
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index d185e8477fdf..6cfd6117fbfd 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -8,7 +8,10 @@
 
 #include <linux/export.h>
 #include <linux/clk.h>
+#include <linux/bootmem.h>
 #include <linux/of_platform.h>
+#include <linux/of_fdt.h>
+
 #include <asm/bootinfo.h>
 #include <asm/time.h>
 
@@ -70,6 +73,25 @@ void __init plat_mem_setup(void)
         __dt_setup_arch(&__dtb_start);
 }
 
+void __init device_tree_init(void)
+{
+        unsigned long base, size;
+
+        if (!initial_boot_params)
+                return;
+
+        base = virt_to_phys((void *)initial_boot_params);
+        size = be32_to_cpu(initial_boot_params->totalsize);
+
+        /* Before we do anything, lets reserve the dt blob */
+        reserve_bootmem(base, size, BOOTMEM_DEFAULT);
+
+        unflatten_device_tree();
+
+        /* free the space reserved for the dt blob */
+        free_bootmem(base, size);
+}
+
 void __init prom_init(void)
 {
         /* call the soc specific detetcion code and get it to fill soc_info */
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 83780f7c842b..befbb760ab76 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -20,10 +20,12 @@
 
 /* clock control register */
 #define CGU_IFCCR       0x0018
+#define CGU_IFCCR_VR9   0x0024
 /* system clock register */
 #define CGU_SYS         0x0010
 /* pci control register */
 #define CGU_PCICR       0x0034
+#define CGU_PCICR_VR9   0x0038
 /* ephy configuration register */
 #define CGU_EPHY        0x10
 /* power control register */
@@ -80,6 +82,9 @@ static void __iomem *pmu_membase;
 void __iomem *ltq_cgu_membase;
 void __iomem *ltq_ebu_membase;
 
+static u32 ifccr = CGU_IFCCR;
+static u32 pcicr = CGU_PCICR;
+
 /* legacy function kept alive to ease clkdev transition */
 void ltq_pmu_enable(unsigned int module)
 {
@@ -103,14 +108,14 @@ EXPORT_SYMBOL(ltq_pmu_disable);
 /* enable a hw clock */
 static int cgu_enable(struct clk *clk)
 {
-        ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
+        ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
         return 0;
 }
 
 /* disable a hw clock */
 static void cgu_disable(struct clk *clk)
 {
-        ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
+        ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
 }
 
 /* enable a clock gate */
@@ -138,22 +143,22 @@ static void pmu_disable(struct clk *clk)
 /* the pci enable helper */
 static int pci_enable(struct clk *clk)
 {
-        unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
+        unsigned int val = ltq_cgu_r32(ifccr);
         /* set bus clock speed */
         if (of_machine_is_compatible("lantiq,ar9")) {
-                ifccr &= ~0x1f00000;
+                val &= ~0x1f00000;
                 if (clk->rate == CLOCK_33M)
-                        ifccr |= 0xe00000;
+                        val |= 0xe00000;
                 else
-                        ifccr |= 0x700000; /* 62.5M */
+                        val |= 0x700000; /* 62.5M */
         } else {
-                ifccr &= ~0xf00000;
+                val &= ~0xf00000;
                 if (clk->rate == CLOCK_33M)
-                        ifccr |= 0x800000;
+                        val |= 0x800000;
                 else
-                        ifccr |= 0x400000; /* 62.5M */
+                        val |= 0x400000; /* 62.5M */
         }
-        ltq_cgu_w32(ifccr, CGU_IFCCR);
+        ltq_cgu_w32(val, ifccr);
         pmu_enable(clk);
         return 0;
 }
@@ -161,18 +166,16 @@ static int pci_enable(struct clk *clk)
 /* enable the external clock as a source */
 static int pci_ext_enable(struct clk *clk)
 {
-        ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
-                CGU_IFCCR);
-        ltq_cgu_w32((1 << 30), CGU_PCICR);
+        ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
+        ltq_cgu_w32((1 << 30), pcicr);
         return 0;
 }
 
 /* disable the external clock as a source */
 static void pci_ext_disable(struct clk *clk)
 {
-        ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
-                CGU_IFCCR);
-        ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
+        ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
+        ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 }
 
 /* enable a clockout source */
@@ -184,11 +187,11 @@ static int clkout_enable(struct clk *clk)
         for (i = 0; i < 4; i++) {
                 if (clk->rates[i] == clk->rate) {
                         int shift = 14 - (2 * clk->module);
-                        unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
+                        unsigned int val = ltq_cgu_r32(ifccr);
 
-                        ifccr &= ~(3 << shift);
-                        ifccr |= i << shift;
-                        ltq_cgu_w32(ifccr, CGU_IFCCR);
+                        val &= ~(3 << shift);
+                        val |= i << shift;
+                        ltq_cgu_w32(val, ifccr);
                         return 0;
                 }
         }
@@ -336,8 +339,12 @@ void __init ltq_soc_init(void)
         clkdev_add_clkout();
 
         /* add the soc dependent clocks */
-        if (!of_machine_is_compatible("lantiq,vr9"))
+        if (of_machine_is_compatible("lantiq,vr9")) {
+                ifccr = CGU_IFCCR_VR9;
+                pcicr = CGU_PCICR_VR9;
+        } else {
                 clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
+        }
 
         if (!of_machine_is_compatible("lantiq,ase")) {
                 clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index aca93eed8779..263beb9322a8 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -41,6 +41,7 @@ config LEMOTE_MACH2F
         select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
         select DMA_NONCOHERENT
         select GENERIC_ISA_DMA_SUPPORT_BROKEN
+        select HAVE_CLK
         select HW_HAS_PCI
         select I8259
         select IRQ_CPU
diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile
index 8699a53f0477..4f9eaa328a16 100644
--- a/arch/mips/loongson/lemote-2f/Makefile
+++ b/arch/mips/loongson/lemote-2f/Makefile
@@ -2,7 +2,7 @@
 # Makefile for lemote loongson2f family machines
 #
 
-obj-y += machtype.o irq.o reset.o ec_kb3310b.o
+obj-y += clock.o machtype.o irq.o reset.o ec_kb3310b.o
 
 #
 # Suspend Support
diff --git a/arch/mips/kernel/cpufreq/loongson2_clock.c b/arch/mips/loongson/lemote-2f/clock.c
index 5426779d9fdb..bc739d4bab2e 100644
--- a/arch/mips/kernel/cpufreq/loongson2_clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -6,14 +6,17 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
-
-#include <linux/module.h>
+#include <linux/clk.h>
 #include <linux/cpufreq.h>
-#include <linux/platform_device.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
 
 #include <asm/clock.h>
-
-#include <loongson.h>
+#include <asm/mach-loongson/loongson.h>
 
 static LIST_HEAD(clock_list);
 static DEFINE_SPINLOCK(clock_lock);
@@ -89,12 +92,6 @@ EXPORT_SYMBOL(clk_put);
 
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
-        return clk_set_rate_ex(clk, rate, 0);
-}
-EXPORT_SYMBOL_GPL(clk_set_rate);
-
-int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
-{
         int ret = 0;
         int regval;
         int i;
@@ -103,7 +100,7 @@ int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
                 unsigned long flags;
 
                 spin_lock_irqsave(&clock_lock, flags);
-                ret = clk->ops->set_rate(clk, rate, algo_id);
+                ret = clk->ops->set_rate(clk, rate, 0);
                 spin_unlock_irqrestore(&clock_lock, flags);
         }
 
@@ -129,7 +126,7 @@ int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
 
         return ret;
 }
-EXPORT_SYMBOL_GPL(clk_set_rate_ex);
+EXPORT_SYMBOL_GPL(clk_set_rate);
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
@@ -146,26 +143,3 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
         return rate;
 }
 EXPORT_SYMBOL_GPL(clk_round_rate);
-
-/*
- * This is the simple version of Loongson-2 wait, Maybe we need do this in
- * interrupt disabled content
- */
-
-DEFINE_SPINLOCK(loongson2_wait_lock);
-void loongson2_cpu_wait(void)
-{
-        u32 cpu_freq;
-        unsigned long flags;
-
-        spin_lock_irqsave(&loongson2_wait_lock, flags);
-        cpu_freq = LOONGSON_CHIPCFG0;
-        LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
-        LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
-        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
-}
-EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
-
-MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
-MODULE_DESCRIPTION("cpufreq driver for Loongson 2F");
-MODULE_LICENSE("GPL");
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
index 237fa214de9f..a9a14d6e81af 100644
--- a/arch/mips/loongson1/Kconfig
+++ b/arch/mips/loongson1/Kconfig
@@ -15,6 +15,7 @@ config LOONGSON1_LS1B
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_SUPPORTS_HIGHMEM
         select SYS_HAS_EARLY_PRINTK
+        select HAVE_CLK
 
 endchoice
 
diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c
index 2d98fb030596..1bbbbec12085 100644
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -38,12 +38,28 @@ struct clk *clk_get(struct device *dev, const char *name)
 }
 EXPORT_SYMBOL(clk_get);
 
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
 unsigned long clk_get_rate(struct clk *clk)
 {
         return clk->rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
 
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+
 static void pll_clk_init(struct clk *clk)
 {
         u32 pll;
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 852ae4bb7a85..6d40bc783459 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -20,6 +20,7 @@ config MACH_TXX9
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_SUPPORTS_BIG_ENDIAN
+        select HAVE_CLK
 
 config TOSHIBA_JMR3927
         bool "Toshiba JMR-TX3927 board"