diff options
author | Peter Milne <peter.milne@d-tacq.com> | 2006-07-01 11:03:20 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-07-12 18:43:06 -0400 |
commit | 39288e1ac10b3b9a68a629be67d81a0b53512c4e (patch) | |
tree | 6919a260a100cf19581d1641b22d1d982080528b | |
parent | 2369df933f1c632ec3f230774019e37c3969b7ec (diff) |
[PATCH] i2c-iop3xx: Avoid addressing self
Avoid addressing self when sending a slave address. Follows instruction
in Intel 80331/80321 manuals.
Ignoring this worked previously on 80321, but causes a hang on i2cdetect
on 80331.
Signed-off-by: Peter Milne <peter.milne@d-tacq.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r-- | drivers/i2c/busses/i2c-iop3xx.c | 17 | ||||
-rw-r--r-- | drivers/i2c/busses/i2c-iop3xx.h | 2 |
2 files changed, 11 insertions, 8 deletions
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c index aca7e1668605..48c56939c861 100644 --- a/drivers/i2c/busses/i2c-iop3xx.c +++ b/drivers/i2c/busses/i2c-iop3xx.c | |||
@@ -21,6 +21,9 @@ | |||
21 | * - Make it work with IXP46x chips | 21 | * - Make it work with IXP46x chips |
22 | * - Cleanup function names, coding style, etc | 22 | * - Cleanup function names, coding style, etc |
23 | * | 23 | * |
24 | * - writing to slave address causes latchup on iop331. | ||
25 | * fix: driver refuses to address self. | ||
26 | * | ||
24 | * This program is free software; you can redistribute it and/or modify | 27 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License as published by | 28 | * it under the terms of the GNU General Public License as published by |
26 | * the Free Software Foundation, version 2. | 29 | * the Free Software Foundation, version 2. |
@@ -73,12 +76,6 @@ iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap) | |||
73 | } | 76 | } |
74 | 77 | ||
75 | static void | 78 | static void |
76 | iop3xx_i2c_set_slave_addr(struct i2c_algo_iop3xx_data *iop3xx_adap) | ||
77 | { | ||
78 | __raw_writel(MYSAR, iop3xx_adap->ioaddr + SAR_OFFSET); | ||
79 | } | ||
80 | |||
81 | static void | ||
82 | iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) | 79 | iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) |
83 | { | 80 | { |
84 | u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE; | 81 | u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE; |
@@ -248,6 +245,13 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, | |||
248 | int status; | 245 | int status; |
249 | int rc; | 246 | int rc; |
250 | 247 | ||
248 | /* avoid writing to my slave address (hangs on 80331), | ||
249 | * forbidden in Intel developer manual | ||
250 | */ | ||
251 | if (msg->addr == MYSAR) { | ||
252 | return -EBUSY; | ||
253 | } | ||
254 | |||
251 | __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET); | 255 | __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET); |
252 | 256 | ||
253 | cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); | 257 | cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); |
@@ -498,7 +502,6 @@ iop3xx_i2c_probe(struct platform_device *pdev) | |||
498 | spin_lock_init(&adapter_data->lock); | 502 | spin_lock_init(&adapter_data->lock); |
499 | 503 | ||
500 | iop3xx_i2c_reset(adapter_data); | 504 | iop3xx_i2c_reset(adapter_data); |
501 | iop3xx_i2c_set_slave_addr(adapter_data); | ||
502 | iop3xx_i2c_enable(adapter_data); | 505 | iop3xx_i2c_enable(adapter_data); |
503 | 506 | ||
504 | platform_set_drvdata(pdev, new_adapter); | 507 | platform_set_drvdata(pdev, new_adapter); |
diff --git a/drivers/i2c/busses/i2c-iop3xx.h b/drivers/i2c/busses/i2c-iop3xx.h index e46ebaea7b1e..8485861f6a36 100644 --- a/drivers/i2c/busses/i2c-iop3xx.h +++ b/drivers/i2c/busses/i2c-iop3xx.h | |||
@@ -80,7 +80,7 @@ | |||
80 | #define IOP3XX_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */ | 80 | #define IOP3XX_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */ |
81 | #define IOP3XX_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */ | 81 | #define IOP3XX_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */ |
82 | 82 | ||
83 | #define MYSAR 0x02 /* SWAG a suitable slave address */ | 83 | #define MYSAR 0 /* default slave address */ |
84 | 84 | ||
85 | #define I2C_ERR 321 | 85 | #define I2C_ERR 321 |
86 | #define I2C_ERR_BERR (I2C_ERR+0) | 86 | #define I2C_ERR_BERR (I2C_ERR+0) |