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authorChris Wilson <chris@chris-wilson.co.uk>2010-08-04 06:25:21 -0400
committerEric Anholt <eric@anholt.net>2010-08-09 14:24:28 -0400
commit94113cecaea5067a0f7e1135abbd92cf2c297d42 (patch)
treeb787ce0cc0da9d3af7e2e1b80e73331f30e63f5e
parent3e33d94df7f5c94adb09139b5d816a248d703a36 (diff)
drm/i915: Do not clobber the contents of TRANS_DP_CTL when enabling.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
-rw-r--r--drivers/gpu/drm/i915/intel_display.c7
2 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 281db6e5403a..97a35a42da28 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2928,6 +2928,7 @@
2928#define TRANS_DP_VSYNC_ACTIVE_LOW 0 2928#define TRANS_DP_VSYNC_ACTIVE_LOW 0
2929#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 2929#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
2930#define TRANS_DP_HSYNC_ACTIVE_LOW 0 2930#define TRANS_DP_HSYNC_ACTIVE_LOW 0
2931#define TRANS_DP_SYNC_MASK (3<<3)
2931 2932
2932/* SNB eDP training params */ 2933/* SNB eDP training params */
2933/* SNB A-stepping */ 2934/* SNB A-stepping */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1490a8c14d26..c7f19ec88f98 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2097,9 +2097,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2097 int reg; 2097 int reg;
2098 2098
2099 reg = I915_READ(trans_dp_ctl); 2099 reg = I915_READ(trans_dp_ctl);
2100 reg &= ~TRANS_DP_PORT_SEL_MASK; 2100 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2101 reg = TRANS_DP_OUTPUT_ENABLE | 2101 TRANS_DP_SYNC_MASK);
2102 TRANS_DP_ENH_FRAMING; 2102 reg |= (TRANS_DP_OUTPUT_ENABLE |
2103 TRANS_DP_ENH_FRAMING);
2103 2104
2104 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 2105 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2105 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH; 2106 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;