diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2009-04-14 23:11:30 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-04-16 05:34:47 -0400 |
commit | f44d6305280378cb34319e0118e18d84cc7ac773 (patch) | |
tree | c9c0b254dff43a48769aad1fe28b208b63b643fe | |
parent | 2160187a0a1cdeeeff1d41f53333bea91c82f259 (diff) |
fec: switch to writel/readl
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/fec.c | 279 | ||||
-rw-r--r-- | drivers/net/fec.h | 119 |
2 files changed, 161 insertions, 237 deletions
diff --git a/drivers/net/fec.c b/drivers/net/fec.c index a515acccc61f..37b333265629 100644 --- a/drivers/net/fec.c +++ b/drivers/net/fec.c | |||
@@ -165,7 +165,7 @@ typedef struct { | |||
165 | */ | 165 | */ |
166 | struct fec_enet_private { | 166 | struct fec_enet_private { |
167 | /* Hardware registers of the FEC device */ | 167 | /* Hardware registers of the FEC device */ |
168 | volatile fec_t *hwp; | 168 | void __iomem *hwp; |
169 | 169 | ||
170 | struct net_device *netdev; | 170 | struct net_device *netdev; |
171 | 171 | ||
@@ -288,15 +288,11 @@ static int mii_queue(struct net_device *dev, int request, | |||
288 | static int | 288 | static int |
289 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | 289 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) |
290 | { | 290 | { |
291 | struct fec_enet_private *fep; | 291 | struct fec_enet_private *fep = netdev_priv(dev); |
292 | volatile fec_t *fecp; | ||
293 | volatile cbd_t *bdp; | 292 | volatile cbd_t *bdp; |
294 | unsigned short status; | 293 | unsigned short status; |
295 | unsigned long flags; | 294 | unsigned long flags; |
296 | 295 | ||
297 | fep = netdev_priv(dev); | ||
298 | fecp = (volatile fec_t*)dev->base_addr; | ||
299 | |||
300 | if (!fep->link) { | 296 | if (!fep->link) { |
301 | /* Link is down or autonegotiation is in progress. */ | 297 | /* Link is down or autonegotiation is in progress. */ |
302 | return 1; | 298 | return 1; |
@@ -363,7 +359,7 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
363 | dev->trans_start = jiffies; | 359 | dev->trans_start = jiffies; |
364 | 360 | ||
365 | /* Trigger transmission start */ | 361 | /* Trigger transmission start */ |
366 | fecp->fec_x_des_active = 0; | 362 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
367 | 363 | ||
368 | /* If this was the last BD in the ring, start at the beginning again. | 364 | /* If this was the last BD in the ring, start at the beginning again. |
369 | */ | 365 | */ |
@@ -436,29 +432,25 @@ static irqreturn_t | |||
436 | fec_enet_interrupt(int irq, void * dev_id) | 432 | fec_enet_interrupt(int irq, void * dev_id) |
437 | { | 433 | { |
438 | struct net_device *dev = dev_id; | 434 | struct net_device *dev = dev_id; |
439 | volatile fec_t *fecp; | 435 | struct fec_enet_private *fep = netdev_priv(dev); |
440 | uint int_events; | 436 | uint int_events; |
441 | irqreturn_t ret = IRQ_NONE; | 437 | irqreturn_t ret = IRQ_NONE; |
442 | 438 | ||
443 | fecp = (volatile fec_t*)dev->base_addr; | 439 | /* Get the interrupt events that caused us to be here. */ |
444 | |||
445 | /* Get the interrupt events that caused us to be here. | ||
446 | */ | ||
447 | do { | 440 | do { |
448 | int_events = fecp->fec_ievent; | 441 | int_events = readl(fep->hwp + FEC_IEVENT); |
449 | fecp->fec_ievent = int_events; | 442 | writel(int_events, fep->hwp + FEC_IEVENT); |
450 | 443 | ||
451 | /* Handle receive event in its own function. | 444 | /* Handle receive event in its own function. */ |
452 | */ | ||
453 | if (int_events & FEC_ENET_RXF) { | 445 | if (int_events & FEC_ENET_RXF) { |
454 | ret = IRQ_HANDLED; | 446 | ret = IRQ_HANDLED; |
455 | fec_enet_rx(dev); | 447 | fec_enet_rx(dev); |
456 | } | 448 | } |
457 | 449 | ||
458 | /* Transmit OK, or non-fatal error. Update the buffer | 450 | /* Transmit OK, or non-fatal error. Update the buffer |
459 | descriptors. FEC handles all errors, we just discover | 451 | * descriptors. FEC handles all errors, we just discover |
460 | them as part of the transmit process. | 452 | * them as part of the transmit process. |
461 | */ | 453 | */ |
462 | if (int_events & FEC_ENET_TXF) { | 454 | if (int_events & FEC_ENET_TXF) { |
463 | ret = IRQ_HANDLED; | 455 | ret = IRQ_HANDLED; |
464 | fec_enet_tx(dev); | 456 | fec_enet_tx(dev); |
@@ -555,8 +547,7 @@ fec_enet_tx(struct net_device *dev) | |||
555 | static void | 547 | static void |
556 | fec_enet_rx(struct net_device *dev) | 548 | fec_enet_rx(struct net_device *dev) |
557 | { | 549 | { |
558 | struct fec_enet_private *fep; | 550 | struct fec_enet_private *fep = netdev_priv(dev); |
559 | volatile fec_t *fecp; | ||
560 | volatile cbd_t *bdp; | 551 | volatile cbd_t *bdp; |
561 | unsigned short status; | 552 | unsigned short status; |
562 | struct sk_buff *skb; | 553 | struct sk_buff *skb; |
@@ -567,9 +558,6 @@ fec_enet_rx(struct net_device *dev) | |||
567 | flush_cache_all(); | 558 | flush_cache_all(); |
568 | #endif | 559 | #endif |
569 | 560 | ||
570 | fep = netdev_priv(dev); | ||
571 | fecp = (volatile fec_t*)dev->base_addr; | ||
572 | |||
573 | spin_lock_irq(&fep->hw_lock); | 561 | spin_lock_irq(&fep->hw_lock); |
574 | 562 | ||
575 | /* First, grab all of the stats for the incoming packet. | 563 | /* First, grab all of the stats for the incoming packet. |
@@ -665,7 +653,7 @@ while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { | |||
665 | * incoming frames. On a heavily loaded network, we should be | 653 | * incoming frames. On a heavily loaded network, we should be |
666 | * able to keep up at the expense of system resources. | 654 | * able to keep up at the expense of system resources. |
667 | */ | 655 | */ |
668 | fecp->fec_r_des_active = 0; | 656 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
669 | #endif | 657 | #endif |
670 | } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ | 658 | } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ |
671 | fep->cur_rx = (cbd_t *)bdp; | 659 | fep->cur_rx = (cbd_t *)bdp; |
@@ -690,30 +678,25 @@ static void | |||
690 | fec_enet_mii(struct net_device *dev) | 678 | fec_enet_mii(struct net_device *dev) |
691 | { | 679 | { |
692 | struct fec_enet_private *fep; | 680 | struct fec_enet_private *fep; |
693 | volatile fec_t *ep; | ||
694 | mii_list_t *mip; | 681 | mii_list_t *mip; |
695 | uint mii_reg; | ||
696 | 682 | ||
697 | fep = netdev_priv(dev); | 683 | fep = netdev_priv(dev); |
698 | spin_lock_irq(&fep->mii_lock); | 684 | spin_lock_irq(&fep->mii_lock); |
699 | 685 | ||
700 | ep = fep->hwp; | ||
701 | mii_reg = ep->fec_mii_data; | ||
702 | |||
703 | if ((mip = mii_head) == NULL) { | 686 | if ((mip = mii_head) == NULL) { |
704 | printk("MII and no head!\n"); | 687 | printk("MII and no head!\n"); |
705 | goto unlock; | 688 | goto unlock; |
706 | } | 689 | } |
707 | 690 | ||
708 | if (mip->mii_func != NULL) | 691 | if (mip->mii_func != NULL) |
709 | (*(mip->mii_func))(mii_reg, dev); | 692 | (*(mip->mii_func))(readl(fep->hwp + FEC_MII_DATA), dev); |
710 | 693 | ||
711 | mii_head = mip->mii_next; | 694 | mii_head = mip->mii_next; |
712 | mip->mii_next = mii_free; | 695 | mip->mii_next = mii_free; |
713 | mii_free = mip; | 696 | mii_free = mip; |
714 | 697 | ||
715 | if ((mip = mii_head) != NULL) | 698 | if ((mip = mii_head) != NULL) |
716 | ep->fec_mii_data = mip->mii_regval; | 699 | writel(mip->mii_regval, fep->hwp + FEC_MII_DATA); |
717 | 700 | ||
718 | unlock: | 701 | unlock: |
719 | spin_unlock_irq(&fep->mii_lock); | 702 | spin_unlock_irq(&fep->mii_lock); |
@@ -745,7 +728,7 @@ mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_devi | |||
745 | mii_tail = mip; | 728 | mii_tail = mip; |
746 | } else { | 729 | } else { |
747 | mii_head = mii_tail = mip; | 730 | mii_head = mii_tail = mip; |
748 | fep->hwp->fec_mii_data = regval; | 731 | writel(regval, fep->hwp + FEC_MII_DATA); |
749 | } | 732 | } |
750 | } else { | 733 | } else { |
751 | retval = 1; | 734 | retval = 1; |
@@ -1245,11 +1228,8 @@ static void __inline__ fec_phy_ack_intr(void) | |||
1245 | static void __inline__ fec_get_mac(struct net_device *dev) | 1228 | static void __inline__ fec_get_mac(struct net_device *dev) |
1246 | { | 1229 | { |
1247 | struct fec_enet_private *fep = netdev_priv(dev); | 1230 | struct fec_enet_private *fep = netdev_priv(dev); |
1248 | volatile fec_t *fecp; | ||
1249 | unsigned char *iap, tmpaddr[ETH_ALEN]; | 1231 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1250 | 1232 | ||
1251 | fecp = fep->hwp; | ||
1252 | |||
1253 | if (FEC_FLASHMAC) { | 1233 | if (FEC_FLASHMAC) { |
1254 | /* | 1234 | /* |
1255 | * Get MAC address from FLASH. | 1235 | * Get MAC address from FLASH. |
@@ -1263,8 +1243,8 @@ static void __inline__ fec_get_mac(struct net_device *dev) | |||
1263 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | 1243 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) |
1264 | iap = fec_mac_default; | 1244 | iap = fec_mac_default; |
1265 | } else { | 1245 | } else { |
1266 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | 1246 | *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW); |
1267 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | 1247 | *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16); |
1268 | iap = &tmpaddr[0]; | 1248 | iap = &tmpaddr[0]; |
1269 | } | 1249 | } |
1270 | 1250 | ||
@@ -1456,11 +1436,9 @@ static void | |||
1456 | mii_discover_phy(uint mii_reg, struct net_device *dev) | 1436 | mii_discover_phy(uint mii_reg, struct net_device *dev) |
1457 | { | 1437 | { |
1458 | struct fec_enet_private *fep; | 1438 | struct fec_enet_private *fep; |
1459 | volatile fec_t *fecp; | ||
1460 | uint phytype; | 1439 | uint phytype; |
1461 | 1440 | ||
1462 | fep = netdev_priv(dev); | 1441 | fep = netdev_priv(dev); |
1463 | fecp = fep->hwp; | ||
1464 | 1442 | ||
1465 | if (fep->phy_addr < 32) { | 1443 | if (fep->phy_addr < 32) { |
1466 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { | 1444 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { |
@@ -1478,7 +1456,8 @@ mii_discover_phy(uint mii_reg, struct net_device *dev) | |||
1478 | } else { | 1456 | } else { |
1479 | printk("FEC: No PHY device found.\n"); | 1457 | printk("FEC: No PHY device found.\n"); |
1480 | /* Disable external MII interface */ | 1458 | /* Disable external MII interface */ |
1481 | fecp->fec_mii_speed = fep->phy_speed = 0; | 1459 | writel(0, fep->hwp + FEC_MII_SPEED); |
1460 | fep->phy_speed = 0; | ||
1482 | #ifdef HAVE_mii_link_interrupt | 1461 | #ifdef HAVE_mii_link_interrupt |
1483 | fec_disable_phy_intr(); | 1462 | fec_disable_phy_intr(); |
1484 | #endif | 1463 | #endif |
@@ -1582,32 +1561,31 @@ fec_enet_close(struct net_device *dev) | |||
1582 | 1561 | ||
1583 | static void set_multicast_list(struct net_device *dev) | 1562 | static void set_multicast_list(struct net_device *dev) |
1584 | { | 1563 | { |
1585 | struct fec_enet_private *fep; | 1564 | struct fec_enet_private *fep = netdev_priv(dev); |
1586 | volatile fec_t *ep; | ||
1587 | struct dev_mc_list *dmi; | 1565 | struct dev_mc_list *dmi; |
1588 | unsigned int i, j, bit, data, crc; | 1566 | unsigned int i, j, bit, data, crc, tmp; |
1589 | unsigned char hash; | 1567 | unsigned char hash; |
1590 | 1568 | ||
1591 | fep = netdev_priv(dev); | ||
1592 | ep = fep->hwp; | ||
1593 | |||
1594 | if (dev->flags&IFF_PROMISC) { | 1569 | if (dev->flags&IFF_PROMISC) { |
1595 | ep->fec_r_cntrl |= 0x0008; | 1570 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1571 | tmp |= 0x8; | ||
1572 | writel(tmp, fep->hwp + FEC_R_CNTRL); | ||
1596 | } else { | 1573 | } else { |
1597 | 1574 | tmp = readl(fep->hwp + FEC_R_CNTRL); | |
1598 | ep->fec_r_cntrl &= ~0x0008; | 1575 | tmp &= ~0x8; |
1576 | writel(tmp, fep->hwp + FEC_R_CNTRL); | ||
1599 | 1577 | ||
1600 | if (dev->flags & IFF_ALLMULTI) { | 1578 | if (dev->flags & IFF_ALLMULTI) { |
1601 | /* Catch all multicast addresses, so set the | 1579 | /* Catch all multicast addresses, so set the |
1602 | * filter to all 1's. | 1580 | * filter to all 1's. |
1603 | */ | 1581 | */ |
1604 | ep->fec_grp_hash_table_high = 0xffffffff; | 1582 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
1605 | ep->fec_grp_hash_table_low = 0xffffffff; | 1583 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); |
1606 | } else { | 1584 | } else { |
1607 | /* Clear filter and add the addresses in hash register. | 1585 | /* Clear filter and add the addresses in hash register. |
1608 | */ | 1586 | */ |
1609 | ep->fec_grp_hash_table_high = 0; | 1587 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
1610 | ep->fec_grp_hash_table_low = 0; | 1588 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); |
1611 | 1589 | ||
1612 | dmi = dev->mc_list; | 1590 | dmi = dev->mc_list; |
1613 | 1591 | ||
@@ -1637,10 +1615,15 @@ static void set_multicast_list(struct net_device *dev) | |||
1637 | */ | 1615 | */ |
1638 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | 1616 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; |
1639 | 1617 | ||
1640 | if (hash > 31) | 1618 | if (hash > 31) { |
1641 | ep->fec_grp_hash_table_high |= 1 << (hash - 32); | 1619 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
1642 | else | 1620 | tmp |= 1 << (hash - 32); |
1643 | ep->fec_grp_hash_table_low |= 1 << hash; | 1621 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
1622 | } else { | ||
1623 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | ||
1624 | tmp |= 1 << hash; | ||
1625 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | ||
1626 | } | ||
1644 | } | 1627 | } |
1645 | } | 1628 | } |
1646 | } | 1629 | } |
@@ -1651,16 +1634,14 @@ static void set_multicast_list(struct net_device *dev) | |||
1651 | static void | 1634 | static void |
1652 | fec_set_mac_address(struct net_device *dev) | 1635 | fec_set_mac_address(struct net_device *dev) |
1653 | { | 1636 | { |
1654 | volatile fec_t *fecp; | 1637 | struct fec_enet_private *fep = netdev_priv(dev); |
1655 | |||
1656 | fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp; | ||
1657 | 1638 | ||
1658 | /* Set station address. */ | 1639 | /* Set station address. */ |
1659 | fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) | | 1640 | writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
1660 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24); | 1641 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), |
1661 | fecp->fec_addr_high = (dev->dev_addr[5] << 16) | | 1642 | fep->hwp + FEC_ADDR_LOW); |
1662 | (dev->dev_addr[4] << 24); | 1643 | writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), |
1663 | 1644 | fep + FEC_ADDR_HIGH); | |
1664 | } | 1645 | } |
1665 | 1646 | ||
1666 | /* | 1647 | /* |
@@ -1674,7 +1655,6 @@ int __init fec_enet_init(struct net_device *dev, int index) | |||
1674 | unsigned long mem_addr; | 1655 | unsigned long mem_addr; |
1675 | volatile cbd_t *bdp; | 1656 | volatile cbd_t *bdp; |
1676 | cbd_t *cbd_base; | 1657 | cbd_t *cbd_base; |
1677 | volatile fec_t *fecp; | ||
1678 | int i, j; | 1658 | int i, j; |
1679 | 1659 | ||
1680 | /* Allocate memory for buffer descriptors. | 1660 | /* Allocate memory for buffer descriptors. |
@@ -1689,17 +1669,13 @@ int __init fec_enet_init(struct net_device *dev, int index) | |||
1689 | spin_lock_init(&fep->hw_lock); | 1669 | spin_lock_init(&fep->hw_lock); |
1690 | spin_lock_init(&fep->mii_lock); | 1670 | spin_lock_init(&fep->mii_lock); |
1691 | 1671 | ||
1692 | /* Create an Ethernet device instance. | ||
1693 | */ | ||
1694 | fecp = (volatile fec_t *)dev->base_addr; | ||
1695 | |||
1696 | fep->index = index; | 1672 | fep->index = index; |
1697 | fep->hwp = fecp; | 1673 | fep->hwp = (void __iomem *)dev->base_addr; |
1698 | fep->netdev = dev; | 1674 | fep->netdev = dev; |
1699 | 1675 | ||
1700 | /* Whack a reset. We should wait for this. | 1676 | /* Whack a reset. We should wait for this. |
1701 | */ | 1677 | */ |
1702 | fecp->fec_ecntrl = 1; | 1678 | writel(1, fep->hwp + FEC_ECNTRL); |
1703 | udelay(10); | 1679 | udelay(10); |
1704 | 1680 | ||
1705 | /* Set the Ethernet address */ | 1681 | /* Set the Ethernet address */ |
@@ -1708,12 +1684,12 @@ int __init fec_enet_init(struct net_device *dev, int index) | |||
1708 | #else | 1684 | #else |
1709 | { | 1685 | { |
1710 | unsigned long l; | 1686 | unsigned long l; |
1711 | l = fecp->fec_addr_low; | 1687 | l = readl(fep->hwp + FEC_ADDR_LOW); |
1712 | dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24); | 1688 | dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24); |
1713 | dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16); | 1689 | dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16); |
1714 | dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8); | 1690 | dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8); |
1715 | dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0); | 1691 | dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0); |
1716 | l = fecp->fec_addr_high; | 1692 | l = readl(fep->hwp + FEC_ADDR_HIGH); |
1717 | dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24); | 1693 | dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24); |
1718 | dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16); | 1694 | dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16); |
1719 | } | 1695 | } |
@@ -1783,22 +1759,22 @@ int __init fec_enet_init(struct net_device *dev, int index) | |||
1783 | 1759 | ||
1784 | /* Set receive and transmit descriptor base. | 1760 | /* Set receive and transmit descriptor base. |
1785 | */ | 1761 | */ |
1786 | fecp->fec_r_des_start = fep->bd_dma; | 1762 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); |
1787 | fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t) | 1763 | writel((unsigned long)fep->bd_dma + sizeof(cbd_t) * RX_RING_SIZE, |
1788 | * RX_RING_SIZE; | 1764 | fep->hwp + FEC_X_DES_START); |
1789 | 1765 | ||
1790 | #ifdef HAVE_mii_link_interrupt | 1766 | #ifdef HAVE_mii_link_interrupt |
1791 | fec_request_mii_intr(dev); | 1767 | fec_request_mii_intr(dev); |
1792 | #endif | 1768 | #endif |
1793 | 1769 | ||
1794 | fecp->fec_grp_hash_table_high = 0; | 1770 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
1795 | fecp->fec_grp_hash_table_low = 0; | 1771 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); |
1796 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; | 1772 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); |
1797 | fecp->fec_ecntrl = 2; | 1773 | writel(2, fep->hwp + FEC_ECNTRL); |
1798 | fecp->fec_r_des_active = 0; | 1774 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
1799 | #ifndef CONFIG_M5272 | 1775 | #ifndef CONFIG_M5272 |
1800 | fecp->fec_hash_table_high = 0; | 1776 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); |
1801 | fecp->fec_hash_table_low = 0; | 1777 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); |
1802 | #endif | 1778 | #endif |
1803 | 1779 | ||
1804 | /* The FEC Ethernet specific entries in the device structure. */ | 1780 | /* The FEC Ethernet specific entries in the device structure. */ |
@@ -1814,20 +1790,21 @@ int __init fec_enet_init(struct net_device *dev, int index) | |||
1814 | mii_free = mii_cmds; | 1790 | mii_free = mii_cmds; |
1815 | 1791 | ||
1816 | /* setup MII interface */ | 1792 | /* setup MII interface */ |
1817 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | 1793 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); |
1818 | fecp->fec_x_cntrl = 0x00; | 1794 | writel(0, fep->hwp + FEC_X_CNTRL); |
1819 | 1795 | ||
1820 | /* | 1796 | /* |
1821 | * Set MII speed to 2.5 MHz | 1797 | * Set MII speed to 2.5 MHz |
1822 | */ | 1798 | */ |
1823 | fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999) | 1799 | fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999) |
1824 | / 2500000) / 2) & 0x3F) << 1; | 1800 | / 2500000) / 2) & 0x3F) << 1; |
1825 | fecp->fec_mii_speed = fep->phy_speed; | 1801 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1826 | fec_restart(dev, 0); | 1802 | fec_restart(dev, 0); |
1827 | 1803 | ||
1828 | /* Clear and enable interrupts */ | 1804 | /* Clear and enable interrupts */ |
1829 | fecp->fec_ievent = 0xffc00000; | 1805 | writel(0xffc00000, fep->hwp + FEC_IEVENT); |
1830 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); | 1806 | writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, |
1807 | fep->hwp + FEC_IMASK); | ||
1831 | 1808 | ||
1832 | /* Queue up command to detect the PHY and initialize the | 1809 | /* Queue up command to detect the PHY and initialize the |
1833 | * remainder of the interface. | 1810 | * remainder of the interface. |
@@ -1846,47 +1823,36 @@ int __init fec_enet_init(struct net_device *dev, int index) | |||
1846 | static void | 1823 | static void |
1847 | fec_restart(struct net_device *dev, int duplex) | 1824 | fec_restart(struct net_device *dev, int duplex) |
1848 | { | 1825 | { |
1849 | struct fec_enet_private *fep; | 1826 | struct fec_enet_private *fep = netdev_priv(dev); |
1850 | volatile cbd_t *bdp; | 1827 | volatile cbd_t *bdp; |
1851 | volatile fec_t *fecp; | ||
1852 | int i; | 1828 | int i; |
1853 | 1829 | ||
1854 | fep = netdev_priv(dev); | 1830 | /* Whack a reset. We should wait for this. */ |
1855 | fecp = fep->hwp; | 1831 | writel(1, fep->hwp + FEC_ECNTRL); |
1856 | |||
1857 | /* Whack a reset. We should wait for this. | ||
1858 | */ | ||
1859 | fecp->fec_ecntrl = 1; | ||
1860 | udelay(10); | 1832 | udelay(10); |
1861 | 1833 | ||
1862 | /* Clear any outstanding interrupt. | 1834 | /* Clear any outstanding interrupt. */ |
1863 | */ | 1835 | writel(0xffc00000, fep->hwp + FEC_IEVENT); |
1864 | fecp->fec_ievent = 0xffc00000; | ||
1865 | 1836 | ||
1866 | /* Set station address. | 1837 | /* Set station address. */ |
1867 | */ | ||
1868 | fec_set_mac_address(dev); | 1838 | fec_set_mac_address(dev); |
1869 | 1839 | ||
1870 | /* Reset all multicast. | 1840 | /* Reset all multicast. */ |
1871 | */ | 1841 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
1872 | fecp->fec_grp_hash_table_high = 0; | 1842 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); |
1873 | fecp->fec_grp_hash_table_low = 0; | ||
1874 | 1843 | ||
1875 | /* Set maximum receive buffer size. | 1844 | /* Set maximum receive buffer size. */ |
1876 | */ | 1845 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); |
1877 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; | ||
1878 | 1846 | ||
1879 | /* Set receive and transmit descriptor base. | 1847 | /* Set receive and transmit descriptor base. */ |
1880 | */ | 1848 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); |
1881 | fecp->fec_r_des_start = fep->bd_dma; | 1849 | writel((unsigned long)fep->bd_dma + sizeof(cbd_t) * RX_RING_SIZE, |
1882 | fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t) | 1850 | fep->hwp + FEC_X_DES_START); |
1883 | * RX_RING_SIZE; | ||
1884 | 1851 | ||
1885 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | 1852 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; |
1886 | fep->cur_rx = fep->rx_bd_base; | 1853 | fep->cur_rx = fep->rx_bd_base; |
1887 | 1854 | ||
1888 | /* Reset SKB transmit buffers. | 1855 | /* Reset SKB transmit buffers. */ |
1889 | */ | ||
1890 | fep->skb_cur = fep->skb_dirty = 0; | 1856 | fep->skb_cur = fep->skb_dirty = 0; |
1891 | for (i=0; i<=TX_RING_MOD_MASK; i++) { | 1857 | for (i=0; i<=TX_RING_MOD_MASK; i++) { |
1892 | if (fep->tx_skbuff[i] != NULL) { | 1858 | if (fep->tx_skbuff[i] != NULL) { |
@@ -1895,96 +1861,81 @@ fec_restart(struct net_device *dev, int duplex) | |||
1895 | } | 1861 | } |
1896 | } | 1862 | } |
1897 | 1863 | ||
1898 | /* Initialize the receive buffer descriptors. | 1864 | /* Initialize the receive buffer descriptors. */ |
1899 | */ | ||
1900 | bdp = fep->rx_bd_base; | 1865 | bdp = fep->rx_bd_base; |
1901 | for (i=0; i<RX_RING_SIZE; i++) { | 1866 | for (i=0; i<RX_RING_SIZE; i++) { |
1902 | 1867 | ||
1903 | /* Initialize the BD for every fragment in the page. | 1868 | /* Initialize the BD for every fragment in the page. */ |
1904 | */ | ||
1905 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | 1869 | bdp->cbd_sc = BD_ENET_RX_EMPTY; |
1906 | bdp++; | 1870 | bdp++; |
1907 | } | 1871 | } |
1908 | 1872 | ||
1909 | /* Set the last buffer to wrap. | 1873 | /* Set the last buffer to wrap. */ |
1910 | */ | ||
1911 | bdp--; | 1874 | bdp--; |
1912 | bdp->cbd_sc |= BD_SC_WRAP; | 1875 | bdp->cbd_sc |= BD_SC_WRAP; |
1913 | 1876 | ||
1914 | /* ...and the same for transmmit. | 1877 | /* ...and the same for transmmit. */ |
1915 | */ | ||
1916 | bdp = fep->tx_bd_base; | 1878 | bdp = fep->tx_bd_base; |
1917 | for (i=0; i<TX_RING_SIZE; i++) { | 1879 | for (i=0; i<TX_RING_SIZE; i++) { |
1918 | 1880 | ||
1919 | /* Initialize the BD for every fragment in the page. | 1881 | /* Initialize the BD for every fragment in the page. */ |
1920 | */ | ||
1921 | bdp->cbd_sc = 0; | 1882 | bdp->cbd_sc = 0; |
1922 | bdp->cbd_bufaddr = 0; | 1883 | bdp->cbd_bufaddr = 0; |
1923 | bdp++; | 1884 | bdp++; |
1924 | } | 1885 | } |
1925 | 1886 | ||
1926 | /* Set the last buffer to wrap. | 1887 | /* Set the last buffer to wrap. */ |
1927 | */ | ||
1928 | bdp--; | 1888 | bdp--; |
1929 | bdp->cbd_sc |= BD_SC_WRAP; | 1889 | bdp->cbd_sc |= BD_SC_WRAP; |
1930 | 1890 | ||
1931 | /* Enable MII mode. | 1891 | /* Enable MII mode. */ |
1932 | */ | ||
1933 | if (duplex) { | 1892 | if (duplex) { |
1934 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */ | 1893 | /* MII enable / FD enable */ |
1935 | fecp->fec_x_cntrl = 0x04; /* FD enable */ | 1894 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); |
1895 | writel(0x04, fep->hwp + FEC_X_CNTRL); | ||
1936 | } else { | 1896 | } else { |
1937 | /* MII enable|No Rcv on Xmit */ | 1897 | /* MII enable / No Rcv on Xmit */ |
1938 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06; | 1898 | writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); |
1939 | fecp->fec_x_cntrl = 0x00; | 1899 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
1940 | } | 1900 | } |
1941 | fep->full_duplex = duplex; | 1901 | fep->full_duplex = duplex; |
1942 | 1902 | ||
1943 | /* Set MII speed. | 1903 | /* Set MII speed. */ |
1944 | */ | 1904 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1945 | fecp->fec_mii_speed = fep->phy_speed; | ||
1946 | 1905 | ||
1947 | /* And last, enable the transmit and receive processing. | 1906 | /* And last, enable the transmit and receive processing. */ |
1948 | */ | 1907 | writel(2, fep->hwp + FEC_ECNTRL); |
1949 | fecp->fec_ecntrl = 2; | 1908 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
1950 | fecp->fec_r_des_active = 0; | ||
1951 | 1909 | ||
1952 | /* Enable interrupts we wish to service. | 1910 | /* Enable interrupts we wish to service. */ |
1953 | */ | 1911 | writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, |
1954 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); | 1912 | fep->hwp + FEC_IMASK); |
1955 | } | 1913 | } |
1956 | 1914 | ||
1957 | static void | 1915 | static void |
1958 | fec_stop(struct net_device *dev) | 1916 | fec_stop(struct net_device *dev) |
1959 | { | 1917 | { |
1960 | volatile fec_t *fecp; | 1918 | struct fec_enet_private *fep = netdev_priv(dev); |
1961 | struct fec_enet_private *fep; | ||
1962 | |||
1963 | fep = netdev_priv(dev); | ||
1964 | fecp = fep->hwp; | ||
1965 | 1919 | ||
1966 | /* | 1920 | /* |
1967 | ** We cannot expect a graceful transmit stop without link !!! | 1921 | ** We cannot expect a graceful transmit stop without link !!! |
1968 | */ | 1922 | */ |
1969 | if (fep->link) | 1923 | if (fep->link) { |
1970 | { | 1924 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ |
1971 | fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */ | ||
1972 | udelay(10); | 1925 | udelay(10); |
1973 | if (!(fecp->fec_ievent & FEC_ENET_GRA)) | 1926 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) |
1974 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | 1927 | printk("fec_stop : Graceful transmit stop did not complete !\n"); |
1975 | } | 1928 | } |
1976 | 1929 | ||
1977 | /* Whack a reset. We should wait for this. | 1930 | /* Whack a reset. We should wait for this. */ |
1978 | */ | 1931 | writel(1, fep->hwp + FEC_ECNTRL); |
1979 | fecp->fec_ecntrl = 1; | ||
1980 | udelay(10); | 1932 | udelay(10); |
1981 | 1933 | ||
1982 | /* Clear outstanding MII command interrupts. | 1934 | /* Clear outstanding MII command interrupts. */ |
1983 | */ | 1935 | writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); |
1984 | fecp->fec_ievent = FEC_ENET_MII; | ||
1985 | 1936 | ||
1986 | fecp->fec_imask = FEC_ENET_MII; | 1937 | writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); |
1987 | fecp->fec_mii_speed = fep->phy_speed; | 1938 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1988 | } | 1939 | } |
1989 | 1940 | ||
1990 | static int __devinit | 1941 | static int __devinit |
diff --git a/drivers/net/fec.h b/drivers/net/fec.h index 76c64c92e190..5474ba39d46c 100644 --- a/drivers/net/fec.h +++ b/drivers/net/fec.h | |||
@@ -20,82 +20,55 @@ | |||
20 | * registers in the same peripheral device on different models | 20 | * registers in the same peripheral device on different models |
21 | * of the ColdFire! | 21 | * of the ColdFire! |
22 | */ | 22 | */ |
23 | typedef struct fec { | 23 | #define FEC_IEVENT 0x004 /* Interrupt event reg */ |
24 | unsigned long fec_reserved0; | 24 | #define FEC_IMASK 0x008 /* Interrupt mask reg */ |
25 | unsigned long fec_ievent; /* Interrupt event reg */ | 25 | #define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ |
26 | unsigned long fec_imask; /* Interrupt mask reg */ | 26 | #define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ |
27 | unsigned long fec_reserved1; | 27 | #define FEC_ECNTRL 0x024 /* Ethernet control reg */ |
28 | unsigned long fec_r_des_active; /* Receive descriptor reg */ | 28 | #define FEC_MII_DATA 0x040 /* MII manage frame reg */ |
29 | unsigned long fec_x_des_active; /* Transmit descriptor reg */ | 29 | #define FEC_MII_SPEED 0x044 /* MII speed control reg */ |
30 | unsigned long fec_reserved2[3]; | 30 | #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ |
31 | unsigned long fec_ecntrl; /* Ethernet control reg */ | 31 | #define FEC_R_CNTRL 0x084 /* Receive control reg */ |
32 | unsigned long fec_reserved3[6]; | 32 | #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ |
33 | unsigned long fec_mii_data; /* MII manage frame reg */ | 33 | #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ |
34 | unsigned long fec_mii_speed; /* MII speed control reg */ | 34 | #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ |
35 | unsigned long fec_reserved4[7]; | 35 | #define FEC_OPD 0x0ec /* Opcode + Pause duration */ |
36 | unsigned long fec_mib_ctrlstat; /* MIB control/status reg */ | 36 | #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ |
37 | unsigned long fec_reserved5[7]; | 37 | #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ |
38 | unsigned long fec_r_cntrl; /* Receive control reg */ | 38 | #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ |
39 | unsigned long fec_reserved6[15]; | 39 | #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ |
40 | unsigned long fec_x_cntrl; /* Transmit Control reg */ | 40 | #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ |
41 | unsigned long fec_reserved7[7]; | 41 | #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ |
42 | unsigned long fec_addr_low; /* Low 32bits MAC address */ | 42 | #define FEC_R_FSTART 0x150 /* FIFO receive start reg */ |
43 | unsigned long fec_addr_high; /* High 16bits MAC address */ | 43 | #define FEC_R_DES_START 0x180 /* Receive descriptor ring */ |
44 | unsigned long fec_opd; /* Opcode + Pause duration */ | 44 | #define FEC_X_DES_START 0x184 /* Transmit descriptor ring */ |
45 | unsigned long fec_reserved8[10]; | 45 | #define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */ |
46 | unsigned long fec_hash_table_high; /* High 32bits hash table */ | ||
47 | unsigned long fec_hash_table_low; /* Low 32bits hash table */ | ||
48 | unsigned long fec_grp_hash_table_high;/* High 32bits hash table */ | ||
49 | unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */ | ||
50 | unsigned long fec_reserved9[7]; | ||
51 | unsigned long fec_x_wmrk; /* FIFO transmit water mark */ | ||
52 | unsigned long fec_reserved10; | ||
53 | unsigned long fec_r_bound; /* FIFO receive bound reg */ | ||
54 | unsigned long fec_r_fstart; /* FIFO receive start reg */ | ||
55 | unsigned long fec_reserved11[11]; | ||
56 | unsigned long fec_r_des_start; /* Receive descriptor ring */ | ||
57 | unsigned long fec_x_des_start; /* Transmit descriptor ring */ | ||
58 | unsigned long fec_r_buff_size; /* Maximum receive buff size */ | ||
59 | } fec_t; | ||
60 | 46 | ||
61 | #else | 47 | #else |
62 | 48 | ||
63 | /* | 49 | #define FEC_ECNTRL; 0x000 /* Ethernet control reg */ |
64 | * Define device register set address map. | 50 | #define FEC_IEVENT; 0x004 /* Interrupt even reg */ |
65 | */ | 51 | #define FEC_IMASK; 0x008 /* Interrupt mask reg */ |
66 | typedef struct fec { | 52 | #define FEC_IVEC; 0x00c /* Interrupt vec status reg */ |
67 | unsigned long fec_ecntrl; /* Ethernet control reg */ | 53 | #define FEC_R_DES_ACTIVE; 0x010 /* Receive descriptor reg */ |
68 | unsigned long fec_ievent; /* Interrupt even reg */ | 54 | #define FEC_X_DES_ACTIVE; 0x01c /* Transmit descriptor reg */ |
69 | unsigned long fec_imask; /* Interrupt mask reg */ | 55 | #define FEC_MII_DATA 0x040 /* MII manage frame reg */ |
70 | unsigned long fec_ivec; /* Interrupt vec status reg */ | 56 | #define FEC_MII_SPEED 0x044 /* MII speed control reg */ |
71 | unsigned long fec_r_des_active; /* Receive descriptor reg */ | 57 | #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ |
72 | unsigned long fec_x_des_active; /* Transmit descriptor reg */ | 58 | #define FEC_R_FSTART 0x090 /* FIFO receive start reg */ |
73 | unsigned long fec_reserved1[10]; | 59 | #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ |
74 | unsigned long fec_mii_data; /* MII manage frame reg */ | 60 | #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ |
75 | unsigned long fec_mii_speed; /* MII speed control reg */ | 61 | #define FEC_R_CNTRL 0x104 /* Receive control reg */ |
76 | unsigned long fec_reserved2[17]; | 62 | #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ |
77 | unsigned long fec_r_bound; /* FIFO receive bound reg */ | 63 | #define FEC_X_CNTRL 0x144 /* Transmit Control reg */ |
78 | unsigned long fec_r_fstart; /* FIFO receive start reg */ | 64 | #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ |
79 | unsigned long fec_reserved3[4]; | 65 | #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ |
80 | unsigned long fec_x_wmrk; /* FIFO transmit water mark */ | 66 | #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ |
81 | unsigned long fec_reserved4; | 67 | #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ |
82 | unsigned long fec_x_fstart; /* FIFO transmit start reg */ | 68 | #define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */ |
83 | unsigned long fec_reserved5[21]; | 69 | #define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */ |
84 | unsigned long fec_r_cntrl; /* Receive control reg */ | 70 | #define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */ |
85 | unsigned long fec_max_frm_len; /* Maximum frame length reg */ | 71 | #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ |
86 | unsigned long fec_reserved6[14]; | ||
87 | unsigned long fec_x_cntrl; /* Transmit Control reg */ | ||
88 | unsigned long fec_reserved7[158]; | ||
89 | unsigned long fec_addr_low; /* Low 32bits MAC address */ | ||
90 | unsigned long fec_addr_high; /* High 16bits MAC address */ | ||
91 | unsigned long fec_grp_hash_table_high;/* High 32bits hash table */ | ||
92 | unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */ | ||
93 | unsigned long fec_r_des_start; /* Receive descriptor ring */ | ||
94 | unsigned long fec_x_des_start; /* Transmit descriptor ring */ | ||
95 | unsigned long fec_r_buff_size; /* Maximum receive buff size */ | ||
96 | unsigned long reserved8[9]; | ||
97 | unsigned long fec_fifo_ram[112]; /* FIFO RAM buffer */ | ||
98 | } fec_t; | ||
99 | 72 | ||
100 | #endif /* CONFIG_M5272 */ | 73 | #endif /* CONFIG_M5272 */ |
101 | 74 | ||