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authorAndi Kleen <ak@suse.de>2006-01-11 16:42:45 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-11 22:01:12 -0500
commit39b3a7910556005a7a0d042ecb7ff98bfa84ea57 (patch)
treeefcb2602e6fd198c9af34e726741eb389fa4e292
parent2d52ede9876ba566b583f255fdc43800eea81baa (diff)
[PATCH] i386/x86-64: Generalize X86_FEATURE_CONSTANT_TSC flag
Define it for i386 too. This is a synthetic flag that signifies that the CPU's TSC runs at a constant P state invariant frequency. Fix up the logic on x86-64/i386 to set it on all known CPUs. Use the AMD defined bit to set it on future AMD CPUs. Cc: venkatesh.pallipadi@intel.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--arch/i386/kernel/cpu/amd.c6
-rw-r--r--arch/i386/kernel/cpu/intel.c5
-rw-r--r--arch/i386/kernel/cpu/proc.c2
-rw-r--r--arch/x86_64/kernel/setup.c5
-rw-r--r--include/asm-i386/cpufeature.h1
5 files changed, 15 insertions, 4 deletions
diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c
index e7697e077f6b..4397f61705e2 100644
--- a/arch/i386/kernel/cpu/amd.c
+++ b/arch/i386/kernel/cpu/amd.c
@@ -216,6 +216,11 @@ static void __init init_amd(struct cpuinfo_x86 *c)
216 c->x86_max_cores = 1; 216 c->x86_max_cores = 1;
217 } 217 }
218 218
219 if (cpuid_eax(0x80000000) >= 0x80000007) {
220 if (cpuid_edx(0x80000007) & (1<<8))
221 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
222 }
223
219#ifdef CONFIG_X86_HT 224#ifdef CONFIG_X86_HT
220 /* 225 /*
221 * On a AMD dual core setup the lower bits of the APIC id 226 * On a AMD dual core setup the lower bits of the APIC id
@@ -233,6 +238,7 @@ static void __init init_amd(struct cpuinfo_x86 *c)
233 cpu, c->x86_max_cores, cpu_core_id[cpu]); 238 cpu, c->x86_max_cores, cpu_core_id[cpu]);
234 } 239 }
235#endif 240#endif
241
236} 242}
237 243
238static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) 244static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c
index 5e2da704f0fa..8c0120186b9f 100644
--- a/arch/i386/kernel/cpu/intel.c
+++ b/arch/i386/kernel/cpu/intel.c
@@ -183,10 +183,13 @@ static void __devinit init_intel(struct cpuinfo_x86 *c)
183 } 183 }
184#endif 184#endif
185 185
186 if (c->x86 == 15) 186 if (c->x86 == 15)
187 set_bit(X86_FEATURE_P4, c->x86_capability); 187 set_bit(X86_FEATURE_P4, c->x86_capability);
188 if (c->x86 == 6) 188 if (c->x86 == 6)
189 set_bit(X86_FEATURE_P3, c->x86_capability); 189 set_bit(X86_FEATURE_P3, c->x86_capability);
190 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
191 (c->x86 == 0x6 && c->x86_model >= 0x0e))
192 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
190} 193}
191 194
192 195
diff --git a/arch/i386/kernel/cpu/proc.c b/arch/i386/kernel/cpu/proc.c
index 6d91b274589c..66592fad2bfe 100644
--- a/arch/i386/kernel/cpu/proc.c
+++ b/arch/i386/kernel/cpu/proc.c
@@ -40,7 +40,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
40 /* Other (Linux-defined) */ 40 /* Other (Linux-defined) */
41 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr", 41 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
42 NULL, NULL, NULL, NULL, 42 NULL, NULL, NULL, NULL,
43 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 43 "constant_tsc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
44 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 44 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
45 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 45 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
46 46
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index 754a05f9b4db..d9c1c3bd6150 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -1032,7 +1032,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1032 1032
1033 if (c->x86 == 15) 1033 if (c->x86 == 15)
1034 c->x86_cache_alignment = c->x86_clflush_size * 2; 1034 c->x86_cache_alignment = c->x86_clflush_size * 2;
1035 if (c->x86 >= 15) 1035 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
1036 (c->x86 == 0x6 && c->x86_model >= 0x0e))
1036 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability); 1037 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
1037 c->x86_max_cores = intel_num_cpu_cores(c); 1038 c->x86_max_cores = intel_num_cpu_cores(c);
1038 1039
@@ -1273,7 +1274,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1273 "tm", 1274 "tm",
1274 "stc" 1275 "stc"
1275 "?", 1276 "?",
1276 "constant_tsc", 1277 /* nothing */ /* constant_tsc - moved to flags */
1277 }; 1278 };
1278 1279
1279 1280
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index ff1187e80c32..c4ec2a4d8fdf 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -69,6 +69,7 @@
69#define X86_FEATURE_K7 (3*32+ 5) /* Athlon */ 69#define X86_FEATURE_K7 (3*32+ 5) /* Athlon */
70#define X86_FEATURE_P3 (3*32+ 6) /* P3 */ 70#define X86_FEATURE_P3 (3*32+ 6) /* P3 */
71#define X86_FEATURE_P4 (3*32+ 7) /* P4 */ 71#define X86_FEATURE_P4 (3*32+ 7) /* P4 */
72#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
72 73
73/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 74/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
74#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ 75#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */