diff options
author | Juha Yrjola <juha.yrjola@solidboot.com> | 2006-09-25 05:41:37 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2006-09-25 05:41:37 -0400 |
commit | eaca33df44c0d00bc12b16e72b728ade25adf14d (patch) | |
tree | e825e325d2b398cd14bccb1ed77a3007c63bd888 | |
parent | dbab288be47ddc84ad52ff926ea1a0efd33acb57 (diff) |
ARM: OMAP: Add write memory barriers to OMAP2 clock code
After adjusting clock parameters, OMAP2 CPUs need a memory
barrier to make sure the changes go into effect immediately.
Otherwise bad things will happen if we try to access the
peripheral whose clock is just being enabled.
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 82643a211008..302d5a796340 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -135,6 +135,7 @@ static int _omap2_clk_enable(struct clk * clk) | |||
135 | regval32 = __raw_readl(clk->enable_reg); | 135 | regval32 = __raw_readl(clk->enable_reg); |
136 | regval32 |= (1 << clk->enable_bit); | 136 | regval32 |= (1 << clk->enable_bit); |
137 | __raw_writel(regval32, clk->enable_reg); | 137 | __raw_writel(regval32, clk->enable_reg); |
138 | wmb(); | ||
138 | 139 | ||
139 | return 0; | 140 | return 0; |
140 | } | 141 | } |
@@ -168,6 +169,7 @@ static void _omap2_clk_disable(struct clk *clk) | |||
168 | regval32 = __raw_readl(clk->enable_reg); | 169 | regval32 = __raw_readl(clk->enable_reg); |
169 | regval32 &= ~(1 << clk->enable_bit); | 170 | regval32 &= ~(1 << clk->enable_bit); |
170 | __raw_writel(regval32, clk->enable_reg); | 171 | __raw_writel(regval32, clk->enable_reg); |
172 | wmb(); | ||
171 | } | 173 | } |
172 | 174 | ||
173 | static int omap2_clk_enable(struct clk *clk) | 175 | static int omap2_clk_enable(struct clk *clk) |
@@ -697,12 +699,14 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
697 | reg_val = __raw_readl(reg); | 699 | reg_val = __raw_readl(reg); |
698 | reg_val &= ~(field_mask << div_off); | 700 | reg_val &= ~(field_mask << div_off); |
699 | reg_val |= (field_val << div_off); | 701 | reg_val |= (field_val << div_off); |
700 | |||
701 | __raw_writel(reg_val, reg); | 702 | __raw_writel(reg_val, reg); |
703 | wmb(); | ||
702 | clk->rate = clk->parent->rate / field_val; | 704 | clk->rate = clk->parent->rate / field_val; |
703 | 705 | ||
704 | if (clk->flags & DELAYED_APP) | 706 | if (clk->flags & DELAYED_APP) { |
705 | __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); | 707 | __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); |
708 | wmb(); | ||
709 | } | ||
706 | ret = 0; | 710 | ret = 0; |
707 | } else if (clk->set_rate != 0) | 711 | } else if (clk->set_rate != 0) |
708 | ret = clk->set_rate(clk, rate); | 712 | ret = clk->set_rate(clk, rate); |
@@ -838,10 +842,12 @@ static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | |||
838 | reg_val = __raw_readl(reg) & ~(field_mask << src_off); | 842 | reg_val = __raw_readl(reg) & ~(field_mask << src_off); |
839 | reg_val |= (field_val << src_off); | 843 | reg_val |= (field_val << src_off); |
840 | __raw_writel(reg_val, reg); | 844 | __raw_writel(reg_val, reg); |
845 | wmb(); | ||
841 | 846 | ||
842 | if (clk->flags & DELAYED_APP) | 847 | if (clk->flags & DELAYED_APP) { |
843 | __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); | 848 | __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); |
844 | 849 | wmb(); | |
850 | } | ||
845 | if (clk->usecount > 0) | 851 | if (clk->usecount > 0) |
846 | _omap2_clk_enable(clk); | 852 | _omap2_clk_enable(clk); |
847 | 853 | ||