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authorMike Frysinger <vapier@gentoo.org>2010-10-27 15:29:26 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:16 -0500
commit10cdc1a78a02bb1d76b28b146083cb060399d86f (patch)
tree0b2cdb9379109ca114983186b4a7430fe896d543
parent73a400646b8e26615f3ef1a0a4bc0cd0d5bd284c (diff)
Blackfin: unify pll.h headers
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat
-rw-r--r--arch/blackfin/include/mach-common/pll.h86
-rw-r--r--arch/blackfin/mach-bf518/include/mach/pll.h64
-rw-r--r--arch/blackfin/mach-bf527/include/mach/pll.h64
-rw-r--r--arch/blackfin/mach-bf533/include/mach/pll.h58
-rw-r--r--arch/blackfin/mach-bf537/include/mach/pll.h58
-rw-r--r--arch/blackfin/mach-bf538/include/mach/pll.h64
-rw-r--r--arch/blackfin/mach-bf548/include/mach/pll.h70
-rw-r--r--arch/blackfin/mach-bf561/include/mach/pll.h64
8 files changed, 93 insertions, 435 deletions
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
new file mode 100644
index 000000000000..382178b361af
--- /dev/null
+++ b/arch/blackfin/include/mach-common/pll.h
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2005-2010 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_COMMON_PLL_H
8#define _MACH_COMMON_PLL_H
9
10#ifndef __ASSEMBLY__
11
12#include <asm/blackfin.h>
13#include <asm/irqflags.h>
14
15#ifndef bfin_iwr_restore
16static inline void
17bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
18{
19#ifdef SIC_IWR
20 bfin_write_SIC_IWR(iwr0);
21#else
22 bfin_write_SIC_IWR0(iwr0);
23# ifdef SIC_IWR1
24 bfin_write_SIC_IWR1(iwr1);
25# endif
26# ifdef SIC_IWR2
27 bfin_write_SIC_IWR2(iwr2);
28# endif
29#endif
30}
31#endif
32
33#ifndef bfin_iwr_save
34static inline void
35bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
36 unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
37{
38#ifdef SIC_IWR
39 *iwr0 = bfin_read_SIC_IWR();
40#else
41 *iwr0 = bfin_read_SIC_IWR0();
42# ifdef SIC_IWR1
43 *iwr1 = bfin_read_SIC_IWR1();
44# endif
45# ifdef SIC_IWR2
46 *iwr2 = bfin_read_SIC_IWR2();
47# endif
48#endif
49 bfin_iwr_restore(niwr0, niwr1, niwr2);
50}
51#endif
52
53static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
54{
55 unsigned long flags, iwr0, iwr1, iwr2;
56
57 if (val == bfin_read_PLL_CTL())
58 return;
59
60 flags = hard_local_irq_save();
61 /* Enable the PLL Wakeup bit in SIC IWR */
62 bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
63
64 bfin_write16(addr, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_iwr_restore(iwr0, iwr1, iwr2);
69 hard_local_irq_restore(flags);
70}
71
72/* Writing to PLL_CTL initiates a PLL relock sequence */
73static inline void bfin_write_PLL_CTL(unsigned int val)
74{
75 _bfin_write_pll_relock(PLL_CTL, val);
76}
77
78/* Writing to VR_CTL initiates a PLL relock sequence */
79static inline void bfin_write_VR_CTL(unsigned int val)
80{
81 _bfin_write_pll_relock(VR_CTL, val);
82}
83
84#endif
85
86#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h
index d5502988896b..94cca674d835 100644
--- a/arch/blackfin/mach-bf518/include/mach/pll.h
+++ b/arch/blackfin/mach-bf518/include/mach/pll.h
@@ -1,63 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
index 24f1d7c02325..94cca674d835 100644
--- a/arch/blackfin/mach-bf527/include/mach/pll.h
+++ b/arch/blackfin/mach-bf527/include/mach/pll.h
@@ -1,63 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf533/include/mach/pll.h
+++ b/arch/blackfin/mach-bf533/include/mach/pll.h
@@ -1,57 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 hard_local_irq_restore(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 flags = hard_local_irq_save();
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 hard_local_irq_restore(flags);
55}
56
57#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf537/include/mach/pll.h
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -1,57 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 hard_local_irq_restore(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 flags = hard_local_irq_save();
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 hard_local_irq_restore(flags);
55}
56
57#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h
index b30bbcd412a7..94cca674d835 100644
--- a/arch/blackfin/mach-bf538/include/mach/pll.h
+++ b/arch/blackfin/mach-bf538/include/mach/pll.h
@@ -1,63 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2008-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
index 7865a090d333..94cca674d835 100644
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ b/arch/blackfin/mach-bf548/include/mach/pll.h
@@ -1,69 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1, iwr2;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 iwr2 = bfin_read32(SIC_IWR2);
26 /* Only allow PPL Wakeup) */
27 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
28 bfin_write32(SIC_IWR1, 0);
29 bfin_write32(SIC_IWR2, 0);
30
31 bfin_write16(PLL_CTL, val);
32 SSYNC();
33 asm("IDLE;");
34
35 bfin_write32(SIC_IWR0, iwr0);
36 bfin_write32(SIC_IWR1, iwr1);
37 bfin_write32(SIC_IWR2, iwr2);
38 hard_local_irq_restore(flags);
39}
40
41/* Writing to VR_CTL initiates a PLL relock sequence. */
42static __inline__ void bfin_write_VR_CTL(unsigned int val)
43{
44 unsigned long flags, iwr0, iwr1, iwr2;
45
46 if (val == bfin_read_VR_CTL())
47 return;
48
49 flags = hard_local_irq_save();
50 /* Enable the PLL Wakeup bit in SIC IWR */
51 iwr0 = bfin_read32(SIC_IWR0);
52 iwr1 = bfin_read32(SIC_IWR1);
53 iwr2 = bfin_read32(SIC_IWR2);
54 /* Only allow PPL Wakeup) */
55 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
56 bfin_write32(SIC_IWR1, 0);
57 bfin_write32(SIC_IWR2, 0);
58
59 bfin_write16(VR_CTL, val);
60 SSYNC();
61 asm("IDLE;");
62
63 bfin_write32(SIC_IWR0, iwr0);
64 bfin_write32(SIC_IWR1, iwr1);
65 bfin_write32(SIC_IWR2, iwr2);
66 hard_local_irq_restore(flags);
67}
68
69#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
index 5cdb655c4465..94cca674d835 100644
--- a/arch/blackfin/mach-bf561/include/mach/pll.h
+++ b/arch/blackfin/mach-bf561/include/mach/pll.h
@@ -1,63 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2005-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 20:02:53 -0500