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authorBalaji Rao <balajirrao@openmoko.org>2009-01-08 19:49:01 -0500
committerSamuel Ortiz <samuel@sortiz.org>2009-01-10 19:34:23 -0500
commitf52046b14b1e1a8a02ae48d0c69d39c5e204644f (patch)
treeb0d6e1ae2c839fe415adcaf054233a73011b69d7
parentc59765042f53a79a7a65585042ff463b69cb248c (diff)
mfd: PCF50633 core driver
This patch implements the core of the PCF50633 driver. This core driver has generic register read/write functions and does interrupt management for its sub devices. Signed-off-by: Balaji Rao <balajirrao@openmoko.org> Cc: Andy Green <andy@openmoko.com> Signed-off-by: Samuel Ortiz <sameo@openedhand.com>
Diffstat
-rw-r--r--drivers/mfd/Kconfig9
-rw-r--r--drivers/mfd/Makefile2
-rw-r--r--drivers/mfd/pcf50633-core.c710
-rw-r--r--include/linux/mfd/pcf50633/core.h218
4 files changed, 939 insertions, 0 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 416f9e7286ba..3ac32e45b03b 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -217,6 +217,15 @@ config MFD_WM8350_I2C
217 I2C as the control interface. Additional options must be 217 I2C as the control interface. Additional options must be
218 selected to enable support for the functionality of the chip. 218 selected to enable support for the functionality of the chip.
219 219
220config MFD_PCF50633
221 tristate "Support for NXP PCF50633"
222 depends on I2C
223 help
224 Say yes here if you have NXP PCF50633 chip on your board.
225 This core driver provides register access and IRQ handling
226 facilities, and registers devices for the various functions
227 so that function-specific drivers can bind to them.
228
220endmenu 229endmenu
221 230
222menu "Multimedia Capabilities Port drivers" 231menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 0c9418b36c26..23d4d10981b3 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -37,3 +37,5 @@ endif
37obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o 37obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o
38 38
39obj-$(CONFIG_PMIC_DA903X) += da903x.o 39obj-$(CONFIG_PMIC_DA903X) += da903x.o
40
41obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o \ No newline at end of file
diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c
new file mode 100644
index 000000000000..24508e28e3fb
--- /dev/null
+++ b/drivers/mfd/pcf50633-core.c
@@ -0,0 +1,710 @@
1/* NXP PCF50633 Power Management Unit (PMU) driver
2 *
3 * (C) 2006-2008 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * Balaji Rao <balajirrao@openmoko.org>
6 * All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/device.h>
17#include <linux/sysfs.h>
18#include <linux/device.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/workqueue.h>
23#include <linux/platform_device.h>
24#include <linux/i2c.h>
25#include <linux/irq.h>
26
27#include <linux/mfd/pcf50633/core.h>
28
29/* Two MBCS registers used during cold start */
30#define PCF50633_REG_MBCS1 0x4b
31#define PCF50633_REG_MBCS2 0x4c
32#define PCF50633_MBCS1_USBPRES 0x01
33#define PCF50633_MBCS1_ADAPTPRES 0x01
34
35static int __pcf50633_read(struct pcf50633 *pcf, u8 reg, int num, u8 *data)
36{
37 int ret;
38
39 ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg,
40 num, data);
41 if (ret < 0)
42 dev_err(pcf->dev, "Error reading %d regs at %d\n", num, reg);
43
44 return ret;
45}
46
47static int __pcf50633_write(struct pcf50633 *pcf, u8 reg, int num, u8 *data)
48{
49 int ret;
50
51 ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg,
52 num, data);
53 if (ret < 0)
54 dev_err(pcf->dev, "Error writing %d regs at %d\n", num, reg);
55
56 return ret;
57
58}
59
60/* Read a block of upto 32 regs */
61int pcf50633_read_block(struct pcf50633 *pcf, u8 reg,
62 int nr_regs, u8 *data)
63{
64 int ret;
65
66 mutex_lock(&pcf->lock);
67 ret = __pcf50633_read(pcf, reg, nr_regs, data);
68 mutex_unlock(&pcf->lock);
69
70 return ret;
71}
72EXPORT_SYMBOL_GPL(pcf50633_read_block);
73
74/* Write a block of upto 32 regs */
75int pcf50633_write_block(struct pcf50633 *pcf , u8 reg,
76 int nr_regs, u8 *data)
77{
78 int ret;
79
80 mutex_lock(&pcf->lock);
81 ret = __pcf50633_write(pcf, reg, nr_regs, data);
82 mutex_unlock(&pcf->lock);
83
84 return ret;
85}
86EXPORT_SYMBOL_GPL(pcf50633_write_block);
87
88u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg)
89{
90 u8 val;
91
92 mutex_lock(&pcf->lock);
93 __pcf50633_read(pcf, reg, 1, &val);
94 mutex_unlock(&pcf->lock);
95
96 return val;
97}
98EXPORT_SYMBOL_GPL(pcf50633_reg_read);
99
100int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val)
101{
102 int ret;
103
104 mutex_lock(&pcf->lock);
105 ret = __pcf50633_write(pcf, reg, 1, &val);
106 mutex_unlock(&pcf->lock);
107
108 return ret;
109}
110EXPORT_SYMBOL_GPL(pcf50633_reg_write);
111
112int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val)
113{
114 int ret;
115 u8 tmp;
116
117 val &= mask;
118
119 mutex_lock(&pcf->lock);
120 ret = __pcf50633_read(pcf, reg, 1, &tmp);
121 if (ret < 0)
122 goto out;
123
124 tmp &= ~mask;
125 tmp |= val;
126 ret = __pcf50633_write(pcf, reg, 1, &tmp);
127
128out:
129 mutex_unlock(&pcf->lock);
130
131 return ret;
132}
133EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask);
134
135int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val)
136{
137 int ret;
138 u8 tmp;
139
140 mutex_lock(&pcf->lock);
141 ret = __pcf50633_read(pcf, reg, 1, &tmp);
142 if (ret < 0)
143 goto out;
144
145 tmp &= ~val;
146 ret = __pcf50633_write(pcf, reg, 1, &tmp);
147
148out:
149 mutex_unlock(&pcf->lock);
150
151 return ret;
152}
153EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits);
154
155/* sysfs attributes */
156static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr,
157 char *buf)
158{
159 struct pcf50633 *pcf = dev_get_drvdata(dev);
160 u8 dump[16];
161 int n, n1, idx = 0;
162 char *buf1 = buf;
163 static u8 address_no_read[] = { /* must be ascending */
164 PCF50633_REG_INT1,
165 PCF50633_REG_INT2,
166 PCF50633_REG_INT3,
167 PCF50633_REG_INT4,
168 PCF50633_REG_INT5,
169 0 /* terminator */
170 };
171
172 for (n = 0; n < 256; n += sizeof(dump)) {
173 for (n1 = 0; n1 < sizeof(dump); n1++)
174 if (n == address_no_read[idx]) {
175 idx++;
176 dump[n1] = 0x00;
177 } else
178 dump[n1] = pcf50633_reg_read(pcf, n + n1);
179
180 hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0);
181 buf1 += strlen(buf1);
182 *buf1++ = '\n';
183 *buf1 = '\0';
184 }
185
186 return buf1 - buf;
187}
188static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL);
189
190static ssize_t show_resume_reason(struct device *dev,
191 struct device_attribute *attr, char *buf)
192{
193 struct pcf50633 *pcf = dev_get_drvdata(dev);
194 int n;
195
196 n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
197 pcf->resume_reason[0],
198 pcf->resume_reason[1],
199 pcf->resume_reason[2],
200 pcf->resume_reason[3],
201 pcf->resume_reason[4]);
202
203 return n;
204}
205static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL);
206
207static struct attribute *pcf_sysfs_entries[] = {
208 &dev_attr_dump_regs.attr,
209 &dev_attr_resume_reason.attr,
210 NULL,
211};
212
213static struct attribute_group pcf_attr_group = {
214 .name = NULL, /* put in device directory */
215 .attrs = pcf_sysfs_entries,
216};
217
218int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
219 void (*handler) (int, void *), void *data)
220{
221 if (irq < 0 || irq > PCF50633_NUM_IRQ || !handler)
222 return -EINVAL;
223
224 if (WARN_ON(pcf->irq_handler[irq].handler))
225 return -EBUSY;
226
227 mutex_lock(&pcf->lock);
228 pcf->irq_handler[irq].handler = handler;
229 pcf->irq_handler[irq].data = data;
230 mutex_unlock(&pcf->lock);
231
232 return 0;
233}
234EXPORT_SYMBOL_GPL(pcf50633_register_irq);
235
236int pcf50633_free_irq(struct pcf50633 *pcf, int irq)
237{
238 if (irq < 0 || irq > PCF50633_NUM_IRQ)
239 return -EINVAL;
240
241 mutex_lock(&pcf->lock);
242 pcf->irq_handler[irq].handler = NULL;
243 mutex_unlock(&pcf->lock);
244
245 return 0;
246}
247EXPORT_SYMBOL_GPL(pcf50633_free_irq);
248
249static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask)
250{
251 u8 reg, bits, tmp;
252 int ret = 0, idx;
253
254 idx = irq >> 3;
255 reg = PCF50633_REG_INT1M + idx;
256 bits = 1 << (irq & 0x07);
257
258 mutex_lock(&pcf->lock);
259
260 if (mask) {
261 ret = __pcf50633_read(pcf, reg, 1, &tmp);
262 if (ret < 0)
263 goto out;
264
265 tmp |= bits;
266
267 ret = __pcf50633_write(pcf, reg, 1, &tmp);
268 if (ret < 0)
269 goto out;
270
271 pcf->mask_regs[idx] &= ~bits;
272 pcf->mask_regs[idx] |= bits;
273 } else {
274 ret = __pcf50633_read(pcf, reg, 1, &tmp);
275 if (ret < 0)
276 goto out;
277
278 tmp &= ~bits;
279
280 ret = __pcf50633_write(pcf, reg, 1, &tmp);
281 if (ret < 0)
282 goto out;
283
284 pcf->mask_regs[idx] &= ~bits;
285 }
286out:
287 mutex_unlock(&pcf->lock);
288
289 return ret;
290}
291
292int pcf50633_irq_mask(struct pcf50633 *pcf, int irq)
293{
294 dev_info(pcf->dev, "Masking IRQ %d\n", irq);
295
296 return __pcf50633_irq_mask_set(pcf, irq, 1);
297}
298EXPORT_SYMBOL_GPL(pcf50633_irq_mask);
299
300int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq)
301{
302 dev_info(pcf->dev, "Unmasking IRQ %d\n", irq);
303
304 return __pcf50633_irq_mask_set(pcf, irq, 0);
305}
306EXPORT_SYMBOL_GPL(pcf50633_irq_unmask);
307
308int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq)
309{
310 u8 reg, bits;
311
312 reg = irq >> 3;
313 bits = 1 << (irq & 0x07);
314
315 return pcf->mask_regs[reg] & bits;
316}
317EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get);
318
319static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq)
320{
321 if (pcf->irq_handler[irq].handler)
322 pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data);
323}
324
325/* Maximum amount of time ONKEY is held before emergency action is taken */
326#define PCF50633_ONKEY1S_TIMEOUT 8
327
328static void pcf50633_irq_worker(struct work_struct *work)
329{
330 struct pcf50633 *pcf;
331 int ret, i, j;
332 u8 pcf_int[5], chgstat;
333
334 pcf = container_of(work, struct pcf50633, irq_work);
335
336 /* Read the 5 INT regs in one transaction */
337 ret = pcf50633_read_block(pcf, PCF50633_REG_INT1,
338 ARRAY_SIZE(pcf_int), pcf_int);
339 if (ret != ARRAY_SIZE(pcf_int)) {
340 dev_err(pcf->dev, "Error reading INT registers\n");
341
342 /*
343 * If this doesn't ACK the interrupt to the chip, we'll be
344 * called once again as we're level triggered.
345 */
346 goto out;
347 }
348
349 /* We immediately read the usb and adapter status. We thus make sure
350 * only of USBINS/USBREM IRQ handlers are called */
351 if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) {
352 chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
353 if (chgstat & (0x3 << 4))
354 pcf_int[0] &= ~(1 << PCF50633_INT1_USBREM);
355 else
356 pcf_int[0] &= ~(1 << PCF50633_INT1_USBINS);
357 }
358
359 /* Make sure only one of ADPINS or ADPREM is set */
360 if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) {
361 chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
362 if (chgstat & (0x3 << 4))
363 pcf_int[0] &= ~(1 << PCF50633_INT1_ADPREM);
364 else
365 pcf_int[0] &= ~(1 << PCF50633_INT1_ADPINS);
366 }
367
368 dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
369 "INT4=0x%02x INT5=0x%02x\n", pcf_int[0],
370 pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]);
371
372 /* Some revisions of the chip don't have a 8s standby mode on
373 * ONKEY1S press. We try to manually do it in such cases. */
374 if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) {
375 dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
376 pcf->onkey1s_held);
377 if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT)
378 if (pcf->pdata->force_shutdown)
379 pcf->pdata->force_shutdown(pcf);
380 }
381
382 if (pcf_int[2] & PCF50633_INT3_ONKEY1S) {
383 dev_info(pcf->dev, "ONKEY1S held\n");
384 pcf->onkey1s_held = 1 ;
385
386 /* Unmask IRQ_SECOND */
387 pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M,
388 PCF50633_INT1_SECOND);
389
390 /* Unmask IRQ_ONKEYR */
391 pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M,
392 PCF50633_INT2_ONKEYR);
393 }
394
395 if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) {
396 pcf->onkey1s_held = 0;
397
398 /* Mask SECOND and ONKEYR interrupts */
399 if (pcf->mask_regs[0] & PCF50633_INT1_SECOND)
400 pcf50633_reg_set_bit_mask(pcf,
401 PCF50633_REG_INT1M,
402 PCF50633_INT1_SECOND,
403 PCF50633_INT1_SECOND);
404
405 if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR)
406 pcf50633_reg_set_bit_mask(pcf,
407 PCF50633_REG_INT2M,
408 PCF50633_INT2_ONKEYR,
409 PCF50633_INT2_ONKEYR);
410 }
411
412 /* Have we just resumed ? */
413 if (pcf->is_suspended) {
414 pcf->is_suspended = 0;
415
416 /* Set the resume reason filtering out non resumers */
417 for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
418 pcf->resume_reason[i] = pcf_int[i] &
419 pcf->pdata->resumers[i];
420
421 /* Make sure we don't pass on any ONKEY events to
422 * userspace now */
423 pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF);
424 }
425
426 for (i = 0; i < ARRAY_SIZE(pcf_int); i++) {
427 /* Unset masked interrupts */
428 pcf_int[i] &= ~pcf->mask_regs[i];
429
430 for (j = 0; j < 8 ; j++)
431 if (pcf_int[i] & (1 << j))
432 pcf50633_irq_call_handler(pcf, (i * 8) + j);
433 }
434
435out:
436 put_device(pcf->dev);
437 enable_irq(pcf->irq);
438}
439
440static irqreturn_t pcf50633_irq(int irq, void *data)
441{
442 struct pcf50633 *pcf = data;
443
444 dev_dbg(pcf->dev, "pcf50633_irq\n");
445
446 get_device(pcf->dev);
447 disable_irq(pcf->irq);
448 schedule_work(&pcf->irq_work);
449
450 return IRQ_HANDLED;
451}
452
453static void
454pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name,
455 struct platform_device **pdev)
456{
457 struct pcf50633_subdev_pdata *subdev_pdata;
458 int ret;
459
460 *pdev = platform_device_alloc(name, -1);
461 if (!*pdev) {
462 dev_err(pcf->dev, "Falied to allocate %s\n", name);
463 return;
464 }
465
466 subdev_pdata = kmalloc(sizeof(*subdev_pdata), GFP_KERNEL);
467 if (!subdev_pdata) {
468 dev_err(pcf->dev, "Error allocating subdev pdata\n");
469 platform_device_put(*pdev);
470 }
471
472 subdev_pdata->pcf = pcf;
473 platform_device_add_data(*pdev, subdev_pdata, sizeof(*subdev_pdata));
474
475 (*pdev)->dev.parent = pcf->dev;
476
477 ret = platform_device_add(*pdev);
478 if (ret) {
479 dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
480 platform_device_put(*pdev);
481 *pdev = NULL;
482 }
483}
484
485#ifdef CONFIG_PM
486static int pcf50633_suspend(struct device *dev, pm_message_t state)
487{
488 struct pcf50633 *pcf;
489 int ret = 0, i;
490 u8 res[5];
491
492 pcf = dev_get_drvdata(dev);
493
494 /* Make sure our interrupt handlers are not called
495 * henceforth */
496 disable_irq(pcf->irq);
497
498 /* Make sure that any running IRQ worker has quit */
499 cancel_work_sync(&pcf->irq_work);
500
501 /* Save the masks */
502 ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M,
503 ARRAY_SIZE(pcf->suspend_irq_masks),
504 pcf->suspend_irq_masks);
505 if (ret < 0) {
506 dev_err(pcf->dev, "error saving irq masks\n");
507 goto out;
508 }
509
510 /* Write wakeup irq masks */
511 for (i = 0; i < ARRAY_SIZE(res); i++)
512 res[i] = ~pcf->pdata->resumers[i];
513
514 ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
515 ARRAY_SIZE(res), &res[0]);
516 if (ret < 0) {
517 dev_err(pcf->dev, "error writing wakeup irq masks\n");
518 goto out;
519 }
520
521 pcf->is_suspended = 1;
522
523out:
524 return ret;
525}
526
527static int pcf50633_resume(struct device *dev)
528{
529 struct pcf50633 *pcf;
530 int ret;
531
532 pcf = dev_get_drvdata(dev);
533
534 /* Write the saved mask registers */
535 ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
536 ARRAY_SIZE(pcf->suspend_irq_masks),
537 pcf->suspend_irq_masks);
538 if (ret < 0)
539 dev_err(pcf->dev, "Error restoring saved suspend masks\n");
540
541 /* Restore regulators' state */
542
543
544 get_device(pcf->dev);
545
546 /*
547 * Clear any pending interrupts and set resume reason if any.
548 * This will leave with enable_irq()
549 */
550 pcf50633_irq_worker(&pcf->irq_work);
551
552 return 0;
553}
554#else
555#define pcf50633_suspend NULL
556#define pcf50633_resume NULL
557#endif
558
559static int __devinit pcf50633_probe(struct i2c_client *client,
560 const struct i2c_device_id *ids)
561{
562 struct pcf50633 *pcf;
563 struct pcf50633_platform_data *pdata = client->dev.platform_data;
564 int i, ret = 0;
565 int version, variant;
566
567 pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
568 if (!pcf)
569 return -ENOMEM;
570
571 pcf->pdata = pdata;
572
573 mutex_init(&pcf->lock);
574
575 i2c_set_clientdata(client, pcf);
576 pcf->dev = &client->dev;
577 pcf->i2c_client = client;
578 pcf->irq = client->irq;
579
580 INIT_WORK(&pcf->irq_work, pcf50633_irq_worker);
581
582 version = pcf50633_reg_read(pcf, 0);
583 variant = pcf50633_reg_read(pcf, 1);
584 if (version < 0 || variant < 0) {
585 dev_err(pcf->dev, "Unable to probe pcf50633\n");
586 ret = -ENODEV;
587 goto err;
588 }
589
590 dev_info(pcf->dev, "Probed device version %d variant %d\n",
591 version, variant);
592
593 /* Enable all interrupts except RTC SECOND */
594 pcf->mask_regs[0] = 0x80;
595 pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]);
596 pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
597 pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
598 pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
599 pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
600
601 /* Create sub devices */
602 pcf50633_client_dev_register(pcf, "pcf50633-input",
603 &pcf->input_pdev);
604 pcf50633_client_dev_register(pcf, "pcf50633-rtc",
605 &pcf->rtc_pdev);
606 pcf50633_client_dev_register(pcf, "pcf50633-mbc",
607 &pcf->mbc_pdev);
608 pcf50633_client_dev_register(pcf, "pcf50633-adc",
609 &pcf->adc_pdev);
610
611 for (i = 0; i < PCF50633_NUM_REGULATORS; i++) {
612 struct platform_device *pdev;
613
614 pdev = platform_device_alloc("pcf50633-regltr", i);
615 if (!pdev) {
616 dev_err(pcf->dev, "Cannot create regulator\n");
617 continue;
618 }
619
620 pdev->dev.parent = pcf->dev;
621 pdev->dev.platform_data = &pdata->reg_init_data[i];
622 pdev->dev.driver_data = pcf;
623 pcf->regulator_pdev[i] = pdev;
624
625 platform_device_add(pdev);
626 }
627
628 if (client->irq) {
629 set_irq_handler(client->irq, handle_level_irq);
630 ret = request_irq(client->irq, pcf50633_irq,
631 IRQF_TRIGGER_LOW, "pcf50633", pcf);
632
633 if (ret) {
634 dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
635 goto err;
636 }
637 } else {
638 dev_err(pcf->dev, "No IRQ configured\n");
639 goto err;
640 }
641
642 if (enable_irq_wake(client->irq) < 0)
643 dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source"
644 "in this hardware revision", client->irq);
645
646 ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
647 if (ret)
648 dev_err(pcf->dev, "error creating sysfs entries\n");
649
650 if (pdata->probe_done)
651 pdata->probe_done(pcf);
652
653 return 0;
654
655err:
656 kfree(pcf);
657 return ret;
658}
659
660static int __devexit pcf50633_remove(struct i2c_client *client)
661{
662 struct pcf50633 *pcf = i2c_get_clientdata(client);
663 int i;
664
665 free_irq(pcf->irq, pcf);
666
667 platform_device_unregister(pcf->input_pdev);
668 platform_device_unregister(pcf->rtc_pdev);
669 platform_device_unregister(pcf->mbc_pdev);
670 platform_device_unregister(pcf->adc_pdev);
671
672 for (i = 0; i < PCF50633_NUM_REGULATORS; i++)
673 platform_device_unregister(pcf->regulator_pdev[i]);
674
675 kfree(pcf);
676
677 return 0;
678}
679
680static struct i2c_device_id pcf50633_id_table[] = {
681 {"pcf50633", 0x73},
682};
683
684static struct i2c_driver pcf50633_driver = {
685 .driver = {
686 .name = "pcf50633",
687 .suspend = pcf50633_suspend,
688 .resume = pcf50633_resume,
689 },
690 .id_table = pcf50633_id_table,
691 .probe = pcf50633_probe,
692 .remove = __devexit_p(pcf50633_remove),
693};
694
695static int __init pcf50633_init(void)
696{
697 return i2c_add_driver(&pcf50633_driver);
698}
699
700static void __exit pcf50633_exit(void)
701{
702 i2c_del_driver(&pcf50633_driver);
703}
704
705MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU");
706MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
707MODULE_LICENSE("GPL");
708
709module_init(pcf50633_init);
710module_exit(pcf50633_exit);
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
new file mode 100644
index 000000000000..4455b212d75a
--- /dev/null
+++ b/include/linux/mfd/pcf50633/core.h
@@ -0,0 +1,218 @@
1/*
2 * core.h -- Core driver for NXP PCF50633
3 *
4 * (C) 2006-2008 by Openmoko, Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __LINUX_MFD_PCF50633_CORE_H
14#define __LINUX_MFD_PCF50633_CORE_H
15
16#include <linux/i2c.h>
17#include <linux/workqueue.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/machine.h>
20#include <linux/power_supply.h>
21
22struct pcf50633;
23
24#define PCF50633_NUM_REGULATORS 11
25
26struct pcf50633_platform_data {
27 struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
28
29 char **batteries;
30 int num_batteries;
31
32 /* Callbacks */
33 void (*probe_done)(struct pcf50633 *);
34 void (*mbc_event_callback)(struct pcf50633 *, int);
35 void (*regulator_registered)(struct pcf50633 *, int);
36 void (*force_shutdown)(struct pcf50633 *);
37
38 u8 resumers[5];
39};
40
41struct pcf50633_subdev_pdata {
42 struct pcf50633 *pcf;
43};
44
45struct pcf50633_irq {
46 void (*handler) (int, void *);
47 void *data;
48};
49
50int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
51 void (*handler) (int, void *), void *data);
52int pcf50633_free_irq(struct pcf50633 *pcf, int irq);
53
54int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
55int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
56int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
57
58int pcf50633_read_block(struct pcf50633 *, u8 reg,
59 int nr_regs, u8 *data);
60int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
61 int nr_regs, u8 *data);
62u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
63int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
64
65int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
66int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
67
68/* Interrupt registers */
69
70#define PCF50633_REG_INT1 0x02
71#define PCF50633_REG_INT2 0x03
72#define PCF50633_REG_INT3 0x04
73#define PCF50633_REG_INT4 0x05
74#define PCF50633_REG_INT5 0x06
75
76#define PCF50633_REG_INT1M 0x07
77#define PCF50633_REG_INT2M 0x08
78#define PCF50633_REG_INT3M 0x09
79#define PCF50633_REG_INT4M 0x0a
80#define PCF50633_REG_INT5M 0x0b
81
82enum {
83 /* Chip IRQs */
84 PCF50633_IRQ_ADPINS,
85 PCF50633_IRQ_ADPREM,
86 PCF50633_IRQ_USBINS,
87 PCF50633_IRQ_USBREM,
88 PCF50633_IRQ_RESERVED1,
89 PCF50633_IRQ_RESERVED2,
90 PCF50633_IRQ_ALARM,
91 PCF50633_IRQ_SECOND,
92 PCF50633_IRQ_ONKEYR,
93 PCF50633_IRQ_ONKEYF,
94 PCF50633_IRQ_EXTON1R,
95 PCF50633_IRQ_EXTON1F,
96 PCF50633_IRQ_EXTON2R,
97 PCF50633_IRQ_EXTON2F,
98 PCF50633_IRQ_EXTON3R,
99 PCF50633_IRQ_EXTON3F,
100 PCF50633_IRQ_BATFULL,
101 PCF50633_IRQ_CHGHALT,
102 PCF50633_IRQ_THLIMON,
103 PCF50633_IRQ_THLIMOFF,
104 PCF50633_IRQ_USBLIMON,
105 PCF50633_IRQ_USBLIMOFF,
106 PCF50633_IRQ_ADCRDY,
107 PCF50633_IRQ_ONKEY1S,
108 PCF50633_IRQ_LOWSYS,
109 PCF50633_IRQ_LOWBAT,
110 PCF50633_IRQ_HIGHTMP,
111 PCF50633_IRQ_AUTOPWRFAIL,
112 PCF50633_IRQ_DWN1PWRFAIL,
113 PCF50633_IRQ_DWN2PWRFAIL,
114 PCF50633_IRQ_LEDPWRFAIL,
115 PCF50633_IRQ_LEDOVP,
116 PCF50633_IRQ_LDO1PWRFAIL,
117 PCF50633_IRQ_LDO2PWRFAIL,
118 PCF50633_IRQ_LDO3PWRFAIL,
119 PCF50633_IRQ_LDO4PWRFAIL,
120 PCF50633_IRQ_LDO5PWRFAIL,
121 PCF50633_IRQ_LDO6PWRFAIL,
122 PCF50633_IRQ_HCLDOPWRFAIL,
123 PCF50633_IRQ_HCLDOOVL,
124
125 /* Always last */
126 PCF50633_NUM_IRQ,
127};
128
129struct pcf50633 {
130 struct device *dev;
131 struct i2c_client *i2c_client;
132
133 struct pcf50633_platform_data *pdata;
134 int irq;
135 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
136 struct work_struct irq_work;
137 struct mutex lock;
138
139 u8 mask_regs[5];
140
141 u8 suspend_irq_masks[5];
142 u8 resume_reason[5];
143 int is_suspended;
144
145 int onkey1s_held;
146
147 struct platform_device *rtc_pdev;
148 struct platform_device *mbc_pdev;
149 struct platform_device *adc_pdev;
150 struct platform_device *input_pdev;
151 struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS];
152};
153
154enum pcf50633_reg_int1 {
155 PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */
156 PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */
157 PCF50633_INT1_USBINS = 0x04, /* USB inserted */
158 PCF50633_INT1_USBREM = 0x08, /* USB removed */
159 /* reserved */
160 PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */
161 PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */
162};
163
164enum pcf50633_reg_int2 {
165 PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */
166 PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */
167 PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */
168 PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */
169 PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */
170 PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */
171 PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */
172 PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */
173};
174
175enum pcf50633_reg_int3 {
176 PCF50633_INT3_BATFULL = 0x01, /* Battery full */
177 PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */
178 PCF50633_INT3_THLIMON = 0x04,
179 PCF50633_INT3_THLIMOFF = 0x08,
180 PCF50633_INT3_USBLIMON = 0x10,
181 PCF50633_INT3_USBLIMOFF = 0x20,
182 PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */
183 PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */
184};
185
186enum pcf50633_reg_int4 {
187 PCF50633_INT4_LOWSYS = 0x01,
188 PCF50633_INT4_LOWBAT = 0x02,
189 PCF50633_INT4_HIGHTMP = 0x04,
190 PCF50633_INT4_AUTOPWRFAIL = 0x08,
191 PCF50633_INT4_DWN1PWRFAIL = 0x10,
192 PCF50633_INT4_DWN2PWRFAIL = 0x20,
193 PCF50633_INT4_LEDPWRFAIL = 0x40,
194 PCF50633_INT4_LEDOVP = 0x80,
195};
196
197enum pcf50633_reg_int5 {
198 PCF50633_INT5_LDO1PWRFAIL = 0x01,
199 PCF50633_INT5_LDO2PWRFAIL = 0x02,
200 PCF50633_INT5_LDO3PWRFAIL = 0x04,
201 PCF50633_INT5_LDO4PWRFAIL = 0x08,
202 PCF50633_INT5_LDO5PWRFAIL = 0x10,
203 PCF50633_INT5_LDO6PWRFAIL = 0x20,
204 PCF50633_INT5_HCLDOPWRFAIL = 0x40,
205 PCF50633_INT5_HCLDOOVL = 0x80,
206};
207
208/* misc. registers */
209#define PCF50633_REG_OOCSHDWN 0x0c
210
211/* LED registers */
212#define PCF50633_REG_LEDOUT 0x28
213#define PCF50633_REG_LEDENA 0x29
214#define PCF50633_REG_LEDCTL 0x2a
215#define PCF50633_REG_LEDDIM 0x2b
216
217#endif
218
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 14:13:43 -0500