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authorSamuel Tardieu <sam@rfc1149.net>2006-09-07 05:57:00 -0400
committerWim Van Sebroeck <wim@iguana.be>2006-10-04 16:43:03 -0400
commit8de6fc1e2023954ec21d4e84d002839afed4cad3 (patch)
treeed8f2587ae005486d49e10b8ca4563285f0ddf3d
parent196f29c8e8cd3352d26ed7bdf44f622e14adb931 (diff)
[WATCHDOG] w83697hf/hg WDT driver - patch 1
This is patch 1 in the series of patches that converts Marcus Junker's w83697hf watchdog driver to Samuel Tardieau's w83697hf/hg watchdog driver. This patch contains following changes: - the note concerning tyan motherboards has been copied from another driver, This doesn't apply here. - the comments concerning CRF6 are wrong as CRF3 is manipulated and CRF6 is never read nor written. - the comments concerning CRF5 are wrong as CRF4 is manipulated and CRF5 is never read nor written. Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
-rw-r--r--drivers/char/watchdog/w83697hf_wdt.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/char/watchdog/w83697hf_wdt.c b/drivers/char/watchdog/w83697hf_wdt.c
index 32710a97b161..c31121eab3c9 100644
--- a/drivers/char/watchdog/w83697hf_wdt.c
+++ b/drivers/char/watchdog/w83697hf_wdt.c
@@ -89,8 +89,6 @@ w83697hf_unselect_wd_register(void)
89 outb_p(0xAA, WDT_EFER); /* Leave extended function mode */ 89 outb_p(0xAA, WDT_EFER); /* Leave extended function mode */
90} 90}
91 91
92/* tyan motherboards seem to set F5 to 0x4C ?
93 * So explicitly init to appropriate value. */
94static void 92static void
95w83697hf_init(void) 93w83697hf_init(void)
96{ 94{
@@ -100,15 +98,15 @@ w83697hf_init(void)
100 98
101 outb_p(0xF3, WDT_EFER); /* Select CRF3 */ 99 outb_p(0xF3, WDT_EFER); /* Select CRF3 */
102 100
103 t=inb_p(WDT_EFDR); /* read CRF6 */ 101 t=inb_p(WDT_EFDR); /* read CRF3 */
104 if (t != 0) { 102 if (t != 0) {
105 printk (KERN_INFO PFX "Watchdog already running. Resetting timeout to %d sec\n", timeout); 103 printk (KERN_INFO PFX "Watchdog already running. Resetting timeout to %d sec\n", timeout);
106 outb_p(timeout, WDT_EFDR); /* Write back to CRF6 */ 104 outb_p(timeout, WDT_EFDR); /* Write back to CRF3 */
107 } 105 }
108 outb_p(0xF4, WDT_EFER); /* Select CRF4 */ 106 outb_p(0xF4, WDT_EFER); /* Select CRF4 */
109 t=inb_p(WDT_EFDR); /* read CRF4 */ 107 t=inb_p(WDT_EFDR); /* read CRF4 */
110 t&=~0x0C; /* set second mode & disable keyboard turning off watchdog */ 108 t&=~0x0C; /* set second mode & disable keyboard turning off watchdog */
111 outb_p(t, WDT_EFDR); /* Write back to CRF5 */ 109 outb_p(t, WDT_EFDR); /* Write back to CRF4 */
112 110
113 w83697hf_unselect_wd_register(); 111 w83697hf_unselect_wd_register();
114} 112}