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authorCatalin Marinas <catalin.marinas@arm.com>2011-03-29 06:40:06 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-05-10 13:15:24 -0400
commitf8bec75acdadd3a6597fe0acb5c3161b71cc2ea0 (patch)
tree3a81e1641c472bcaca63f7d10824a66b85ad1a0b
parent866d7f5622cf5830b085a4471e67d4ed9106cb2e (diff)
MIPS: Rename .data..mostly and properly handle it in linker script
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/include/asm/cache.h2
-rw-r--r--arch/mips/kernel/vmlinux.lds.S1
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 650ac9ba734c..b4db69fbc40c 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -17,6 +17,6 @@
17#define SMP_CACHE_SHIFT L1_CACHE_SHIFT 17#define SMP_CACHE_SHIFT L1_CACHE_SHIFT
18#define SMP_CACHE_BYTES L1_CACHE_BYTES 18#define SMP_CACHE_BYTES L1_CACHE_BYTES
19 19
20#define __read_mostly __attribute__((__section__(".data.read_mostly"))) 20#define __read_mostly __attribute__((__section__(".data..read_mostly")))
21 21
22#endif /* _ASM_CACHE_H */ 22#endif /* _ASM_CACHE_H */
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 832afbb87588..e4b0b0bec039 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -74,6 +74,7 @@ SECTIONS
74 INIT_TASK_DATA(PAGE_SIZE) 74 INIT_TASK_DATA(PAGE_SIZE)
75 NOSAVE_DATA 75 NOSAVE_DATA
76 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) 76 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
77 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
77 DATA_DATA 78 DATA_DATA
78 CONSTRUCTORS 79 CONSTRUCTORS
79 } 80 }