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authorPrarit Bhargava <prarit@sgi.com>2005-07-06 18:26:51 -0400
committerTony Luck <tony.luck@intel.com>2005-07-06 18:26:51 -0400
commitc13cf3714fc84ad2fd65771aa08e47c95a9f26ef (patch)
treef3fdd5f81fc0e39029f7cc6c8e4f41d6a736a4de
parentcb4cb2cb9b0b14bdf2fc7125e099ed7e818cea42 (diff)
[IA64] hotplug/ia64: SN Hotplug Driver: moving of header files
This patch moves header files out of the arch/ia64/sn directories and into include/asm-ia64/sn. These files were being included by other subsystems and should be under include/asm-ia64/sn. Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
-rw-r--r--arch/ia64/sn/include/xtalk/hubdev.h2
-rw-r--r--arch/ia64/sn/kernel/io_init.c14
-rw-r--r--arch/ia64/sn/kernel/irq.c5
-rw-r--r--arch/ia64/sn/pci/pci_dma.c3
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_ate.c2
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_dma.c15
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_provider.c13
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_reg.c8
-rw-r--r--include/asm-ia64/sn/pcibr_provider.h (renamed from arch/ia64/sn/include/pci/pcibr_provider.h)7
-rw-r--r--include/asm-ia64/sn/pcidev.h6
-rw-r--r--include/asm-ia64/sn/pic.h (renamed from arch/ia64/sn/include/pci/pic.h)14
-rw-r--r--include/asm-ia64/sn/tiocp.h (renamed from arch/ia64/sn/include/pci/tiocp.h)2
12 files changed, 49 insertions, 42 deletions
diff --git a/arch/ia64/sn/include/xtalk/hubdev.h b/arch/ia64/sn/include/xtalk/hubdev.h
index 868e7ecae84b..580a1c0403a7 100644
--- a/arch/ia64/sn/include/xtalk/hubdev.h
+++ b/arch/ia64/sn/include/xtalk/hubdev.h
@@ -8,6 +8,8 @@
8#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H 8#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H
9#define _ASM_IA64_SN_XTALK_HUBDEV_H 9#define _ASM_IA64_SN_XTALK_HUBDEV_H
10 10
11#include "xtalk/xwidgetdev.h"
12
11#define HUB_WIDGET_ID_MAX 0xf 13#define HUB_WIDGET_ID_MAX 0xf
12#define DEV_PER_WIDGET (2*2*8) 14#define DEV_PER_WIDGET (2*2*8)
13#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */ 15#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 2f03e3f52b63..041c4be02b2a 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -9,17 +9,17 @@
9#include <linux/bootmem.h> 9#include <linux/bootmem.h>
10#include <linux/nodemask.h> 10#include <linux/nodemask.h>
11#include <asm/sn/types.h> 11#include <asm/sn/types.h>
12#include <asm/sn/sn_sal.h>
13#include <asm/sn/addrs.h> 12#include <asm/sn/addrs.h>
14#include <asm/sn/pcibus_provider_defs.h>
15#include <asm/sn/pcidev.h>
16#include "pci/pcibr_provider.h"
17#include "xtalk/xwidgetdev.h"
18#include <asm/sn/geo.h> 13#include <asm/sn/geo.h>
19#include "xtalk/hubdev.h"
20#include <asm/sn/io.h> 14#include <asm/sn/io.h>
15#include <asm/sn/pcibr_provider.h>
16#include <asm/sn/pcibus_provider_defs.h>
17#include <asm/sn/pcidev.h>
21#include <asm/sn/simulator.h> 18#include <asm/sn/simulator.h>
19#include <asm/sn/sn_sal.h>
22#include <asm/sn/tioca_provider.h> 20#include <asm/sn/tioca_provider.h>
21#include "xtalk/hubdev.h"
22#include "xtalk/xwidgetdev.h"
23 23
24nasid_t master_nasid = INVALID_NASID; /* Partition Master */ 24nasid_t master_nasid = INVALID_NASID; /* Partition Master */
25 25
@@ -226,7 +226,7 @@ static void sn_fixup_ionodes(void)
226 * from our PCI provider include PIO maps to BAR space and interrupt 226 * from our PCI provider include PIO maps to BAR space and interrupt
227 * objects. 227 * objects.
228 */ 228 */
229static void sn_pci_fixup_slot(struct pci_dev *dev) 229void sn_pci_fixup_slot(struct pci_dev *dev)
230{ 230{
231 int idx; 231 int idx;
232 int segment = 0; 232 int segment = 0;
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
index e6f7551edfda..cf4dbf9645f1 100644
--- a/arch/ia64/sn/kernel/irq.c
+++ b/arch/ia64/sn/kernel/irq.c
@@ -10,13 +10,12 @@
10 10
11#include <linux/irq.h> 11#include <linux/irq.h>
12#include <linux/spinlock.h> 12#include <linux/spinlock.h>
13#include <asm/sn/intr.h>
14#include <asm/sn/addrs.h> 13#include <asm/sn/addrs.h>
15#include <asm/sn/arch.h> 14#include <asm/sn/arch.h>
16#include "xtalk/xwidgetdev.h" 15#include <asm/sn/intr.h>
16#include <asm/sn/pcibr_provider.h>
17#include <asm/sn/pcibus_provider_defs.h> 17#include <asm/sn/pcibus_provider_defs.h>
18#include <asm/sn/pcidev.h> 18#include <asm/sn/pcidev.h>
19#include "pci/pcibr_provider.h"
20#include <asm/sn/shub_mmr.h> 19#include <asm/sn/shub_mmr.h>
21#include <asm/sn/sn_sal.h> 20#include <asm/sn/sn_sal.h>
22 21
diff --git a/arch/ia64/sn/pci/pci_dma.c b/arch/ia64/sn/pci/pci_dma.c
index 5da9bdbde7cb..a2f7a88aefbb 100644
--- a/arch/ia64/sn/pci/pci_dma.c
+++ b/arch/ia64/sn/pci/pci_dma.c
@@ -11,9 +11,10 @@
11 11
12#include <linux/module.h> 12#include <linux/module.h>
13#include <asm/dma.h> 13#include <asm/dma.h>
14#include <asm/sn/sn_sal.h> 14#include <asm/sn/pcibr_provider.h>
15#include <asm/sn/pcibus_provider_defs.h> 15#include <asm/sn/pcibus_provider_defs.h>
16#include <asm/sn/pcidev.h> 16#include <asm/sn/pcidev.h>
17#include <asm/sn/sn_sal.h>
17 18
18#define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset) 19#define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset)
19#define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG)) 20#define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_ate.c b/arch/ia64/sn/pci/pcibr/pcibr_ate.c
index 0e47bce85f2d..d1647b863e61 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_ate.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_ate.c
@@ -8,9 +8,9 @@
8 8
9#include <linux/types.h> 9#include <linux/types.h>
10#include <asm/sn/sn_sal.h> 10#include <asm/sn/sn_sal.h>
11#include <asm/sn/pcibr_provider.h>
11#include <asm/sn/pcibus_provider_defs.h> 12#include <asm/sn/pcibus_provider_defs.h>
12#include <asm/sn/pcidev.h> 13#include <asm/sn/pcidev.h>
13#include "pci/pcibr_provider.h"
14 14
15int pcibr_invalidate_ate = 0; /* by default don't invalidate ATE on free */ 15int pcibr_invalidate_ate = 0; /* by default don't invalidate ATE on free */
16 16
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
index 64af2b2c1787..b058dc2a0b9d 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
@@ -8,18 +8,17 @@
8 8
9#include <linux/types.h> 9#include <linux/types.h>
10#include <linux/pci.h> 10#include <linux/pci.h>
11#include <asm/sn/sn_sal.h> 11#include <asm/sn/addrs.h>
12#include <asm/sn/geo.h> 12#include <asm/sn/geo.h>
13#include "xtalk/xwidgetdev.h" 13#include <asm/sn/pcibr_provider.h>
14#include "xtalk/hubdev.h"
15#include <asm/sn/pcibus_provider_defs.h> 14#include <asm/sn/pcibus_provider_defs.h>
16#include <asm/sn/pcidev.h> 15#include <asm/sn/pcidev.h>
17#include "pci/tiocp.h" 16#include <asm/sn/pic.h>
18#include "pci/pic.h" 17#include <asm/sn/sn_sal.h>
19#include "pci/pcibr_provider.h" 18#include <asm/sn/tiocp.h>
20#include "pci/tiocp.h"
21#include "tio.h" 19#include "tio.h"
22#include <asm/sn/addrs.h> 20#include "xtalk/xwidgetdev.h"
21#include "xtalk/hubdev.h"
23 22
24extern int sn_ioif_inited; 23extern int sn_ioif_inited;
25 24
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
index 3893999d23d8..9bc4de4a3ec0 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
@@ -6,18 +6,17 @@
6 * Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#include <linux/types.h>
10#include <linux/interrupt.h> 9#include <linux/interrupt.h>
10#include <linux/types.h>
11#include <linux/pci.h> 11#include <linux/pci.h>
12#include <asm/sn/sn_sal.h> 12#include <asm/sn/addrs.h>
13#include "xtalk/xwidgetdev.h"
14#include <asm/sn/geo.h> 13#include <asm/sn/geo.h>
15#include "xtalk/hubdev.h" 14#include <asm/sn/pcibr_provider.h>
16#include <asm/sn/pcibus_provider_defs.h> 15#include <asm/sn/pcibus_provider_defs.h>
17#include <asm/sn/pcidev.h> 16#include <asm/sn/pcidev.h>
18#include "pci/pcibr_provider.h" 17#include <asm/sn/sn_sal.h>
19#include <asm/sn/addrs.h> 18#include "xtalk/xwidgetdev.h"
20 19#include "xtalk/hubdev.h"
21 20
22static int sal_pcibr_error_interrupt(struct pcibus_info *soft) 21static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
23{ 22{
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
index 865c11c3b50a..21426d02fbe6 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
@@ -6,13 +6,13 @@
6 * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#include <linux/types.h>
10#include <linux/interrupt.h> 9#include <linux/interrupt.h>
10#include <linux/types.h>
11#include <asm/sn/pcibr_provider.h>
11#include <asm/sn/pcibus_provider_defs.h> 12#include <asm/sn/pcibus_provider_defs.h>
12#include <asm/sn/pcidev.h> 13#include <asm/sn/pcidev.h>
13#include "pci/tiocp.h" 14#include <asm/sn/pic.h>
14#include "pci/pic.h" 15#include <asm/sn/tiocp.h>
15#include "pci/pcibr_provider.h"
16 16
17union br_ptr { 17union br_ptr {
18 struct tiocp tio; 18 struct tiocp tio;
diff --git a/arch/ia64/sn/include/pci/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
index 1cd291d8badd..cbb4604c9349 100644
--- a/arch/ia64/sn/include/pci/pcibr_provider.h
+++ b/include/asm-ia64/sn/pcibr_provider.h
@@ -8,6 +8,9 @@
8#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H 8#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H 9#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
10 10
11#include <asm/sn/intr.h>
12#include <asm/sn/pcibus_provider_defs.h>
13
11/* Workarounds */ 14/* Workarounds */
12#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */ 15#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
13 16
@@ -20,7 +23,7 @@
20#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC) 23#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
21 24
22 25
23/* 26/*
24 * The different PCI Bridge types supported on the SGI Altix platforms 27 * The different PCI Bridge types supported on the SGI Altix platforms
25 */ 28 */
26#define PCIBR_BRIDGETYPE_UNKNOWN -1 29#define PCIBR_BRIDGETYPE_UNKNOWN -1
@@ -100,7 +103,7 @@ struct pcibus_info {
100 103
101 struct ate_resource pbi_int_ate_resource; 104 struct ate_resource pbi_int_ate_resource;
102 uint64_t pbi_int_ate_size; 105 uint64_t pbi_int_ate_size;
103 106
104 uint64_t pbi_dir_xbase; 107 uint64_t pbi_dir_xbase;
105 char pbi_hub_xid; 108 char pbi_hub_xid;
106 109
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
index 42aea21ee187..9610fcc63545 100644
--- a/include/asm-ia64/sn/pcidev.h
+++ b/include/asm-ia64/sn/pcidev.h
@@ -13,6 +13,8 @@
13#define SN_PCIDEV_INFO(pci_dev) \ 13#define SN_PCIDEV_INFO(pci_dev) \
14 ((struct pcidev_info *)(pci_dev)->sysdata) 14 ((struct pcidev_info *)(pci_dev)->sysdata)
15 15
16#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
17 (struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
16/* 18/*
17 * Given a pci_bus, return the sn pcibus_bussoft struct. Note that 19 * Given a pci_bus, return the sn pcibus_bussoft struct. Note that
18 * this only works for root busses, not for busses represented by PPB's. 20 * this only works for root busses, not for busses represented by PPB's.
@@ -53,6 +55,8 @@ struct pcidev_info {
53 55
54extern void sn_irq_fixup(struct pci_dev *pci_dev, 56extern void sn_irq_fixup(struct pci_dev *pci_dev,
55 struct sn_irq_info *sn_irq_info); 57 struct sn_irq_info *sn_irq_info);
56 58extern void sn_irq_unfixup(struct pci_dev *pci_dev);
59extern void sn_pci_fixup_slot(struct pci_dev *dev);
60extern void sn_pci_unfixup_slot(struct pci_dev *dev);
57extern void sn_irq_lh_init(void); 61extern void sn_irq_lh_init(void);
58#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */ 62#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/arch/ia64/sn/include/pci/pic.h b/include/asm-ia64/sn/pic.h
index fd18acecb1e6..0de82e6b0893 100644
--- a/arch/ia64/sn/include/pci/pic.h
+++ b/include/asm-ia64/sn/pic.h
@@ -15,7 +15,7 @@
15 * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC) 15 * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
16 * be designated as 'device 0'. That is a departure from earlier SGI 16 * be designated as 'device 0'. That is a departure from earlier SGI
17 * PCI bridges. Because of that we use config space 1 to access the 17 * PCI bridges. Because of that we use config space 1 to access the
18 * config space of the first actual PCI device on the bus. 18 * config space of the first actual PCI device on the bus.
19 * Here's what the PIC manual says: 19 * Here's what the PIC manual says:
20 * 20 *
21 * The current PCI-X bus specification now defines that the parent 21 * The current PCI-X bus specification now defines that the parent
@@ -29,14 +29,14 @@
29 * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc. 29 * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
30 * PCI-X requires we start a 1, not 0 and currently the PX brick 30 * PCI-X requires we start a 1, not 0 and currently the PX brick
31 * does associate our: 31 * does associate our:
32 * 32 *
33 * device 0 with configuration space window 1, 33 * device 0 with configuration space window 1,
34 * device 1 with configuration space window 2, 34 * device 1 with configuration space window 2,
35 * device 2 with configuration space window 3, 35 * device 2 with configuration space window 3,
36 * device 3 with configuration space window 4. 36 * device 3 with configuration space window 4.
37 * 37 *
38 * The net effect is that all config space access are off-by-one with 38 * The net effect is that all config space access are off-by-one with
39 * relation to other per-slot accesses on the PIC. 39 * relation to other per-slot accesses on the PIC.
40 * Here is a table that shows some of that: 40 * Here is a table that shows some of that:
41 * 41 *
42 * Internal Slot# 42 * Internal Slot#
@@ -65,7 +65,7 @@
65 *****************************************************************************/ 65 *****************************************************************************/
66 66
67/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0] 67/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
68 * of a 64-bit register. When writing PIC registers, always write the 68 * of a 64-bit register. When writing PIC registers, always write the
69 * entire 64 bits. 69 * entire 64 bits.
70 */ 70 */
71 71
@@ -164,7 +164,7 @@ struct pic {
164 uint64_t clear_all; /* 0x000{438,,,5F8} */ 164 uint64_t clear_all; /* 0x000{438,,,5F8} */
165 } p_buf_count[8]; 165 } p_buf_count[8];
166 166
167 167
168 /* 0x000600-0x0009FF -- PCI/X registers */ 168 /* 0x000600-0x0009FF -- PCI/X registers */
169 uint64_t p_pcix_bus_err_addr; /* 0x000600 */ 169 uint64_t p_pcix_bus_err_addr; /* 0x000600 */
170 uint64_t p_pcix_bus_err_attr; /* 0x000608 */ 170 uint64_t p_pcix_bus_err_attr; /* 0x000608 */
diff --git a/arch/ia64/sn/include/pci/tiocp.h b/include/asm-ia64/sn/tiocp.h
index f07c83b2bf6e..5f2489c9d2dd 100644
--- a/arch/ia64/sn/include/pci/tiocp.h
+++ b/include/asm-ia64/sn/tiocp.h
@@ -111,7 +111,7 @@ struct tiocp{
111 uint64_t clear_all; /* 0x000{438,,,5F8} */ 111 uint64_t clear_all; /* 0x000{438,,,5F8} */
112 } cp_buf_count[8]; 112 } cp_buf_count[8];
113 113
114 114
115 /* 0x000600-0x0009FF -- PCI/X registers */ 115 /* 0x000600-0x0009FF -- PCI/X registers */
116 uint64_t cp_pcix_bus_err_addr; /* 0x000600 */ 116 uint64_t cp_pcix_bus_err_addr; /* 0x000600 */
117 uint64_t cp_pcix_bus_err_attr; /* 0x000608 */ 117 uint64_t cp_pcix_bus_err_attr; /* 0x000608 */