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authorAlex Deucher <alexdeucher@gmail.com>2011-04-26 13:27:43 -0400
committerDave Airlie <airlied@redhat.com>2011-04-27 03:03:56 -0400
commit6565945b60922211c299968ba66a66617af32c9f (patch)
treefca477c8c1d8da6f918898fa6f1b75888779f47f
parent834f0c353ae430c1a6ce023c9b77bbd3ff9241a7 (diff)
drm/radeon/kms: add info query for tile pipes
needed by mesa for htile setup. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c13
-rw-r--r--include/drm/radeon_drm.h1
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index bf7d4c061451..871df0376b1c 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -221,6 +221,19 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
221 return -EINVAL; 221 return -EINVAL;
222 } 222 }
223 break; 223 break;
224 case RADEON_INFO_NUM_TILE_PIPES:
225 if (rdev->family >= CHIP_CAYMAN)
226 value = rdev->config.cayman.max_tile_pipes;
227 else if (rdev->family >= CHIP_CEDAR)
228 value = rdev->config.evergreen.max_tile_pipes;
229 else if (rdev->family >= CHIP_RV770)
230 value = rdev->config.rv770.max_tile_pipes;
231 else if (rdev->family >= CHIP_R600)
232 value = rdev->config.r600.max_tile_pipes;
233 else {
234 return -EINVAL;
235 }
236 break;
224 default: 237 default:
225 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 238 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
226 return -EINVAL; 239 return -EINVAL;
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 3bce1a4fc305..7aa5dddb2098 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -909,6 +909,7 @@ struct drm_radeon_cs {
909#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ 909#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */
910#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ 910#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */
911#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ 911#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */
912#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
912 913
913struct drm_radeon_info { 914struct drm_radeon_info {
914 uint32_t request; 915 uint32_t request;