aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSascha Hauer <sascha@de.rmk.(none)>2005-05-10 14:01:35 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-05-10 14:01:35 -0400
commitd7def6c22dfa9f32b3d9e5546a7a6a90c644ff5f (patch)
treebae4cdc4e45905416e0868053d62b3dd4869c047
parentfa4354359f800ef9d68ed644438efd45b559b443 (diff)
[PATCH] ARM: 2666/1: i.MX pwm controller defines
Patch from Sascha Hauer This patch adds the defines for the i.MX PWM controller Signed-off-by: Steven Scholz Signed-off-by: Sascha Hauer Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--include/asm-arm/arch-imx/imx-regs.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index f32c203952cf..93b840e8fa60 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -228,6 +228,30 @@
228#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) 228#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
229 229
230/* 230/*
231 * PWM controller
232 */
233#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */
234#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */
235#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */
236#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */
237
238#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */
239#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */
240#define PWMC_SWR (0x01<<16) /* Software Reset */
241#define PWMC_CLKSRC (0x01<<15) /* Clock Source */
242#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */
243#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */
244#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */
245#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */
246#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */
247#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
248#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */
249
250#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
251#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
252#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
253
254/*
231 * DMA Controller 255 * DMA Controller
232 */ 256 */
233#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ 257#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */