m68knommu: fix cache flushing for the 527x ColdFire processors

Fix cache flushing for the 527x ColdFire processors
Its CACR register format is slightly different.

Along with this add support for flushing the 523x cache, which uses
the same format as the 527x ColdFire's, and was missing flush support.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

1 files changed, 9 insertions, 2 deletions

diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 87e5dc0413b4..c65f00a94553 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -51,13 +51,20 @@ static inline void __flush_cache_all(void)
                 "movec  %%d0,%%CACR\n\t"
                 : : : "d0", "a0" );
 #endif /* CONFIG_M5407 */
-#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
+#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
+        __asm__ __volatile__ (
+                "movel  #0x81400100, %%d0\n\t"
+                "movec  %%d0, %%CACR\n\t"
+                "nop\n\t"
+                : : : "d0" );
+#endif /* CONFIG_M523x || CONFIG_M527x */
+#if defined(CONFIG_M528x)
         __asm__ __volatile__ (
                 "movel  #0x81000200, %%d0\n\t"
                 "movec  %%d0, %%CACR\n\t"
                 "nop\n\t"
                 : : : "d0" );
-#endif /* CONFIG_M527x || CONFIG_M528x */
+#endif /* CONFIG_M528x */
 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
         __asm__ __volatile__ (
                 "movel  #0x81000100, %%d0\n\t"