Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging

* 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging:
  hwmon: (lm85) extend to support EMC6D103 chips
  MAINTAINERS: Remove stale hwmon quilt tree
  hwmon: (k10temp) add support for AMD Family 12h/14h CPUs
  hwmon: (jc42) do not allow writing to locked registers
  hwmon: (jc42) more helpful documentation
  hwmon: (jc42) fix type mismatch

7 files changed, 86 insertions, 26 deletions

diff --git a/Documentation/hwmon/jc42 b/Documentation/hwmon/jc42
index 0e76ef12e4c6..a22ecf48f255 100644
--- a/Documentation/hwmon/jc42
+++ b/Documentation/hwmon/jc42
@@ -51,7 +51,8 @@ Supported chips:
   * JEDEC JC 42.4 compliant temperature sensor chips
     Prefix: 'jc42'
     Addresses scanned: I2C 0x18 - 0x1f
-    Datasheet: -
+    Datasheet:
+        http://www.jedec.org/sites/default/files/docs/4_01_04R19.pdf
 
 Author:
         Guenter Roeck <guenter.roeck@ericsson.com>
@@ -60,7 +61,11 @@ Author:
 Description
 -----------
 
-This driver implements support for JEDEC JC 42.4 compliant temperature sensors.
+This driver implements support for JEDEC JC 42.4 compliant temperature sensors,
+which are used on many DDR3 memory modules for mobile devices and servers. Some
+systems use the sensor to prevent memory overheating by automatically throttling
+the memory controller.
+
 The driver auto-detects the chips listed above, but can be manually instantiated
 to support other JC 42.4 compliant chips.
 
@@ -81,15 +86,19 @@ limits. The chip supports only a single register to configure the hysteresis,
 which applies to all limits. This register can be written by writing into
 temp1_crit_hyst. Other hysteresis attributes are read-only.
 
+If the BIOS has configured the sensor for automatic temperature management, it
+is likely that it has locked the registers, i.e., that the temperature limits
+cannot be changed.
+
 Sysfs entries
 -------------
 
 temp1_input             Temperature (RO)
-temp1_min               Minimum temperature (RW)
-temp1_max               Maximum temperature (RW)
-temp1_crit              Critical high temperature (RW)
+temp1_min               Minimum temperature (RO or RW)
+temp1_max               Maximum temperature (RO or RW)
+temp1_crit              Critical high temperature (RO or RW)
 
-temp1_crit_hyst         Critical hysteresis temperature (RW)
+temp1_crit_hyst         Critical hysteresis temperature (RO or RW)
 temp1_max_hyst          Maximum hysteresis temperature (RO)
 
 temp1_min_alarm         Temperature low alarm
diff --git a/Documentation/hwmon/k10temp b/Documentation/hwmon/k10temp
index 6526eee525a6..d2b56a4fd1f5 100644
--- a/Documentation/hwmon/k10temp
+++ b/Documentation/hwmon/k10temp
@@ -9,6 +9,8 @@ Supported chips:
   Socket S1G3: Athlon II, Sempron, Turion II
 * AMD Family 11h processors:
   Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
+* AMD Family 12h processors: "Llano"
+* AMD Family 14h processors: "Brazos" (C/E/G-Series)
 
   Prefix: 'k10temp'
   Addresses scanned: PCI space
@@ -17,10 +19,14 @@ Supported chips:
     http://support.amd.com/us/Processor_TechDocs/31116.pdf
   BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors:
     http://support.amd.com/us/Processor_TechDocs/41256.pdf
+  BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
+    http://support.amd.com/us/Processor_TechDocs/43170.pdf
   Revision Guide for AMD Family 10h Processors:
     http://support.amd.com/us/Processor_TechDocs/41322.pdf
   Revision Guide for AMD Family 11h Processors:
     http://support.amd.com/us/Processor_TechDocs/41788.pdf
+  Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
+    http://support.amd.com/us/Processor_TechDocs/47534.pdf
   AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:
     http://support.amd.com/us/Processor_TechDocs/43373.pdf
   AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
@@ -34,7 +40,7 @@ Description
 -----------
 
 This driver permits reading of the internal temperature sensor of AMD
-Family 10h and 11h processors.
+Family 10h/11h/12h/14h processors.
 
 All these processors have a sensor, but on those for Socket F or AM2+,
 the sensor may return inconsistent values (erratum 319).  The driver
diff --git a/MAINTAINERS b/MAINTAINERS
index 3f1e0081d3cb..6f99e1260db8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2873,7 +2873,6 @@ M:	Guenter Roeck <guenter.roeck@ericsson.com>
 L:      lm-sensors@lm-sensors.org
 W:      http://www.lm-sensors.org/
 T:      quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
-T:      quilt kernel.org/pub/linux/kernel/people/groeck/linux-staging/
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
 S:      Maintained
 F:      Documentation/hwmon/
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 773e484f1646..297bc9a7d6e6 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -238,13 +238,13 @@ config SENSORS_K8TEMP
           will be called k8temp.
 
 config SENSORS_K10TEMP
-        tristate "AMD Phenom/Sempron/Turion/Opteron temperature sensor"
+        tristate "AMD Family 10h/11h/12h/14h temperature sensor"
         depends on X86 && PCI
         help
           If you say yes here you get support for the temperature
           sensor(s) inside your CPU. Supported are later revisions of
-          the AMD Family 10h and all revisions of the AMD Family 11h
-          microarchitectures.
+          the AMD Family 10h and all revisions of the AMD Family 11h,
+          12h (Llano), and 14h (Brazos) microarchitectures.
 
           This driver can also be built as a module.  If so, the module
           will be called k10temp.
@@ -455,13 +455,14 @@ config SENSORS_JZ4740
           called jz4740-hwmon.
 
 config SENSORS_JC42
-        tristate "JEDEC JC42.4 compliant temperature sensors"
+        tristate "JEDEC JC42.4 compliant memory module temperature sensors"
         depends on I2C
         help
-          If you say yes here you get support for Jedec JC42.4 compliant
-          temperature sensors. Support will include, but not be limited to,
-          ADT7408, CAT34TS02,, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243,
-          MCP9843, SE97, SE98, STTS424, TSE2002B3, and TS3000B3.
+          If you say yes here, you get support for JEDEC JC42.4 compliant
+          temperature sensors, which are used on many DDR3 memory modules for
+          mobile devices and servers.  Support will include, but not be limited
+          to, ADT7408, CAT34TS02, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243,
+          MCP9843, SE97, SE98, STTS424(E), TSE2002B3, and TS3000B3.
 
           This driver can also be built as a module.  If so, the module
           will be called jc42.
@@ -574,7 +575,7 @@ config SENSORS_LM85
         help
           If you say yes here you get support for National Semiconductor LM85
           sensor chips and clones: ADM1027, ADT7463, ADT7468, EMC6D100,
-          EMC6D101 and EMC6D102.
+          EMC6D101, EMC6D102, and EMC6D103.
 
           This driver can also be built as a module.  If so, the module
           will be called lm85.
diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c
index 340fc78c8dde..934991237061 100644
--- a/drivers/hwmon/jc42.c
+++ b/drivers/hwmon/jc42.c
@@ -53,6 +53,8 @@ static const unsigned short normal_i2c[] = {
 
 /* Configuration register defines */
 #define JC42_CFG_CRIT_ONLY      (1 << 2)
+#define JC42_CFG_TCRIT_LOCK     (1 << 6)
+#define JC42_CFG_EVENT_LOCK     (1 << 7)
 #define JC42_CFG_SHUTDOWN       (1 << 8)
 #define JC42_CFG_HYST_SHIFT     9
 #define JC42_CFG_HYST_MASK      0x03
@@ -332,7 +334,7 @@ static ssize_t set_temp_crit_hyst(struct device *dev,
 {
         struct i2c_client *client = to_i2c_client(dev);
         struct jc42_data *data = i2c_get_clientdata(client);
-        long val;
+        unsigned long val;
         int diff, hyst;
         int err;
         int ret = count;
@@ -380,14 +382,14 @@ static ssize_t show_alarm(struct device *dev,
 
 static DEVICE_ATTR(temp1_input, S_IRUGO,
                    show_temp_input, NULL);
-static DEVICE_ATTR(temp1_crit, S_IWUSR | S_IRUGO,
+static DEVICE_ATTR(temp1_crit, S_IRUGO,
                    show_temp_crit, set_temp_crit);
-static DEVICE_ATTR(temp1_min, S_IWUSR | S_IRUGO,
+static DEVICE_ATTR(temp1_min, S_IRUGO,
                    show_temp_min, set_temp_min);
-static DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO,
+static DEVICE_ATTR(temp1_max, S_IRUGO,
                    show_temp_max, set_temp_max);
 
-static DEVICE_ATTR(temp1_crit_hyst, S_IWUSR | S_IRUGO,
+static DEVICE_ATTR(temp1_crit_hyst, S_IRUGO,
                    show_temp_crit_hyst, set_temp_crit_hyst);
 static DEVICE_ATTR(temp1_max_hyst, S_IRUGO,
                    show_temp_max_hyst, NULL);
@@ -412,8 +414,31 @@ static struct attribute *jc42_attributes[] = {
         NULL
 };
 
+static mode_t jc42_attribute_mode(struct kobject *kobj,
+                                  struct attribute *attr, int index)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct i2c_client *client = to_i2c_client(dev);
+        struct jc42_data *data = i2c_get_clientdata(client);
+        unsigned int config = data->config;
+        bool readonly;
+
+        if (attr == &dev_attr_temp1_crit.attr)
+                readonly = config & JC42_CFG_TCRIT_LOCK;
+        else if (attr == &dev_attr_temp1_min.attr ||
+                 attr == &dev_attr_temp1_max.attr)
+                readonly = config & JC42_CFG_EVENT_LOCK;
+        else if (attr == &dev_attr_temp1_crit_hyst.attr)
+                readonly = config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK);
+        else
+                readonly = true;
+
+        return S_IRUGO | (readonly ? 0 : S_IWUSR);
+}
+
 static const struct attribute_group jc42_group = {
         .attrs = jc42_attributes,
+        .is_visible = jc42_attribute_mode,
 };
 
 /* Return 0 if detection is successful, -ENODEV otherwise */
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index da5a2404cd3e..82bf65aa2968 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -1,5 +1,5 @@
 /*
- * k10temp.c - AMD Family 10h/11h processor hardware monitoring
+ * k10temp.c - AMD Family 10h/11h/12h/14h processor hardware monitoring
  *
  * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
  *
@@ -25,7 +25,7 @@
 #include <linux/pci.h>
 #include <asm/processor.h>
 
-MODULE_DESCRIPTION("AMD Family 10h/11h CPU core temperature monitor");
+MODULE_DESCRIPTION("AMD Family 10h/11h/12h/14h CPU core temperature monitor");
 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
 MODULE_LICENSE("GPL");
 
@@ -208,6 +208,7 @@ static void __devexit k10temp_remove(struct pci_dev *pdev)
 static const struct pci_device_id k10temp_id_table[] = {
         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
+        { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
         {}
 };
 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
diff --git a/drivers/hwmon/lm85.c b/drivers/hwmon/lm85.c
index 1e229847f37a..d2cc28660816 100644
--- a/drivers/hwmon/lm85.c
+++ b/drivers/hwmon/lm85.c
@@ -41,7 +41,7 @@ static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END };
 enum chips {
         any_chip, lm85b, lm85c,
         adm1027, adt7463, adt7468,
-        emc6d100, emc6d102
+        emc6d100, emc6d102, emc6d103
 };
 
 /* The LM85 registers */
@@ -90,6 +90,9 @@ enum chips {
 #define LM85_VERSTEP_EMC6D100_A0        0x60
 #define LM85_VERSTEP_EMC6D100_A1        0x61
 #define LM85_VERSTEP_EMC6D102           0x65
+#define LM85_VERSTEP_EMC6D103_A0        0x68
+#define LM85_VERSTEP_EMC6D103_A1        0x69
+#define LM85_VERSTEP_EMC6D103S          0x6A    /* Also known as EMC6D103:A2 */
 
 #define LM85_REG_CONFIG                 0x40
 
@@ -348,6 +351,7 @@ static const struct i2c_device_id lm85_id[] = {
         { "emc6d100", emc6d100 },
         { "emc6d101", emc6d100 },
         { "emc6d102", emc6d102 },
+        { "emc6d103", emc6d103 },
         { }
 };
 MODULE_DEVICE_TABLE(i2c, lm85_id);
@@ -1250,6 +1254,20 @@ static int lm85_detect(struct i2c_client *client, struct i2c_board_info *info)
                 case LM85_VERSTEP_EMC6D102:
                         type_name = "emc6d102";
                         break;
+                case LM85_VERSTEP_EMC6D103_A0:
+                case LM85_VERSTEP_EMC6D103_A1:
+                        type_name = "emc6d103";
+                        break;
+                /*
+                 * Registers apparently missing in EMC6D103S/EMC6D103:A2
+                 * compared to EMC6D103:A0, EMC6D103:A1, and EMC6D102
+                 * (according to the data sheets), but used unconditionally
+                 * in the driver: 62[5:7], 6D[0:7], and 6E[0:7].
+                 * So skip EMC6D103S for now.
+                case LM85_VERSTEP_EMC6D103S:
+                        type_name = "emc6d103s";
+                        break;
+                 */
                 }
         } else {
                 dev_dbg(&adapter->dev,
@@ -1283,6 +1301,7 @@ static int lm85_probe(struct i2c_client *client,
         case adt7468:
         case emc6d100:
         case emc6d102:
+        case emc6d103:
                 data->freq_map = adm1027_freq_map;
                 break;
         default:
@@ -1468,7 +1487,7 @@ static struct lm85_data *lm85_update_device(struct device *dev)
                         /* More alarm bits */
                         data->alarms |= lm85_read_value(client,
                                                 EMC6D100_REG_ALARM3) << 16;
-                } else if (data->type == emc6d102) {
+                } else if (data->type == emc6d102 || data->type == emc6d103) {
                         /* Have to read LSB bits after the MSB ones because
                            the reading of the MSB bits has frozen the
                            LSBs (backward from the ADM1027).