aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2009-03-14 10:23:03 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-03-23 09:38:26 -0400
commit345953cf9a44b19c98f8c0fe6ca7724202bcdb94 (patch)
treeebb9a63082aea202de6e711d639ce52894d0f533
parent9aac397525dc7945b1582a80cef5860516bca452 (diff)
powerpc/mm: Fix Respect _PAGE_COHERENT on classic ppc32 SW TLB load machines
Grant picked up the wrong version of "Respect _PAGE_COHERENT on classic ppc32 SW" (commit a4bd6a93c3f14691c8a29e53eb04dc734b27f0db) It was missing the code to actually deal with the fixup of _PAGE_COHERENT based on the CPU feature. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--arch/powerpc/kernel/head_32.S9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 7db2e42d97a2..d794a637e421 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -513,6 +513,9 @@ InstructionTLBMiss:
513 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ 513 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
514 ori r1,r1,0xe04 /* clear out reserved bits */ 514 ori r1,r1,0xe04 /* clear out reserved bits */
515 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ 515 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
516BEGIN_FTR_SECTION
517 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
518END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
516 mtspr SPRN_RPA,r1 519 mtspr SPRN_RPA,r1
517 mfspr r3,SPRN_IMISS 520 mfspr r3,SPRN_IMISS
518 tlbli r3 521 tlbli r3
@@ -587,6 +590,9 @@ DataLoadTLBMiss:
587 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ 590 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
588 ori r1,r1,0xe04 /* clear out reserved bits */ 591 ori r1,r1,0xe04 /* clear out reserved bits */
589 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ 592 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
593BEGIN_FTR_SECTION
594 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
595END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
590 mtspr SPRN_RPA,r1 596 mtspr SPRN_RPA,r1
591 mfspr r3,SPRN_DMISS 597 mfspr r3,SPRN_DMISS
592 tlbld r3 598 tlbld r3
@@ -655,6 +661,9 @@ DataStoreTLBMiss:
655 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ 661 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
656 li r1,0xe05 /* clear out reserved bits & PP lsb */ 662 li r1,0xe05 /* clear out reserved bits & PP lsb */
657 andc r1,r3,r1 /* PP = user? 2: 0 */ 663 andc r1,r3,r1 /* PP = user? 2: 0 */
664BEGIN_FTR_SECTION
665 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
666END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
658 mtspr SPRN_RPA,r1 667 mtspr SPRN_RPA,r1
659 mfspr r3,SPRN_DMISS 668 mfspr r3,SPRN_DMISS
660 tlbld r3 669 tlbld r3