aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJarod Wilson <jwilson@redhat.com>2008-03-28 10:02:50 -0400
committerStefan Richter <stefanr@s5r6.in-berlin.de>2008-04-18 11:55:34 -0400
commit022147242ff6e4b7ab770f00716063f48c088391 (patch)
treea59646ee968d029550fcb5d99ab2a9885a0f9377
parent130d5496e2c9104dcabdaa5c19cd941770e20edc (diff)
firewire: fw-ohci: make sure HCControl register LPS bit is set
I've now witnessed multiple occasions where one of my controllers (a very poorly working JMicron PCIe card) fails to get its registers properly set up in ohci_enable(), apparently due to an occasionally very slow to initiate SClk. The easy fix for this problem is to add a tiny while loop to try again a time or three after initially enabling LPS before we move on (or give up). Of course, the card still isn't fully functional yet, but this gets it at least one tiny step closer... Signed-off-by: Jarod Wilson <jwilson@redhat.com> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
-rw-r--r--drivers/firewire/fw-ohci.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/firewire/fw-ohci.c b/drivers/firewire/fw-ohci.c
index 973e762efc24..e88260b67611 100644
--- a/drivers/firewire/fw-ohci.c
+++ b/drivers/firewire/fw-ohci.c
@@ -1390,6 +1390,8 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1390{ 1390{
1391 struct fw_ohci *ohci = fw_ohci(card); 1391 struct fw_ohci *ohci = fw_ohci(card);
1392 struct pci_dev *dev = to_pci_dev(card->device); 1392 struct pci_dev *dev = to_pci_dev(card->device);
1393 u32 lps;
1394 int i;
1393 1395
1394 if (software_reset(ohci)) { 1396 if (software_reset(ohci)) {
1395 fw_error("Failed to reset ohci card.\n"); 1397 fw_error("Failed to reset ohci card.\n");
@@ -1401,13 +1403,24 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1401 * most of the registers. In fact, on some cards (ALI M5251), 1403 * most of the registers. In fact, on some cards (ALI M5251),
1402 * accessing registers in the SClk domain without LPS enabled 1404 * accessing registers in the SClk domain without LPS enabled
1403 * will lock up the machine. Wait 50msec to make sure we have 1405 * will lock up the machine. Wait 50msec to make sure we have
1404 * full link enabled. 1406 * full link enabled. However, with some cards (well, at least
1407 * a JMicron PCIe card), we have to try again sometimes.
1405 */ 1408 */
1406 reg_write(ohci, OHCI1394_HCControlSet, 1409 reg_write(ohci, OHCI1394_HCControlSet,
1407 OHCI1394_HCControl_LPS | 1410 OHCI1394_HCControl_LPS |
1408 OHCI1394_HCControl_postedWriteEnable); 1411 OHCI1394_HCControl_postedWriteEnable);
1409 flush_writes(ohci); 1412 flush_writes(ohci);
1410 msleep(50); 1413
1414 for (lps = 0, i = 0; !lps && i < 3; i++) {
1415 msleep(50);
1416 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1417 OHCI1394_HCControl_LPS;
1418 }
1419
1420 if (!lps) {
1421 fw_error("Failed to set Link Power Status\n");
1422 return -EIO;
1423 }
1411 1424
1412 reg_write(ohci, OHCI1394_HCControlClear, 1425 reg_write(ohci, OHCI1394_HCControlClear,
1413 OHCI1394_HCControl_noByteSwapData); 1426 OHCI1394_HCControl_noByteSwapData);