diff options
author | Francisco Jerez <currojerez@riseup.net> | 2010-10-10 00:01:08 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-11-17 23:38:29 -0500 |
commit | f13b32630dda7e583a84a8c535880cff7e4a9bdd (patch) | |
tree | a527aa3fd21cb58aaa95e0d70566acb14ea0586f | |
parent | 1397b42b5a2e5b3b982078c89f3594c123e3c2b3 (diff) |
drm/nouveau: Expose some BO usage flags to userspace.
This will be needed for Z compression and to take smarter placement
decisions.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Acked-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bo.c | 15 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_gem.c | 36 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_state.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_crtc.c | 4 | ||||
-rw-r--r-- | include/drm/nouveau_drm.h | 7 |
6 files changed, 46 insertions, 22 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 80353e2b8409..f55dd9145b7c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c | |||
@@ -144,7 +144,8 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, | |||
144 | nvbo->tile_mode = tile_mode; | 144 | nvbo->tile_mode = tile_mode; |
145 | nvbo->tile_flags = tile_flags; | 145 | nvbo->tile_flags = tile_flags; |
146 | 146 | ||
147 | nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size); | 147 | nouveau_bo_fixup_align(dev, tile_mode, nouveau_bo_tile_layout(nvbo), |
148 | &align, &size); | ||
148 | align >>= PAGE_SHIFT; | 149 | align >>= PAGE_SHIFT; |
149 | 150 | ||
150 | nouveau_bo_placement_set(nvbo, flags, 0); | 151 | nouveau_bo_placement_set(nvbo, flags, 0); |
@@ -525,7 +526,8 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |||
525 | stride = 16 * 4; | 526 | stride = 16 * 4; |
526 | height = amount / stride; | 527 | height = amount / stride; |
527 | 528 | ||
528 | if (new_mem->mem_type == TTM_PL_VRAM && nvbo->tile_flags) { | 529 | if (new_mem->mem_type == TTM_PL_VRAM && |
530 | nouveau_bo_tile_layout(nvbo)) { | ||
529 | ret = RING_SPACE(chan, 8); | 531 | ret = RING_SPACE(chan, 8); |
530 | if (ret) | 532 | if (ret) |
531 | return ret; | 533 | return ret; |
@@ -546,7 +548,8 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |||
546 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); | 548 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); |
547 | OUT_RING (chan, 1); | 549 | OUT_RING (chan, 1); |
548 | } | 550 | } |
549 | if (old_mem->mem_type == TTM_PL_VRAM && nvbo->tile_flags) { | 551 | if (old_mem->mem_type == TTM_PL_VRAM && |
552 | nouveau_bo_tile_layout(nvbo)) { | ||
550 | ret = RING_SPACE(chan, 8); | 553 | ret = RING_SPACE(chan, 8); |
551 | if (ret) | 554 | if (ret) |
552 | return ret; | 555 | return ret; |
@@ -753,7 +756,8 @@ nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, | |||
753 | if (dev_priv->card_type == NV_50) { | 756 | if (dev_priv->card_type == NV_50) { |
754 | ret = nv50_mem_vm_bind_linear(dev, | 757 | ret = nv50_mem_vm_bind_linear(dev, |
755 | offset + dev_priv->vm_vram_base, | 758 | offset + dev_priv->vm_vram_base, |
756 | new_mem->size, nvbo->tile_flags, | 759 | new_mem->size, |
760 | nouveau_bo_tile_layout(nvbo), | ||
757 | offset); | 761 | offset); |
758 | if (ret) | 762 | if (ret) |
759 | return ret; | 763 | return ret; |
@@ -894,7 +898,8 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |||
894 | * nothing to do here. | 898 | * nothing to do here. |
895 | */ | 899 | */ |
896 | if (bo->mem.mem_type != TTM_PL_VRAM) { | 900 | if (bo->mem.mem_type != TTM_PL_VRAM) { |
897 | if (dev_priv->card_type < NV_50 || !nvbo->tile_flags) | 901 | if (dev_priv->card_type < NV_50 || |
902 | !nouveau_bo_tile_layout(nvbo)) | ||
898 | return 0; | 903 | return 0; |
899 | } | 904 | } |
900 | 905 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 135594c44167..60a54fae90c1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -100,6 +100,9 @@ struct nouveau_bo { | |||
100 | int pin_refcnt; | 100 | int pin_refcnt; |
101 | }; | 101 | }; |
102 | 102 | ||
103 | #define nouveau_bo_tile_layout(nvbo) \ | ||
104 | ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) | ||
105 | |||
103 | static inline struct nouveau_bo * | 106 | static inline struct nouveau_bo * |
104 | nouveau_bo(struct ttm_buffer_object *bo) | 107 | nouveau_bo(struct ttm_buffer_object *bo) |
105 | { | 108 | { |
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 5c4c929d7f74..9a1fdcf400c2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c | |||
@@ -107,23 +107,29 @@ nouveau_gem_info(struct drm_gem_object *gem, struct drm_nouveau_gem_info *rep) | |||
107 | } | 107 | } |
108 | 108 | ||
109 | static bool | 109 | static bool |
110 | nouveau_gem_tile_flags_valid(struct drm_device *dev, uint32_t tile_flags) { | 110 | nouveau_gem_tile_flags_valid(struct drm_device *dev, uint32_t tile_flags) |
111 | switch (tile_flags) { | 111 | { |
112 | case 0x0000: | 112 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
113 | case 0x1800: | 113 | |
114 | case 0x2800: | 114 | if (dev_priv->card_type >= NV_50) { |
115 | case 0x4800: | 115 | switch (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) { |
116 | case 0x7000: | 116 | case 0x0000: |
117 | case 0x7400: | 117 | case 0x1800: |
118 | case 0x7a00: | 118 | case 0x2800: |
119 | case 0xe000: | 119 | case 0x4800: |
120 | break; | 120 | case 0x7000: |
121 | default: | 121 | case 0x7400: |
122 | NV_ERROR(dev, "bad page flags: 0x%08x\n", tile_flags); | 122 | case 0x7a00: |
123 | return false; | 123 | case 0xe000: |
124 | return true; | ||
125 | } | ||
126 | } else { | ||
127 | if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)) | ||
128 | return true; | ||
124 | } | 129 | } |
125 | 130 | ||
126 | return true; | 131 | NV_ERROR(dev, "bad page flags: 0x%08x\n", tile_flags); |
132 | return false; | ||
127 | } | 133 | } |
128 | 134 | ||
129 | int | 135 | int |
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index af2bec36d91b..ea3452194cd6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c | |||
@@ -1041,6 +1041,9 @@ int nouveau_ioctl_getparam(struct drm_device *dev, void *data, | |||
1041 | case NOUVEAU_GETPARAM_PTIMER_TIME: | 1041 | case NOUVEAU_GETPARAM_PTIMER_TIME: |
1042 | getparam->value = dev_priv->engine.timer.read(dev); | 1042 | getparam->value = dev_priv->engine.timer.read(dev); |
1043 | break; | 1043 | break; |
1044 | case NOUVEAU_GETPARAM_HAS_BO_USAGE: | ||
1045 | getparam->value = 1; | ||
1046 | break; | ||
1044 | case NOUVEAU_GETPARAM_GRAPH_UNITS: | 1047 | case NOUVEAU_GETPARAM_GRAPH_UNITS: |
1045 | /* NV40 and NV50 versions are quite different, but register | 1048 | /* NV40 and NV50 versions are quite different, but register |
1046 | * address is the same. User is supposed to know the card | 1049 | * address is the same. User is supposed to know the card |
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c index 16380d52cd88..56476d0c6de8 100644 --- a/drivers/gpu/drm/nouveau/nv50_crtc.c +++ b/drivers/gpu/drm/nouveau/nv50_crtc.c | |||
@@ -546,7 +546,7 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, | |||
546 | } | 546 | } |
547 | 547 | ||
548 | nv_crtc->fb.offset = fb->nvbo->bo.offset - dev_priv->vm_vram_base; | 548 | nv_crtc->fb.offset = fb->nvbo->bo.offset - dev_priv->vm_vram_base; |
549 | nv_crtc->fb.tile_flags = fb->nvbo->tile_flags; | 549 | nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo); |
550 | nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8; | 550 | nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8; |
551 | if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) { | 551 | if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) { |
552 | ret = RING_SPACE(evo, 2); | 552 | ret = RING_SPACE(evo, 2); |
@@ -578,7 +578,7 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, | |||
578 | fb->nvbo->tile_mode); | 578 | fb->nvbo->tile_mode); |
579 | } | 579 | } |
580 | if (dev_priv->chipset == 0x50) | 580 | if (dev_priv->chipset == 0x50) |
581 | OUT_RING(evo, (fb->nvbo->tile_flags << 8) | format); | 581 | OUT_RING(evo, (nv_crtc->fb.tile_flags << 8) | format); |
582 | else | 582 | else |
583 | OUT_RING(evo, format); | 583 | OUT_RING(evo, format); |
584 | 584 | ||
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h index 01a714119506..bc5590b1a1ac 100644 --- a/include/drm/nouveau_drm.h +++ b/include/drm/nouveau_drm.h | |||
@@ -80,6 +80,7 @@ struct drm_nouveau_gpuobj_free { | |||
80 | #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 | 80 | #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 |
81 | #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 | 81 | #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 |
82 | #define NOUVEAU_GETPARAM_PTIMER_TIME 14 | 82 | #define NOUVEAU_GETPARAM_PTIMER_TIME 14 |
83 | #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 | ||
83 | struct drm_nouveau_getparam { | 84 | struct drm_nouveau_getparam { |
84 | uint64_t param; | 85 | uint64_t param; |
85 | uint64_t value; | 86 | uint64_t value; |
@@ -95,6 +96,12 @@ struct drm_nouveau_setparam { | |||
95 | #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) | 96 | #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) |
96 | #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) | 97 | #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) |
97 | 98 | ||
99 | #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 | ||
100 | #define NOUVEAU_GEM_TILE_16BPP 0x00000001 | ||
101 | #define NOUVEAU_GEM_TILE_32BPP 0x00000002 | ||
102 | #define NOUVEAU_GEM_TILE_ZETA 0x00000004 | ||
103 | #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 | ||
104 | |||
98 | struct drm_nouveau_gem_info { | 105 | struct drm_nouveau_gem_info { |
99 | uint32_t handle; | 106 | uint32_t handle; |
100 | uint32_t domain; | 107 | uint32_t domain; |