diff options
author | Maciej Patelczyk <maciej.patelczyk@intel.com> | 2011-04-27 13:50:50 -0400 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2011-07-03 07:00:38 -0400 |
commit | e76d80579c2b5b4ecac107b83c22ceeb9e23bd1b (patch) | |
tree | bdd8f946c25d9aa087d07359e068c1ee0750e649 | |
parent | d2d61433a85f814c7bc0b20993bb39e97f2dde76 (diff) |
isci: Implement SCU AFE recipe 10.
Updated SCU AFE initialization values accordingly to the recipe 10.
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
-rw-r--r-- | drivers/scsi/isci/core/scic_sds_controller.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/scsi/isci/core/scic_sds_controller.c b/drivers/scsi/isci/core/scic_sds_controller.c index c684d9ec8c97..5e8dea57b5ef 100644 --- a/drivers/scsi/isci/core/scic_sds_controller.c +++ b/drivers/scsi/isci/core/scic_sds_controller.c | |||
@@ -442,11 +442,20 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s | |||
442 | writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0); | 442 | writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0); |
443 | udelay(AFE_REGISTER_WRITE_DELAY); | 443 | udelay(AFE_REGISTER_WRITE_DELAY); |
444 | 444 | ||
445 | if (is_b0()) { | ||
446 | /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement | ||
447 | * Timer, PM Stagger Timer */ | ||
448 | writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2); | ||
449 | udelay(AFE_REGISTER_WRITE_DELAY); | ||
450 | } | ||
451 | |||
445 | /* Configure bias currents to normal */ | 452 | /* Configure bias currents to normal */ |
446 | if (is_a0()) | 453 | if (is_a0()) |
447 | writel(0x00005500, &scic->scu_registers->afe.afe_bias_control); | 454 | writel(0x00005500, &scic->scu_registers->afe.afe_bias_control); |
448 | else | 455 | else if (is_a2()) |
449 | writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control); | 456 | writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control); |
457 | else if (is_b0()) | ||
458 | writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control); | ||
450 | 459 | ||
451 | udelay(AFE_REGISTER_WRITE_DELAY); | 460 | udelay(AFE_REGISTER_WRITE_DELAY); |
452 | 461 | ||
@@ -464,7 +473,7 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s | |||
464 | udelay(AFE_REGISTER_WRITE_DELAY); | 473 | udelay(AFE_REGISTER_WRITE_DELAY); |
465 | } while ((afe_status & 0x00001000) == 0); | 474 | } while ((afe_status & 0x00001000) == 0); |
466 | 475 | ||
467 | if (is_b0()) { | 476 | if (is_a0() || is_a2()) { |
468 | /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */ | 477 | /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */ |
469 | writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0); | 478 | writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0); |
470 | udelay(AFE_REGISTER_WRITE_DELAY); | 479 | udelay(AFE_REGISTER_WRITE_DELAY); |