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authorLinus Torvalds <torvalds@linux-foundation.org>2008-10-11 12:19:02 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-10-11 12:19:02 -0400
commit835a1c092432b3293ba6c4dec45ee6869c6f61fd (patch)
treea48582e4e4de3a8924b700c5ccaae78cd299cd73
parentd3570a5a7b8d0604fa012129f92637dc1534f62c (diff)
parent9609e74093abd9f61fb1d20a8915a8ea87c77d5a (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (49 commits) MIPS: RB532: provide GPIO_BUILTIN_NR and irq_to_gpio/gpio_to_irq MIPS: Move ptrace prototypes to ptrace.h MIPS: Ptrace support for HARDWARE_WATCHPOINTS MIPS: Scheduler support for HARDWARE_WATCHPOINTS. MIPS: Watch exception handling for HARDWARE_WATCHPOINTS. MIPS: Probe watch registers and report configuration. MIPS: Add HARDWARE_WATCHPOINTS definitions and support code. MIPS: Add HARDWARE_WATCHPOINTS configure option. MIPS: Replace use of <asm-generic/uaccess.h> with native implementations. MIPS: TXx9: Add TX4939 ATA support (v2) MIPS: Rewrite spinlocks to ticket locks. MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment. MIPS: IP checksums: Remove unncessary .set pseudos MIPS: IP checksums: Remove unncessary folding of sum to 16 bit. MIPS: Move headfiles to new location below arch/mips/include MIPS: Alchemy: rename directory MIPS: Optimize get_user and put_user for 64-bit MIPS: TXx9: Implement prom_free_prom_memory MIPS: TXx9: Add RBTX4939 board support MIPS: TXx9: Add TX4939 SoC support ...
Diffstat
-rw-r--r--Documentation/kernel-parameters.txt4
-rw-r--r--arch/mips/Kconfig16
-rw-r--r--arch/mips/Makefile122
-rw-r--r--arch/mips/alchemy/Kconfig (renamed from arch/mips/au1000/Kconfig)0
-rw-r--r--arch/mips/alchemy/common/Makefile (renamed from arch/mips/au1000/common/Makefile)0
-rw-r--r--arch/mips/alchemy/common/au1xxx_irqmap.c (renamed from arch/mips/au1000/common/au1xxx_irqmap.c)0
-rw-r--r--arch/mips/alchemy/common/clocks.c (renamed from arch/mips/au1000/common/clocks.c)0
-rw-r--r--arch/mips/alchemy/common/cputable.c (renamed from arch/mips/au1000/common/cputable.c)0
-rw-r--r--arch/mips/alchemy/common/dbdma.c (renamed from arch/mips/au1000/common/dbdma.c)0
-rw-r--r--arch/mips/alchemy/common/dma.c (renamed from arch/mips/au1000/common/dma.c)0
-rw-r--r--arch/mips/alchemy/common/gpio.c (renamed from arch/mips/au1000/common/gpio.c)0
-rw-r--r--arch/mips/alchemy/common/irq.c (renamed from arch/mips/au1000/common/irq.c)0
-rw-r--r--arch/mips/alchemy/common/pci.c (renamed from arch/mips/au1000/common/pci.c)0
-rw-r--r--arch/mips/alchemy/common/platform.c (renamed from arch/mips/au1000/common/platform.c)0
-rw-r--r--arch/mips/alchemy/common/power.c (renamed from arch/mips/au1000/common/power.c)0
-rw-r--r--arch/mips/alchemy/common/prom.c (renamed from arch/mips/au1000/common/prom.c)0
-rw-r--r--arch/mips/alchemy/common/puts.c (renamed from arch/mips/au1000/common/puts.c)0
-rw-r--r--arch/mips/alchemy/common/reset.c (renamed from arch/mips/au1000/common/reset.c)0
-rw-r--r--arch/mips/alchemy/common/setup.c (renamed from arch/mips/au1000/common/setup.c)0
-rw-r--r--arch/mips/alchemy/common/sleeper.S (renamed from arch/mips/au1000/common/sleeper.S)10
-rw-r--r--arch/mips/alchemy/common/time.c (renamed from arch/mips/au1000/common/time.c)0
-rw-r--r--arch/mips/alchemy/db1x00/Makefile (renamed from arch/mips/au1000/db1x00/Makefile)0
-rw-r--r--arch/mips/alchemy/db1x00/board_setup.c (renamed from arch/mips/au1000/db1x00/board_setup.c)0
-rw-r--r--arch/mips/alchemy/db1x00/init.c (renamed from arch/mips/au1000/db1x00/init.c)0
-rw-r--r--arch/mips/alchemy/db1x00/irqmap.c (renamed from arch/mips/au1000/db1x00/irqmap.c)0
-rw-r--r--arch/mips/alchemy/mtx-1/Makefile (renamed from arch/mips/au1000/mtx-1/Makefile)0
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c (renamed from arch/mips/au1000/mtx-1/board_setup.c)0
-rw-r--r--arch/mips/alchemy/mtx-1/init.c (renamed from arch/mips/au1000/mtx-1/init.c)0
-rw-r--r--arch/mips/alchemy/mtx-1/irqmap.c (renamed from arch/mips/au1000/mtx-1/irqmap.c)0
-rw-r--r--arch/mips/alchemy/mtx-1/platform.c (renamed from arch/mips/au1000/mtx-1/platform.c)0
-rw-r--r--arch/mips/alchemy/pb1000/Makefile (renamed from arch/mips/au1000/pb1000/Makefile)0
-rw-r--r--arch/mips/alchemy/pb1000/board_setup.c (renamed from arch/mips/au1000/pb1000/board_setup.c)0
-rw-r--r--arch/mips/alchemy/pb1000/init.c (renamed from arch/mips/au1000/pb1000/init.c)0
-rw-r--r--arch/mips/alchemy/pb1000/irqmap.c (renamed from arch/mips/au1000/pb1000/irqmap.c)0
-rw-r--r--arch/mips/alchemy/pb1100/Makefile (renamed from arch/mips/au1000/pb1100/Makefile)0
-rw-r--r--arch/mips/alchemy/pb1100/board_setup.c (renamed from arch/mips/au1000/pb1100/board_setup.c)0
-rw-r--r--arch/mips/alchemy/pb1100/init.c (renamed from arch/mips/au1000/pb1100/init.c)0
-rw-r--r--arch/mips/alchemy/pb1100/irqmap.c (renamed from arch/mips/au1000/pb1100/irqmap.c)0
-rw-r--r--arch/mips/alchemy/pb1200/Makefile (renamed from arch/mips/au1000/pb1200/Makefile)0
-rw-r--r--arch/mips/alchemy/pb1200/board_setup.c (renamed from arch/mips/au1000/pb1200/board_setup.c)0
-rw-r--r--arch/mips/alchemy/pb1200/init.c (renamed from arch/mips/au1000/pb1200/init.c)0
-rw-r--r--arch/mips/alchemy/pb1200/irqmap.c (renamed from arch/mips/au1000/pb1200/irqmap.c)0
-rw-r--r--arch/mips/alchemy/pb1200/platform.c (renamed from arch/mips/au1000/pb1200/platform.c)0
-rw-r--r--arch/mips/alchemy/pb1500/Makefile (renamed from arch/mips/au1000/pb1500/Makefile)0
-rw-r--r--arch/mips/alchemy/pb1500/board_setup.c (renamed from arch/mips/au1000/pb1500/board_setup.c)0
-rw-r--r--arch/mips/alchemy/pb1500/init.c (renamed from arch/mips/au1000/pb1500/init.c)0
-rw-r--r--arch/mips/alchemy/pb1500/irqmap.c (renamed from arch/mips/au1000/pb1500/irqmap.c)0
-rw-r--r--arch/mips/alchemy/pb1550/Makefile (renamed from arch/mips/au1000/pb1550/Makefile)0
-rw-r--r--arch/mips/alchemy/pb1550/board_setup.c (renamed from arch/mips/au1000/pb1550/board_setup.c)0
-rw-r--r--arch/mips/alchemy/pb1550/init.c (renamed from arch/mips/au1000/pb1550/init.c)0
-rw-r--r--arch/mips/alchemy/pb1550/irqmap.c (renamed from arch/mips/au1000/pb1550/irqmap.c)0
-rw-r--r--arch/mips/alchemy/xxs1500/Makefile (renamed from arch/mips/au1000/xxs1500/Makefile)0
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c (renamed from arch/mips/au1000/xxs1500/board_setup.c)0
-rw-r--r--arch/mips/alchemy/xxs1500/init.c (renamed from arch/mips/au1000/xxs1500/init.c)0
-rw-r--r--arch/mips/alchemy/xxs1500/irqmap.c (renamed from arch/mips/au1000/xxs1500/irqmap.c)0
-rw-r--r--arch/mips/include/asm/Kbuild (renamed from include/asm-mips/Kbuild)0
-rw-r--r--arch/mips/include/asm/a.out.h (renamed from include/asm-mips/a.out.h)0
-rw-r--r--arch/mips/include/asm/abi.h (renamed from include/asm-mips/abi.h)0
-rw-r--r--arch/mips/include/asm/addrspace.h (renamed from include/asm-mips/addrspace.h)0
-rw-r--r--arch/mips/include/asm/asm.h (renamed from include/asm-mips/asm.h)0
-rw-r--r--arch/mips/include/asm/asmmacro-32.h (renamed from include/asm-mips/asmmacro-32.h)0
-rw-r--r--arch/mips/include/asm/asmmacro-64.h (renamed from include/asm-mips/asmmacro-64.h)0
-rw-r--r--arch/mips/include/asm/asmmacro.h (renamed from include/asm-mips/asmmacro.h)0
-rw-r--r--arch/mips/include/asm/atomic.h (renamed from include/asm-mips/atomic.h)0
-rw-r--r--arch/mips/include/asm/auxvec.h (renamed from include/asm-mips/auxvec.h)0
-rw-r--r--arch/mips/include/asm/barrier.h (renamed from include/asm-mips/barrier.h)0
-rw-r--r--arch/mips/include/asm/bcache.h (renamed from include/asm-mips/bcache.h)0
-rw-r--r--arch/mips/include/asm/bitops.h (renamed from include/asm-mips/bitops.h)0
-rw-r--r--arch/mips/include/asm/bootinfo.h (renamed from include/asm-mips/bootinfo.h)0
-rw-r--r--arch/mips/include/asm/branch.h (renamed from include/asm-mips/branch.h)0
-rw-r--r--arch/mips/include/asm/break.h (renamed from include/asm-mips/break.h)0
-rw-r--r--arch/mips/include/asm/bug.h (renamed from include/asm-mips/bug.h)0
-rw-r--r--arch/mips/include/asm/bugs.h (renamed from include/asm-mips/bugs.h)0
-rw-r--r--arch/mips/include/asm/byteorder.h (renamed from include/asm-mips/byteorder.h)0
-rw-r--r--arch/mips/include/asm/cache.h (renamed from include/asm-mips/cache.h)0
-rw-r--r--arch/mips/include/asm/cachectl.h (renamed from include/asm-mips/cachectl.h)0
-rw-r--r--arch/mips/include/asm/cacheflush.h (renamed from include/asm-mips/cacheflush.h)0
-rw-r--r--arch/mips/include/asm/cacheops.h (renamed from include/asm-mips/cacheops.h)0
-rw-r--r--arch/mips/include/asm/checksum.h (renamed from include/asm-mips/checksum.h)0
-rw-r--r--arch/mips/include/asm/cmp.h (renamed from include/asm-mips/cmp.h)0
-rw-r--r--arch/mips/include/asm/cmpxchg.h (renamed from include/asm-mips/cmpxchg.h)0
-rw-r--r--arch/mips/include/asm/compat-signal.h (renamed from include/asm-mips/compat-signal.h)0
-rw-r--r--arch/mips/include/asm/compat.h (renamed from include/asm-mips/compat.h)0
-rw-r--r--arch/mips/include/asm/compiler.h (renamed from include/asm-mips/compiler.h)0
-rw-r--r--arch/mips/include/asm/cpu-features.h (renamed from include/asm-mips/cpu-features.h)0
-rw-r--r--arch/mips/include/asm/cpu-info.h (renamed from include/asm-mips/cpu-info.h)6
-rw-r--r--arch/mips/include/asm/cpu.h (renamed from include/asm-mips/cpu.h)0
-rw-r--r--arch/mips/include/asm/cputime.h (renamed from include/asm-mips/cputime.h)0
-rw-r--r--arch/mips/include/asm/current.h (renamed from include/asm-mips/current.h)0
-rw-r--r--arch/mips/include/asm/debug.h (renamed from include/asm-mips/debug.h)0
-rw-r--r--arch/mips/include/asm/dec/ecc.h (renamed from include/asm-mips/dec/ecc.h)0
-rw-r--r--arch/mips/include/asm/dec/interrupts.h (renamed from include/asm-mips/dec/interrupts.h)0
-rw-r--r--arch/mips/include/asm/dec/ioasic.h (renamed from include/asm-mips/dec/ioasic.h)0
-rw-r--r--arch/mips/include/asm/dec/ioasic_addrs.h (renamed from include/asm-mips/dec/ioasic_addrs.h)0
-rw-r--r--arch/mips/include/asm/dec/ioasic_ints.h (renamed from include/asm-mips/dec/ioasic_ints.h)0
-rw-r--r--arch/mips/include/asm/dec/kn01.h (renamed from include/asm-mips/dec/kn01.h)0
-rw-r--r--arch/mips/include/asm/dec/kn02.h (renamed from include/asm-mips/dec/kn02.h)0
-rw-r--r--arch/mips/include/asm/dec/kn02ba.h (renamed from include/asm-mips/dec/kn02ba.h)0
-rw-r--r--arch/mips/include/asm/dec/kn02ca.h (renamed from include/asm-mips/dec/kn02ca.h)0
-rw-r--r--arch/mips/include/asm/dec/kn02xa.h (renamed from include/asm-mips/dec/kn02xa.h)0
-rw-r--r--arch/mips/include/asm/dec/kn03.h (renamed from include/asm-mips/dec/kn03.h)0
-rw-r--r--arch/mips/include/asm/dec/kn05.h (renamed from include/asm-mips/dec/kn05.h)0
-rw-r--r--arch/mips/include/asm/dec/kn230.h (renamed from include/asm-mips/dec/kn230.h)0
-rw-r--r--arch/mips/include/asm/dec/machtype.h (renamed from include/asm-mips/dec/machtype.h)0
-rw-r--r--arch/mips/include/asm/dec/prom.h (renamed from include/asm-mips/dec/prom.h)0
-rw-r--r--arch/mips/include/asm/dec/system.h (renamed from include/asm-mips/dec/system.h)0
-rw-r--r--arch/mips/include/asm/delay.h (renamed from include/asm-mips/delay.h)0
-rw-r--r--arch/mips/include/asm/device.h (renamed from include/asm-mips/device.h)0
-rw-r--r--arch/mips/include/asm/div64.h (renamed from include/asm-mips/div64.h)0
-rw-r--r--arch/mips/include/asm/dma-mapping.h (renamed from include/asm-mips/dma-mapping.h)0
-rw-r--r--arch/mips/include/asm/dma.h (renamed from include/asm-mips/dma.h)0
-rw-r--r--arch/mips/include/asm/ds1286.h (renamed from include/asm-mips/ds1286.h)0
-rw-r--r--arch/mips/include/asm/ds1287.h (renamed from include/asm-mips/ds1287.h)0
-rw-r--r--arch/mips/include/asm/dsp.h (renamed from include/asm-mips/dsp.h)0
-rw-r--r--arch/mips/include/asm/edac.h (renamed from include/asm-mips/edac.h)0
-rw-r--r--arch/mips/include/asm/elf.h (renamed from include/asm-mips/elf.h)0
-rw-r--r--arch/mips/include/asm/emergency-restart.h (renamed from include/asm-mips/emergency-restart.h)0
-rw-r--r--arch/mips/include/asm/emma2rh/emma2rh.h (renamed from include/asm-mips/emma2rh/emma2rh.h)0
-rw-r--r--arch/mips/include/asm/emma2rh/markeins.h (renamed from include/asm-mips/emma2rh/markeins.h)0
-rw-r--r--arch/mips/include/asm/errno.h (renamed from include/asm-mips/errno.h)0
-rw-r--r--arch/mips/include/asm/fb.h (renamed from include/asm-mips/fb.h)0
-rw-r--r--arch/mips/include/asm/fcntl.h (renamed from include/asm-mips/fcntl.h)0
-rw-r--r--arch/mips/include/asm/fixmap.h (renamed from include/asm-mips/fixmap.h)0
-rw-r--r--arch/mips/include/asm/floppy.h (renamed from include/asm-mips/floppy.h)0
-rw-r--r--arch/mips/include/asm/fpregdef.h (renamed from include/asm-mips/fpregdef.h)0
-rw-r--r--arch/mips/include/asm/fpu.h (renamed from include/asm-mips/fpu.h)0
-rw-r--r--arch/mips/include/asm/fpu_emulator.h (renamed from include/asm-mips/fpu_emulator.h)0
-rw-r--r--arch/mips/include/asm/futex.h (renamed from include/asm-mips/futex.h)0
-rw-r--r--arch/mips/include/asm/fw/arc/hinv.h (renamed from include/asm-mips/fw/arc/hinv.h)0
-rw-r--r--arch/mips/include/asm/fw/arc/types.h (renamed from include/asm-mips/fw/arc/types.h)0
-rw-r--r--arch/mips/include/asm/fw/cfe/cfe_api.h (renamed from include/asm-mips/fw/cfe/cfe_api.h)0
-rw-r--r--arch/mips/include/asm/fw/cfe/cfe_error.h (renamed from include/asm-mips/fw/cfe/cfe_error.h)0
-rw-r--r--arch/mips/include/asm/gcmpregs.h (renamed from include/asm-mips/gcmpregs.h)0
-rw-r--r--arch/mips/include/asm/gic.h (renamed from include/asm-mips/gic.h)0
-rw-r--r--arch/mips/include/asm/gpio.h (renamed from include/asm-mips/gpio.h)0
-rw-r--r--arch/mips/include/asm/gt64120.h (renamed from include/asm-mips/gt64120.h)0
-rw-r--r--arch/mips/include/asm/hardirq.h (renamed from include/asm-mips/hardirq.h)0
-rw-r--r--arch/mips/include/asm/hazards.h (renamed from include/asm-mips/hazards.h)0
-rw-r--r--arch/mips/include/asm/highmem.h (renamed from include/asm-mips/highmem.h)0
-rw-r--r--arch/mips/include/asm/hw_irq.h (renamed from include/asm-mips/hw_irq.h)0
-rw-r--r--arch/mips/include/asm/i8253.h (renamed from include/asm-mips/i8253.h)0
-rw-r--r--arch/mips/include/asm/i8259.h (renamed from include/asm-mips/i8259.h)0
-rw-r--r--arch/mips/include/asm/ide.h (renamed from include/asm-mips/ide.h)0
-rw-r--r--arch/mips/include/asm/inst.h (renamed from include/asm-mips/inst.h)0
-rw-r--r--arch/mips/include/asm/io.h (renamed from include/asm-mips/io.h)0
-rw-r--r--arch/mips/include/asm/ioctl.h (renamed from include/asm-mips/ioctl.h)0
-rw-r--r--arch/mips/include/asm/ioctls.h (renamed from include/asm-mips/ioctls.h)0
-rw-r--r--arch/mips/include/asm/ip32/crime.h (renamed from include/asm-mips/ip32/crime.h)0
-rw-r--r--arch/mips/include/asm/ip32/ip32_ints.h (renamed from include/asm-mips/ip32/ip32_ints.h)0
-rw-r--r--arch/mips/include/asm/ip32/mace.h (renamed from include/asm-mips/ip32/mace.h)0
-rw-r--r--arch/mips/include/asm/ipcbuf.h (renamed from include/asm-mips/ipcbuf.h)0
-rw-r--r--arch/mips/include/asm/irq.h (renamed from include/asm-mips/irq.h)0
-rw-r--r--arch/mips/include/asm/irq_cpu.h (renamed from include/asm-mips/irq_cpu.h)0
-rw-r--r--arch/mips/include/asm/irq_gt641xx.h (renamed from include/asm-mips/irq_gt641xx.h)0
-rw-r--r--arch/mips/include/asm/irq_regs.h (renamed from include/asm-mips/irq_regs.h)0
-rw-r--r--arch/mips/include/asm/irqflags.h (renamed from include/asm-mips/irqflags.h)0
-rw-r--r--arch/mips/include/asm/isadep.h (renamed from include/asm-mips/isadep.h)0
-rw-r--r--arch/mips/include/asm/jazz.h (renamed from include/asm-mips/jazz.h)0
-rw-r--r--arch/mips/include/asm/jazzdma.h (renamed from include/asm-mips/jazzdma.h)0
-rw-r--r--arch/mips/include/asm/kdebug.h (renamed from include/asm-mips/kdebug.h)0
-rw-r--r--arch/mips/include/asm/kexec.h (renamed from include/asm-mips/kexec.h)0
-rw-r--r--arch/mips/include/asm/kgdb.h (renamed from include/asm-mips/kgdb.h)0
-rw-r--r--arch/mips/include/asm/kmap_types.h (renamed from include/asm-mips/kmap_types.h)0
-rw-r--r--arch/mips/include/asm/kspd.h (renamed from include/asm-mips/kspd.h)0
-rw-r--r--arch/mips/include/asm/lasat/ds1603.h (renamed from include/asm-mips/lasat/ds1603.h)0
-rw-r--r--arch/mips/include/asm/lasat/eeprom.h (renamed from include/asm-mips/lasat/eeprom.h)0
-rw-r--r--arch/mips/include/asm/lasat/head.h (renamed from include/asm-mips/lasat/head.h)0
-rw-r--r--arch/mips/include/asm/lasat/lasat.h (renamed from include/asm-mips/lasat/lasat.h)0
-rw-r--r--arch/mips/include/asm/lasat/lasatint.h (renamed from include/asm-mips/lasat/lasatint.h)0
-rw-r--r--arch/mips/include/asm/lasat/picvue.h (renamed from include/asm-mips/lasat/picvue.h)0
-rw-r--r--arch/mips/include/asm/lasat/serial.h (renamed from include/asm-mips/lasat/serial.h)0
-rw-r--r--arch/mips/include/asm/linkage.h (renamed from include/asm-mips/linkage.h)0
-rw-r--r--arch/mips/include/asm/local.h (renamed from include/asm-mips/local.h)0
-rw-r--r--arch/mips/include/asm/m48t35.h (renamed from include/asm-mips/m48t35.h)0
-rw-r--r--arch/mips/include/asm/m48t37.h (renamed from include/asm-mips/m48t37.h)0
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h (renamed from include/asm-mips/mach-au1x00/au1000.h)0
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000_dma.h (renamed from include/asm-mips/mach-au1x00/au1000_dma.h)0
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000_gpio.h (renamed from include/asm-mips/mach-au1x00/au1000_gpio.h)0
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1100_mmc.h (renamed from include/asm-mips/mach-au1x00/au1100_mmc.h)0
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1550_spi.h (renamed from include/asm-mips/mach-au1x00/au1550_spi.h)0
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-rw-r--r--arch/mips/include/asm/vr41xx/vr41xx.h (renamed from include/asm-mips/vr41xx/vr41xx.h)0
-rw-r--r--arch/mips/include/asm/war.h (renamed from include/asm-mips/war.h)0
-rw-r--r--arch/mips/include/asm/watch.h32
-rw-r--r--arch/mips/include/asm/wbflush.h (renamed from include/asm-mips/wbflush.h)0
-rw-r--r--arch/mips/include/asm/xor.h (renamed from include/asm-mips/xor.h)0
-rw-r--r--arch/mips/include/asm/xtalk/xtalk.h (renamed from include/asm-mips/xtalk/xtalk.h)0
-rw-r--r--arch/mips/include/asm/xtalk/xwidget.h (renamed from include/asm-mips/xtalk/xwidget.h)0
-rw-r--r--arch/mips/kernel/Makefile2
-rw-r--r--arch/mips/kernel/cpu-probe.c2
-rw-r--r--arch/mips/kernel/genex.S4
-rw-r--r--arch/mips/kernel/proc.c13
-rw-r--r--arch/mips/kernel/ptrace.c100
-rw-r--r--arch/mips/kernel/ptrace32.c59
-rw-r--r--arch/mips/kernel/scall64-n32.S2
-rw-r--r--arch/mips/kernel/scall64-o32.S2
-rw-r--r--arch/mips/kernel/signal32.c12
-rw-r--r--arch/mips/kernel/traps.c24
-rw-r--r--arch/mips/kernel/watch.c188
-rw-r--r--arch/mips/lib/csum_partial.S57
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/pci-tx4938.c2
-rw-r--r--arch/mips/pci/pci-tx4939.c109
-rw-r--r--arch/mips/pmc-sierra/msp71xx/Makefile1
-rw-r--r--arch/mips/pmc-sierra/msp71xx/gpio.c218
-rw-r--r--arch/mips/pmc-sierra/msp71xx/gpio_extended.c148
-rw-r--r--arch/mips/rb532/devices.c22
-rw-r--r--arch/mips/rb532/gpio.c238
-rw-r--r--arch/mips/rb532/irq.c2
-rw-r--r--arch/mips/rb532/prom.c12
-rw-r--r--arch/mips/rb532/serial.c6
-rw-r--r--arch/mips/rb532/setup.c4
-rw-r--r--arch/mips/txx9/Kconfig24
-rw-r--r--arch/mips/txx9/generic/Makefile2
-rw-r--r--arch/mips/txx9/generic/irq_tx4927.c11
-rw-r--r--arch/mips/txx9/generic/irq_tx4938.c11
-rw-r--r--arch/mips/txx9/generic/irq_tx4939.c215
-rw-r--r--arch/mips/txx9/generic/setup.c431
-rw-r--r--arch/mips/txx9/generic/setup_tx3927.c37
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c97
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c122
-rw-r--r--arch/mips/txx9/generic/setup_tx4939.c506
-rw-r--r--arch/mips/txx9/generic/spi_eeprom.c (renamed from arch/mips/txx9/rbtx4938/spi_eeprom.c)28
-rw-r--r--arch/mips/txx9/jmr3927/prom.c1
-rw-r--r--arch/mips/txx9/jmr3927/setup.c25
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c11
-rw-r--r--arch/mips/txx9/rbtx4927/prom.c1
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c25
-rw-r--r--arch/mips/txx9/rbtx4938/Makefile2
-rw-r--r--arch/mips/txx9/rbtx4938/irq.c8
-rw-r--r--arch/mips/txx9/rbtx4938/prom.c3
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c63
-rw-r--r--arch/mips/txx9/rbtx4939/Makefile3
-rw-r--r--arch/mips/txx9/rbtx4939/irq.c96
-rw-r--r--arch/mips/txx9/rbtx4939/prom.c17
-rw-r--r--arch/mips/txx9/rbtx4939/setup.c307
-rw-r--r--include/asm-mips/mach-rc32434/irq.h8
-rw-r--r--include/asm-mips/mach-rc32434/rc32434.h61
568 files changed, 4561 insertions, 605 deletions
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 329dcabe4c5e..d0fff6302f68 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -1014,6 +1014,10 @@ and is between 256 and 4096 characters. It is defined in the file
1014 (only serial suported for now) 1014 (only serial suported for now)
1015 Format: <serial_device>[,baud] 1015 Format: <serial_device>[,baud]
1016 1016
1017 kmac= [MIPS] korina ethernet MAC address.
1018 Configure the RouterBoard 532 series on-chip
1019 Ethernet adapter MAC address.
1020
1017 l2cr= [PPC] 1021 l2cr= [PPC]
1018 1022
1019 l3cr= [PPC] 1023 l3cr= [PPC]
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1e06d233fa83..cd5fbf6f0784 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -568,7 +568,7 @@ config MIKROTIK_RB532
568 select SYS_SUPPORTS_LITTLE_ENDIAN 568 select SYS_SUPPORTS_LITTLE_ENDIAN
569 select SWAP_IO_SPACE 569 select SWAP_IO_SPACE
570 select BOOT_RAW 570 select BOOT_RAW
571 select GENERIC_GPIO 571 select ARCH_REQUIRE_GPIOLIB
572 help 572 help
573 Support the Mikrotik(tm) RouterBoard 532 series, 573 Support the Mikrotik(tm) RouterBoard 532 series,
574 based on the IDT RC32434 SoC. 574 based on the IDT RC32434 SoC.
@@ -598,7 +598,7 @@ config WR_PPMC
598 598
599endchoice 599endchoice
600 600
601source "arch/mips/au1000/Kconfig" 601source "arch/mips/alchemy/Kconfig"
602source "arch/mips/basler/excite/Kconfig" 602source "arch/mips/basler/excite/Kconfig"
603source "arch/mips/jazz/Kconfig" 603source "arch/mips/jazz/Kconfig"
604source "arch/mips/lasat/Kconfig" 604source "arch/mips/lasat/Kconfig"
@@ -610,11 +610,6 @@ source "arch/mips/vr41xx/Kconfig"
610 610
611endmenu 611endmenu
612 612
613config GENERIC_LOCKBREAK
614 bool
615 default y
616 depends on SMP && PREEMPT
617
618config RWSEM_GENERIC_SPINLOCK 613config RWSEM_GENERIC_SPINLOCK
619 bool 614 bool
620 default y 615 default y
@@ -1273,6 +1268,13 @@ config CPU_SUPPORTS_32BIT_KERNEL
1273config CPU_SUPPORTS_64BIT_KERNEL 1268config CPU_SUPPORTS_64BIT_KERNEL
1274 bool 1269 bool
1275 1270
1271#
1272# Set to y for ptrace access to watch registers.
1273#
1274config HARDWARE_WATCHPOINTS
1275 bool
1276 default y if CPU_MIPS32 || CPU_MIPS64
1277
1276menu "Kernel type" 1278menu "Kernel type"
1277 1279
1278choice 1280choice
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9aab51caf16a..7f39fd8a91fe 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -170,123 +170,123 @@ libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
170# Acer PICA 61, Mips Magnum 4000 and Olivetti M700. 170# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
171# 171#
172core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/ 172core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
173cflags-$(CONFIG_MACH_JAZZ) += -Iinclude/asm-mips/mach-jazz 173cflags-$(CONFIG_MACH_JAZZ) += -I$(srctree)/arch/mips/include/asm/mach-jazz
174load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000 174load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
175 175
176# 176#
177# Common Alchemy Au1x00 stuff 177# Common Alchemy Au1x00 stuff
178# 178#
179core-$(CONFIG_SOC_AU1X00) += arch/mips/au1000/common/ 179core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/
180cflags-$(CONFIG_SOC_AU1X00) += -Iinclude/asm-mips/mach-au1x00 180cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
181 181
182# 182#
183# AMD Alchemy Pb1000 eval board 183# AMD Alchemy Pb1000 eval board
184# 184#
185libs-$(CONFIG_MIPS_PB1000) += arch/mips/au1000/pb1000/ 185libs-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/pb1000/
186cflags-$(CONFIG_MIPS_PB1000) += -Iinclude/asm-mips/mach-pb1x00 186cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
187load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000 187load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000
188 188
189# 189#
190# AMD Alchemy Pb1100 eval board 190# AMD Alchemy Pb1100 eval board
191# 191#
192libs-$(CONFIG_MIPS_PB1100) += arch/mips/au1000/pb1100/ 192libs-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/pb1100/
193cflags-$(CONFIG_MIPS_PB1100) += -Iinclude/asm-mips/mach-pb1x00 193cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
194load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 194load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000
195 195
196# 196#
197# AMD Alchemy Pb1500 eval board 197# AMD Alchemy Pb1500 eval board
198# 198#
199libs-$(CONFIG_MIPS_PB1500) += arch/mips/au1000/pb1500/ 199libs-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/pb1500/
200cflags-$(CONFIG_MIPS_PB1500) += -Iinclude/asm-mips/mach-pb1x00 200cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
201load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 201load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000
202 202
203# 203#
204# AMD Alchemy Pb1550 eval board 204# AMD Alchemy Pb1550 eval board
205# 205#
206libs-$(CONFIG_MIPS_PB1550) += arch/mips/au1000/pb1550/ 206libs-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/pb1550/
207cflags-$(CONFIG_MIPS_PB1550) += -Iinclude/asm-mips/mach-pb1x00 207cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
208load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 208load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
209 209
210# 210#
211# AMD Alchemy Pb1200 eval board 211# AMD Alchemy Pb1200 eval board
212# 212#
213libs-$(CONFIG_MIPS_PB1200) += arch/mips/au1000/pb1200/ 213libs-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/pb1200/
214cflags-$(CONFIG_MIPS_PB1200) += -Iinclude/asm-mips/mach-pb1x00 214cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
215load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 215load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
216 216
217# 217#
218# AMD Alchemy Db1000 eval board 218# AMD Alchemy Db1000 eval board
219# 219#
220libs-$(CONFIG_MIPS_DB1000) += arch/mips/au1000/db1x00/ 220libs-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/db1x00/
221cflags-$(CONFIG_MIPS_DB1000) += -Iinclude/asm-mips/mach-db1x00 221cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
222load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 222load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000
223 223
224# 224#
225# AMD Alchemy Db1100 eval board 225# AMD Alchemy Db1100 eval board
226# 226#
227libs-$(CONFIG_MIPS_DB1100) += arch/mips/au1000/db1x00/ 227libs-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/db1x00/
228cflags-$(CONFIG_MIPS_DB1100) += -Iinclude/asm-mips/mach-db1x00 228cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
229load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000 229load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000
230 230
231# 231#
232# AMD Alchemy Db1500 eval board 232# AMD Alchemy Db1500 eval board
233# 233#
234libs-$(CONFIG_MIPS_DB1500) += arch/mips/au1000/db1x00/ 234libs-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/db1x00/
235cflags-$(CONFIG_MIPS_DB1500) += -Iinclude/asm-mips/mach-db1x00 235cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
236load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000 236load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000
237 237
238# 238#
239# AMD Alchemy Db1550 eval board 239# AMD Alchemy Db1550 eval board
240# 240#
241libs-$(CONFIG_MIPS_DB1550) += arch/mips/au1000/db1x00/ 241libs-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/db1x00/
242cflags-$(CONFIG_MIPS_DB1550) += -Iinclude/asm-mips/mach-db1x00 242cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
243load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 243load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
244 244
245# 245#
246# AMD Alchemy Db1200 eval board 246# AMD Alchemy Db1200 eval board
247# 247#
248libs-$(CONFIG_MIPS_DB1200) += arch/mips/au1000/pb1200/ 248libs-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/pb1200/
249cflags-$(CONFIG_MIPS_DB1200) += -Iinclude/asm-mips/mach-db1x00 249cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
250load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 250load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
251 251
252# 252#
253# AMD Alchemy Bosporus eval board 253# AMD Alchemy Bosporus eval board
254# 254#
255libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/au1000/db1x00/ 255libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/db1x00/
256cflags-$(CONFIG_MIPS_BOSPORUS) += -Iinclude/asm-mips/mach-db1x00 256cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
257load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000 257load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000
258 258
259# 259#
260# AMD Alchemy Mirage eval board 260# AMD Alchemy Mirage eval board
261# 261#
262libs-$(CONFIG_MIPS_MIRAGE) += arch/mips/au1000/db1x00/ 262libs-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/db1x00/
263cflags-$(CONFIG_MIPS_MIRAGE) += -Iinclude/asm-mips/mach-db1x00 263cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
264load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 264load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000
265 265
266# 266#
267# 4G-Systems eval board 267# 4G-Systems eval board
268# 268#
269libs-$(CONFIG_MIPS_MTX1) += arch/mips/au1000/mtx-1/ 269libs-$(CONFIG_MIPS_MTX1) += arch/mips/alchemy/mtx-1/
270load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 270load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
271 271
272# 272#
273# MyCable eval board 273# MyCable eval board
274# 274#
275libs-$(CONFIG_MIPS_XXS1500) += arch/mips/au1000/xxs1500/ 275libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/
276load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 276load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
277 277
278# 278#
279# Cobalt Server 279# Cobalt Server
280# 280#
281core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ 281core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
282cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/mach-cobalt 282cflags-$(CONFIG_MIPS_COBALT) += -I$(srctree)/arch/mips/include/asm/mach-cobalt
283load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000 283load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
284 284
285# 285#
286# DECstation family 286# DECstation family
287# 287#
288core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/ 288core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/
289cflags-$(CONFIG_MACH_DECSTATION)+= -Iinclude/asm-mips/mach-dec 289cflags-$(CONFIG_MACH_DECSTATION)+= -I$(srctree)/arch/mips/include/asm/mach-dec
290libs-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/prom/ 290libs-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/prom/
291load-$(CONFIG_MACH_DECSTATION) += 0xffffffff80040000 291load-$(CONFIG_MACH_DECSTATION) += 0xffffffff80040000
292 292
@@ -294,7 +294,7 @@ load-$(CONFIG_MACH_DECSTATION) += 0xffffffff80040000
294# Wind River PPMC Board (4KC + GT64120) 294# Wind River PPMC Board (4KC + GT64120)
295# 295#
296core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/ 296core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/
297cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc 297cflags-$(CONFIG_WR_PPMC) += -I$(srctree)/arch/mips/include/asm/mach-wrppmc
298load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 298load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
299 299
300# 300#
@@ -302,13 +302,13 @@ load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
302# 302#
303core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/ 303core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/
304load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000 304load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000
305cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote 305cflags-$(CONFIG_LEMOTE_FULONG) += -I$(srctree)/arch/mips/include/asm/mach-lemote
306 306
307# 307#
308# MIPS Malta board 308# MIPS Malta board
309# 309#
310core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/ 310core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/
311cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-malta 311cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta
312load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 312load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
313all-$(CONFIG_MIPS_MALTA) := vmlinux.bin 313all-$(CONFIG_MIPS_MALTA) := vmlinux.bin
314 314
@@ -316,14 +316,14 @@ all-$(CONFIG_MIPS_MALTA) := vmlinux.bin
316# MIPS SIM 316# MIPS SIM
317# 317#
318core-$(CONFIG_MIPS_SIM) += arch/mips/mipssim/ 318core-$(CONFIG_MIPS_SIM) += arch/mips/mipssim/
319cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-mipssim 319cflags-$(CONFIG_MIPS_SIM) += -I$(srctree)/arch/mips/include/asm/mach-mipssim
320load-$(CONFIG_MIPS_SIM) += 0x80100000 320load-$(CONFIG_MIPS_SIM) += 0x80100000
321 321
322# 322#
323# PMC-Sierra MSP SOCs 323# PMC-Sierra MSP SOCs
324# 324#
325core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/ 325core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/
326cflags-$(CONFIG_PMC_MSP) += -Iinclude/asm-mips/pmc-sierra/msp71xx \ 326cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
327 -mno-branch-likely 327 -mno-branch-likely
328load-$(CONFIG_PMC_MSP) += 0xffffffff80100000 328load-$(CONFIG_PMC_MSP) += 0xffffffff80100000
329 329
@@ -331,28 +331,28 @@ load-$(CONFIG_PMC_MSP) += 0xffffffff80100000
331# PMC-Sierra Yosemite 331# PMC-Sierra Yosemite
332# 332#
333core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ 333core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/
334cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite 334cflags-$(CONFIG_PMC_YOSEMITE) += -I$(srctree)/arch/mips/include/asm/mach-yosemite
335load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 335load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
336 336
337# 337#
338# Basler eXcite 338# Basler eXcite
339# 339#
340core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/ 340core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
341cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite 341cflags-$(CONFIG_BASLER_EXCITE) += -I$(srctree)/arch/mips/include/asm/mach-excite
342load-$(CONFIG_BASLER_EXCITE) += 0x80100000 342load-$(CONFIG_BASLER_EXCITE) += 0x80100000
343 343
344# 344#
345# LASAT platforms 345# LASAT platforms
346# 346#
347core-$(CONFIG_LASAT) += arch/mips/lasat/ 347core-$(CONFIG_LASAT) += arch/mips/lasat/
348cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat 348cflags-$(CONFIG_LASAT) += -I$(srctree)/arch/mips/include/asm/mach-lasat
349load-$(CONFIG_LASAT) += 0xffffffff80000000 349load-$(CONFIG_LASAT) += 0xffffffff80000000
350 350
351# 351#
352# Common VR41xx 352# Common VR41xx
353# 353#
354core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ 354core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/
355cflags-$(CONFIG_MACH_VR41XX) += -Iinclude/asm-mips/mach-vr41xx 355cflags-$(CONFIG_MACH_VR41XX) += -I$(srctree)/arch/mips/include/asm/mach-vr41xx
356 356
357# 357#
358# ZAO Networks Capcella (VR4131) 358# ZAO Networks Capcella (VR4131)
@@ -385,13 +385,13 @@ load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
385# Common NXP PNX8550 385# Common NXP PNX8550
386# 386#
387core-$(CONFIG_SOC_PNX8550) += arch/mips/nxp/pnx8550/common/ 387core-$(CONFIG_SOC_PNX8550) += arch/mips/nxp/pnx8550/common/
388cflags-$(CONFIG_SOC_PNX8550) += -Iinclude/asm-mips/mach-pnx8550 388cflags-$(CONFIG_SOC_PNX8550) += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
389 389
390# 390#
391# NXP PNX8550 JBS board 391# NXP PNX8550 JBS board
392# 392#
393libs-$(CONFIG_PNX8550_JBS) += arch/mips/nxp/pnx8550/jbs/ 393libs-$(CONFIG_PNX8550_JBS) += arch/mips/nxp/pnx8550/jbs/
394#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 394#cflags-$(CONFIG_PNX8550_JBS) += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
395load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 395load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
396 396
397# NXP PNX8550 STB810 board 397# NXP PNX8550 STB810 board
@@ -402,7 +402,7 @@ load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000
402# NEC EMMA2RH boards 402# NEC EMMA2RH boards
403# 403#
404core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/ 404core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/
405cflags-$(CONFIG_EMMA2RH) += -Iinclude/asm-mips/mach-emma2rh 405cflags-$(CONFIG_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
406 406
407# NEC EMMA2RH Mark-eins 407# NEC EMMA2RH Mark-eins
408core-$(CONFIG_MARKEINS) += arch/mips/emma2rh/markeins/ 408core-$(CONFIG_MARKEINS) += arch/mips/emma2rh/markeins/
@@ -418,7 +418,7 @@ load-$(CONFIG_MARKEINS) += 0xffffffff88100000
418# address by 8kb. 418# address by 8kb.
419# 419#
420core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/ 420core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/
421cflags-$(CONFIG_SGI_IP22) += -Iinclude/asm-mips/mach-ip22 421cflags-$(CONFIG_SGI_IP22) += -I$(srctree)/arch/mips/include/asm/mach-ip22
422ifdef CONFIG_32BIT 422ifdef CONFIG_32BIT
423load-$(CONFIG_SGI_IP22) += 0xffffffff88002000 423load-$(CONFIG_SGI_IP22) += 0xffffffff88002000
424endif 424endif
@@ -435,7 +435,7 @@ endif
435# 435#
436ifdef CONFIG_SGI_IP27 436ifdef CONFIG_SGI_IP27
437core-$(CONFIG_SGI_IP27) += arch/mips/sgi-ip27/ 437core-$(CONFIG_SGI_IP27) += arch/mips/sgi-ip27/
438cflags-$(CONFIG_SGI_IP27) += -Iinclude/asm-mips/mach-ip27 438cflags-$(CONFIG_SGI_IP27) += -I$(srctree)/arch/mips/include/asm/mach-ip27
439ifdef CONFIG_MAPPED_KERNEL 439ifdef CONFIG_MAPPED_KERNEL
440load-$(CONFIG_SGI_IP27) += 0xc00000004001c000 440load-$(CONFIG_SGI_IP27) += 0xc00000004001c000
441OBJCOPYFLAGS := --change-addresses=0x3fffffff80000000 441OBJCOPYFLAGS := --change-addresses=0x3fffffff80000000
@@ -460,7 +460,7 @@ ifdef CONFIG_SGI_IP28
460 endif 460 endif
461endif 461endif
462core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ 462core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/
463cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28 463cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -I$(srctree)/arch/mips/include/asm/mach-ip28
464load-$(CONFIG_SGI_IP28) += 0xa800000020004000 464load-$(CONFIG_SGI_IP28) += 0xa800000020004000
465 465
466# 466#
@@ -472,7 +472,7 @@ load-$(CONFIG_SGI_IP28) += 0xa800000020004000
472# will break. 472# will break.
473# 473#
474core-$(CONFIG_SGI_IP32) += arch/mips/sgi-ip32/ 474core-$(CONFIG_SGI_IP32) += arch/mips/sgi-ip32/
475cflags-$(CONFIG_SGI_IP32) += -Iinclude/asm-mips/mach-ip32 475cflags-$(CONFIG_SGI_IP32) += -I$(srctree)/arch/mips/include/asm/mach-ip32
476load-$(CONFIG_SGI_IP32) += 0xffffffff80004000 476load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
477 477
478# 478#
@@ -484,22 +484,22 @@ load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
484# 484#
485core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/ 485core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/
486core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/common/ 486core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/common/
487cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte \ 487cflags-$(CONFIG_SIBYTE_BCM112X) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
488 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL 488 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
489 489
490core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/ 490core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/
491core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/common/ 491core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/common/
492cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte \ 492cflags-$(CONFIG_SIBYTE_SB1250) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
493 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL 493 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
494 494
495core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/ 495core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/
496core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/common/ 496core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/common/
497cflags-$(CONFIG_SIBYTE_BCM1x55) += -Iinclude/asm-mips/mach-sibyte \ 497cflags-$(CONFIG_SIBYTE_BCM1x55) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
498 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL 498 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
499 499
500core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/ 500core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/
501core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/common/ 501core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/common/
502cflags-$(CONFIG_SIBYTE_BCM1x80) += -Iinclude/asm-mips/mach-sibyte \ 502cflags-$(CONFIG_SIBYTE_BCM1x80) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
503 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL 503 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
504 504
505# 505#
@@ -529,14 +529,14 @@ load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
529# Broadcom BCM47XX boards 529# Broadcom BCM47XX boards
530# 530#
531core-$(CONFIG_BCM47XX) += arch/mips/bcm47xx/ 531core-$(CONFIG_BCM47XX) += arch/mips/bcm47xx/
532cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx 532cflags-$(CONFIG_BCM47XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
533load-$(CONFIG_BCM47XX) := 0xffffffff80001000 533load-$(CONFIG_BCM47XX) := 0xffffffff80001000
534 534
535# 535#
536# SNI RM 536# SNI RM
537# 537#
538core-$(CONFIG_SNI_RM) += arch/mips/sni/ 538core-$(CONFIG_SNI_RM) += arch/mips/sni/
539cflags-$(CONFIG_SNI_RM) += -Iinclude/asm-mips/mach-rm 539cflags-$(CONFIG_SNI_RM) += -I$(srctree)/arch/mips/include/asm/mach-rm
540ifdef CONFIG_CPU_LITTLE_ENDIAN 540ifdef CONFIG_CPU_LITTLE_ENDIAN
541load-$(CONFIG_SNI_RM) += 0xffffffff80600000 541load-$(CONFIG_SNI_RM) += 0xffffffff80600000
542else 542else
@@ -548,10 +548,10 @@ all-$(CONFIG_SNI_RM) := vmlinux.ecoff
548# Common TXx9 548# Common TXx9
549# 549#
550core-$(CONFIG_MACH_TX39XX) += arch/mips/txx9/generic/ 550core-$(CONFIG_MACH_TX39XX) += arch/mips/txx9/generic/
551cflags-$(CONFIG_MACH_TX39XX) += -Iinclude/asm-mips/mach-tx39xx 551cflags-$(CONFIG_MACH_TX39XX) += -I$(srctree)/arch/mips/include/asm/mach-tx39xx
552load-$(CONFIG_MACH_TX39XX) += 0xffffffff80050000 552load-$(CONFIG_MACH_TX39XX) += 0xffffffff80050000
553core-$(CONFIG_MACH_TX49XX) += arch/mips/txx9/generic/ 553core-$(CONFIG_MACH_TX49XX) += arch/mips/txx9/generic/
554cflags-$(CONFIG_MACH_TX49XX) += -Iinclude/asm-mips/mach-tx49xx 554cflags-$(CONFIG_MACH_TX49XX) += -I$(srctree)/arch/mips/include/asm/mach-tx49xx
555load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000 555load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000
556 556
557# 557#
@@ -563,21 +563,17 @@ core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/
563# Routerboard 532 board 563# Routerboard 532 board
564# 564#
565core-$(CONFIG_MIKROTIK_RB532) += arch/mips/rb532/ 565core-$(CONFIG_MIKROTIK_RB532) += arch/mips/rb532/
566cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434 566cflags-$(CONFIG_MIKROTIK_RB532) += -I$(srctree)/arch/mips/include/asm/mach-rc32434
567load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000 567load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
568 568
569# 569#
570# Toshiba RBTX4927 board or 570# Toshiba RBTX49XX boards
571# Toshiba RBTX4937 board
572# 571#
573core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ 572core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
574
575#
576# Toshiba RBTX4938 board
577#
578core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ 573core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
574core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
579 575
580cflags-y += -Iinclude/asm-mips/mach-generic 576cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
581drivers-$(CONFIG_PCI) += arch/mips/pci/ 577drivers-$(CONFIG_PCI) += arch/mips/pci/
582 578
583ifdef CONFIG_32BIT 579ifdef CONFIG_32BIT
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/alchemy/Kconfig
index e4a057d80ab6..e4a057d80ab6 100644
--- a/arch/mips/au1000/Kconfig
+++ b/arch/mips/alchemy/Kconfig
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/alchemy/common/Makefile
index df48fd65bbf3..df48fd65bbf3 100644
--- a/arch/mips/au1000/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/alchemy/common/au1xxx_irqmap.c
index c7ca1596394c..c7ca1596394c 100644
--- a/arch/mips/au1000/common/au1xxx_irqmap.c
+++ b/arch/mips/alchemy/common/au1xxx_irqmap.c
diff --git a/arch/mips/au1000/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index 043429d17c5f..043429d17c5f 100644
--- a/arch/mips/au1000/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/alchemy/common/cputable.c
index ba6430bc2d03..ba6430bc2d03 100644
--- a/arch/mips/au1000/common/cputable.c
+++ b/arch/mips/alchemy/common/cputable.c
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 601ee9180ee4..601ee9180ee4 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
diff --git a/arch/mips/au1000/common/dma.c b/arch/mips/alchemy/common/dma.c
index d6fbda232e6a..d6fbda232e6a 100644
--- a/arch/mips/au1000/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
diff --git a/arch/mips/au1000/common/gpio.c b/arch/mips/alchemy/common/gpio.c
index e660ddd611c4..e660ddd611c4 100644
--- a/arch/mips/au1000/common/gpio.c
+++ b/arch/mips/alchemy/common/gpio.c
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/alchemy/common/irq.c
index 40c6ceceb5f9..40c6ceceb5f9 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/alchemy/common/pci.c
index 7866cf50cf99..7866cf50cf99 100644
--- a/arch/mips/au1000/common/pci.c
+++ b/arch/mips/alchemy/common/pci.c
diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/alchemy/common/platform.c
index dc8a67efac28..dc8a67efac28 100644
--- a/arch/mips/au1000/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/alchemy/common/power.c
index bd854a6d1d89..bd854a6d1d89 100644
--- a/arch/mips/au1000/common/power.c
+++ b/arch/mips/alchemy/common/power.c
diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/alchemy/common/prom.c
index 18b310b475ca..18b310b475ca 100644
--- a/arch/mips/au1000/common/prom.c
+++ b/arch/mips/alchemy/common/prom.c
diff --git a/arch/mips/au1000/common/puts.c b/arch/mips/alchemy/common/puts.c
index 55bbe24d45b6..55bbe24d45b6 100644
--- a/arch/mips/au1000/common/puts.c
+++ b/arch/mips/alchemy/common/puts.c
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/alchemy/common/reset.c
index d555429c8d6f..d555429c8d6f 100644
--- a/arch/mips/au1000/common/reset.c
+++ b/arch/mips/alchemy/common/reset.c
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/alchemy/common/setup.c
index 1ac6b06f42a3..1ac6b06f42a3 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
diff --git a/arch/mips/au1000/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 4b3cf021a454..3006e270c8bc 100644
--- a/arch/mips/au1000/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -79,12 +79,12 @@ LEAF(save_and_sleep)
79/* Put SDRAM into self refresh. Preload instructions into cache, 79/* Put SDRAM into self refresh. Preload instructions into cache,
80 * issue a precharge, then auto refresh, then sleep commands to it. 80 * issue a precharge, then auto refresh, then sleep commands to it.
81 */ 81 */
82 la t0, sdsleep 82 la t0, sdsleep
83 .set mips3 83 .set mips3
84 cache 0x14, 0(t0) 84 cache 0x14, 0(t0)
85 cache 0x14, 32(t0) 85 cache 0x14, 32(t0)
86 cache 0x14, 64(t0) 86 cache 0x14, 64(t0)
87 cache 0x14, 96(t0) 87 cache 0x14, 96(t0)
88 .set mips0 88 .set mips0
89 89
90sdsleep: 90sdsleep:
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/alchemy/common/time.c
index 563d9390a872..563d9390a872 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/alchemy/common/time.c
diff --git a/arch/mips/au1000/db1x00/Makefile b/arch/mips/alchemy/db1x00/Makefile
index 274db3b55d82..274db3b55d82 100644
--- a/arch/mips/au1000/db1x00/Makefile
+++ b/arch/mips/alchemy/db1x00/Makefile
diff --git a/arch/mips/au1000/db1x00/board_setup.c b/arch/mips/alchemy/db1x00/board_setup.c
index 9e5ccbbfcedd..9e5ccbbfcedd 100644
--- a/arch/mips/au1000/db1x00/board_setup.c
+++ b/arch/mips/alchemy/db1x00/board_setup.c
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/alchemy/db1x00/init.c
index 847413514964..847413514964 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/alchemy/db1x00/init.c
diff --git a/arch/mips/au1000/db1x00/irqmap.c b/arch/mips/alchemy/db1x00/irqmap.c
index 94c090e8bf7a..94c090e8bf7a 100644
--- a/arch/mips/au1000/db1x00/irqmap.c
+++ b/arch/mips/alchemy/db1x00/irqmap.c
diff --git a/arch/mips/au1000/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
index 7c67b3d33bec..7c67b3d33bec 100644
--- a/arch/mips/au1000/mtx-1/Makefile
+++ b/arch/mips/alchemy/mtx-1/Makefile
diff --git a/arch/mips/au1000/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 3f8079186cf2..3f8079186cf2 100644
--- a/arch/mips/au1000/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
index 3bae13c28954..3bae13c28954 100644
--- a/arch/mips/au1000/mtx-1/init.c
+++ b/arch/mips/alchemy/mtx-1/init.c
diff --git a/arch/mips/au1000/mtx-1/irqmap.c b/arch/mips/alchemy/mtx-1/irqmap.c
index f2bf02951e9c..f2bf02951e9c 100644
--- a/arch/mips/au1000/mtx-1/irqmap.c
+++ b/arch/mips/alchemy/mtx-1/irqmap.c
diff --git a/arch/mips/au1000/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c
index 8b5914d1241f..8b5914d1241f 100644
--- a/arch/mips/au1000/mtx-1/platform.c
+++ b/arch/mips/alchemy/mtx-1/platform.c
diff --git a/arch/mips/au1000/pb1000/Makefile b/arch/mips/alchemy/pb1000/Makefile
index 99bbec0ca41b..99bbec0ca41b 100644
--- a/arch/mips/au1000/pb1000/Makefile
+++ b/arch/mips/alchemy/pb1000/Makefile
diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/alchemy/pb1000/board_setup.c
index 25df167a95b3..25df167a95b3 100644
--- a/arch/mips/au1000/pb1000/board_setup.c
+++ b/arch/mips/alchemy/pb1000/board_setup.c
diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/alchemy/pb1000/init.c
index 8a9c7d57208d..8a9c7d57208d 100644
--- a/arch/mips/au1000/pb1000/init.c
+++ b/arch/mips/alchemy/pb1000/init.c
diff --git a/arch/mips/au1000/pb1000/irqmap.c b/arch/mips/alchemy/pb1000/irqmap.c
index b3d56b0af321..b3d56b0af321 100644
--- a/arch/mips/au1000/pb1000/irqmap.c
+++ b/arch/mips/alchemy/pb1000/irqmap.c
diff --git a/arch/mips/au1000/pb1100/Makefile b/arch/mips/alchemy/pb1100/Makefile
index 793e97c49e46..793e97c49e46 100644
--- a/arch/mips/au1000/pb1100/Makefile
+++ b/arch/mips/alchemy/pb1100/Makefile
diff --git a/arch/mips/au1000/pb1100/board_setup.c b/arch/mips/alchemy/pb1100/board_setup.c
index c0bfd59a7a36..c0bfd59a7a36 100644
--- a/arch/mips/au1000/pb1100/board_setup.c
+++ b/arch/mips/alchemy/pb1100/board_setup.c
diff --git a/arch/mips/au1000/pb1100/init.c b/arch/mips/alchemy/pb1100/init.c
index 7c6792308bc5..7c6792308bc5 100644
--- a/arch/mips/au1000/pb1100/init.c
+++ b/arch/mips/alchemy/pb1100/init.c
diff --git a/arch/mips/au1000/pb1100/irqmap.c b/arch/mips/alchemy/pb1100/irqmap.c
index 9b7dd8b41283..9b7dd8b41283 100644
--- a/arch/mips/au1000/pb1100/irqmap.c
+++ b/arch/mips/alchemy/pb1100/irqmap.c
diff --git a/arch/mips/au1000/pb1200/Makefile b/arch/mips/alchemy/pb1200/Makefile
index d678adf7ce85..d678adf7ce85 100644
--- a/arch/mips/au1000/pb1200/Makefile
+++ b/arch/mips/alchemy/pb1200/Makefile
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/alchemy/pb1200/board_setup.c
index 6cb2115059ad..6cb2115059ad 100644
--- a/arch/mips/au1000/pb1200/board_setup.c
+++ b/arch/mips/alchemy/pb1200/board_setup.c
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/alchemy/pb1200/init.c
index e9b2a0fd48ae..e9b2a0fd48ae 100644
--- a/arch/mips/au1000/pb1200/init.c
+++ b/arch/mips/alchemy/pb1200/init.c
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/alchemy/pb1200/irqmap.c
index 2a505ad8715b..2a505ad8715b 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/alchemy/pb1200/irqmap.c
diff --git a/arch/mips/au1000/pb1200/platform.c b/arch/mips/alchemy/pb1200/platform.c
index f8fb0aeac571..f8fb0aeac571 100644
--- a/arch/mips/au1000/pb1200/platform.c
+++ b/arch/mips/alchemy/pb1200/platform.c
diff --git a/arch/mips/au1000/pb1500/Makefile b/arch/mips/alchemy/pb1500/Makefile
index 602f38df20bb..602f38df20bb 100644
--- a/arch/mips/au1000/pb1500/Makefile
+++ b/arch/mips/alchemy/pb1500/Makefile
diff --git a/arch/mips/au1000/pb1500/board_setup.c b/arch/mips/alchemy/pb1500/board_setup.c
index 035771c6e5b8..035771c6e5b8 100644
--- a/arch/mips/au1000/pb1500/board_setup.c
+++ b/arch/mips/alchemy/pb1500/board_setup.c
diff --git a/arch/mips/au1000/pb1500/init.c b/arch/mips/alchemy/pb1500/init.c
index 3b6e395cf952..3b6e395cf952 100644
--- a/arch/mips/au1000/pb1500/init.c
+++ b/arch/mips/alchemy/pb1500/init.c
diff --git a/arch/mips/au1000/pb1500/irqmap.c b/arch/mips/alchemy/pb1500/irqmap.c
index 39c4682766a8..39c4682766a8 100644
--- a/arch/mips/au1000/pb1500/irqmap.c
+++ b/arch/mips/alchemy/pb1500/irqmap.c
diff --git a/arch/mips/au1000/pb1550/Makefile b/arch/mips/alchemy/pb1550/Makefile
index 7d8beca87fa5..7d8beca87fa5 100644
--- a/arch/mips/au1000/pb1550/Makefile
+++ b/arch/mips/alchemy/pb1550/Makefile
diff --git a/arch/mips/au1000/pb1550/board_setup.c b/arch/mips/alchemy/pb1550/board_setup.c
index 0ed76b64b6ab..0ed76b64b6ab 100644
--- a/arch/mips/au1000/pb1550/board_setup.c
+++ b/arch/mips/alchemy/pb1550/board_setup.c
diff --git a/arch/mips/au1000/pb1550/init.c b/arch/mips/alchemy/pb1550/init.c
index e1055a13a1a0..e1055a13a1a0 100644
--- a/arch/mips/au1000/pb1550/init.c
+++ b/arch/mips/alchemy/pb1550/init.c
diff --git a/arch/mips/au1000/pb1550/irqmap.c b/arch/mips/alchemy/pb1550/irqmap.c
index a02a4d1fa899..a02a4d1fa899 100644
--- a/arch/mips/au1000/pb1550/irqmap.c
+++ b/arch/mips/alchemy/pb1550/irqmap.c
diff --git a/arch/mips/au1000/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
index db3c526f64d8..db3c526f64d8 100644
--- a/arch/mips/au1000/xxs1500/Makefile
+++ b/arch/mips/alchemy/xxs1500/Makefile
diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 4c587acac5c3..4c587acac5c3 100644
--- a/arch/mips/au1000/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
index 7516434760a1..7516434760a1 100644
--- a/arch/mips/au1000/xxs1500/init.c
+++ b/arch/mips/alchemy/xxs1500/init.c
diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/alchemy/xxs1500/irqmap.c
index edf06ed11870..edf06ed11870 100644
--- a/arch/mips/au1000/xxs1500/irqmap.c
+++ b/arch/mips/alchemy/xxs1500/irqmap.c
diff --git a/include/asm-mips/Kbuild b/arch/mips/include/asm/Kbuild
index 7897f05e3165..7897f05e3165 100644
--- a/include/asm-mips/Kbuild
+++ b/arch/mips/include/asm/Kbuild
diff --git a/include/asm-mips/a.out.h b/arch/mips/include/asm/a.out.h
index cad8371422ab..cad8371422ab 100644
--- a/include/asm-mips/a.out.h
+++ b/arch/mips/include/asm/a.out.h
diff --git a/include/asm-mips/abi.h b/arch/mips/include/asm/abi.h
index 1dd74fbdc09b..1dd74fbdc09b 100644
--- a/include/asm-mips/abi.h
+++ b/arch/mips/include/asm/abi.h
diff --git a/include/asm-mips/addrspace.h b/arch/mips/include/asm/addrspace.h
index 569f80aacbd2..569f80aacbd2 100644
--- a/include/asm-mips/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
diff --git a/include/asm-mips/asm.h b/arch/mips/include/asm/asm.h
index 608cfcfbb3ea..608cfcfbb3ea 100644
--- a/include/asm-mips/asm.h
+++ b/arch/mips/include/asm/asm.h
diff --git a/include/asm-mips/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index 5de3963f511e..5de3963f511e 100644
--- a/include/asm-mips/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
diff --git a/include/asm-mips/asmmacro-64.h b/arch/mips/include/asm/asmmacro-64.h
index 225feefcb25d..225feefcb25d 100644
--- a/include/asm-mips/asmmacro-64.h
+++ b/arch/mips/include/asm/asmmacro-64.h
diff --git a/include/asm-mips/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 7a881755800f..7a881755800f 100644
--- a/include/asm-mips/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
diff --git a/include/asm-mips/atomic.h b/arch/mips/include/asm/atomic.h
index 1232be3885b0..1232be3885b0 100644
--- a/include/asm-mips/atomic.h
+++ b/arch/mips/include/asm/atomic.h
diff --git a/include/asm-mips/auxvec.h b/arch/mips/include/asm/auxvec.h
index 7cf7f2d21943..7cf7f2d21943 100644
--- a/include/asm-mips/auxvec.h
+++ b/arch/mips/include/asm/auxvec.h
diff --git a/include/asm-mips/barrier.h b/arch/mips/include/asm/barrier.h
index 8e9ac313ca3b..8e9ac313ca3b 100644
--- a/include/asm-mips/barrier.h
+++ b/arch/mips/include/asm/barrier.h
diff --git a/include/asm-mips/bcache.h b/arch/mips/include/asm/bcache.h
index 0ba9d6ef76a7..0ba9d6ef76a7 100644
--- a/include/asm-mips/bcache.h
+++ b/arch/mips/include/asm/bcache.h
diff --git a/include/asm-mips/bitops.h b/arch/mips/include/asm/bitops.h
index 49df8c4c9d25..49df8c4c9d25 100644
--- a/include/asm-mips/bitops.h
+++ b/arch/mips/include/asm/bitops.h
diff --git a/include/asm-mips/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 610fe3af7a03..610fe3af7a03 100644
--- a/include/asm-mips/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
diff --git a/include/asm-mips/branch.h b/arch/mips/include/asm/branch.h
index 37c6857c8d4a..37c6857c8d4a 100644
--- a/include/asm-mips/branch.h
+++ b/arch/mips/include/asm/branch.h
diff --git a/include/asm-mips/break.h b/arch/mips/include/asm/break.h
index 25b980c91e7e..25b980c91e7e 100644
--- a/include/asm-mips/break.h
+++ b/arch/mips/include/asm/break.h
diff --git a/include/asm-mips/bug.h b/arch/mips/include/asm/bug.h
index 7eb63de808bc..7eb63de808bc 100644
--- a/include/asm-mips/bug.h
+++ b/arch/mips/include/asm/bug.h
diff --git a/include/asm-mips/bugs.h b/arch/mips/include/asm/bugs.h
index 9dc10df32078..9dc10df32078 100644
--- a/include/asm-mips/bugs.h
+++ b/arch/mips/include/asm/bugs.h
diff --git a/include/asm-mips/byteorder.h b/arch/mips/include/asm/byteorder.h
index fe7dc2d59b69..fe7dc2d59b69 100644
--- a/include/asm-mips/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
diff --git a/include/asm-mips/cache.h b/arch/mips/include/asm/cache.h
index 37f175c42bb5..37f175c42bb5 100644
--- a/include/asm-mips/cache.h
+++ b/arch/mips/include/asm/cache.h
diff --git a/include/asm-mips/cachectl.h b/arch/mips/include/asm/cachectl.h
index f3ce721861d3..f3ce721861d3 100644
--- a/include/asm-mips/cachectl.h
+++ b/arch/mips/include/asm/cachectl.h
diff --git a/include/asm-mips/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 03b1d69b142f..03b1d69b142f 100644
--- a/include/asm-mips/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
diff --git a/include/asm-mips/cacheops.h b/arch/mips/include/asm/cacheops.h
index 256ad2cc6eb8..256ad2cc6eb8 100644
--- a/include/asm-mips/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
diff --git a/include/asm-mips/checksum.h b/arch/mips/include/asm/checksum.h
index 290485ac5407..290485ac5407 100644
--- a/include/asm-mips/checksum.h
+++ b/arch/mips/include/asm/checksum.h
diff --git a/include/asm-mips/cmp.h b/arch/mips/include/asm/cmp.h
index 89a73fb93ae6..89a73fb93ae6 100644
--- a/include/asm-mips/cmp.h
+++ b/arch/mips/include/asm/cmp.h
diff --git a/include/asm-mips/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 4a812c3ceb90..4a812c3ceb90 100644
--- a/include/asm-mips/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
diff --git a/include/asm-mips/compat-signal.h b/arch/mips/include/asm/compat-signal.h
index 368a99e5c3e1..368a99e5c3e1 100644
--- a/include/asm-mips/compat-signal.h
+++ b/arch/mips/include/asm/compat-signal.h
diff --git a/include/asm-mips/compat.h b/arch/mips/include/asm/compat.h
index ac5d541368e9..ac5d541368e9 100644
--- a/include/asm-mips/compat.h
+++ b/arch/mips/include/asm/compat.h
diff --git a/include/asm-mips/compiler.h b/arch/mips/include/asm/compiler.h
index 71f5c5cfc58a..71f5c5cfc58a 100644
--- a/include/asm-mips/compiler.h
+++ b/arch/mips/include/asm/compiler.h
diff --git a/include/asm-mips/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 5ea701fc3425..5ea701fc3425 100644
--- a/include/asm-mips/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
diff --git a/include/asm-mips/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 2de73dbb2e9e..744cd8fb107f 100644
--- a/include/asm-mips/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -12,6 +12,8 @@
12#ifndef __ASM_CPU_INFO_H 12#ifndef __ASM_CPU_INFO_H
13#define __ASM_CPU_INFO_H 13#define __ASM_CPU_INFO_H
14 14
15#include <linux/types.h>
16
15#include <asm/cache.h> 17#include <asm/cache.h>
16 18
17/* 19/*
@@ -69,6 +71,10 @@ struct cpuinfo_mips {
69 int tc_id; /* Thread Context number */ 71 int tc_id; /* Thread Context number */
70#endif 72#endif
71 void *data; /* Additional data */ 73 void *data; /* Additional data */
74 unsigned int watch_reg_count; /* Number that exist */
75 unsigned int watch_reg_use_cnt; /* Usable by ptrace */
76#define NUM_WATCH_REGS 4
77 u16 watch_reg_masks[NUM_WATCH_REGS];
72} __attribute__((aligned(SMP_CACHE_BYTES))); 78} __attribute__((aligned(SMP_CACHE_BYTES)));
73 79
74extern struct cpuinfo_mips cpu_data[]; 80extern struct cpuinfo_mips cpu_data[];
diff --git a/include/asm-mips/cpu.h b/arch/mips/include/asm/cpu.h
index 229a786101d9..229a786101d9 100644
--- a/include/asm-mips/cpu.h
+++ b/arch/mips/include/asm/cpu.h
diff --git a/include/asm-mips/cputime.h b/arch/mips/include/asm/cputime.h
index c00eacbdd979..c00eacbdd979 100644
--- a/include/asm-mips/cputime.h
+++ b/arch/mips/include/asm/cputime.h
diff --git a/include/asm-mips/current.h b/arch/mips/include/asm/current.h
index 559db66b9790..559db66b9790 100644
--- a/include/asm-mips/current.h
+++ b/arch/mips/include/asm/current.h
diff --git a/include/asm-mips/debug.h b/arch/mips/include/asm/debug.h
index 1fd5a2b39445..1fd5a2b39445 100644
--- a/include/asm-mips/debug.h
+++ b/arch/mips/include/asm/debug.h
diff --git a/include/asm-mips/dec/ecc.h b/arch/mips/include/asm/dec/ecc.h
index 707ffdbc9add..707ffdbc9add 100644
--- a/include/asm-mips/dec/ecc.h
+++ b/arch/mips/include/asm/dec/ecc.h
diff --git a/include/asm-mips/dec/interrupts.h b/arch/mips/include/asm/dec/interrupts.h
index e10d341067c8..e10d341067c8 100644
--- a/include/asm-mips/dec/interrupts.h
+++ b/arch/mips/include/asm/dec/interrupts.h
diff --git a/include/asm-mips/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h
index 98badd6bf22d..98badd6bf22d 100644
--- a/include/asm-mips/dec/ioasic.h
+++ b/arch/mips/include/asm/dec/ioasic.h
diff --git a/include/asm-mips/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h
index 4cbc1f8a1129..4cbc1f8a1129 100644
--- a/include/asm-mips/dec/ioasic_addrs.h
+++ b/arch/mips/include/asm/dec/ioasic_addrs.h
diff --git a/include/asm-mips/dec/ioasic_ints.h b/arch/mips/include/asm/dec/ioasic_ints.h
index 9aaa9869615f..9aaa9869615f 100644
--- a/include/asm-mips/dec/ioasic_ints.h
+++ b/arch/mips/include/asm/dec/ioasic_ints.h
diff --git a/include/asm-mips/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
index 28fa717ac423..28fa717ac423 100644
--- a/include/asm-mips/dec/kn01.h
+++ b/arch/mips/include/asm/dec/kn01.h
diff --git a/include/asm-mips/dec/kn02.h b/arch/mips/include/asm/dec/kn02.h
index 93430b5f4724..93430b5f4724 100644
--- a/include/asm-mips/dec/kn02.h
+++ b/arch/mips/include/asm/dec/kn02.h
diff --git a/include/asm-mips/dec/kn02ba.h b/arch/mips/include/asm/dec/kn02ba.h
index c957a4f1b32d..c957a4f1b32d 100644
--- a/include/asm-mips/dec/kn02ba.h
+++ b/arch/mips/include/asm/dec/kn02ba.h
diff --git a/include/asm-mips/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h
index 92c0fe256099..92c0fe256099 100644
--- a/include/asm-mips/dec/kn02ca.h
+++ b/arch/mips/include/asm/dec/kn02ca.h
diff --git a/include/asm-mips/dec/kn02xa.h b/arch/mips/include/asm/dec/kn02xa.h
index b56b4577f6ef..b56b4577f6ef 100644
--- a/include/asm-mips/dec/kn02xa.h
+++ b/arch/mips/include/asm/dec/kn02xa.h
diff --git a/include/asm-mips/dec/kn03.h b/arch/mips/include/asm/dec/kn03.h
index edede923ffb8..edede923ffb8 100644
--- a/include/asm-mips/dec/kn03.h
+++ b/arch/mips/include/asm/dec/kn03.h
diff --git a/include/asm-mips/dec/kn05.h b/arch/mips/include/asm/dec/kn05.h
index 56d22dc8803a..56d22dc8803a 100644
--- a/include/asm-mips/dec/kn05.h
+++ b/arch/mips/include/asm/dec/kn05.h
diff --git a/include/asm-mips/dec/kn230.h b/arch/mips/include/asm/dec/kn230.h
index ff1bf17de8d8..ff1bf17de8d8 100644
--- a/include/asm-mips/dec/kn230.h
+++ b/arch/mips/include/asm/dec/kn230.h
diff --git a/include/asm-mips/dec/machtype.h b/arch/mips/include/asm/dec/machtype.h
index a6ecdebc430a..a6ecdebc430a 100644
--- a/include/asm-mips/dec/machtype.h
+++ b/arch/mips/include/asm/dec/machtype.h
diff --git a/include/asm-mips/dec/prom.h b/arch/mips/include/asm/dec/prom.h
index b9c8203688d5..b9c8203688d5 100644
--- a/include/asm-mips/dec/prom.h
+++ b/arch/mips/include/asm/dec/prom.h
diff --git a/include/asm-mips/dec/system.h b/arch/mips/include/asm/dec/system.h
index b2afaccd6831..b2afaccd6831 100644
--- a/include/asm-mips/dec/system.h
+++ b/arch/mips/include/asm/dec/system.h
diff --git a/include/asm-mips/delay.h b/arch/mips/include/asm/delay.h
index b0bccd2c4ed5..b0bccd2c4ed5 100644
--- a/include/asm-mips/delay.h
+++ b/arch/mips/include/asm/delay.h
diff --git a/include/asm-mips/device.h b/arch/mips/include/asm/device.h
index d8f9872b0e2d..d8f9872b0e2d 100644
--- a/include/asm-mips/device.h
+++ b/arch/mips/include/asm/device.h
diff --git a/include/asm-mips/div64.h b/arch/mips/include/asm/div64.h
index d1d699105c11..d1d699105c11 100644
--- a/include/asm-mips/div64.h
+++ b/arch/mips/include/asm/div64.h
diff --git a/include/asm-mips/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index c64afb40cd06..c64afb40cd06 100644
--- a/include/asm-mips/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
diff --git a/include/asm-mips/dma.h b/arch/mips/include/asm/dma.h
index 1353c81065d1..1353c81065d1 100644
--- a/include/asm-mips/dma.h
+++ b/arch/mips/include/asm/dma.h
diff --git a/include/asm-mips/ds1286.h b/arch/mips/include/asm/ds1286.h
index 6983b6ff0af3..6983b6ff0af3 100644
--- a/include/asm-mips/ds1286.h
+++ b/arch/mips/include/asm/ds1286.h
diff --git a/include/asm-mips/ds1287.h b/arch/mips/include/asm/ds1287.h
index ba1702e86931..ba1702e86931 100644
--- a/include/asm-mips/ds1287.h
+++ b/arch/mips/include/asm/ds1287.h
diff --git a/include/asm-mips/dsp.h b/arch/mips/include/asm/dsp.h
index e9bfc0813c72..e9bfc0813c72 100644
--- a/include/asm-mips/dsp.h
+++ b/arch/mips/include/asm/dsp.h
diff --git a/include/asm-mips/edac.h b/arch/mips/include/asm/edac.h
index 4da0c1fe30d9..4da0c1fe30d9 100644
--- a/include/asm-mips/edac.h
+++ b/arch/mips/include/asm/edac.h
diff --git a/include/asm-mips/elf.h b/arch/mips/include/asm/elf.h
index f69f7acba637..f69f7acba637 100644
--- a/include/asm-mips/elf.h
+++ b/arch/mips/include/asm/elf.h
diff --git a/include/asm-mips/emergency-restart.h b/arch/mips/include/asm/emergency-restart.h
index 108d8c48e42e..108d8c48e42e 100644
--- a/include/asm-mips/emergency-restart.h
+++ b/arch/mips/include/asm/emergency-restart.h
diff --git a/include/asm-mips/emma2rh/emma2rh.h b/arch/mips/include/asm/emma2rh/emma2rh.h
index 6a1af0af51e3..6a1af0af51e3 100644
--- a/include/asm-mips/emma2rh/emma2rh.h
+++ b/arch/mips/include/asm/emma2rh/emma2rh.h
diff --git a/include/asm-mips/emma2rh/markeins.h b/arch/mips/include/asm/emma2rh/markeins.h
index 973b0628490d..973b0628490d 100644
--- a/include/asm-mips/emma2rh/markeins.h
+++ b/arch/mips/include/asm/emma2rh/markeins.h
diff --git a/include/asm-mips/errno.h b/arch/mips/include/asm/errno.h
index 3c0d840e4577..3c0d840e4577 100644
--- a/include/asm-mips/errno.h
+++ b/arch/mips/include/asm/errno.h
diff --git a/include/asm-mips/fb.h b/arch/mips/include/asm/fb.h
index bd3f68c9ddfc..bd3f68c9ddfc 100644
--- a/include/asm-mips/fb.h
+++ b/arch/mips/include/asm/fb.h
diff --git a/include/asm-mips/fcntl.h b/arch/mips/include/asm/fcntl.h
index 2a52333a062d..2a52333a062d 100644
--- a/include/asm-mips/fcntl.h
+++ b/arch/mips/include/asm/fcntl.h
diff --git a/include/asm-mips/fixmap.h b/arch/mips/include/asm/fixmap.h
index 9cc8522a394f..9cc8522a394f 100644
--- a/include/asm-mips/fixmap.h
+++ b/arch/mips/include/asm/fixmap.h
diff --git a/include/asm-mips/floppy.h b/arch/mips/include/asm/floppy.h
index 992d232adc83..992d232adc83 100644
--- a/include/asm-mips/floppy.h
+++ b/arch/mips/include/asm/floppy.h
diff --git a/include/asm-mips/fpregdef.h b/arch/mips/include/asm/fpregdef.h
index 2b5fddc8f487..2b5fddc8f487 100644
--- a/include/asm-mips/fpregdef.h
+++ b/arch/mips/include/asm/fpregdef.h
diff --git a/include/asm-mips/fpu.h b/arch/mips/include/asm/fpu.h
index 8a3ef247659a..8a3ef247659a 100644
--- a/include/asm-mips/fpu.h
+++ b/arch/mips/include/asm/fpu.h
diff --git a/include/asm-mips/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index 2731c38bd7ae..2731c38bd7ae 100644
--- a/include/asm-mips/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
diff --git a/include/asm-mips/futex.h b/arch/mips/include/asm/futex.h
index b9cce90346cf..b9cce90346cf 100644
--- a/include/asm-mips/futex.h
+++ b/arch/mips/include/asm/futex.h
diff --git a/include/asm-mips/fw/arc/hinv.h b/arch/mips/include/asm/fw/arc/hinv.h
index e6ff4add04e2..e6ff4add04e2 100644
--- a/include/asm-mips/fw/arc/hinv.h
+++ b/arch/mips/include/asm/fw/arc/hinv.h
diff --git a/include/asm-mips/fw/arc/types.h b/arch/mips/include/asm/fw/arc/types.h
index b9adcd6f0860..b9adcd6f0860 100644
--- a/include/asm-mips/fw/arc/types.h
+++ b/arch/mips/include/asm/fw/arc/types.h
diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h
index 0995575db320..0995575db320 100644
--- a/include/asm-mips/fw/cfe/cfe_api.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_api.h
diff --git a/include/asm-mips/fw/cfe/cfe_error.h b/arch/mips/include/asm/fw/cfe/cfe_error.h
index b80374636279..b80374636279 100644
--- a/include/asm-mips/fw/cfe/cfe_error.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_error.h
diff --git a/include/asm-mips/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h
index d74a8a4ca861..d74a8a4ca861 100644
--- a/include/asm-mips/gcmpregs.h
+++ b/arch/mips/include/asm/gcmpregs.h
diff --git a/include/asm-mips/gic.h b/arch/mips/include/asm/gic.h
index 954807d9d66a..954807d9d66a 100644
--- a/include/asm-mips/gic.h
+++ b/arch/mips/include/asm/gic.h
diff --git a/include/asm-mips/gpio.h b/arch/mips/include/asm/gpio.h
index 06e46faf862d..06e46faf862d 100644
--- a/include/asm-mips/gpio.h
+++ b/arch/mips/include/asm/gpio.h
diff --git a/include/asm-mips/gt64120.h b/arch/mips/include/asm/gt64120.h
index e64b41093c49..e64b41093c49 100644
--- a/include/asm-mips/gt64120.h
+++ b/arch/mips/include/asm/gt64120.h
diff --git a/include/asm-mips/hardirq.h b/arch/mips/include/asm/hardirq.h
index 90bf399e6dd9..90bf399e6dd9 100644
--- a/include/asm-mips/hardirq.h
+++ b/arch/mips/include/asm/hardirq.h
diff --git a/include/asm-mips/hazards.h b/arch/mips/include/asm/hazards.h
index 2de638f84c86..2de638f84c86 100644
--- a/include/asm-mips/hazards.h
+++ b/arch/mips/include/asm/hazards.h
diff --git a/include/asm-mips/highmem.h b/arch/mips/include/asm/highmem.h
index 4374ab2adc75..4374ab2adc75 100644
--- a/include/asm-mips/highmem.h
+++ b/arch/mips/include/asm/highmem.h
diff --git a/include/asm-mips/hw_irq.h b/arch/mips/include/asm/hw_irq.h
index aca05a43a97b..aca05a43a97b 100644
--- a/include/asm-mips/hw_irq.h
+++ b/arch/mips/include/asm/hw_irq.h
diff --git a/include/asm-mips/i8253.h b/arch/mips/include/asm/i8253.h
index 5dabc870b322..5dabc870b322 100644
--- a/include/asm-mips/i8253.h
+++ b/arch/mips/include/asm/i8253.h
diff --git a/include/asm-mips/i8259.h b/arch/mips/include/asm/i8259.h
index 8572a2d90484..8572a2d90484 100644
--- a/include/asm-mips/i8259.h
+++ b/arch/mips/include/asm/i8259.h
diff --git a/include/asm-mips/ide.h b/arch/mips/include/asm/ide.h
index bb674c3b0303..bb674c3b0303 100644
--- a/include/asm-mips/ide.h
+++ b/arch/mips/include/asm/ide.h
diff --git a/include/asm-mips/inst.h b/arch/mips/include/asm/inst.h
index 6489f00731ca..6489f00731ca 100644
--- a/include/asm-mips/inst.h
+++ b/arch/mips/include/asm/inst.h
diff --git a/include/asm-mips/io.h b/arch/mips/include/asm/io.h
index 501a40b9f18d..501a40b9f18d 100644
--- a/include/asm-mips/io.h
+++ b/arch/mips/include/asm/io.h
diff --git a/include/asm-mips/ioctl.h b/arch/mips/include/asm/ioctl.h
index 85067e248a83..85067e248a83 100644
--- a/include/asm-mips/ioctl.h
+++ b/arch/mips/include/asm/ioctl.h
diff --git a/include/asm-mips/ioctls.h b/arch/mips/include/asm/ioctls.h
index 3f04a995ec54..3f04a995ec54 100644
--- a/include/asm-mips/ioctls.h
+++ b/arch/mips/include/asm/ioctls.h
diff --git a/include/asm-mips/ip32/crime.h b/arch/mips/include/asm/ip32/crime.h
index 7c36b0e5b1c6..7c36b0e5b1c6 100644
--- a/include/asm-mips/ip32/crime.h
+++ b/arch/mips/include/asm/ip32/crime.h
diff --git a/include/asm-mips/ip32/ip32_ints.h b/arch/mips/include/asm/ip32/ip32_ints.h
index 85bc5302bce0..85bc5302bce0 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/arch/mips/include/asm/ip32/ip32_ints.h
diff --git a/include/asm-mips/ip32/mace.h b/arch/mips/include/asm/ip32/mace.h
index d08d7c672139..d08d7c672139 100644
--- a/include/asm-mips/ip32/mace.h
+++ b/arch/mips/include/asm/ip32/mace.h
diff --git a/include/asm-mips/ipcbuf.h b/arch/mips/include/asm/ipcbuf.h
index d47d08f264e7..d47d08f264e7 100644
--- a/include/asm-mips/ipcbuf.h
+++ b/arch/mips/include/asm/ipcbuf.h
diff --git a/include/asm-mips/irq.h b/arch/mips/include/asm/irq.h
index a58f0eecc68f..a58f0eecc68f 100644
--- a/include/asm-mips/irq.h
+++ b/arch/mips/include/asm/irq.h
diff --git a/include/asm-mips/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
index ef6a07cddb23..ef6a07cddb23 100644
--- a/include/asm-mips/irq_cpu.h
+++ b/arch/mips/include/asm/irq_cpu.h
diff --git a/include/asm-mips/irq_gt641xx.h b/arch/mips/include/asm/irq_gt641xx.h
index f9a7c3ac2e66..f9a7c3ac2e66 100644
--- a/include/asm-mips/irq_gt641xx.h
+++ b/arch/mips/include/asm/irq_gt641xx.h
diff --git a/include/asm-mips/irq_regs.h b/arch/mips/include/asm/irq_regs.h
index 33bd2a06de57..33bd2a06de57 100644
--- a/include/asm-mips/irq_regs.h
+++ b/arch/mips/include/asm/irq_regs.h
diff --git a/include/asm-mips/irqflags.h b/arch/mips/include/asm/irqflags.h
index 701ec0ba8fa9..701ec0ba8fa9 100644
--- a/include/asm-mips/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
diff --git a/include/asm-mips/isadep.h b/arch/mips/include/asm/isadep.h
index 24c6cda79377..24c6cda79377 100644
--- a/include/asm-mips/isadep.h
+++ b/arch/mips/include/asm/isadep.h
diff --git a/include/asm-mips/jazz.h b/arch/mips/include/asm/jazz.h
index 83f449dec95e..83f449dec95e 100644
--- a/include/asm-mips/jazz.h
+++ b/arch/mips/include/asm/jazz.h
diff --git a/include/asm-mips/jazzdma.h b/arch/mips/include/asm/jazzdma.h
index 8bb37bba68f0..8bb37bba68f0 100644
--- a/include/asm-mips/jazzdma.h
+++ b/arch/mips/include/asm/jazzdma.h
diff --git a/include/asm-mips/kdebug.h b/arch/mips/include/asm/kdebug.h
index 5bf62aafc890..5bf62aafc890 100644
--- a/include/asm-mips/kdebug.h
+++ b/arch/mips/include/asm/kdebug.h
diff --git a/include/asm-mips/kexec.h b/arch/mips/include/asm/kexec.h
index 4314892aaebb..4314892aaebb 100644
--- a/include/asm-mips/kexec.h
+++ b/arch/mips/include/asm/kexec.h
diff --git a/include/asm-mips/kgdb.h b/arch/mips/include/asm/kgdb.h
index 48223b09396c..48223b09396c 100644
--- a/include/asm-mips/kgdb.h
+++ b/arch/mips/include/asm/kgdb.h
diff --git a/include/asm-mips/kmap_types.h b/arch/mips/include/asm/kmap_types.h
index 806aae3c5338..806aae3c5338 100644
--- a/include/asm-mips/kmap_types.h
+++ b/arch/mips/include/asm/kmap_types.h
diff --git a/include/asm-mips/kspd.h b/arch/mips/include/asm/kspd.h
index 4e9e724c8935..4e9e724c8935 100644
--- a/include/asm-mips/kspd.h
+++ b/arch/mips/include/asm/kspd.h
diff --git a/include/asm-mips/lasat/ds1603.h b/arch/mips/include/asm/lasat/ds1603.h
index edcd7544b358..edcd7544b358 100644
--- a/include/asm-mips/lasat/ds1603.h
+++ b/arch/mips/include/asm/lasat/ds1603.h
diff --git a/include/asm-mips/lasat/eeprom.h b/arch/mips/include/asm/lasat/eeprom.h
index 3dac203697fa..3dac203697fa 100644
--- a/include/asm-mips/lasat/eeprom.h
+++ b/arch/mips/include/asm/lasat/eeprom.h
diff --git a/include/asm-mips/lasat/head.h b/arch/mips/include/asm/lasat/head.h
index f5589f31a197..f5589f31a197 100644
--- a/include/asm-mips/lasat/head.h
+++ b/arch/mips/include/asm/lasat/head.h
diff --git a/include/asm-mips/lasat/lasat.h b/arch/mips/include/asm/lasat/lasat.h
index caeba1e302a2..caeba1e302a2 100644
--- a/include/asm-mips/lasat/lasat.h
+++ b/arch/mips/include/asm/lasat/lasat.h
diff --git a/include/asm-mips/lasat/lasatint.h b/arch/mips/include/asm/lasat/lasatint.h
index e0d2458b43d0..e0d2458b43d0 100644
--- a/include/asm-mips/lasat/lasatint.h
+++ b/arch/mips/include/asm/lasat/lasatint.h
diff --git a/include/asm-mips/lasat/picvue.h b/arch/mips/include/asm/lasat/picvue.h
index 42a492edc40e..42a492edc40e 100644
--- a/include/asm-mips/lasat/picvue.h
+++ b/arch/mips/include/asm/lasat/picvue.h
diff --git a/include/asm-mips/lasat/serial.h b/arch/mips/include/asm/lasat/serial.h
index 1c37d70579b8..1c37d70579b8 100644
--- a/include/asm-mips/lasat/serial.h
+++ b/arch/mips/include/asm/lasat/serial.h
diff --git a/include/asm-mips/linkage.h b/arch/mips/include/asm/linkage.h
index e9a940d1b0c6..e9a940d1b0c6 100644
--- a/include/asm-mips/linkage.h
+++ b/arch/mips/include/asm/linkage.h
diff --git a/include/asm-mips/local.h b/arch/mips/include/asm/local.h
index f96fd59e0845..f96fd59e0845 100644
--- a/include/asm-mips/local.h
+++ b/arch/mips/include/asm/local.h
diff --git a/include/asm-mips/m48t35.h b/arch/mips/include/asm/m48t35.h
index f44852e9a96d..f44852e9a96d 100644
--- a/include/asm-mips/m48t35.h
+++ b/arch/mips/include/asm/m48t35.h
diff --git a/include/asm-mips/m48t37.h b/arch/mips/include/asm/m48t37.h
index cabf86264f36..cabf86264f36 100644
--- a/include/asm-mips/m48t37.h
+++ b/arch/mips/include/asm/m48t37.h
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 0d302bad4492..0d302bad4492 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
diff --git a/include/asm-mips/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
index c333b4e1cd44..c333b4e1cd44 100644
--- a/include/asm-mips/mach-au1x00/au1000_dma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
diff --git a/include/asm-mips/mach-au1x00/au1000_gpio.h b/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
index d8c96fda5549..d8c96fda5549 100644
--- a/include/asm-mips/mach-au1x00/au1000_gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index c35e20918490..c35e20918490 100644
--- a/include/asm-mips/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/arch/mips/include/asm/mach-au1x00/au1550_spi.h
index 08e1958e9410..08e1958e9410 100644
--- a/include/asm-mips/mach-au1x00/au1550_spi.h
+++ b/arch/mips/include/asm/mach-au1x00/au1550_spi.h
diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h
index 1b3655090ed3..1b3655090ed3 100644
--- a/include/asm-mips/mach-au1x00/au1xxx.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx.h
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 44a67bf05dc1..44a67bf05dc1 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
index 60638b8969ba..60638b8969ba 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
index 892b7f168eb4..892b7f168eb4 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
diff --git a/include/asm-mips/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index 2dc61e009a08..2dc61e009a08 100644
--- a/include/asm-mips/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h
index 364cea2dc71f..364cea2dc71f 100644
--- a/include/asm-mips/mach-au1x00/ioremap.h
+++ b/arch/mips/include/asm/mach-au1x00/ioremap.h
diff --git a/include/asm-mips/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h
index e38715577c51..e38715577c51 100644
--- a/include/asm-mips/mach-au1x00/prom.h
+++ b/arch/mips/include/asm/mach-au1x00/prom.h
diff --git a/include/asm-mips/mach-au1x00/war.h b/arch/mips/include/asm/mach-au1x00/war.h
index dd57d03d68ba..dd57d03d68ba 100644
--- a/include/asm-mips/mach-au1x00/war.h
+++ b/arch/mips/include/asm/mach-au1x00/war.h
diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index d008f47a28bd..d008f47a28bd 100644
--- a/include/asm-mips/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
index cfc8f4d618ce..cfc8f4d618ce 100644
--- a/include/asm-mips/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
diff --git a/include/asm-mips/mach-bcm47xx/war.h b/arch/mips/include/asm/mach-bcm47xx/war.h
index 4a2b7986b582..4a2b7986b582 100644
--- a/include/asm-mips/mach-bcm47xx/war.h
+++ b/arch/mips/include/asm/mach-bcm47xx/war.h
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/arch/mips/include/asm/mach-cobalt/cobalt.h
index 5b9fce73f11d..5b9fce73f11d 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/arch/mips/include/asm/mach-cobalt/cobalt.h
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
index b3314cf53194..b3314cf53194 100644
--- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-cobalt/irq.h b/arch/mips/include/asm/mach-cobalt/irq.h
index 57c8c9ac5851..57c8c9ac5851 100644
--- a/include/asm-mips/mach-cobalt/irq.h
+++ b/arch/mips/include/asm/mach-cobalt/irq.h
diff --git a/include/asm-mips/mach-cobalt/mach-gt64120.h b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
index ae9c5523c7ef..ae9c5523c7ef 100644
--- a/include/asm-mips/mach-cobalt/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
diff --git a/include/asm-mips/mach-cobalt/war.h b/arch/mips/include/asm/mach-cobalt/war.h
index 97884fd18ac0..97884fd18ac0 100644
--- a/include/asm-mips/mach-cobalt/war.h
+++ b/arch/mips/include/asm/mach-cobalt/war.h
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 27f26102b1bb..27f26102b1bb 100644
--- a/include/asm-mips/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index 1a515b8c870f..1a515b8c870f 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/arch/mips/include/asm/mach-dec/mc146818rtc.h
index 6724e99e43e1..6724e99e43e1 100644
--- a/include/asm-mips/mach-dec/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-dec/mc146818rtc.h
diff --git a/include/asm-mips/mach-dec/war.h b/arch/mips/include/asm/mach-dec/war.h
index ca5e2ef909ad..ca5e2ef909ad 100644
--- a/include/asm-mips/mach-dec/war.h
+++ b/arch/mips/include/asm/mach-dec/war.h
diff --git a/include/asm-mips/mach-emma2rh/irq.h b/arch/mips/include/asm/mach-emma2rh/irq.h
index 5439eb856461..5439eb856461 100644
--- a/include/asm-mips/mach-emma2rh/irq.h
+++ b/arch/mips/include/asm/mach-emma2rh/irq.h
diff --git a/include/asm-mips/mach-emma2rh/war.h b/arch/mips/include/asm/mach-emma2rh/war.h
index b660a4c30e6a..b660a4c30e6a 100644
--- a/include/asm-mips/mach-emma2rh/war.h
+++ b/arch/mips/include/asm/mach-emma2rh/war.h
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
index 107104c3cd12..107104c3cd12 100644
--- a/include/asm-mips/mach-excite/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h
index 4c29ba44992c..4c29ba44992c 100644
--- a/include/asm-mips/mach-excite/excite.h
+++ b/arch/mips/include/asm/mach-excite/excite.h
diff --git a/include/asm-mips/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h
index 0a1ef69bece7..0a1ef69bece7 100644
--- a/include/asm-mips/mach-excite/excite_fpga.h
+++ b/arch/mips/include/asm/mach-excite/excite_fpga.h
diff --git a/include/asm-mips/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h
index c4cf6140622e..c4cf6140622e 100644
--- a/include/asm-mips/mach-excite/excite_nandflash.h
+++ b/arch/mips/include/asm/mach-excite/excite_nandflash.h
diff --git a/include/asm-mips/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h
index 94705a46f72e..94705a46f72e 100644
--- a/include/asm-mips/mach-excite/rm9k_eth.h
+++ b/arch/mips/include/asm/mach-excite/rm9k_eth.h
diff --git a/include/asm-mips/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
index 3fa3c08d2da7..3fa3c08d2da7 100644
--- a/include/asm-mips/mach-excite/rm9k_wdt.h
+++ b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
diff --git a/include/asm-mips/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
index 009577734a8d..009577734a8d 100644
--- a/include/asm-mips/mach-excite/rm9k_xicap.h
+++ b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
diff --git a/include/asm-mips/mach-excite/war.h b/arch/mips/include/asm/mach-excite/war.h
index 1f82180c1598..1f82180c1598 100644
--- a/include/asm-mips/mach-excite/war.h
+++ b/arch/mips/include/asm/mach-excite/war.h
diff --git a/include/asm-mips/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
index 7c185bb06f13..7c185bb06f13 100644
--- a/include/asm-mips/mach-generic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 76e04e7feb84..76e04e7feb84 100644
--- a/include/asm-mips/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
diff --git a/include/asm-mips/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index 001a8ce17c17..001a8ce17c17 100644
--- a/include/asm-mips/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
diff --git a/include/asm-mips/mach-generic/gpio.h b/arch/mips/include/asm/mach-generic/gpio.h
index b4e70208da64..b4e70208da64 100644
--- a/include/asm-mips/mach-generic/gpio.h
+++ b/arch/mips/include/asm/mach-generic/gpio.h
diff --git a/include/asm-mips/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h
index 73008f7bdc93..73008f7bdc93 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/arch/mips/include/asm/mach-generic/ide.h
diff --git a/include/asm-mips/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h
index b379938d47f0..b379938d47f0 100644
--- a/include/asm-mips/mach-generic/ioremap.h
+++ b/arch/mips/include/asm/mach-generic/ioremap.h
diff --git a/include/asm-mips/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index 70d9a25132c5..70d9a25132c5 100644
--- a/include/asm-mips/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
diff --git a/include/asm-mips/mach-generic/kernel-entry-init.h b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
index 7e66505fa574..7e66505fa574 100644
--- a/include/asm-mips/mach-generic/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
diff --git a/include/asm-mips/mach-generic/kmalloc.h b/arch/mips/include/asm/mach-generic/kmalloc.h
index b8e6deba352f..b8e6deba352f 100644
--- a/include/asm-mips/mach-generic/kmalloc.h
+++ b/arch/mips/include/asm/mach-generic/kmalloc.h
diff --git a/include/asm-mips/mach-generic/mangle-port.h b/arch/mips/include/asm/mach-generic/mangle-port.h
index f49dc990214b..f49dc990214b 100644
--- a/include/asm-mips/mach-generic/mangle-port.h
+++ b/arch/mips/include/asm/mach-generic/mangle-port.h
diff --git a/include/asm-mips/mach-generic/mc146818rtc.h b/arch/mips/include/asm/mach-generic/mc146818rtc.h
index 0b9a942f079d..0b9a942f079d 100644
--- a/include/asm-mips/mach-generic/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-generic/mc146818rtc.h
diff --git a/include/asm-mips/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index c9fa4b14968d..c9fa4b14968d 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
diff --git a/include/asm-mips/mach-generic/topology.h b/arch/mips/include/asm/mach-generic/topology.h
index 5428f333a02c..5428f333a02c 100644
--- a/include/asm-mips/mach-generic/topology.h
+++ b/arch/mips/include/asm/mach-generic/topology.h
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
index 9c8735158da1..9c8735158da1 100644
--- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-ip22/ds1286.h b/arch/mips/include/asm/mach-ip22/ds1286.h
index f19f1eafbc71..f19f1eafbc71 100644
--- a/include/asm-mips/mach-ip22/ds1286.h
+++ b/arch/mips/include/asm/mach-ip22/ds1286.h
diff --git a/include/asm-mips/mach-ip22/spaces.h b/arch/mips/include/asm/mach-ip22/spaces.h
index 7f9fa6f66059..7f9fa6f66059 100644
--- a/include/asm-mips/mach-ip22/spaces.h
+++ b/arch/mips/include/asm/mach-ip22/spaces.h
diff --git a/include/asm-mips/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index a44fa9656a82..a44fa9656a82 100644
--- a/include/asm-mips/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
index 7d3112b148d9..7d3112b148d9 100644
--- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index ed7e6222dc15..ed7e6222dc15 100644
--- a/include/asm-mips/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
diff --git a/include/asm-mips/mach-ip27/irq.h b/arch/mips/include/asm/mach-ip27/irq.h
index cf4384bfa846..cf4384bfa846 100644
--- a/include/asm-mips/mach-ip27/irq.h
+++ b/arch/mips/include/asm/mach-ip27/irq.h
diff --git a/include/asm-mips/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
index 624d66c7f290..624d66c7f290 100644
--- a/include/asm-mips/mach-ip27/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
diff --git a/include/asm-mips/mach-ip27/kmalloc.h b/arch/mips/include/asm/mach-ip27/kmalloc.h
index 426bd049b2d7..426bd049b2d7 100644
--- a/include/asm-mips/mach-ip27/kmalloc.h
+++ b/arch/mips/include/asm/mach-ip27/kmalloc.h
diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/arch/mips/include/asm/mach-ip27/mangle-port.h
index f6e4912ea062..f6e4912ea062 100644
--- a/include/asm-mips/mach-ip27/mangle-port.h
+++ b/arch/mips/include/asm/mach-ip27/mangle-port.h
diff --git a/include/asm-mips/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h
index 986a3b9b59a7..986a3b9b59a7 100644
--- a/include/asm-mips/mach-ip27/mmzone.h
+++ b/arch/mips/include/asm/mach-ip27/mmzone.h
diff --git a/include/asm-mips/mach-ip27/spaces.h b/arch/mips/include/asm/mach-ip27/spaces.h
index b18802a0b17e..b18802a0b17e 100644
--- a/include/asm-mips/mach-ip27/spaces.h
+++ b/arch/mips/include/asm/mach-ip27/spaces.h
diff --git a/include/asm-mips/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index 7785bec732f2..7785bec732f2 100644
--- a/include/asm-mips/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
diff --git a/include/asm-mips/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index e2ddcc9b1fff..e2ddcc9b1fff 100644
--- a/include/asm-mips/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
diff --git a/include/asm-mips/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
index 9a53b326f848..9a53b326f848 100644
--- a/include/asm-mips/mach-ip28/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-ip28/ds1286.h b/arch/mips/include/asm/mach-ip28/ds1286.h
index 471bb9a33e0f..471bb9a33e0f 100644
--- a/include/asm-mips/mach-ip28/ds1286.h
+++ b/arch/mips/include/asm/mach-ip28/ds1286.h
diff --git a/include/asm-mips/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h
index 05aabb27e5e7..05aabb27e5e7 100644
--- a/include/asm-mips/mach-ip28/spaces.h
+++ b/arch/mips/include/asm/mach-ip28/spaces.h
diff --git a/include/asm-mips/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index a1baafab486a..a1baafab486a 100644
--- a/include/asm-mips/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
index 6782fccebe8d..6782fccebe8d 100644
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index a5511ebb2d53..a5511ebb2d53 100644
--- a/include/asm-mips/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/arch/mips/include/asm/mach-ip32/kmalloc.h
index b1e0be60f720..b1e0be60f720 100644
--- a/include/asm-mips/mach-ip32/kmalloc.h
+++ b/arch/mips/include/asm/mach-ip32/kmalloc.h
diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/arch/mips/include/asm/mach-ip32/mangle-port.h
index f1d0f1756a9f..f1d0f1756a9f 100644
--- a/include/asm-mips/mach-ip32/mangle-port.h
+++ b/arch/mips/include/asm/mach-ip32/mangle-port.h
diff --git a/include/asm-mips/mach-ip32/mc146818rtc.h b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
index c28ba8d84076..c28ba8d84076 100644
--- a/include/asm-mips/mach-ip32/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
diff --git a/include/asm-mips/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index d194056dcd7a..d194056dcd7a 100644
--- a/include/asm-mips/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
diff --git a/include/asm-mips/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index d66979a124a8..d66979a124a8 100644
--- a/include/asm-mips/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
diff --git a/include/asm-mips/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 56e9ca6ae426..56e9ca6ae426 100644
--- a/include/asm-mips/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
diff --git a/include/asm-mips/mach-jazz/mc146818rtc.h b/arch/mips/include/asm/mach-jazz/mc146818rtc.h
index 987f727afe25..987f727afe25 100644
--- a/include/asm-mips/mach-jazz/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-jazz/mc146818rtc.h
diff --git a/include/asm-mips/mach-jazz/war.h b/arch/mips/include/asm/mach-jazz/war.h
index 6158ee861bfd..6158ee861bfd 100644
--- a/include/asm-mips/mach-jazz/war.h
+++ b/arch/mips/include/asm/mach-jazz/war.h
diff --git a/include/asm-mips/mach-lasat/irq.h b/arch/mips/include/asm/mach-lasat/irq.h
index 3a282419d5f9..3a282419d5f9 100644
--- a/include/asm-mips/mach-lasat/irq.h
+++ b/arch/mips/include/asm/mach-lasat/irq.h
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/arch/mips/include/asm/mach-lasat/mach-gt64120.h
index 1a9ad45cc135..1a9ad45cc135 100644
--- a/include/asm-mips/mach-lasat/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-lasat/mach-gt64120.h
diff --git a/include/asm-mips/mach-lasat/war.h b/arch/mips/include/asm/mach-lasat/war.h
index bb1e0325c9be..bb1e0325c9be 100644
--- a/include/asm-mips/mach-lasat/war.h
+++ b/arch/mips/include/asm/mach-lasat/war.h
diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index 7e914777ebc4..7e914777ebc4 100644
--- a/include/asm-mips/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/arch/mips/include/asm/mach-lemote/mc146818rtc.h
index ed5147e11085..ed5147e11085 100644
--- a/include/asm-mips/mach-lemote/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-lemote/mc146818rtc.h
diff --git a/include/asm-mips/mach-lemote/war.h b/arch/mips/include/asm/mach-lemote/war.h
index 05f89e0f2a11..05f89e0f2a11 100644
--- a/include/asm-mips/mach-lemote/war.h
+++ b/arch/mips/include/asm/mach-lemote/war.h
diff --git a/include/asm-mips/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
index 7f3e3f9bd23a..7f3e3f9bd23a 100644
--- a/include/asm-mips/mach-malta/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-malta/irq.h b/arch/mips/include/asm/mach-malta/irq.h
index 9b9da26683c2..9b9da26683c2 100644
--- a/include/asm-mips/mach-malta/irq.h
+++ b/arch/mips/include/asm/mach-malta/irq.h
diff --git a/include/asm-mips/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
index 0b793e7bf67e..0b793e7bf67e 100644
--- a/include/asm-mips/mach-malta/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
diff --git a/include/asm-mips/mach-malta/mach-gt64120.h b/arch/mips/include/asm/mach-malta/mach-gt64120.h
index 0f863148f3b6..0f863148f3b6 100644
--- a/include/asm-mips/mach-malta/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-malta/mach-gt64120.h
diff --git a/include/asm-mips/mach-malta/mc146818rtc.h b/arch/mips/include/asm/mach-malta/mc146818rtc.h
index ea612f37f614..ea612f37f614 100644
--- a/include/asm-mips/mach-malta/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-malta/mc146818rtc.h
diff --git a/include/asm-mips/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 7c6931d5f45f..7c6931d5f45f 100644
--- a/include/asm-mips/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
diff --git a/include/asm-mips/mach-mipssim/cpu-feature-overrides.h b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
index 779b02205737..779b02205737 100644
--- a/include/asm-mips/mach-mipssim/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-mipssim/war.h b/arch/mips/include/asm/mach-mipssim/war.h
index c8a74a3515e0..c8a74a3515e0 100644
--- a/include/asm-mips/mach-mipssim/war.h
+++ b/arch/mips/include/asm/mach-mipssim/war.h
diff --git a/include/asm-mips/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
index 622c58710e5b..622c58710e5b 100644
--- a/include/asm-mips/mach-pb1x00/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
index 6d1ff9060e44..6d1ff9060e44 100644
--- a/include/asm-mips/mach-pb1x00/pb1000.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h
index b1a60f1cbd02..b1a60f1cbd02 100644
--- a/include/asm-mips/mach-pb1x00/pb1100.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1100.h
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index c8618df88cb5..c8618df88cb5 100644
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h
index da51a2eb7b82..da51a2eb7b82 100644
--- a/include/asm-mips/mach-pb1x00/pb1500.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1500.h
diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 6704a11497db..6704a11497db 100644
--- a/include/asm-mips/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
diff --git a/include/asm-mips/mach-pnx8550/cm.h b/arch/mips/include/asm/mach-pnx8550/cm.h
index bb0a56c7d011..bb0a56c7d011 100644
--- a/include/asm-mips/mach-pnx8550/cm.h
+++ b/arch/mips/include/asm/mach-pnx8550/cm.h
diff --git a/include/asm-mips/mach-pnx8550/glb.h b/arch/mips/include/asm/mach-pnx8550/glb.h
index 07aa85e609bc..07aa85e609bc 100644
--- a/include/asm-mips/mach-pnx8550/glb.h
+++ b/arch/mips/include/asm/mach-pnx8550/glb.h
diff --git a/include/asm-mips/mach-pnx8550/int.h b/arch/mips/include/asm/mach-pnx8550/int.h
index 0e0668b524f4..0e0668b524f4 100644
--- a/include/asm-mips/mach-pnx8550/int.h
+++ b/arch/mips/include/asm/mach-pnx8550/int.h
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
index bdde00c9199b..bdde00c9199b 100644
--- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
diff --git a/include/asm-mips/mach-pnx8550/nand.h b/arch/mips/include/asm/mach-pnx8550/nand.h
index aefbc514ab09..aefbc514ab09 100644
--- a/include/asm-mips/mach-pnx8550/nand.h
+++ b/arch/mips/include/asm/mach-pnx8550/nand.h
diff --git a/include/asm-mips/mach-pnx8550/pci.h b/arch/mips/include/asm/mach-pnx8550/pci.h
index b921508d701b..b921508d701b 100644
--- a/include/asm-mips/mach-pnx8550/pci.h
+++ b/arch/mips/include/asm/mach-pnx8550/pci.h
diff --git a/include/asm-mips/mach-pnx8550/uart.h b/arch/mips/include/asm/mach-pnx8550/uart.h
index ad7608d44874..ad7608d44874 100644
--- a/include/asm-mips/mach-pnx8550/uart.h
+++ b/arch/mips/include/asm/mach-pnx8550/uart.h
diff --git a/include/asm-mips/mach-pnx8550/usb.h b/arch/mips/include/asm/mach-pnx8550/usb.h
index 483b7fc65d41..483b7fc65d41 100644
--- a/include/asm-mips/mach-pnx8550/usb.h
+++ b/arch/mips/include/asm/mach-pnx8550/usb.h
diff --git a/include/asm-mips/mach-pnx8550/war.h b/arch/mips/include/asm/mach-pnx8550/war.h
index d0458dd082f9..d0458dd082f9 100644
--- a/include/asm-mips/mach-pnx8550/war.h
+++ b/arch/mips/include/asm/mach-pnx8550/war.h
diff --git a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
index f3bc7efa2608..f3bc7efa2608 100644
--- a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-rc32434/ddr.h b/arch/mips/include/asm/mach-rc32434/ddr.h
index 291e2cf9dde0..291e2cf9dde0 100644
--- a/include/asm-mips/mach-rc32434/ddr.h
+++ b/arch/mips/include/asm/mach-rc32434/ddr.h
diff --git a/include/asm-mips/mach-rc32434/dma.h b/arch/mips/include/asm/mach-rc32434/dma.h
index 5f898b5873f7..5f898b5873f7 100644
--- a/include/asm-mips/mach-rc32434/dma.h
+++ b/arch/mips/include/asm/mach-rc32434/dma.h
diff --git a/include/asm-mips/mach-rc32434/dma_v.h b/arch/mips/include/asm/mach-rc32434/dma_v.h
index 173a9f9146cd..173a9f9146cd 100644
--- a/include/asm-mips/mach-rc32434/dma_v.h
+++ b/arch/mips/include/asm/mach-rc32434/dma_v.h
diff --git a/include/asm-mips/mach-rc32434/eth.h b/arch/mips/include/asm/mach-rc32434/eth.h
index a25cbc56173d..a25cbc56173d 100644
--- a/include/asm-mips/mach-rc32434/eth.h
+++ b/arch/mips/include/asm/mach-rc32434/eth.h
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
index f946f5f45bbb..c8e554eafce3 100644
--- a/include/asm-mips/mach-rc32434/gpio.h
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -14,6 +14,16 @@
14#define _RC32434_GPIO_H_ 14#define _RC32434_GPIO_H_
15 15
16#include <linux/types.h> 16#include <linux/types.h>
17#include <asm-generic/gpio.h>
18
19#define NR_BUILTIN_GPIO 32
20
21#define gpio_get_value __gpio_get_value
22#define gpio_set_value __gpio_set_value
23#define gpio_cansleep __gpio_cansleep
24
25#define gpio_to_irq(gpio) (8 + 4 * 32 + gpio)
26#define irq_to_gpio(irq) (irq - (8 + 4 * 32))
17 27
18struct rb532_gpio_reg { 28struct rb532_gpio_reg {
19 u32 gpiofunc; /* GPIO Function Register 29 u32 gpiofunc; /* GPIO Function Register
@@ -61,66 +71,18 @@ struct rb532_gpio_reg {
61/* PCI messaging unit */ 71/* PCI messaging unit */
62#define RC32434_PCI_MSU_GPIO (1 << 13) 72#define RC32434_PCI_MSU_GPIO (1 << 13)
63 73
74/* NAND GPIO signals */
75#define GPIO_RDY 8
76#define GPIO_WPX 9
77#define GPIO_ALE 10
78#define GPIO_CLE 11
79
80/* Compact Flash GPIO pin */
81#define CF_GPIO_NUM 13
64 82
65extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val); 83extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
66extern unsigned get_434_reg(unsigned reg_offs); 84extern unsigned get_434_reg(unsigned reg_offs);
67extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); 85extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
68extern unsigned char get_latch_u5(void); 86extern unsigned char get_latch_u5(void);
69 87
70extern int rb532_gpio_get_value(unsigned gpio);
71extern void rb532_gpio_set_value(unsigned gpio, int value);
72extern int rb532_gpio_direction_input(unsigned gpio);
73extern int rb532_gpio_direction_output(unsigned gpio, int value);
74extern void rb532_gpio_set_int_level(unsigned gpio, int value);
75extern int rb532_gpio_get_int_level(unsigned gpio);
76extern void rb532_gpio_set_int_status(unsigned gpio, int value);
77extern int rb532_gpio_get_int_status(unsigned gpio);
78
79
80/* Wrappers for the arch-neutral GPIO API */
81
82static inline int gpio_request(unsigned gpio, const char *label)
83{
84 /* Not yet implemented */
85 return 0;
86}
87
88static inline void gpio_free(unsigned gpio)
89{
90 /* Not yet implemented */
91}
92
93static inline int gpio_direction_input(unsigned gpio)
94{
95 return rb532_gpio_direction_input(gpio);
96}
97
98static inline int gpio_direction_output(unsigned gpio, int value)
99{
100 return rb532_gpio_direction_output(gpio, value);
101}
102
103static inline int gpio_get_value(unsigned gpio)
104{
105 return rb532_gpio_get_value(gpio);
106}
107
108static inline void gpio_set_value(unsigned gpio, int value)
109{
110 rb532_gpio_set_value(gpio, value);
111}
112
113static inline int gpio_to_irq(unsigned gpio)
114{
115 return gpio;
116}
117
118static inline int irq_to_gpio(unsigned irq)
119{
120 return irq;
121}
122
123/* For cansleep */
124#include <asm-generic/gpio.h>
125
126#endif /* _RC32434_GPIO_H_ */ 88#endif /* _RC32434_GPIO_H_ */
diff --git a/include/asm-mips/mach-rc32434/integ.h b/arch/mips/include/asm/mach-rc32434/integ.h
index fa65bc3d8807..fa65bc3d8807 100644
--- a/include/asm-mips/mach-rc32434/integ.h
+++ b/arch/mips/include/asm/mach-rc32434/integ.h
diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h
new file mode 100644
index 000000000000..56738d8ec4e2
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/irq.h
@@ -0,0 +1,33 @@
1#ifndef __ASM_RC32434_IRQ_H
2#define __ASM_RC32434_IRQ_H
3
4#define NR_IRQS 256
5
6#include <asm/mach-generic/irq.h>
7#include <asm/mach-rc32434/rb.h>
8
9/* Interrupt Controller */
10#define IC_GROUP0_PEND (REGBASE + 0x38000)
11#define IC_GROUP0_MASK (REGBASE + 0x38008)
12#define IC_GROUP_OFFSET 0x0C
13
14#define NUM_INTR_GROUPS 5
15
16/* 16550 UARTs */
17#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
18 /* GRP3 IRQ numbers start here */
19#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
20 /* GRP4 IRQ numbers start here */
21#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
22 /* GRP5 IRQ numbers start here */
23#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
24#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
25
26#define UART0_IRQ (GROUP3_IRQ_BASE + 0)
27
28#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
29#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
30#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
31#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
32
33#endif /* __ASM_RC32434_IRQ_H */
diff --git a/include/asm-mips/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h
index 410638f2af74..410638f2af74 100644
--- a/include/asm-mips/mach-rc32434/pci.h
+++ b/arch/mips/include/asm/mach-rc32434/pci.h
diff --git a/include/asm-mips/mach-rc32434/prom.h b/arch/mips/include/asm/mach-rc32434/prom.h
index 1d66ddcda89a..660707f1bcce 100644
--- a/include/asm-mips/mach-rc32434/prom.h
+++ b/arch/mips/include/asm/mach-rc32434/prom.h
@@ -28,14 +28,10 @@
28 28
29#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8)) 29#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8))
30 30
31#define GPIO_INIT_NOBUTTON ""
32#define GPIO_INIT_BUTTON " 2"
33
34#define SR_NMI 0x00180000 31#define SR_NMI 0x00180000
35#define SERIAL_SPEED_ENTRY 0x00000001 32#define SERIAL_SPEED_ENTRY 0x00000001
36 33
37#define FREQ_TAG "HZ=" 34#define FREQ_TAG "HZ="
38#define GPIO_TAG "gpio="
39#define KMAC_TAG "kmac=" 35#define KMAC_TAG "kmac="
40#define MEM_TAG "mem=" 36#define MEM_TAG "mem="
41#define BOARD_TAG "board=" 37#define BOARD_TAG "board="
diff --git a/include/asm-mips/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index e0a76e3ffea8..79e8ef67d0d3 100644
--- a/include/asm-mips/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -17,7 +17,10 @@
17 17
18#include <linux/genhd.h> 18#include <linux/genhd.h>
19 19
20#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000)) 20#define REGBASE 0x18000000
21#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
22#define UART0BASE 0x58000
23#define RST (1 << 15)
21#define DEV0BASE 0x010000 24#define DEV0BASE 0x010000
22#define DEV0MASK 0x010004 25#define DEV0MASK 0x010004
23#define DEV0C 0x010008 26#define DEV0C 0x010008
diff --git a/arch/mips/include/asm/mach-rc32434/rc32434.h b/arch/mips/include/asm/mach-rc32434/rc32434.h
new file mode 100644
index 000000000000..fce25d4231fc
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/rc32434.h
@@ -0,0 +1,19 @@
1/*
2 * Definitions for IDT RC323434 CPU.
3 */
4
5#ifndef _ASM_RC32434_RC32434_H_
6#define _ASM_RC32434_RC32434_H_
7
8#include <linux/delay.h>
9#include <linux/io.h>
10
11#define IDT_CLOCK_MULT 2
12
13/* cpu pipeline flush */
14static inline void rc32434_sync(void)
15{
16 __asm__ volatile ("sync");
17}
18
19#endif /* _ASM_RC32434_RC32434_H_ */
diff --git a/include/asm-mips/mach-rc32434/timer.h b/arch/mips/include/asm/mach-rc32434/timer.h
index e49b1d57a017..e49b1d57a017 100644
--- a/include/asm-mips/mach-rc32434/timer.h
+++ b/arch/mips/include/asm/mach-rc32434/timer.h
diff --git a/include/asm-mips/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 3ddf187e98a6..3ddf187e98a6 100644
--- a/include/asm-mips/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
index ccf543363537..ccf543363537 100644
--- a/include/asm-mips/mach-rm/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-rm/mc146818rtc.h b/arch/mips/include/asm/mach-rm/mc146818rtc.h
index 145bce096fe9..145bce096fe9 100644
--- a/include/asm-mips/mach-rm/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-rm/mc146818rtc.h
diff --git a/include/asm-mips/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 948d3129a114..948d3129a114 100644
--- a/include/asm-mips/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
index 1c1f92415b9a..1c1f92415b9a 100644
--- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 7950ef4f032c..7950ef4f032c 100644
--- a/include/asm-mips/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
diff --git a/include/asm-mips/mach-tx39xx/ioremap.h b/arch/mips/include/asm/mach-tx39xx/ioremap.h
index 93c6c04ffda3..93c6c04ffda3 100644
--- a/include/asm-mips/mach-tx39xx/ioremap.h
+++ b/arch/mips/include/asm/mach-tx39xx/ioremap.h
diff --git a/include/asm-mips/mach-tx39xx/mangle-port.h b/arch/mips/include/asm/mach-tx39xx/mangle-port.h
index ef0b502fd8b7..ef0b502fd8b7 100644
--- a/include/asm-mips/mach-tx39xx/mangle-port.h
+++ b/arch/mips/include/asm/mach-tx39xx/mangle-port.h
diff --git a/include/asm-mips/mach-tx39xx/war.h b/arch/mips/include/asm/mach-tx39xx/war.h
index 433814616359..433814616359 100644
--- a/include/asm-mips/mach-tx39xx/war.h
+++ b/arch/mips/include/asm/mach-tx39xx/war.h
diff --git a/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
index 275eaf92c748..275eaf92c748 100644
--- a/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-tx49xx/ioremap.h b/arch/mips/include/asm/mach-tx49xx/ioremap.h
index 1e7beae72229..1e7beae72229 100644
--- a/include/asm-mips/mach-tx49xx/ioremap.h
+++ b/arch/mips/include/asm/mach-tx49xx/ioremap.h
diff --git a/include/asm-mips/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
index 913ff196259d..913ff196259d 100644
--- a/include/asm-mips/mach-tx49xx/kmalloc.h
+++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
diff --git a/include/asm-mips/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 39b5d1177c57..39b5d1177c57 100644
--- a/include/asm-mips/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
diff --git a/include/asm-mips/mach-vr41xx/irq.h b/arch/mips/include/asm/mach-vr41xx/irq.h
index 862058d3f81b..862058d3f81b 100644
--- a/include/asm-mips/mach-vr41xx/irq.h
+++ b/arch/mips/include/asm/mach-vr41xx/irq.h
diff --git a/include/asm-mips/mach-vr41xx/war.h b/arch/mips/include/asm/mach-vr41xx/war.h
index 56a38926412a..56a38926412a 100644
--- a/include/asm-mips/mach-vr41xx/war.h
+++ b/arch/mips/include/asm/mach-vr41xx/war.h
diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
index 83746b84a5ec..83746b84a5ec 100644
--- a/include/asm-mips/mach-wrppmc/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
diff --git a/include/asm-mips/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
index ac48629bb1ce..ac48629bb1ce 100644
--- a/include/asm-mips/mach-wrppmc/war.h
+++ b/arch/mips/include/asm/mach-wrppmc/war.h
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
index 470e5e9e10d6..470e5e9e10d6 100644
--- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-yosemite/war.h b/arch/mips/include/asm/mach-yosemite/war.h
index e5c6d53efc86..e5c6d53efc86 100644
--- a/include/asm-mips/mach-yosemite/war.h
+++ b/arch/mips/include/asm/mach-yosemite/war.h
diff --git a/include/asm-mips/mc146818-time.h b/arch/mips/include/asm/mc146818-time.h
index cdc379a0a94e..cdc379a0a94e 100644
--- a/include/asm-mips/mc146818-time.h
+++ b/arch/mips/include/asm/mc146818-time.h
diff --git a/include/asm-mips/mc146818rtc.h b/arch/mips/include/asm/mc146818rtc.h
index 68b4da6d520b..68b4da6d520b 100644
--- a/include/asm-mips/mc146818rtc.h
+++ b/arch/mips/include/asm/mc146818rtc.h
diff --git a/include/asm-mips/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index a0f04bb99c99..a0f04bb99c99 100644
--- a/include/asm-mips/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
diff --git a/include/asm-mips/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 7f0b034dd9a5..7f0b034dd9a5 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
diff --git a/include/asm-mips/mips-boards/launch.h b/arch/mips/include/asm/mips-boards/launch.h
index d8ae7f95a522..d8ae7f95a522 100644
--- a/include/asm-mips/mips-boards/launch.h
+++ b/arch/mips/include/asm/mips-boards/launch.h
diff --git a/include/asm-mips/mips-boards/malta.h b/arch/mips/include/asm/mips-boards/malta.h
index c1891578fa65..c1891578fa65 100644
--- a/include/asm-mips/mips-boards/malta.h
+++ b/arch/mips/include/asm/mips-boards/malta.h
diff --git a/include/asm-mips/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index cea872fc6f5c..cea872fc6f5c 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/arch/mips/include/asm/mips-boards/msc01_pci.h
index e036b7dd6deb..e036b7dd6deb 100644
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/arch/mips/include/asm/mips-boards/msc01_pci.h
diff --git a/include/asm-mips/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index 2971d60f2e95..2971d60f2e95 100644
--- a/include/asm-mips/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
diff --git a/include/asm-mips/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h
index a9db576a9768..a9db576a9768 100644
--- a/include/asm-mips/mips-boards/prom.h
+++ b/arch/mips/include/asm/mips-boards/prom.h
diff --git a/include/asm-mips/mips-boards/sim.h b/arch/mips/include/asm/mips-boards/sim.h
index acb7c2331d98..acb7c2331d98 100644
--- a/include/asm-mips/mips-boards/sim.h
+++ b/arch/mips/include/asm/mips-boards/sim.h
diff --git a/include/asm-mips/mips-boards/simint.h b/arch/mips/include/asm/mips-boards/simint.h
index 8ef6db76d5c1..8ef6db76d5c1 100644
--- a/include/asm-mips/mips-boards/simint.h
+++ b/arch/mips/include/asm/mips-boards/simint.h
diff --git a/include/asm-mips/mips_mt.h b/arch/mips/include/asm/mips_mt.h
index ac7935203f89..ac7935203f89 100644
--- a/include/asm-mips/mips_mt.h
+++ b/arch/mips/include/asm/mips_mt.h
diff --git a/include/asm-mips/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index c9420aa97e32..c9420aa97e32 100644
--- a/include/asm-mips/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
diff --git a/include/asm-mips/mipsprom.h b/arch/mips/include/asm/mipsprom.h
index 146d41b67adc..146d41b67adc 100644
--- a/include/asm-mips/mipsprom.h
+++ b/arch/mips/include/asm/mipsprom.h
diff --git a/include/asm-mips/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 979866000da4..979866000da4 100644
--- a/include/asm-mips/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
diff --git a/include/asm-mips/mman.h b/arch/mips/include/asm/mman.h
index e4d6f1fb1cf7..e4d6f1fb1cf7 100644
--- a/include/asm-mips/mman.h
+++ b/arch/mips/include/asm/mman.h
diff --git a/include/asm-mips/mmu.h b/arch/mips/include/asm/mmu.h
index 4063edd79623..4063edd79623 100644
--- a/include/asm-mips/mmu.h
+++ b/arch/mips/include/asm/mmu.h
diff --git a/include/asm-mips/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 0c4f245eaeb2..d7f3eb03ad12 100644
--- a/include/asm-mips/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -220,8 +220,8 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
220 oldasid = read_c0_entryhi() & ASID_MASK; 220 oldasid = read_c0_entryhi() & ASID_MASK;
221 if(smtc_live_asid[mytlb][oldasid]) { 221 if(smtc_live_asid[mytlb][oldasid]) {
222 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 222 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
223 if(smtc_live_asid[mytlb][oldasid] == 0) 223 if(smtc_live_asid[mytlb][oldasid] == 0)
224 smtc_flush_tlb_asid(oldasid); 224 smtc_flush_tlb_asid(oldasid);
225 } 225 }
226 /* See comments for similar code above */ 226 /* See comments for similar code above */
227 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 227 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
@@ -285,8 +285,8 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
285 285
286 /* SMTC shares the TLB (and ASIDs) across VPEs */ 286 /* SMTC shares the TLB (and ASIDs) across VPEs */
287 for_each_online_cpu(i) { 287 for_each_online_cpu(i) {
288 if((smtc_status & SMTC_TLB_SHARED) 288 if((smtc_status & SMTC_TLB_SHARED)
289 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 289 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
290 cpu_context(i, mm) = 0; 290 cpu_context(i, mm) = 0;
291 } 291 }
292#endif /* CONFIG_MIPS_MT_SMTC */ 292#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/include/asm-mips/mmzone.h b/arch/mips/include/asm/mmzone.h
index f53ec54c92ff..f53ec54c92ff 100644
--- a/include/asm-mips/mmzone.h
+++ b/arch/mips/include/asm/mmzone.h
diff --git a/include/asm-mips/module.h b/arch/mips/include/asm/module.h
index de6d09ebbd80..de6d09ebbd80 100644
--- a/include/asm-mips/module.h
+++ b/arch/mips/include/asm/module.h
diff --git a/include/asm-mips/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h
index 7989b9ffc1d2..7989b9ffc1d2 100644
--- a/include/asm-mips/msc01_ic.h
+++ b/arch/mips/include/asm/msc01_ic.h
diff --git a/include/asm-mips/msgbuf.h b/arch/mips/include/asm/msgbuf.h
index 0d6c7f14de31..0d6c7f14de31 100644
--- a/include/asm-mips/msgbuf.h
+++ b/arch/mips/include/asm/msgbuf.h
diff --git a/include/asm-mips/mutex.h b/arch/mips/include/asm/mutex.h
index 458c1f7fbc18..458c1f7fbc18 100644
--- a/include/asm-mips/mutex.h
+++ b/arch/mips/include/asm/mutex.h
diff --git a/include/asm-mips/nile4.h b/arch/mips/include/asm/nile4.h
index c3ca959aa4d9..c3ca959aa4d9 100644
--- a/include/asm-mips/nile4.h
+++ b/arch/mips/include/asm/nile4.h
diff --git a/include/asm-mips/paccess.h b/arch/mips/include/asm/paccess.h
index c2394f8b0fe1..c2394f8b0fe1 100644
--- a/include/asm-mips/paccess.h
+++ b/arch/mips/include/asm/paccess.h
diff --git a/include/asm-mips/page.h b/arch/mips/include/asm/page.h
index fe7a88ea066e..fe7a88ea066e 100644
--- a/include/asm-mips/page.h
+++ b/arch/mips/include/asm/page.h
diff --git a/include/asm-mips/param.h b/arch/mips/include/asm/param.h
index 1d9bb8c5ab24..1d9bb8c5ab24 100644
--- a/include/asm-mips/param.h
+++ b/arch/mips/include/asm/param.h
diff --git a/include/asm-mips/parport.h b/arch/mips/include/asm/parport.h
index f52656826cce..f52656826cce 100644
--- a/include/asm-mips/parport.h
+++ b/arch/mips/include/asm/parport.h
diff --git a/include/asm-mips/pci.h b/arch/mips/include/asm/pci.h
index 5510c53b7feb..5510c53b7feb 100644
--- a/include/asm-mips/pci.h
+++ b/arch/mips/include/asm/pci.h
diff --git a/include/asm-mips/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index 5f4b9d4e4114..5f4b9d4e4114 100644
--- a/include/asm-mips/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
diff --git a/include/asm-mips/percpu.h b/arch/mips/include/asm/percpu.h
index 844e763e9332..844e763e9332 100644
--- a/include/asm-mips/percpu.h
+++ b/arch/mips/include/asm/percpu.h
diff --git a/include/asm-mips/pgalloc.h b/arch/mips/include/asm/pgalloc.h
index 1275831dda29..1275831dda29 100644
--- a/include/asm-mips/pgalloc.h
+++ b/arch/mips/include/asm/pgalloc.h
diff --git a/include/asm-mips/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 55813d6150c7..55813d6150c7 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
diff --git a/include/asm-mips/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 943515f0ef87..943515f0ef87 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
diff --git a/include/asm-mips/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 51b34a48c84a..51b34a48c84a 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
diff --git a/include/asm-mips/pgtable.h b/arch/mips/include/asm/pgtable.h
index 6a0edf72ffbc..6a0edf72ffbc 100644
--- a/include/asm-mips/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h b/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h
new file mode 100644
index 000000000000..ebdbab973e41
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h
@@ -0,0 +1,46 @@
1/*
2 * include/asm-mips/pmc-sierra/msp71xx/gpio.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * @author Patrick Glass <patrickglass@gmail.com>
9 */
10
11#ifndef __PMC_MSP71XX_GPIO_H
12#define __PMC_MSP71XX_GPIO_H
13
14/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */
15#define ARCH_NR_GPIOS (28 + (3 * 8))
16
17/* new generic GPIO API - see Documentation/gpio.txt */
18#include <asm-generic/gpio.h>
19
20#define gpio_get_value __gpio_get_value
21#define gpio_set_value __gpio_set_value
22#define gpio_cansleep __gpio_cansleep
23
24/* Setup calls for the gpio and gpio extended */
25extern void msp71xx_init_gpio(void);
26extern void msp71xx_init_gpio_extended(void);
27extern int msp71xx_set_output_drive(unsigned gpio, int value);
28
29/* Custom output drive functionss */
30static inline int gpio_set_output_drive(unsigned gpio, int value)
31{
32 return msp71xx_set_output_drive(gpio, value);
33}
34
35/* IRQ's are not supported for gpio lines */
36static inline int gpio_to_irq(unsigned gpio)
37{
38 return -EINVAL;
39}
40
41static inline int irq_to_gpio(unsigned irq)
42{
43 return -EINVAL;
44}
45
46#endif /* __PMC_MSP71XX_GPIO_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h
index c84bcf9570b1..c84bcf9570b1 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h
index 1d9f05474820..1d9f05474820 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h
index 415606903617..415606903617 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
index 14ca7dc382a8..14ca7dc382a8 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
index 60a5a38dd5b2..60a5a38dd5b2 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
index 603eb737b4a8..603eb737b4a8 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h
index 96d4c8ce8c83..96d4c8ce8c83 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h
diff --git a/include/asm-mips/pmc-sierra/msp71xx/war.h b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
index 0bf48fc1892b..0bf48fc1892b 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/war.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
diff --git a/include/asm-mips/pmon.h b/arch/mips/include/asm/pmon.h
index 6ad519189ce2..6ad519189ce2 100644
--- a/include/asm-mips/pmon.h
+++ b/arch/mips/include/asm/pmon.h
diff --git a/include/asm-mips/poll.h b/arch/mips/include/asm/poll.h
index 47b952080431..47b952080431 100644
--- a/include/asm-mips/poll.h
+++ b/arch/mips/include/asm/poll.h
diff --git a/include/asm-mips/posix_types.h b/arch/mips/include/asm/posix_types.h
index c200102c8586..c200102c8586 100644
--- a/include/asm-mips/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
diff --git a/include/asm-mips/prefetch.h b/arch/mips/include/asm/prefetch.h
index 17850834ccb0..17850834ccb0 100644
--- a/include/asm-mips/prefetch.h
+++ b/arch/mips/include/asm/prefetch.h
diff --git a/include/asm-mips/processor.h b/arch/mips/include/asm/processor.h
index a1e4453469f9..18ee58e39445 100644
--- a/include/asm-mips/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -105,6 +105,19 @@ struct mips_dsp_state {
105 {0,} \ 105 {0,} \
106} 106}
107 107
108struct mips3264_watch_reg_state {
109 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
110 64 bit kernel. We use unsigned long as it has the same
111 property. */
112 unsigned long watchlo[NUM_WATCH_REGS];
113 /* Only the mask and IRW bits from watchhi. */
114 u16 watchhi[NUM_WATCH_REGS];
115};
116
117union mips_watch_reg_state {
118 struct mips3264_watch_reg_state mips3264;
119};
120
108typedef struct { 121typedef struct {
109 unsigned long seg; 122 unsigned long seg;
110} mm_segment_t; 123} mm_segment_t;
@@ -137,6 +150,9 @@ struct thread_struct {
137 /* Saved state of the DSP ASE, if available. */ 150 /* Saved state of the DSP ASE, if available. */
138 struct mips_dsp_state dsp; 151 struct mips_dsp_state dsp;
139 152
153 /* Saved watch register state, if available. */
154 union mips_watch_reg_state watch;
155
140 /* Other stuff associated with the thread. */ 156 /* Other stuff associated with the thread. */
141 unsigned long cp0_badvaddr; /* Last user fault */ 157 unsigned long cp0_badvaddr; /* Last user fault */
142 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 158 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
@@ -193,6 +209,10 @@ struct thread_struct {
193 .dspcontrol = 0, \ 209 .dspcontrol = 0, \
194 }, \ 210 }, \
195 /* \ 211 /* \
212 * saved watch register stuff \
213 */ \
214 .watch = {{{0,},},}, \
215 /* \
196 * Other stuff associated with the process \ 216 * Other stuff associated with the process \
197 */ \ 217 */ \
198 .cp0_badvaddr = 0, \ 218 .cp0_badvaddr = 0, \
diff --git a/include/asm-mips/ptrace.h b/arch/mips/include/asm/ptrace.h
index 786f7e3c99bc..9c22571b160d 100644
--- a/include/asm-mips/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -9,6 +9,9 @@
9#ifndef _ASM_PTRACE_H 9#ifndef _ASM_PTRACE_H
10#define _ASM_PTRACE_H 10#define _ASM_PTRACE_H
11 11
12#ifdef CONFIG_64BIT
13#define __ARCH_WANT_COMPAT_SYS_PTRACE
14#endif
12 15
13/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ 16/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
14#define FPR_BASE 32 17#define FPR_BASE 32
@@ -71,11 +74,63 @@ struct pt_regs {
71#define PTRACE_POKEDATA_3264 0xc3 74#define PTRACE_POKEDATA_3264 0xc3
72#define PTRACE_GET_THREAD_AREA_3264 0xc4 75#define PTRACE_GET_THREAD_AREA_3264 0xc4
73 76
77/* Read and write watchpoint registers. */
78enum pt_watch_style {
79 pt_watch_style_mips32,
80 pt_watch_style_mips64
81};
82struct mips32_watch_regs {
83 uint32_t watchlo[8];
84 /* Lower 16 bits of watchhi. */
85 uint16_t watchhi[8];
86 /* Valid mask and I R W bits.
87 * bit 0 -- 1 if W bit is usable.
88 * bit 1 -- 1 if R bit is usable.
89 * bit 2 -- 1 if I bit is usable.
90 * bits 3 - 11 -- Valid watchhi mask bits.
91 */
92 uint16_t watch_masks[8];
93 /* The number of valid watch register pairs. */
94 uint32_t num_valid;
95} __attribute__((aligned(8)));
96
97struct mips64_watch_regs {
98 uint64_t watchlo[8];
99 uint16_t watchhi[8];
100 uint16_t watch_masks[8];
101 uint32_t num_valid;
102} __attribute__((aligned(8)));
103
104struct pt_watch_regs {
105 enum pt_watch_style style;
106 union {
107 struct mips32_watch_regs mips32;
108 struct mips32_watch_regs mips64;
109 };
110};
111
112#define PTRACE_GET_WATCH_REGS 0xd0
113#define PTRACE_SET_WATCH_REGS 0xd1
114
74#ifdef __KERNEL__ 115#ifdef __KERNEL__
75 116
117#include <linux/compiler.h>
76#include <linux/linkage.h> 118#include <linux/linkage.h>
77#include <asm/isadep.h> 119#include <asm/isadep.h>
78 120
121struct task_struct;
122
123extern int ptrace_getregs(struct task_struct *child, __s64 __user *data);
124extern int ptrace_setregs(struct task_struct *child, __s64 __user *data);
125
126extern int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
127extern int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
128
129extern int ptrace_get_watch_regs(struct task_struct *child,
130 struct pt_watch_regs __user *addr);
131extern int ptrace_set_watch_regs(struct task_struct *child,
132 struct pt_watch_regs __user *addr);
133
79/* 134/*
80 * Does the process account for user or for system time? 135 * Does the process account for user or for system time?
81 */ 136 */
diff --git a/include/asm-mips/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h
index a37d12b3b61c..a37d12b3b61c 100644
--- a/include/asm-mips/r4k-timer.h
+++ b/arch/mips/include/asm/r4k-timer.h
diff --git a/include/asm-mips/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 4c140db36786..4c140db36786 100644
--- a/include/asm-mips/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
diff --git a/include/asm-mips/reboot.h b/arch/mips/include/asm/reboot.h
index e48c0bfab257..e48c0bfab257 100644
--- a/include/asm-mips/reboot.h
+++ b/arch/mips/include/asm/reboot.h
diff --git a/include/asm-mips/reg.h b/arch/mips/include/asm/reg.h
index 634b55d7e7f6..634b55d7e7f6 100644
--- a/include/asm-mips/reg.h
+++ b/arch/mips/include/asm/reg.h
diff --git a/include/asm-mips/regdef.h b/arch/mips/include/asm/regdef.h
index 7c8ecb6b9c40..7c8ecb6b9c40 100644
--- a/include/asm-mips/regdef.h
+++ b/arch/mips/include/asm/regdef.h
diff --git a/include/asm-mips/resource.h b/arch/mips/include/asm/resource.h
index 87cb3085269c..87cb3085269c 100644
--- a/include/asm-mips/resource.h
+++ b/arch/mips/include/asm/resource.h
diff --git a/include/asm-mips/rm9k-ocd.h b/arch/mips/include/asm/rm9k-ocd.h
index b0b80d9ecf96..b0b80d9ecf96 100644
--- a/include/asm-mips/rm9k-ocd.h
+++ b/arch/mips/include/asm/rm9k-ocd.h
diff --git a/include/asm-mips/rtlx.h b/arch/mips/include/asm/rtlx.h
index 4ca3063ed2ce..4ca3063ed2ce 100644
--- a/include/asm-mips/rtlx.h
+++ b/arch/mips/include/asm/rtlx.h
diff --git a/include/asm-mips/scatterlist.h b/arch/mips/include/asm/scatterlist.h
index 83d69fe17c9f..83d69fe17c9f 100644
--- a/include/asm-mips/scatterlist.h
+++ b/arch/mips/include/asm/scatterlist.h
diff --git a/include/asm-mips/seccomp.h b/arch/mips/include/asm/seccomp.h
index 36ed44070256..36ed44070256 100644
--- a/include/asm-mips/seccomp.h
+++ b/arch/mips/include/asm/seccomp.h
diff --git a/include/asm-mips/sections.h b/arch/mips/include/asm/sections.h
index b7e37262c246..b7e37262c246 100644
--- a/include/asm-mips/sections.h
+++ b/arch/mips/include/asm/sections.h
diff --git a/include/asm-mips/segment.h b/arch/mips/include/asm/segment.h
index 92ac001fc483..92ac001fc483 100644
--- a/include/asm-mips/segment.h
+++ b/arch/mips/include/asm/segment.h
diff --git a/include/asm-mips/sembuf.h b/arch/mips/include/asm/sembuf.h
index 7281a4decaa0..7281a4decaa0 100644
--- a/include/asm-mips/sembuf.h
+++ b/arch/mips/include/asm/sembuf.h
diff --git a/include/asm-mips/serial.h b/arch/mips/include/asm/serial.h
index c07ebd8eb9e7..c07ebd8eb9e7 100644
--- a/include/asm-mips/serial.h
+++ b/arch/mips/include/asm/serial.h
diff --git a/include/asm-mips/setup.h b/arch/mips/include/asm/setup.h
index e600cedda976..e600cedda976 100644
--- a/include/asm-mips/setup.h
+++ b/arch/mips/include/asm/setup.h
diff --git a/include/asm-mips/sgi/gio.h b/arch/mips/include/asm/sgi/gio.h
index 889cf028c95d..889cf028c95d 100644
--- a/include/asm-mips/sgi/gio.h
+++ b/arch/mips/include/asm/sgi/gio.h
diff --git a/include/asm-mips/sgi/hpc3.h b/arch/mips/include/asm/sgi/hpc3.h
index c4729f531919..c4729f531919 100644
--- a/include/asm-mips/sgi/hpc3.h
+++ b/arch/mips/include/asm/sgi/hpc3.h
diff --git a/include/asm-mips/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
index 343ed15f8dc4..343ed15f8dc4 100644
--- a/include/asm-mips/sgi/ioc.h
+++ b/arch/mips/include/asm/sgi/ioc.h
diff --git a/include/asm-mips/sgi/ip22.h b/arch/mips/include/asm/sgi/ip22.h
index c0501f91719b..c0501f91719b 100644
--- a/include/asm-mips/sgi/ip22.h
+++ b/arch/mips/include/asm/sgi/ip22.h
diff --git a/include/asm-mips/sgi/mc.h b/arch/mips/include/asm/sgi/mc.h
index 1576c2394de8..1576c2394de8 100644
--- a/include/asm-mips/sgi/mc.h
+++ b/arch/mips/include/asm/sgi/mc.h
diff --git a/include/asm-mips/sgi/pi1.h b/arch/mips/include/asm/sgi/pi1.h
index c9506915dc5c..c9506915dc5c 100644
--- a/include/asm-mips/sgi/pi1.h
+++ b/arch/mips/include/asm/sgi/pi1.h
diff --git a/include/asm-mips/sgi/seeq.h b/arch/mips/include/asm/sgi/seeq.h
index af0ffd76899d..af0ffd76899d 100644
--- a/include/asm-mips/sgi/seeq.h
+++ b/arch/mips/include/asm/sgi/seeq.h
diff --git a/include/asm-mips/sgi/sgi.h b/arch/mips/include/asm/sgi/sgi.h
index 645cea7c0f8e..645cea7c0f8e 100644
--- a/include/asm-mips/sgi/sgi.h
+++ b/arch/mips/include/asm/sgi/sgi.h
diff --git a/include/asm-mips/sgi/wd.h b/arch/mips/include/asm/sgi/wd.h
index 0d6c3a4da891..0d6c3a4da891 100644
--- a/include/asm-mips/sgi/wd.h
+++ b/arch/mips/include/asm/sgi/wd.h
diff --git a/include/asm-mips/sgialib.h b/arch/mips/include/asm/sgialib.h
index bfce5c786f1c..bfce5c786f1c 100644
--- a/include/asm-mips/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
diff --git a/include/asm-mips/sgiarcs.h b/arch/mips/include/asm/sgiarcs.h
index 721327f88601..721327f88601 100644
--- a/include/asm-mips/sgiarcs.h
+++ b/arch/mips/include/asm/sgiarcs.h
diff --git a/include/asm-mips/sgidefs.h b/arch/mips/include/asm/sgidefs.h
index 876442fcfb32..876442fcfb32 100644
--- a/include/asm-mips/sgidefs.h
+++ b/arch/mips/include/asm/sgidefs.h
diff --git a/include/asm-mips/shmbuf.h b/arch/mips/include/asm/shmbuf.h
index f994438277bf..f994438277bf 100644
--- a/include/asm-mips/shmbuf.h
+++ b/arch/mips/include/asm/shmbuf.h
diff --git a/include/asm-mips/shmparam.h b/arch/mips/include/asm/shmparam.h
index 09290720751c..09290720751c 100644
--- a/include/asm-mips/shmparam.h
+++ b/arch/mips/include/asm/shmparam.h
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/arch/mips/include/asm/sibyte/bcm1480_int.h
index 6109557c14e9..6109557c14e9 100644
--- a/include/asm-mips/sibyte/bcm1480_int.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_int.h
diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
index fd75817f7ac4..fd75817f7ac4 100644
--- a/include/asm-mips/sibyte/bcm1480_l2c.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/arch/mips/include/asm/sibyte/bcm1480_mc.h
index f26a41a82b59..f26a41a82b59 100644
--- a/include/asm-mips/sibyte/bcm1480_mc.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_mc.h
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/arch/mips/include/asm/sibyte/bcm1480_regs.h
index b4077bb72611..b4077bb72611 100644
--- a/include/asm-mips/sibyte/bcm1480_regs.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_regs.h
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h
index 25ef24cbb92a..25ef24cbb92a 100644
--- a/include/asm-mips/sibyte/bcm1480_scd.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h
diff --git a/include/asm-mips/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h
index ebefe797fc1d..ebefe797fc1d 100644
--- a/include/asm-mips/sibyte/bigsur.h
+++ b/arch/mips/include/asm/sibyte/bigsur.h
diff --git a/include/asm-mips/sibyte/board.h b/arch/mips/include/asm/sibyte/board.h
index 25372ae0e814..25372ae0e814 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/arch/mips/include/asm/sibyte/board.h
diff --git a/include/asm-mips/sibyte/carmel.h b/arch/mips/include/asm/sibyte/carmel.h
index 11cad71323e8..11cad71323e8 100644
--- a/include/asm-mips/sibyte/carmel.h
+++ b/arch/mips/include/asm/sibyte/carmel.h
diff --git a/include/asm-mips/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h
index 80c1a052662a..80c1a052662a 100644
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/arch/mips/include/asm/sibyte/sb1250.h
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/arch/mips/include/asm/sibyte/sb1250_defs.h
index 09365f9111fa..09365f9111fa 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/arch/mips/include/asm/sibyte/sb1250_defs.h
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/arch/mips/include/asm/sibyte/sb1250_dma.h
index bad56171d747..bad56171d747 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/arch/mips/include/asm/sibyte/sb1250_dma.h
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/arch/mips/include/asm/sibyte/sb1250_genbus.h
index 94e9c7c8e783..94e9c7c8e783 100644
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ b/arch/mips/include/asm/sibyte/sb1250_genbus.h
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/arch/mips/include/asm/sibyte/sb1250_int.h
index f2850b4bcfd4..f2850b4bcfd4 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/arch/mips/include/asm/sibyte/sb1250_int.h
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/arch/mips/include/asm/sibyte/sb1250_l2c.h
index 6554dcf05cfe..6554dcf05cfe 100644
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ b/arch/mips/include/asm/sibyte/sb1250_l2c.h
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h
index 081e8b1c4ad0..081e8b1c4ad0 100644
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
index b6faf08ca81d..b6faf08ca81d 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h
index 1eb1b5a88736..1eb1b5a88736 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mc.h
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/arch/mips/include/asm/sibyte/sb1250_regs.h
index 8f53ec817a5e..8f53ec817a5e 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/arch/mips/include/asm/sibyte/sb1250_regs.h
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/arch/mips/include/asm/sibyte/sb1250_scd.h
index e49c3e89b5ee..e49c3e89b5ee 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/arch/mips/include/asm/sibyte/sb1250_scd.h
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/arch/mips/include/asm/sibyte/sb1250_smbus.h
index 04769923cf1e..04769923cf1e 100644
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ b/arch/mips/include/asm/sibyte/sb1250_smbus.h
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/arch/mips/include/asm/sibyte/sb1250_syncser.h
index d4b8558e0bf1..d4b8558e0bf1 100644
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ b/arch/mips/include/asm/sibyte/sb1250_syncser.h
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/arch/mips/include/asm/sibyte/sb1250_uart.h
index d835bf280140..d835bf280140 100644
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ b/arch/mips/include/asm/sibyte/sb1250_uart.h
diff --git a/include/asm-mips/sibyte/sentosa.h b/arch/mips/include/asm/sibyte/sentosa.h
index 64c47874f32d..64c47874f32d 100644
--- a/include/asm-mips/sibyte/sentosa.h
+++ b/arch/mips/include/asm/sibyte/sentosa.h
diff --git a/include/asm-mips/sibyte/swarm.h b/arch/mips/include/asm/sibyte/swarm.h
index 114d9d29ca9d..114d9d29ca9d 100644
--- a/include/asm-mips/sibyte/swarm.h
+++ b/arch/mips/include/asm/sibyte/swarm.h
diff --git a/include/asm-mips/sigcontext.h b/arch/mips/include/asm/sigcontext.h
index 9ce0607d7a4e..9ce0607d7a4e 100644
--- a/include/asm-mips/sigcontext.h
+++ b/arch/mips/include/asm/sigcontext.h
diff --git a/include/asm-mips/siginfo.h b/arch/mips/include/asm/siginfo.h
index 96e28f18dad1..96e28f18dad1 100644
--- a/include/asm-mips/siginfo.h
+++ b/arch/mips/include/asm/siginfo.h
diff --git a/include/asm-mips/signal.h b/arch/mips/include/asm/signal.h
index bee5153aca48..bee5153aca48 100644
--- a/include/asm-mips/signal.h
+++ b/arch/mips/include/asm/signal.h
diff --git a/include/asm-mips/sim.h b/arch/mips/include/asm/sim.h
index 0cd719fabb51..0cd719fabb51 100644
--- a/include/asm-mips/sim.h
+++ b/arch/mips/include/asm/sim.h
diff --git a/include/asm-mips/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 43c207e72a63..43c207e72a63 100644
--- a/include/asm-mips/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
diff --git a/include/asm-mips/smp.h b/arch/mips/include/asm/smp.h
index 0ff5b523ea77..0ff5b523ea77 100644
--- a/include/asm-mips/smp.h
+++ b/arch/mips/include/asm/smp.h
diff --git a/include/asm-mips/smtc.h b/arch/mips/include/asm/smtc.h
index ea60bf08dcb0..ea60bf08dcb0 100644
--- a/include/asm-mips/smtc.h
+++ b/arch/mips/include/asm/smtc.h
diff --git a/include/asm-mips/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h
index 8ce517574340..8ce517574340 100644
--- a/include/asm-mips/smtc_ipi.h
+++ b/arch/mips/include/asm/smtc_ipi.h
diff --git a/include/asm-mips/smtc_proc.h b/arch/mips/include/asm/smtc_proc.h
index 25da651f1f5f..25da651f1f5f 100644
--- a/include/asm-mips/smtc_proc.h
+++ b/arch/mips/include/asm/smtc_proc.h
diff --git a/include/asm-mips/smvp.h b/arch/mips/include/asm/smvp.h
index 0d0e80a39e8a..0d0e80a39e8a 100644
--- a/include/asm-mips/smvp.h
+++ b/arch/mips/include/asm/smvp.h
diff --git a/include/asm-mips/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
index fec9bdd34913..fec9bdd34913 100644
--- a/include/asm-mips/sn/addrs.h
+++ b/arch/mips/include/asm/sn/addrs.h
diff --git a/include/asm-mips/sn/agent.h b/arch/mips/include/asm/sn/agent.h
index ac4ea85c3a5c..ac4ea85c3a5c 100644
--- a/include/asm-mips/sn/agent.h
+++ b/arch/mips/include/asm/sn/agent.h
diff --git a/include/asm-mips/sn/arch.h b/arch/mips/include/asm/sn/arch.h
index bd75945e10ff..bd75945e10ff 100644
--- a/include/asm-mips/sn/arch.h
+++ b/arch/mips/include/asm/sn/arch.h
diff --git a/include/asm-mips/sn/fru.h b/arch/mips/include/asm/sn/fru.h
index b3e3606723b7..b3e3606723b7 100644
--- a/include/asm-mips/sn/fru.h
+++ b/arch/mips/include/asm/sn/fru.h
diff --git a/include/asm-mips/sn/gda.h b/arch/mips/include/asm/sn/gda.h
index 9cb6ff770915..9cb6ff770915 100644
--- a/include/asm-mips/sn/gda.h
+++ b/arch/mips/include/asm/sn/gda.h
diff --git a/include/asm-mips/sn/hub.h b/arch/mips/include/asm/sn/hub.h
index 1992d9254a08..1992d9254a08 100644
--- a/include/asm-mips/sn/hub.h
+++ b/arch/mips/include/asm/sn/hub.h
diff --git a/include/asm-mips/sn/intr.h b/arch/mips/include/asm/sn/intr.h
index 6718b644b970..6718b644b970 100644
--- a/include/asm-mips/sn/intr.h
+++ b/arch/mips/include/asm/sn/intr.h
diff --git a/include/asm-mips/sn/io.h b/arch/mips/include/asm/sn/io.h
index 24c6775fbb0f..24c6775fbb0f 100644
--- a/include/asm-mips/sn/io.h
+++ b/arch/mips/include/asm/sn/io.h
diff --git a/include/asm-mips/sn/ioc3.h b/arch/mips/include/asm/sn/ioc3.h
index 099677774d71..099677774d71 100644
--- a/include/asm-mips/sn/ioc3.h
+++ b/arch/mips/include/asm/sn/ioc3.h
diff --git a/include/asm-mips/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
index 96cfd2ab1bcd..09e590daca17 100644
--- a/include/asm-mips/sn/klconfig.h
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -425,7 +425,7 @@ typedef struct lboard_s {
425 unsigned char brd_sversion; /* version of this structure */ 425 unsigned char brd_sversion; /* version of this structure */
426 unsigned char brd_brevision; /* board revision */ 426 unsigned char brd_brevision; /* board revision */
427 unsigned char brd_promver; /* board prom version, if any */ 427 unsigned char brd_promver; /* board prom version, if any */
428 unsigned char brd_flags; /* Enabled, Disabled etc */ 428 unsigned char brd_flags; /* Enabled, Disabled etc */
429 unsigned char brd_slot; /* slot number */ 429 unsigned char brd_slot; /* slot number */
430 unsigned short brd_debugsw; /* Debug switches */ 430 unsigned short brd_debugsw; /* Debug switches */
431 moduleid_t brd_module; /* module to which it belongs */ 431 moduleid_t brd_module; /* module to which it belongs */
@@ -595,9 +595,9 @@ typedef struct klcpu_s { /* CPU */
595 klinfo_t cpu_info; 595 klinfo_t cpu_info;
596 unsigned short cpu_prid; /* Processor PRID value */ 596 unsigned short cpu_prid; /* Processor PRID value */
597 unsigned short cpu_fpirr; /* FPU IRR value */ 597 unsigned short cpu_fpirr; /* FPU IRR value */
598 unsigned short cpu_speed; /* Speed in MHZ */ 598 unsigned short cpu_speed; /* Speed in MHZ */
599 unsigned short cpu_scachesz; /* secondary cache size in MB */ 599 unsigned short cpu_scachesz; /* secondary cache size in MB */
600 unsigned short cpu_scachespeed;/* secondary cache speed in MHz */ 600 unsigned short cpu_scachespeed;/* secondary cache speed in MHz */
601} klcpu_t ; 601} klcpu_t ;
602 602
603#define CPU_STRUCT_VERSION 2 603#define CPU_STRUCT_VERSION 2
@@ -621,7 +621,7 @@ typedef struct klhub_uart_s { /* HUB */
621 621
622typedef struct klmembnk_s { /* MEMORY BANK */ 622typedef struct klmembnk_s { /* MEMORY BANK */
623 klinfo_t membnk_info; 623 klinfo_t membnk_info;
624 short membnk_memsz; /* Total memory in megabytes */ 624 short membnk_memsz; /* Total memory in megabytes */
625 short membnk_dimm_select; /* bank to physical addr mapping*/ 625 short membnk_dimm_select; /* bank to physical addr mapping*/
626 short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */ 626 short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
627 short membnk_attr; 627 short membnk_attr;
@@ -657,7 +657,7 @@ typedef struct klmod_serial_num_s {
657 657
658typedef struct klxbow_s { /* XBOW */ 658typedef struct klxbow_s { /* XBOW */
659 klinfo_t xbow_info ; 659 klinfo_t xbow_info ;
660 klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */ 660 klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
661 int xbow_master_hub_link; 661 int xbow_master_hub_link;
662 /* type of brd connected+component struct ptr+flags */ 662 /* type of brd connected+component struct ptr+flags */
663} klxbow_t ; 663} klxbow_t ;
@@ -673,9 +673,9 @@ typedef struct klpci_device_s {
673 673
674typedef struct klbri_s { /* BRIDGE */ 674typedef struct klbri_s { /* BRIDGE */
675 klinfo_t bri_info ; 675 klinfo_t bri_info ;
676 unsigned char bri_eprominfo ; /* IO6prom connected to bridge */ 676 unsigned char bri_eprominfo ; /* IO6prom connected to bridge */
677 unsigned char bri_bustype ; /* PCI/VME BUS bridge/GIO */ 677 unsigned char bri_bustype ; /* PCI/VME BUS bridge/GIO */
678 pci_t pci_specific ; /* PCI Board config info */ 678 pci_t pci_specific ; /* PCI Board config info */
679 klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */ 679 klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */
680 klconf_off_t bri_mfg_nic ; 680 klconf_off_t bri_mfg_nic ;
681} klbri_t ; 681} klbri_t ;
@@ -684,9 +684,9 @@ typedef struct klbri_s { /* BRIDGE */
684 684
685typedef struct klioc3_s { /* IOC3 */ 685typedef struct klioc3_s { /* IOC3 */
686 klinfo_t ioc3_info ; 686 klinfo_t ioc3_info ;
687 unsigned char ioc3_ssram ; /* Info about ssram */ 687 unsigned char ioc3_ssram ; /* Info about ssram */
688 unsigned char ioc3_nvram ; /* Info about nvram */ 688 unsigned char ioc3_nvram ; /* Info about nvram */
689 klinfo_t ioc3_superio ; /* Info about superio */ 689 klinfo_t ioc3_superio ; /* Info about superio */
690 klconf_off_t ioc3_tty_off ; 690 klconf_off_t ioc3_tty_off ;
691 klinfo_t ioc3_enet ; 691 klinfo_t ioc3_enet ;
692 klconf_off_t ioc3_enet_off ; 692 klconf_off_t ioc3_enet_off ;
@@ -698,13 +698,13 @@ typedef struct klioc3_s { /* IOC3 */
698typedef struct klvmeb_s { /* VME BRIDGE - PCI CTLR */ 698typedef struct klvmeb_s { /* VME BRIDGE - PCI CTLR */
699 klinfo_t vmeb_info ; 699 klinfo_t vmeb_info ;
700 vmeb_t vmeb_specific ; 700 vmeb_t vmeb_specific ;
701 klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ 701 klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */
702} klvmeb_t ; 702} klvmeb_t ;
703 703
704typedef struct klvmed_s { /* VME DEVICE - VME BOARD */ 704typedef struct klvmed_s { /* VME DEVICE - VME BOARD */
705 klinfo_t vmed_info ; 705 klinfo_t vmed_info ;
706 vmed_t vmed_specific ; 706 vmed_t vmed_specific ;
707 klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ 707 klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */
708} klvmed_t ; 708} klvmed_t ;
709 709
710#define ROUTER_VECTOR_VERS 2 710#define ROUTER_VECTOR_VERS 2
@@ -714,7 +714,7 @@ typedef struct klrou_s { /* ROUTER */
714 klinfo_t rou_info ; 714 klinfo_t rou_info ;
715 unsigned int rou_flags ; /* PCFG_ROUTER_xxx flags */ 715 unsigned int rou_flags ; /* PCFG_ROUTER_xxx flags */
716 nic_t rou_box_nic ; /* nic of the containing module */ 716 nic_t rou_box_nic ; /* nic of the containing module */
717 klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */ 717 klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
718 klconf_off_t rou_mfg_nic ; /* MFG NIC string */ 718 klconf_off_t rou_mfg_nic ; /* MFG NIC string */
719 u64 rou_vector; /* vector from master node */ 719 u64 rou_vector; /* vector from master node */
720} klrou_t ; 720} klrou_t ;
@@ -769,7 +769,7 @@ typedef struct klgsn_s { /* GSN board */
769 769
770typedef struct klscsi_s { /* SCSI Controller */ 770typedef struct klscsi_s { /* SCSI Controller */
771 klinfo_t scsi_info ; 771 klinfo_t scsi_info ;
772 scsi_t scsi_specific ; 772 scsi_t scsi_specific ;
773 unsigned char scsi_numdevs ; 773 unsigned char scsi_numdevs ;
774 klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ; 774 klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ;
775} klscsi_t ; 775} klscsi_t ;
@@ -803,13 +803,13 @@ typedef struct klmsdev_s { /* mouse device */
803 803
804typedef struct klfddi_s { /* FDDI */ 804typedef struct klfddi_s { /* FDDI */
805 klinfo_t fddi_info ; 805 klinfo_t fddi_info ;
806 fddi_t fddi_specific ; 806 fddi_t fddi_specific ;
807 klconf_off_t fddi_devinfo[MAX_FDDI_DEVS] ; 807 klconf_off_t fddi_devinfo[MAX_FDDI_DEVS] ;
808} klfddi_t ; 808} klfddi_t ;
809 809
810typedef struct klmio_s { /* MIO */ 810typedef struct klmio_s { /* MIO */
811 klinfo_t mio_info ; 811 klinfo_t mio_info ;
812 mio_t mio_specific ; 812 mio_t mio_specific ;
813} klmio_t ; 813} klmio_t ;
814 814
815 815
diff --git a/include/asm-mips/sn/kldir.h b/arch/mips/include/asm/sn/kldir.h
index 1327e12e9645..1327e12e9645 100644
--- a/include/asm-mips/sn/kldir.h
+++ b/arch/mips/include/asm/sn/kldir.h
diff --git a/include/asm-mips/sn/klkernvars.h b/arch/mips/include/asm/sn/klkernvars.h
index 5de4c5e8ab30..5de4c5e8ab30 100644
--- a/include/asm-mips/sn/klkernvars.h
+++ b/arch/mips/include/asm/sn/klkernvars.h
diff --git a/include/asm-mips/sn/launch.h b/arch/mips/include/asm/sn/launch.h
index b7c2226312c6..b7c2226312c6 100644
--- a/include/asm-mips/sn/launch.h
+++ b/arch/mips/include/asm/sn/launch.h
diff --git a/include/asm-mips/sn/mapped_kernel.h b/arch/mips/include/asm/sn/mapped_kernel.h
index 721496a0bb92..721496a0bb92 100644
--- a/include/asm-mips/sn/mapped_kernel.h
+++ b/arch/mips/include/asm/sn/mapped_kernel.h
diff --git a/include/asm-mips/sn/nmi.h b/arch/mips/include/asm/sn/nmi.h
index 6b7b0b5f3729..6b7b0b5f3729 100644
--- a/include/asm-mips/sn/nmi.h
+++ b/arch/mips/include/asm/sn/nmi.h
diff --git a/include/asm-mips/sn/sn0/addrs.h b/arch/mips/include/asm/sn/sn0/addrs.h
index b06190093bbc..b06190093bbc 100644
--- a/include/asm-mips/sn/sn0/addrs.h
+++ b/arch/mips/include/asm/sn/sn0/addrs.h
diff --git a/include/asm-mips/sn/sn0/arch.h b/arch/mips/include/asm/sn/sn0/arch.h
index f734f2007f24..f734f2007f24 100644
--- a/include/asm-mips/sn/sn0/arch.h
+++ b/arch/mips/include/asm/sn/sn0/arch.h
diff --git a/include/asm-mips/sn/sn0/hub.h b/arch/mips/include/asm/sn/sn0/hub.h
index 3e228f8e7969..3e228f8e7969 100644
--- a/include/asm-mips/sn/sn0/hub.h
+++ b/arch/mips/include/asm/sn/sn0/hub.h
diff --git a/include/asm-mips/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
index 0187895e556c..d0c29d4de084 100644
--- a/include/asm-mips/sn/sn0/hubio.h
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -175,10 +175,10 @@ typedef union hubii_wid_u {
175 u64 wid_reg_value; 175 u64 wid_reg_value;
176 struct { 176 struct {
177 u64 wid_rsvd: 32, /* unused */ 177 u64 wid_rsvd: 32, /* unused */
178 wid_rev_num: 4, /* revision number */ 178 wid_rev_num: 4, /* revision number */
179 wid_part_num: 16, /* the widget type: hub=c101 */ 179 wid_part_num: 16, /* the widget type: hub=c101 */
180 wid_mfg_num: 11, /* Manufacturer id (IBM) */ 180 wid_mfg_num: 11, /* Manufacturer id (IBM) */
181 wid_rsvd1: 1; /* Reserved */ 181 wid_rsvd1: 1; /* Reserved */
182 } wid_fields_s; 182 } wid_fields_s;
183} hubii_wid_t; 183} hubii_wid_t;
184 184
@@ -187,13 +187,13 @@ typedef union hubii_wcr_u {
187 u64 wcr_reg_value; 187 u64 wcr_reg_value;
188 struct { 188 struct {
189 u64 wcr_rsvd: 41, /* unused */ 189 u64 wcr_rsvd: 41, /* unused */
190 wcr_e_thresh: 5, /* elasticity threshold */ 190 wcr_e_thresh: 5, /* elasticity threshold */
191 wcr_dir_con: 1, /* widget direct connect */ 191 wcr_dir_con: 1, /* widget direct connect */
192 wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ 192 wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
193 wcr_xbar_crd: 3, /* LLP crossbar credit */ 193 wcr_xbar_crd: 3, /* LLP crossbar credit */
194 wcr_rsvd1: 8, /* Reserved */ 194 wcr_rsvd1: 8, /* Reserved */
195 wcr_tag_mode: 1, /* Tag mode */ 195 wcr_tag_mode: 1, /* Tag mode */
196 wcr_widget_id: 4; /* LLP crossbar credit */ 196 wcr_widget_id: 4; /* LLP crossbar credit */
197 } wcr_fields_s; 197 } wcr_fields_s;
198} hubii_wcr_t; 198} hubii_wcr_t;
199 199
@@ -220,14 +220,14 @@ typedef union hubii_ilcsr_u {
220 u64 icsr_reg_value; 220 u64 icsr_reg_value;
221 struct { 221 struct {
222 u64 icsr_rsvd: 22, /* unused */ 222 u64 icsr_rsvd: 22, /* unused */
223 icsr_max_burst: 10, /* max burst */ 223 icsr_max_burst: 10, /* max burst */
224 icsr_rsvd4: 6, /* reserved */ 224 icsr_rsvd4: 6, /* reserved */
225 icsr_max_retry: 10, /* max retry */ 225 icsr_max_retry: 10, /* max retry */
226 icsr_rsvd3: 2, /* reserved */ 226 icsr_rsvd3: 2, /* reserved */
227 icsr_lnk_stat: 2, /* link status */ 227 icsr_lnk_stat: 2, /* link status */
228 icsr_bm8: 1, /* Bit mode 8 */ 228 icsr_bm8: 1, /* Bit mode 8 */
229 icsr_llp_en: 1, /* LLP enable bit */ 229 icsr_llp_en: 1, /* LLP enable bit */
230 icsr_rsvd2: 1, /* reserver */ 230 icsr_rsvd2: 1, /* reserver */
231 icsr_wrm_reset: 1, /* Warm reset bit */ 231 icsr_wrm_reset: 1, /* Warm reset bit */
232 icsr_rsvd1: 2, /* Data ready offset */ 232 icsr_rsvd1: 2, /* Data ready offset */
233 icsr_null_to: 6; /* Null timeout */ 233 icsr_null_to: 6; /* Null timeout */
@@ -240,9 +240,9 @@ typedef union hubii_iowa_u {
240 u64 iowa_reg_value; 240 u64 iowa_reg_value;
241 struct { 241 struct {
242 u64 iowa_rsvd: 48, /* unused */ 242 u64 iowa_rsvd: 48, /* unused */
243 iowa_wxoac: 8, /* xtalk widget access bits */ 243 iowa_wxoac: 8, /* xtalk widget access bits */
244 iowa_rsvd1: 7, /* xtalk widget access bits */ 244 iowa_rsvd1: 7, /* xtalk widget access bits */
245 iowa_w0oac: 1; /* xtalk widget access bits */ 245 iowa_w0oac: 1; /* xtalk widget access bits */
246 } iowa_fields_s; 246 } iowa_fields_s;
247} hubii_iowa_t; 247} hubii_iowa_t;
248 248
@@ -261,7 +261,7 @@ typedef union hubii_illr_u {
261 struct { 261 struct {
262 u64 illr_rsvd: 32, /* unused */ 262 u64 illr_rsvd: 32, /* unused */
263 illr_cb_cnt: 16, /* checkbit error count */ 263 illr_cb_cnt: 16, /* checkbit error count */
264 illr_sn_cnt: 16; /* sequence number count */ 264 illr_sn_cnt: 16; /* sequence number count */
265 } illr_fields_s; 265 } illr_fields_s;
266} hubii_illr_t; 266} hubii_illr_t;
267 267
@@ -275,7 +275,7 @@ typedef union io_perf_sel {
275 struct { 275 struct {
276 u64 perf_rsvd : 48, 276 u64 perf_rsvd : 48,
277 perf_icct : 8, 277 perf_icct : 8,
278 perf_ippr1 : 4, 278 perf_ippr1 : 4,
279 perf_ippr0 : 4; 279 perf_ippr0 : 4;
280 } perf_sel_bits; 280 } perf_sel_bits;
281} io_perf_sel_t; 281} io_perf_sel_t;
@@ -733,7 +733,7 @@ typedef union hubii_ifdr_u {
733 u64 ifdr_rsvd: 49, 733 u64 ifdr_rsvd: 49,
734 ifdr_maxrp: 7, 734 ifdr_maxrp: 7,
735 ifdr_rsvd1: 1, 735 ifdr_rsvd1: 1,
736 ifdr_maxrq: 7; 736 ifdr_maxrq: 7;
737 } hi_ifdr_fields; 737 } hi_ifdr_fields;
738} hubii_ifdr_t; 738} hubii_ifdr_t;
739 739
diff --git a/include/asm-mips/sn/sn0/hubmd.h b/arch/mips/include/asm/sn/sn0/hubmd.h
index 14c225d80664..14c225d80664 100644
--- a/include/asm-mips/sn/sn0/hubmd.h
+++ b/arch/mips/include/asm/sn/sn0/hubmd.h
diff --git a/include/asm-mips/sn/sn0/hubni.h b/arch/mips/include/asm/sn/sn0/hubni.h
index b40d3ef97a12..b40d3ef97a12 100644
--- a/include/asm-mips/sn/sn0/hubni.h
+++ b/arch/mips/include/asm/sn/sn0/hubni.h
diff --git a/include/asm-mips/sn/sn0/hubpi.h b/arch/mips/include/asm/sn/sn0/hubpi.h
index e39f5f9da040..e39f5f9da040 100644
--- a/include/asm-mips/sn/sn0/hubpi.h
+++ b/arch/mips/include/asm/sn/sn0/hubpi.h
diff --git a/include/asm-mips/sn/sn0/ip27.h b/arch/mips/include/asm/sn/sn0/ip27.h
index 3c97e0855c8d..3c97e0855c8d 100644
--- a/include/asm-mips/sn/sn0/ip27.h
+++ b/arch/mips/include/asm/sn/sn0/ip27.h
diff --git a/include/asm-mips/sn/sn_private.h b/arch/mips/include/asm/sn/sn_private.h
index 1a2c3025bf28..1a2c3025bf28 100644
--- a/include/asm-mips/sn/sn_private.h
+++ b/arch/mips/include/asm/sn/sn_private.h
diff --git a/include/asm-mips/sn/types.h b/arch/mips/include/asm/sn/types.h
index 74d0bb260b86..74d0bb260b86 100644
--- a/include/asm-mips/sn/types.h
+++ b/arch/mips/include/asm/sn/types.h
diff --git a/include/asm-mips/sni.h b/arch/mips/include/asm/sni.h
index 8c1eb02c6d16..8c1eb02c6d16 100644
--- a/include/asm-mips/sni.h
+++ b/arch/mips/include/asm/sni.h
diff --git a/include/asm-mips/socket.h b/arch/mips/include/asm/socket.h
index facc2d7a87ca..facc2d7a87ca 100644
--- a/include/asm-mips/socket.h
+++ b/arch/mips/include/asm/socket.h
diff --git a/include/asm-mips/sockios.h b/arch/mips/include/asm/sockios.h
index ed1a5f78d22f..ed1a5f78d22f 100644
--- a/include/asm-mips/sockios.h
+++ b/arch/mips/include/asm/sockios.h
diff --git a/include/asm-mips/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index 795ac6c23203..795ac6c23203 100644
--- a/include/asm-mips/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
diff --git a/include/asm-mips/spinlock.h b/arch/mips/include/asm/spinlock.h
index bb897016c491..5d98a3cb85b7 100644
--- a/include/asm-mips/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -9,62 +9,125 @@
9#ifndef _ASM_SPINLOCK_H 9#ifndef _ASM_SPINLOCK_H
10#define _ASM_SPINLOCK_H 10#define _ASM_SPINLOCK_H
11 11
12#include <linux/compiler.h>
13
12#include <asm/barrier.h> 14#include <asm/barrier.h>
13#include <asm/war.h> 15#include <asm/war.h>
14 16
15/* 17/*
16 * Your basic SMP spinlocks, allowing only a single CPU anywhere 18 * Your basic SMP spinlocks, allowing only a single CPU anywhere
19 *
20 * Simple spin lock operations. There are two variants, one clears IRQ's
21 * on the local processor, one does not.
22 *
23 * These are fair FIFO ticket locks
24 *
25 * (the type definitions are in asm/spinlock_types.h)
17 */ 26 */
18 27
19#define __raw_spin_is_locked(x) ((x)->lock != 0)
20#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
21#define __raw_spin_unlock_wait(x) \
22 do { cpu_relax(); } while ((x)->lock)
23 28
24/* 29/*
25 * Simple spin lock operations. There are two variants, one clears IRQ's 30 * Ticket locks are conceptually two parts, one indicating the current head of
26 * on the local processor, one does not. 31 * the queue, and the other indicating the current tail. The lock is acquired
27 * 32 * by atomically noting the tail and incrementing it by one (thus adding
28 * We make no fairness assumptions. They have a cost. 33 * ourself to the queue and noting our position), then waiting until the head
34 * becomes equal to the the initial value of the tail.
29 */ 35 */
30 36
37static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
38{
39 unsigned int counters = ACCESS_ONCE(lock->lock);
40
41 return ((counters >> 14) ^ counters) & 0x1fff;
42}
43
44#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
45#define __raw_spin_unlock_wait(x) \
46 while (__raw_spin_is_locked(x)) { cpu_relax(); }
47
48static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
49{
50 unsigned int counters = ACCESS_ONCE(lock->lock);
51
52 return (((counters >> 14) - counters) & 0x1fff) > 1;
53}
54
31static inline void __raw_spin_lock(raw_spinlock_t *lock) 55static inline void __raw_spin_lock(raw_spinlock_t *lock)
32{ 56{
33 unsigned int tmp; 57 int my_ticket;
58 int tmp;
34 59
35 if (R10000_LLSC_WAR) { 60 if (R10000_LLSC_WAR) {
36 __asm__ __volatile__( 61 __asm__ __volatile__ (
37 " .set noreorder # __raw_spin_lock \n" 62 " .set push # __raw_spin_lock \n"
38 "1: ll %1, %2 \n" 63 " .set noreorder \n"
39 " bnez %1, 1b \n" 64 " \n"
40 " li %1, 1 \n" 65 "1: ll %[ticket], %[ticket_ptr] \n"
41 " sc %1, %0 \n" 66 " addiu %[my_ticket], %[ticket], 0x4000 \n"
42 " beqzl %1, 1b \n" 67 " sc %[my_ticket], %[ticket_ptr] \n"
68 " beqzl %[my_ticket], 1b \n"
43 " nop \n" 69 " nop \n"
44 " .set reorder \n" 70 " srl %[my_ticket], %[ticket], 14 \n"
45 : "=m" (lock->lock), "=&r" (tmp) 71 " andi %[my_ticket], %[my_ticket], 0x1fff \n"
46 : "m" (lock->lock) 72 " andi %[ticket], %[ticket], 0x1fff \n"
47 : "memory"); 73 " bne %[ticket], %[my_ticket], 4f \n"
74 " subu %[ticket], %[my_ticket], %[ticket] \n"
75 "2: \n"
76 " .subsection 2 \n"
77 "4: andi %[ticket], %[ticket], 0x1fff \n"
78 "5: sll %[ticket], 5 \n"
79 " \n"
80 "6: bnez %[ticket], 6b \n"
81 " subu %[ticket], 1 \n"
82 " \n"
83 " lw %[ticket], %[ticket_ptr] \n"
84 " andi %[ticket], %[ticket], 0x1fff \n"
85 " beq %[ticket], %[my_ticket], 2b \n"
86 " subu %[ticket], %[my_ticket], %[ticket] \n"
87 " b 5b \n"
88 " subu %[ticket], %[ticket], 1 \n"
89 " .previous \n"
90 " .set pop \n"
91 : [ticket_ptr] "+m" (lock->lock),
92 [ticket] "=&r" (tmp),
93 [my_ticket] "=&r" (my_ticket));
48 } else { 94 } else {
49 __asm__ __volatile__( 95 __asm__ __volatile__ (
50 " .set noreorder # __raw_spin_lock \n" 96 " .set push # __raw_spin_lock \n"
51 "1: ll %1, %2 \n" 97 " .set noreorder \n"
52 " bnez %1, 2f \n" 98 " \n"
53 " li %1, 1 \n" 99 " ll %[ticket], %[ticket_ptr] \n"
54 " sc %1, %0 \n" 100 "1: addiu %[my_ticket], %[ticket], 0x4000 \n"
55 " beqz %1, 2f \n" 101 " sc %[my_ticket], %[ticket_ptr] \n"
102 " beqz %[my_ticket], 3f \n"
56 " nop \n" 103 " nop \n"
104 " srl %[my_ticket], %[ticket], 14 \n"
105 " andi %[my_ticket], %[my_ticket], 0x1fff \n"
106 " andi %[ticket], %[ticket], 0x1fff \n"
107 " bne %[ticket], %[my_ticket], 4f \n"
108 " subu %[ticket], %[my_ticket], %[ticket] \n"
109 "2: \n"
57 " .subsection 2 \n" 110 " .subsection 2 \n"
58 "2: ll %1, %2 \n" 111 "3: b 1b \n"
59 " bnez %1, 2b \n" 112 " ll %[ticket], %[ticket_ptr] \n"
60 " li %1, 1 \n" 113 " \n"
61 " b 1b \n" 114 "4: andi %[ticket], %[ticket], 0x1fff \n"
62 " nop \n" 115 "5: sll %[ticket], 5 \n"
116 " \n"
117 "6: bnez %[ticket], 6b \n"
118 " subu %[ticket], 1 \n"
119 " \n"
120 " lw %[ticket], %[ticket_ptr] \n"
121 " andi %[ticket], %[ticket], 0x1fff \n"
122 " beq %[ticket], %[my_ticket], 2b \n"
123 " subu %[ticket], %[my_ticket], %[ticket] \n"
124 " b 5b \n"
125 " subu %[ticket], %[ticket], 1 \n"
63 " .previous \n" 126 " .previous \n"
64 " .set reorder \n" 127 " .set pop \n"
65 : "=m" (lock->lock), "=&r" (tmp) 128 : [ticket_ptr] "+m" (lock->lock),
66 : "m" (lock->lock) 129 [ticket] "=&r" (tmp),
67 : "memory"); 130 [my_ticket] "=&r" (my_ticket));
68 } 131 }
69 132
70 smp_llsc_mb(); 133 smp_llsc_mb();
@@ -72,55 +135,103 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
72 135
73static inline void __raw_spin_unlock(raw_spinlock_t *lock) 136static inline void __raw_spin_unlock(raw_spinlock_t *lock)
74{ 137{
75 smp_mb(); 138 int tmp;
76 139
77 __asm__ __volatile__( 140 smp_llsc_mb();
78 " .set noreorder # __raw_spin_unlock \n" 141
79 " sw $0, %0 \n" 142 if (R10000_LLSC_WAR) {
80 " .set\treorder \n" 143 __asm__ __volatile__ (
81 : "=m" (lock->lock) 144 " # __raw_spin_unlock \n"
82 : "m" (lock->lock) 145 "1: ll %[ticket], %[ticket_ptr] \n"
83 : "memory"); 146 " addiu %[ticket], %[ticket], 1 \n"
147 " ori %[ticket], %[ticket], 0x2000 \n"
148 " xori %[ticket], %[ticket], 0x2000 \n"
149 " sc %[ticket], %[ticket_ptr] \n"
150 " beqzl %[ticket], 2f \n"
151 : [ticket_ptr] "+m" (lock->lock),
152 [ticket] "=&r" (tmp));
153 } else {
154 __asm__ __volatile__ (
155 " .set push # __raw_spin_unlock \n"
156 " .set noreorder \n"
157 " \n"
158 " ll %[ticket], %[ticket_ptr] \n"
159 "1: addiu %[ticket], %[ticket], 1 \n"
160 " ori %[ticket], %[ticket], 0x2000 \n"
161 " xori %[ticket], %[ticket], 0x2000 \n"
162 " sc %[ticket], %[ticket_ptr] \n"
163 " beqz %[ticket], 2f \n"
164 " nop \n"
165 " \n"
166 " .subsection 2 \n"
167 "2: b 1b \n"
168 " ll %[ticket], %[ticket_ptr] \n"
169 " .previous \n"
170 " .set pop \n"
171 : [ticket_ptr] "+m" (lock->lock),
172 [ticket] "=&r" (tmp));
173 }
84} 174}
85 175
86static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) 176static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
87{ 177{
88 unsigned int temp, res; 178 int tmp, tmp2, tmp3;
89 179
90 if (R10000_LLSC_WAR) { 180 if (R10000_LLSC_WAR) {
91 __asm__ __volatile__( 181 __asm__ __volatile__ (
92 " .set noreorder # __raw_spin_trylock \n" 182 " .set push # __raw_spin_trylock \n"
93 "1: ll %0, %3 \n" 183 " .set noreorder \n"
94 " ori %2, %0, 1 \n" 184 " \n"
95 " sc %2, %1 \n" 185 "1: ll %[ticket], %[ticket_ptr] \n"
96 " beqzl %2, 1b \n" 186 " srl %[my_ticket], %[ticket], 14 \n"
97 " nop \n" 187 " andi %[my_ticket], %[my_ticket], 0x1fff \n"
98 " andi %2, %0, 1 \n" 188 " andi %[now_serving], %[ticket], 0x1fff \n"
99 " .set reorder" 189 " bne %[my_ticket], %[now_serving], 3f \n"
100 : "=&r" (temp), "=m" (lock->lock), "=&r" (res) 190 " addiu %[ticket], %[ticket], 0x4000 \n"
101 : "m" (lock->lock) 191 " sc %[ticket], %[ticket_ptr] \n"
102 : "memory"); 192 " beqzl %[ticket], 1b \n"
193 " li %[ticket], 1 \n"
194 "2: \n"
195 " .subsection 2 \n"
196 "3: b 2b \n"
197 " li %[ticket], 0 \n"
198 " .previous \n"
199 " .set pop \n"
200 : [ticket_ptr] "+m" (lock->lock),
201 [ticket] "=&r" (tmp),
202 [my_ticket] "=&r" (tmp2),
203 [now_serving] "=&r" (tmp3));
103 } else { 204 } else {
104 __asm__ __volatile__( 205 __asm__ __volatile__ (
105 " .set noreorder # __raw_spin_trylock \n" 206 " .set push # __raw_spin_trylock \n"
106 "1: ll %0, %3 \n" 207 " .set noreorder \n"
107 " ori %2, %0, 1 \n" 208 " \n"
108 " sc %2, %1 \n" 209 " ll %[ticket], %[ticket_ptr] \n"
109 " beqz %2, 2f \n" 210 "1: srl %[my_ticket], %[ticket], 14 \n"
110 " andi %2, %0, 1 \n" 211 " andi %[my_ticket], %[my_ticket], 0x1fff \n"
212 " andi %[now_serving], %[ticket], 0x1fff \n"
213 " bne %[my_ticket], %[now_serving], 3f \n"
214 " addiu %[ticket], %[ticket], 0x4000 \n"
215 " sc %[ticket], %[ticket_ptr] \n"
216 " beqz %[ticket], 4f \n"
217 " li %[ticket], 1 \n"
218 "2: \n"
111 " .subsection 2 \n" 219 " .subsection 2 \n"
112 "2: b 1b \n" 220 "3: b 2b \n"
113 " nop \n" 221 " li %[ticket], 0 \n"
222 "4: b 1b \n"
223 " ll %[ticket], %[ticket_ptr] \n"
114 " .previous \n" 224 " .previous \n"
115 " .set reorder" 225 " .set pop \n"
116 : "=&r" (temp), "=m" (lock->lock), "=&r" (res) 226 : [ticket_ptr] "+m" (lock->lock),
117 : "m" (lock->lock) 227 [ticket] "=&r" (tmp),
118 : "memory"); 228 [my_ticket] "=&r" (tmp2),
229 [now_serving] "=&r" (tmp3));
119 } 230 }
120 231
121 smp_llsc_mb(); 232 smp_llsc_mb();
122 233
123 return res == 0; 234 return tmp;
124} 235}
125 236
126/* 237/*
diff --git a/include/asm-mips/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
index ce26c5048b15..adeedaa116c1 100644
--- a/include/asm-mips/spinlock_types.h
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -6,7 +6,12 @@
6#endif 6#endif
7 7
8typedef struct { 8typedef struct {
9 volatile unsigned int lock; 9 /*
10 * bits 0..13: serving_now
11 * bits 14 : junk data
12 * bits 15..28: ticket
13 */
14 unsigned int lock;
10} raw_spinlock_t; 15} raw_spinlock_t;
11 16
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 } 17#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
diff --git a/include/asm-mips/stackframe.h b/arch/mips/include/asm/stackframe.h
index 4c37c4e5f72e..4c37c4e5f72e 100644
--- a/include/asm-mips/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
diff --git a/include/asm-mips/stacktrace.h b/arch/mips/include/asm/stacktrace.h
index 0bf82818aa53..0bf82818aa53 100644
--- a/include/asm-mips/stacktrace.h
+++ b/arch/mips/include/asm/stacktrace.h
diff --git a/include/asm-mips/stat.h b/arch/mips/include/asm/stat.h
index 6e00f751ab6d..6e00f751ab6d 100644
--- a/include/asm-mips/stat.h
+++ b/arch/mips/include/asm/stat.h
diff --git a/include/asm-mips/statfs.h b/arch/mips/include/asm/statfs.h
index c3ddf973c1c0..c3ddf973c1c0 100644
--- a/include/asm-mips/statfs.h
+++ b/arch/mips/include/asm/statfs.h
diff --git a/include/asm-mips/string.h b/arch/mips/include/asm/string.h
index 436e3ad352d9..436e3ad352d9 100644
--- a/include/asm-mips/string.h
+++ b/arch/mips/include/asm/string.h
diff --git a/include/asm-mips/suspend.h b/arch/mips/include/asm/suspend.h
index 2562f8f9be0e..2562f8f9be0e 100644
--- a/include/asm-mips/suspend.h
+++ b/arch/mips/include/asm/suspend.h
diff --git a/include/asm-mips/sysmips.h b/arch/mips/include/asm/sysmips.h
index 4f47b7d6a5f7..4f47b7d6a5f7 100644
--- a/include/asm-mips/sysmips.h
+++ b/arch/mips/include/asm/sysmips.h
diff --git a/include/asm-mips/system.h b/arch/mips/include/asm/system.h
index a944eda4faf5..cd30f83235bb 100644
--- a/include/asm-mips/system.h
+++ b/arch/mips/include/asm/system.h
@@ -20,6 +20,7 @@
20#include <asm/cmpxchg.h> 20#include <asm/cmpxchg.h>
21#include <asm/cpu-features.h> 21#include <asm/cpu-features.h>
22#include <asm/dsp.h> 22#include <asm/dsp.h>
23#include <asm/watch.h>
23#include <asm/war.h> 24#include <asm/war.h>
24 25
25 26
@@ -76,6 +77,7 @@ do { \
76 __restore_dsp(current); \ 77 __restore_dsp(current); \
77 if (cpu_has_userlocal) \ 78 if (cpu_has_userlocal) \
78 write_c0_userlocal(current_thread_info()->tp_value); \ 79 write_c0_userlocal(current_thread_info()->tp_value); \
80 __restore_watch(); \
79} while (0) 81} while (0)
80 82
81static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) 83static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
diff --git a/include/asm-mips/termbits.h b/arch/mips/include/asm/termbits.h
index c83c68444e86..c83c68444e86 100644
--- a/include/asm-mips/termbits.h
+++ b/arch/mips/include/asm/termbits.h
diff --git a/include/asm-mips/termios.h b/arch/mips/include/asm/termios.h
index a275661fa7e1..a275661fa7e1 100644
--- a/include/asm-mips/termios.h
+++ b/arch/mips/include/asm/termios.h
diff --git a/include/asm-mips/thread_info.h b/arch/mips/include/asm/thread_info.h
index bb3060699df2..3f76de73c943 100644
--- a/include/asm-mips/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -124,6 +124,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
124#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ 124#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */
125#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ 125#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
126#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ 126#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
127#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
127#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 128#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
128 129
129#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 130#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -140,6 +141,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
140#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) 141#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
141#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) 142#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
142#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 143#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
144#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
143 145
144/* work to do on interrupt/exception return */ 146/* work to do on interrupt/exception return */
145#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP) 147#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP)
diff --git a/include/asm-mips/time.h b/arch/mips/include/asm/time.h
index d3bd5c5aa2ec..d3bd5c5aa2ec 100644
--- a/include/asm-mips/time.h
+++ b/arch/mips/include/asm/time.h
diff --git a/include/asm-mips/timex.h b/arch/mips/include/asm/timex.h
index 6529704aa73a..6529704aa73a 100644
--- a/include/asm-mips/timex.h
+++ b/arch/mips/include/asm/timex.h
diff --git a/include/asm-mips/titan_dep.h b/arch/mips/include/asm/titan_dep.h
index fee1908c65d2..fee1908c65d2 100644
--- a/include/asm-mips/titan_dep.h
+++ b/arch/mips/include/asm/titan_dep.h
diff --git a/include/asm-mips/tlb.h b/arch/mips/include/asm/tlb.h
index 80d9dfcf1e88..80d9dfcf1e88 100644
--- a/include/asm-mips/tlb.h
+++ b/arch/mips/include/asm/tlb.h
diff --git a/include/asm-mips/tlbdebug.h b/arch/mips/include/asm/tlbdebug.h
index bb8f5c29c3d9..bb8f5c29c3d9 100644
--- a/include/asm-mips/tlbdebug.h
+++ b/arch/mips/include/asm/tlbdebug.h
diff --git a/include/asm-mips/tlbflush.h b/arch/mips/include/asm/tlbflush.h
index 86b21de12e91..86b21de12e91 100644
--- a/include/asm-mips/tlbflush.h
+++ b/arch/mips/include/asm/tlbflush.h
diff --git a/include/asm-mips/topology.h b/arch/mips/include/asm/topology.h
index 259145e07e97..259145e07e97 100644
--- a/include/asm-mips/topology.h
+++ b/arch/mips/include/asm/topology.h
diff --git a/include/asm-mips/traps.h b/arch/mips/include/asm/traps.h
index 90ff2f497c50..90ff2f497c50 100644
--- a/include/asm-mips/traps.h
+++ b/arch/mips/include/asm/traps.h
diff --git a/arch/mips/include/asm/txx9/boards.h b/arch/mips/include/asm/txx9/boards.h
new file mode 100644
index 000000000000..cbe9476d963e
--- /dev/null
+++ b/arch/mips/include/asm/txx9/boards.h
@@ -0,0 +1,13 @@
1#ifdef CONFIG_TOSHIBA_JMR3927
2BOARD_VEC(jmr3927_vec)
3#endif
4#ifdef CONFIG_TOSHIBA_RBTX4927
5BOARD_VEC(rbtx4927_vec)
6BOARD_VEC(rbtx4937_vec)
7#endif
8#ifdef CONFIG_TOSHIBA_RBTX4938
9BOARD_VEC(rbtx4938_vec)
10#endif
11#ifdef CONFIG_TOSHIBA_RBTX4939
12BOARD_VEC(rbtx4939_vec)
13#endif
diff --git a/include/asm-mips/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 5b1ccf901c62..4316a3e57678 100644
--- a/include/asm-mips/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -42,9 +42,10 @@ struct txx9_board_vec {
42}; 42};
43extern struct txx9_board_vec *txx9_board_vec; 43extern struct txx9_board_vec *txx9_board_vec;
44extern int (*txx9_irq_dispatch)(int pending); 44extern int (*txx9_irq_dispatch)(int pending);
45void prom_init_cmdline(void);
46char *prom_getcmdline(void); 45char *prom_getcmdline(void);
46const char *prom_getenv(const char *name);
47void txx9_wdt_init(unsigned long base); 47void txx9_wdt_init(unsigned long base);
48void txx9_wdt_now(unsigned long base);
48void txx9_spi_init(int busid, unsigned long base, int irq); 49void txx9_spi_init(int busid, unsigned long base, int irq);
49void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr); 50void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr);
50void txx9_sio_init(unsigned long baseaddr, int irq, 51void txx9_sio_init(unsigned long baseaddr, int irq,
@@ -59,4 +60,30 @@ static inline void txx9_sio_putchar_init(unsigned long baseaddr)
59} 60}
60#endif 61#endif
61 62
63struct physmap_flash_data;
64void txx9_physmap_flash_init(int no, unsigned long addr, unsigned long size,
65 const struct physmap_flash_data *pdata);
66
67/* 8 bit version of __fls(): find first bit set (returns 0..7) */
68static inline unsigned int __fls8(unsigned char x)
69{
70 int r = 7;
71
72 if (!(x & 0xf0)) {
73 r -= 4;
74 x <<= 4;
75 }
76 if (!(x & 0xc0)) {
77 r -= 2;
78 x <<= 2;
79 }
80 if (!(x & 0x80))
81 r -= 1;
82 return r;
83}
84
85void txx9_iocled_init(unsigned long baseaddr,
86 int basenum, unsigned int num, int lowactive,
87 const char *color, char **deftriggers);
88
62#endif /* __ASM_TXX9_GENERIC_H */ 89#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h
index a409c446bf18..a409c446bf18 100644
--- a/include/asm-mips/txx9/jmr3927.h
+++ b/arch/mips/include/asm/txx9/jmr3927.h
diff --git a/include/asm-mips/txx9/pci.h b/arch/mips/include/asm/txx9/pci.h
index 3d32529060aa..3d32529060aa 100644
--- a/include/asm-mips/txx9/pci.h
+++ b/arch/mips/include/asm/txx9/pci.h
diff --git a/include/asm-mips/txx9/rbtx4927.h b/arch/mips/include/asm/txx9/rbtx4927.h
index 6fcec912c143..b2adab3d1acc 100644
--- a/include/asm-mips/txx9/rbtx4927.h
+++ b/arch/mips/include/asm/txx9/rbtx4927.h
@@ -34,8 +34,10 @@
34#define RBTX4927_PCIIO 0x16000000 34#define RBTX4927_PCIIO 0x16000000
35#define RBTX4927_PCIIO_SIZE 0x01000000 35#define RBTX4927_PCIIO_SIZE 0x01000000
36 36
37#define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
37#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) 38#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
38#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) 39#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
40#define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
39#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) 41#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
40#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) 42#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
41#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) 43#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
@@ -47,6 +49,7 @@
47 49
48#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) 50#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
49#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) 51#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
52#define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
50#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) 53#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
51#define rbtx4927_softresetlock_addr \ 54#define rbtx4927_softresetlock_addr \
52 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) 55 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
diff --git a/include/asm-mips/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h
index 9f0441a28126..9f0441a28126 100644
--- a/include/asm-mips/txx9/rbtx4938.h
+++ b/arch/mips/include/asm/txx9/rbtx4938.h
diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h
new file mode 100644
index 000000000000..1acf428c0b4f
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4939.h
@@ -0,0 +1,133 @@
1/*
2 * Definitions for RBTX4939
3 *
4 * (C) Copyright TOSHIBA CORPORATION 2005-2006
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 */
10#ifndef __ASM_TXX9_RBTX4939_H
11#define __ASM_TXX9_RBTX4939_H
12
13#include <asm/addrspace.h>
14#include <asm/txx9irq.h>
15#include <asm/txx9/generic.h>
16#include <asm/txx9/tx4939.h>
17
18/* Address map */
19#define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
20#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
21#define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002)
22#define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004)
23#define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006)
24#define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008)
25#define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a)
26#define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000)
27#define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002)
28#define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004)
29#define RBTX4939_IEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00002000)
30#define RBTX4939_IPOL_ADDR (IO_BASE + TXX9_CE(1) + 0x00002002)
31#define RBTX4939_IFAC1_ADDR (IO_BASE + TXX9_CE(1) + 0x00002004)
32#define RBTX4939_IFAC2_ADDR (IO_BASE + TXX9_CE(1) + 0x00002006)
33#define RBTX4939_SOFTINT_ADDR (IO_BASE + TXX9_CE(1) + 0x00003000)
34#define RBTX4939_ISASTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004000)
35#define RBTX4939_PCISTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004002)
36#define RBTX4939_ROME_ADDR (IO_BASE + TXX9_CE(1) + 0x00004004)
37#define RBTX4939_SPICS_ADDR (IO_BASE + TXX9_CE(1) + 0x00004006)
38#define RBTX4939_AUDI_ADDR (IO_BASE + TXX9_CE(1) + 0x00004008)
39#define RBTX4939_ISAGPIO_ADDR (IO_BASE + TXX9_CE(1) + 0x0000400a)
40#define RBTX4939_PE1_ADDR (IO_BASE + TXX9_CE(1) + 0x00005000)
41#define RBTX4939_PE2_ADDR (IO_BASE + TXX9_CE(1) + 0x00005002)
42#define RBTX4939_PE3_ADDR (IO_BASE + TXX9_CE(1) + 0x00005004)
43#define RBTX4939_VP_ADDR (IO_BASE + TXX9_CE(1) + 0x00005006)
44#define RBTX4939_VPRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00005008)
45#define RBTX4939_VPSOUT_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500a)
46#define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c)
47#define RBTX4939_7SEG_ADDR(s, ch) \
48 (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
49#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
50#define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002)
51#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
52#define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000)
53
54/* Ethernet port address */
55#define RBTX4939_ETHER_ADDR (RBTX4939_ETHER_BASE + 0x300)
56
57/* bits for IEN/IPOL/IFAC */
58#define RBTX4938_INTB_ISA0 0
59#define RBTX4938_INTB_ISA11 1
60#define RBTX4938_INTB_ISA12 2
61#define RBTX4938_INTB_ISA15 3
62#define RBTX4938_INTB_I2S 4
63#define RBTX4938_INTB_SW 5
64#define RBTX4938_INTF_ISA0 (1 << RBTX4938_INTB_ISA0)
65#define RBTX4938_INTF_ISA11 (1 << RBTX4938_INTB_ISA11)
66#define RBTX4938_INTF_ISA12 (1 << RBTX4938_INTB_ISA12)
67#define RBTX4938_INTF_ISA15 (1 << RBTX4938_INTB_ISA15)
68#define RBTX4938_INTF_I2S (1 << RBTX4938_INTB_I2S)
69#define RBTX4938_INTF_SW (1 << RBTX4938_INTB_SW)
70
71/* bits for PE1,PE2,PE3 */
72#define RBTX4939_PE1_ATA(ch) (0x01 << (ch))
73#define RBTX4939_PE1_RMII(ch) (0x04 << (ch))
74#define RBTX4939_PE2_SIO0 0x01
75#define RBTX4939_PE2_SIO2 0x02
76#define RBTX4939_PE2_SIO3 0x04
77#define RBTX4939_PE2_CIR 0x08
78#define RBTX4939_PE2_SPI 0x10
79#define RBTX4939_PE2_GPIO 0x20
80#define RBTX4939_PE3_VP 0x01
81#define RBTX4939_PE3_VP_P 0x02
82#define RBTX4939_PE3_VP_S 0x04
83
84#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
85#define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
86#define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
87#define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
88#define rbtx4939_config3_addr ((u8 __iomem *)RBTX4939_CONFIG3_ADDR)
89#define rbtx4939_config4_addr ((u8 __iomem *)RBTX4939_CONFIG4_ADDR)
90#define rbtx4939_ustat_addr ((u8 __iomem *)RBTX4939_USTAT_ADDR)
91#define rbtx4939_udipsw_addr ((u8 __iomem *)RBTX4939_UDIPSW_ADDR)
92#define rbtx4939_bdipsw_addr ((u8 __iomem *)RBTX4939_BDIPSW_ADDR)
93#define rbtx4939_ien_addr ((u8 __iomem *)RBTX4939_IEN_ADDR)
94#define rbtx4939_ipol_addr ((u8 __iomem *)RBTX4939_IPOL_ADDR)
95#define rbtx4939_ifac1_addr ((u8 __iomem *)RBTX4939_IFAC1_ADDR)
96#define rbtx4939_ifac2_addr ((u8 __iomem *)RBTX4939_IFAC2_ADDR)
97#define rbtx4939_softint_addr ((u8 __iomem *)RBTX4939_SOFTINT_ADDR)
98#define rbtx4939_isastat_addr ((u8 __iomem *)RBTX4939_ISASTAT_ADDR)
99#define rbtx4939_pcistat_addr ((u8 __iomem *)RBTX4939_PCISTAT_ADDR)
100#define rbtx4939_rome_addr ((u8 __iomem *)RBTX4939_ROME_ADDR)
101#define rbtx4939_spics_addr ((u8 __iomem *)RBTX4939_SPICS_ADDR)
102#define rbtx4939_audi_addr ((u8 __iomem *)RBTX4939_AUDI_ADDR)
103#define rbtx4939_isagpio_addr ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR)
104#define rbtx4939_pe1_addr ((u8 __iomem *)RBTX4939_PE1_ADDR)
105#define rbtx4939_pe2_addr ((u8 __iomem *)RBTX4939_PE2_ADDR)
106#define rbtx4939_pe3_addr ((u8 __iomem *)RBTX4939_PE3_ADDR)
107#define rbtx4939_vp_addr ((u8 __iomem *)RBTX4939_VP_ADDR)
108#define rbtx4939_vpreset_addr ((u8 __iomem *)RBTX4939_VPRESET_ADDR)
109#define rbtx4939_vpsout_addr ((u8 __iomem *)RBTX4939_VPSOUT_ADDR)
110#define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
111#define rbtx4939_7seg_addr(s, ch) \
112 ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
113#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
114#define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
115#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
116
117/*
118 * IRQ mappings
119 */
120#define RBTX4939_NR_IRQ_IOC 8
121
122#define RBTX4939_IRQ_IOC (TXX9_IRQ_BASE + TX4939_NUM_IR)
123#define RBTX4939_IRQ_END (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC)
124
125/* IOC (ISA, etc) */
126#define RBTX4939_IRQ_IOCINT (TXX9_IRQ_BASE + TX4939_IR_INT(0))
127/* Onboard 10M Ether */
128#define RBTX4939_IRQ_ETHER (TXX9_IRQ_BASE + TX4939_IR_INT(1))
129
130void rbtx4939_prom_init(void);
131void rbtx4939_irq_setup(void);
132
133#endif /* __ASM_TXX9_RBTX4939_H */
diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
index 02e161d0755d..d1d6332b4ca6 100644
--- a/include/asm-mips/txx9/smsc_fdc37m81x.h
+++ b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
@@ -62,6 +62,7 @@ void smsc_fdc37m81x_config_beg(void);
62 62
63void smsc_fdc37m81x_config_end(void); 63void smsc_fdc37m81x_config_end(void);
64 64
65u8 smsc_fdc37m81x_config_get(u8 reg);
65void smsc_fdc37m81x_config_set(u8 reg, u8 val); 66void smsc_fdc37m81x_config_set(u8 reg, u8 val);
66 67
67#endif 68#endif
diff --git a/include/asm-mips/txx9/spi.h b/arch/mips/include/asm/txx9/spi.h
index ddfb2a0dc432..0d727f354557 100644
--- a/include/asm-mips/txx9/spi.h
+++ b/arch/mips/include/asm/txx9/spi.h
@@ -13,7 +13,22 @@
13#ifndef __ASM_TXX9_SPI_H 13#ifndef __ASM_TXX9_SPI_H
14#define __ASM_TXX9_SPI_H 14#define __ASM_TXX9_SPI_H
15 15
16extern int spi_eeprom_register(int chipid); 16#include <linux/errno.h>
17extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); 17
18#ifdef CONFIG_SPI
19int spi_eeprom_register(int busid, int chipid, int size);
20int spi_eeprom_read(int busid, int chipid,
21 int address, unsigned char *buf, int len);
22#else
23static inline int spi_eeprom_register(int busid, int chipid, int size)
24{
25 return -ENODEV;
26}
27static inline int spi_eeprom_read(int busid, int chipid,
28 int address, unsigned char *buf, int len)
29{
30 return -ENODEV;
31}
32#endif
18 33
19#endif /* __ASM_TXX9_SPI_H */ 34#endif /* __ASM_TXX9_SPI_H */
diff --git a/include/asm-mips/txx9/tx3927.h b/arch/mips/include/asm/txx9/tx3927.h
index 587deb9592d2..dc30c8d42061 100644
--- a/include/asm-mips/txx9/tx3927.h
+++ b/arch/mips/include/asm/txx9/tx3927.h
@@ -325,6 +325,7 @@ struct tx3927_ccfg_reg {
325#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000) 325#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
326#define TX3927_ROMC_SIZE(ch) \ 326#define TX3927_ROMC_SIZE(ch) \
327 (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf)) 327 (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
328#define TX3927_ROMC_WIDTH(ch) (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1))
328 329
329void tx3927_wdt_init(void); 330void tx3927_wdt_init(void);
330void tx3927_setup(void); 331void tx3927_setup(void);
@@ -335,5 +336,6 @@ void tx3927_pcic_setup(struct pci_controller *channel,
335 unsigned long sdram_size, int extarb); 336 unsigned long sdram_size, int extarb);
336void tx3927_setup_pcierr_irq(void); 337void tx3927_setup_pcierr_irq(void);
337void tx3927_irq_init(void); 338void tx3927_irq_init(void);
339void tx3927_mtd_init(int ch);
338 340
339#endif /* __ASM_TXX9_TX3927_H */ 341#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h
index 195f6515db9a..7d813f1cb98d 100644
--- a/include/asm-mips/txx9/tx4927.h
+++ b/arch/mips/include/asm/txx9/tx4927.h
@@ -50,12 +50,23 @@
50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) 50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) 51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
52 52
53#define TX4927_IR_ECCERR 0
54#define TX4927_IR_WTOERR 1
55#define TX4927_NUM_IR_INT 6
53#define TX4927_IR_INT(n) (2 + (n)) 56#define TX4927_IR_INT(n) (2 + (n))
57#define TX4927_NUM_IR_SIO 2
54#define TX4927_IR_SIO(n) (8 + (n)) 58#define TX4927_IR_SIO(n) (8 + (n))
59#define TX4927_NUM_IR_DMA 4
60#define TX4927_IR_DMA(n) (10 + (n))
61#define TX4927_IR_PIO 14
62#define TX4927_IR_PDMAC 15
55#define TX4927_IR_PCIC 16 63#define TX4927_IR_PCIC 16
56#define TX4927_NUM_IR_TMR 3 64#define TX4927_NUM_IR_TMR 3
57#define TX4927_IR_TMR(n) (17 + (n)) 65#define TX4927_IR_TMR(n) (17 + (n))
58#define TX4927_IR_PCIERR 22 66#define TX4927_IR_PCIERR 22
67#define TX4927_IR_PCIPME 23
68#define TX4927_IR_ACLC 24
69#define TX4927_IR_ACLCPME 25
59#define TX4927_NUM_IR 32 70#define TX4927_NUM_IR 32
60 71
61#define TX4927_IRC_INT 2 /* IP[2] in Status register */ 72#define TX4927_IRC_INT 2 /* IP[2] in Status register */
@@ -196,6 +207,8 @@ struct tx4927_ccfg_reg {
196#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20) 207#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
197#define TX4927_EBUSC_SIZE(ch) \ 208#define TX4927_EBUSC_SIZE(ch) \
198 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf)) 209 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
210#define TX4927_EBUSC_WIDTH(ch) \
211 (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3))
199 212
200/* utilities */ 213/* utilities */
201static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) 214static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
@@ -251,5 +264,6 @@ int tx4927_report_pciclk(void);
251int tx4927_pciclk66_setup(void); 264int tx4927_pciclk66_setup(void);
252void tx4927_setup_pcierr_irq(void); 265void tx4927_setup_pcierr_irq(void);
253void tx4927_irq_init(void); 266void tx4927_irq_init(void);
267void tx4927_mtd_init(int ch);
254 268
255#endif /* __ASM_TXX9_TX4927_H */ 269#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/arch/mips/include/asm/txx9/tx4927pcic.h
index c470b8a5fe57..c470b8a5fe57 100644
--- a/include/asm-mips/txx9/tx4927pcic.h
+++ b/arch/mips/include/asm/txx9/tx4927pcic.h
diff --git a/include/asm-mips/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
index 8175d4ccbc39..989e7751135a 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -274,6 +274,7 @@ struct tx4938_ccfg_reg {
274#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch) 274#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
275#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch) 275#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) 276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
277#define TX4938_EBUSC_WIDTH(ch) TX4927_EBUSC_WIDTH(ch)
277 278
278#define tx4938_get_mem_size() tx4927_get_mem_size() 279#define tx4938_get_mem_size() tx4927_get_mem_size()
279void tx4938_wdt_init(void); 280void tx4938_wdt_init(void);
@@ -289,5 +290,6 @@ struct pci_dev;
289int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); 290int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
290void tx4938_setup_pcierr_irq(void); 291void tx4938_setup_pcierr_irq(void);
291void tx4938_irq_init(void); 292void tx4938_irq_init(void);
293void tx4938_mtd_init(int ch);
292 294
293#endif 295#endif
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
new file mode 100644
index 000000000000..88badb423010
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -0,0 +1,545 @@
1/*
2 * Definitions for TX4939
3 *
4 * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 */
10#ifndef __ASM_TXX9_TX4939_H
11#define __ASM_TXX9_TX4939_H
12
13/* some controllers are compatible with 4927/4938 */
14#include <asm/txx9/tx4938.h>
15
16#ifdef CONFIG_64BIT
17#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
18#else
19#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
20#endif
21#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
22
23#define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
24#define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000)
25#define TX4939_SRAMC_REG (TX4939_REG_BASE + 0x6000)
26#define TX4939_CRYPTO_REG (TX4939_REG_BASE + 0x6800)
27#define TX4939_PCIC1_REG (TX4939_REG_BASE + 0x7000)
28#define TX4939_DDRC_REG (TX4939_REG_BASE + 0x8000)
29#define TX4939_EBUSC_REG (TX4939_REG_BASE + 0x9000)
30#define TX4939_VPC_REG (TX4939_REG_BASE + 0xa000)
31#define TX4939_DMA_REG(ch) (TX4939_REG_BASE + 0xb000 + (ch) * 0x800)
32#define TX4939_PCIC_REG (TX4939_REG_BASE + 0xd000)
33#define TX4939_CCFG_REG (TX4939_REG_BASE + 0xe000)
34#define TX4939_IRC_REG (TX4939_REG_BASE + 0xe800)
35#define TX4939_NR_TMR 6 /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */
36#define TX4939_TMR_REG(ch) \
37 (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100)
38#define TX4939_NR_SIO 4 /* 0xf300, 0xf400, 0xf380, 0xf480 */
39#define TX4939_SIO_REG(ch) \
40 (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6))
41#define TX4939_ACLC_REG (TX4939_REG_BASE + 0xf700)
42#define TX4939_SPI_REG (TX4939_REG_BASE + 0xf800)
43#define TX4939_I2C_REG (TX4939_REG_BASE + 0xf900)
44#define TX4939_I2S_REG (TX4939_REG_BASE + 0xfa00)
45#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00)
46#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00)
47
48struct tx4939_le_reg {
49 __u32 r;
50 __u32 unused;
51};
52
53struct tx4939_ddrc_reg {
54 struct tx4939_le_reg ctl[47];
55 __u64 unused0[17];
56 __u64 winen;
57 __u64 win[4];
58};
59
60struct tx4939_ccfg_reg {
61 __u64 ccfg;
62 __u64 crir;
63 __u64 pcfg;
64 __u64 toea;
65 __u64 clkctr;
66 __u64 unused0;
67 __u64 garbc;
68 __u64 unused1[2];
69 __u64 ramp;
70 __u64 unused2[2];
71 __u64 dskwctrl;
72 __u64 mclkosc;
73 __u64 mclkctl;
74 __u64 unused3[17];
75 struct {
76 __u64 mr;
77 __u64 dr;
78 } gpio[2];
79};
80
81struct tx4939_irc_reg {
82 struct tx4939_le_reg den;
83 struct tx4939_le_reg scipb;
84 struct tx4939_le_reg dm[2];
85 struct tx4939_le_reg lvl[16];
86 struct tx4939_le_reg msk;
87 struct tx4939_le_reg edc;
88 struct tx4939_le_reg pnd0;
89 struct tx4939_le_reg cs;
90 struct tx4939_le_reg pnd1;
91 struct tx4939_le_reg dm2[2];
92 struct tx4939_le_reg dbr[2];
93 struct tx4939_le_reg dben;
94 struct tx4939_le_reg unused0[2];
95 struct tx4939_le_reg flag[2];
96 struct tx4939_le_reg pol;
97 struct tx4939_le_reg cnt;
98 struct tx4939_le_reg maskint;
99 struct tx4939_le_reg maskext;
100};
101
102struct tx4939_rtc_reg {
103 __u32 ctl;
104 __u32 adr;
105 __u32 dat;
106 __u32 tbc;
107};
108
109struct tx4939_crypto_reg {
110 struct tx4939_le_reg csr;
111 struct tx4939_le_reg idesptr;
112 struct tx4939_le_reg cdesptr;
113 struct tx4939_le_reg buserr;
114 struct tx4939_le_reg cip_tout;
115 struct tx4939_le_reg cir;
116 union {
117 struct {
118 struct tx4939_le_reg data[8];
119 struct tx4939_le_reg ctrl;
120 } gen;
121 struct {
122 struct {
123 struct tx4939_le_reg l;
124 struct tx4939_le_reg u;
125 } key[3], ini;
126 struct tx4939_le_reg ctrl;
127 } des;
128 struct {
129 struct tx4939_le_reg key[4];
130 struct tx4939_le_reg ini[4];
131 struct tx4939_le_reg ctrl;
132 } aes;
133 struct {
134 struct {
135 struct tx4939_le_reg l;
136 struct tx4939_le_reg u;
137 } cnt;
138 struct tx4939_le_reg ini[5];
139 struct tx4939_le_reg unused;
140 struct tx4939_le_reg ctrl;
141 } hash;
142 } cdr;
143 struct tx4939_le_reg unused0[7];
144 struct tx4939_le_reg rcsr;
145 struct tx4939_le_reg rpr;
146 __u64 rdr;
147 __u64 ror[3];
148 struct tx4939_le_reg unused1[2];
149 struct tx4939_le_reg xorslr;
150 struct tx4939_le_reg xorsur;
151};
152
153struct tx4939_crypto_desc {
154 __u32 src;
155 __u32 dst;
156 __u32 next;
157 __u32 ctrl;
158 __u32 index;
159 __u32 xor;
160};
161
162struct tx4939_vpc_reg {
163 struct tx4939_le_reg csr;
164 struct {
165 struct tx4939_le_reg ctrlA;
166 struct tx4939_le_reg ctrlB;
167 struct tx4939_le_reg idesptr;
168 struct tx4939_le_reg cdesptr;
169 } port[3];
170 struct tx4939_le_reg buserr;
171};
172
173struct tx4939_vpc_desc {
174 __u32 src;
175 __u32 next;
176 __u32 ctrl1;
177 __u32 ctrl2;
178};
179
180/*
181 * IRC
182 */
183#define TX4939_IR_NONE 0
184#define TX4939_IR_DDR 1
185#define TX4939_IR_WTOERR 2
186#define TX4939_NUM_IR_INT 3
187#define TX4939_IR_INT(n) (3 + (n))
188#define TX4939_NUM_IR_ETH 2
189#define TX4939_IR_ETH(n) ((n) ? 43 : 6)
190#define TX4939_IR_VIDEO 7
191#define TX4939_IR_CIR 8
192#define TX4939_NUM_IR_SIO 4
193#define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */
194#define TX4939_NUM_IR_DMA 4
195#define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
196#define TX4939_IR_IRC 14
197#define TX4939_IR_PDMAC 15
198#define TX4939_NUM_IR_TMR 6
199#define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
200#define TX4939_NUM_IR_ATA 2
201#define TX4939_IR_ATA(n) (19 + (n))
202#define TX4939_IR_ACLC 21
203#define TX4939_IR_CIPHER 26
204#define TX4939_IR_INTA 27
205#define TX4939_IR_INTB 28
206#define TX4939_IR_INTC 29
207#define TX4939_IR_INTD 30
208#define TX4939_IR_I2C 33
209#define TX4939_IR_SPI 34
210#define TX4939_IR_PCIC 35
211#define TX4939_IR_PCIC1 36
212#define TX4939_IR_PCIERR 37
213#define TX4939_IR_PCIPME 38
214#define TX4939_IR_NDFMC 39
215#define TX4939_IR_ACLCPME 40
216#define TX4939_IR_RTC 41
217#define TX4939_IR_RND 42
218#define TX4939_IR_I2S 47
219#define TX4939_NUM_IR 64
220
221#define TX4939_IRC_INT 2 /* IP[2] in Status register */
222
223/*
224 * CCFG
225 */
226/* CCFG : Chip Configuration */
227#define TX4939_CCFG_PCIBOOT 0x0000040000000000ULL
228#define TX4939_CCFG_WDRST 0x0000020000000000ULL
229#define TX4939_CCFG_WDREXEN 0x0000010000000000ULL
230#define TX4939_CCFG_BCFG_MASK 0x000000ff00000000ULL
231#define TX4939_CCFG_GTOT_MASK 0x06000000
232#define TX4939_CCFG_GTOT_4096 0x06000000
233#define TX4939_CCFG_GTOT_2048 0x04000000
234#define TX4939_CCFG_GTOT_1024 0x02000000
235#define TX4939_CCFG_GTOT_512 0x00000000
236#define TX4939_CCFG_TINTDIS 0x01000000
237#define TX4939_CCFG_PCI66 0x00800000
238#define TX4939_CCFG_PCIMODE 0x00400000
239#define TX4939_CCFG_SSCG 0x00100000
240#define TX4939_CCFG_MULCLK_MASK 0x000e0000
241#define TX4939_CCFG_MULCLK_8 (0x7 << 17)
242#define TX4939_CCFG_MULCLK_9 (0x0 << 17)
243#define TX4939_CCFG_MULCLK_10 (0x1 << 17)
244#define TX4939_CCFG_MULCLK_11 (0x2 << 17)
245#define TX4939_CCFG_MULCLK_12 (0x3 << 17)
246#define TX4939_CCFG_MULCLK_13 (0x4 << 17)
247#define TX4939_CCFG_MULCLK_14 (0x5 << 17)
248#define TX4939_CCFG_MULCLK_15 (0x6 << 17)
249#define TX4939_CCFG_BEOW 0x00010000
250#define TX4939_CCFG_WR 0x00008000
251#define TX4939_CCFG_TOE 0x00004000
252#define TX4939_CCFG_PCIARB 0x00002000
253#define TX4939_CCFG_YDIVMODE_MASK 0x00001c00
254#define TX4939_CCFG_YDIVMODE_2 (0x0 << 10)
255#define TX4939_CCFG_YDIVMODE_3 (0x1 << 10)
256#define TX4939_CCFG_YDIVMODE_5 (0x6 << 10)
257#define TX4939_CCFG_YDIVMODE_6 (0x7 << 10)
258#define TX4939_CCFG_PTSEL 0x00000200
259#define TX4939_CCFG_BESEL 0x00000100
260#define TX4939_CCFG_SYSSP_MASK 0x000000c0
261#define TX4939_CCFG_ACKSEL 0x00000020
262#define TX4939_CCFG_ROMW 0x00000010
263#define TX4939_CCFG_ENDIAN 0x00000004
264#define TX4939_CCFG_ARMODE 0x00000002
265#define TX4939_CCFG_ACEHOLD 0x00000001
266
267/* PCFG : Pin Configuration */
268#define TX4939_PCFG_SIO2MODE_MASK 0xc000000000000000ULL
269#define TX4939_PCFG_SIO2MODE_GPIO 0x8000000000000000ULL
270#define TX4939_PCFG_SIO2MODE_SIO2 0x4000000000000000ULL
271#define TX4939_PCFG_SIO2MODE_SIO0 0x0000000000000000ULL
272#define TX4939_PCFG_SPIMODE 0x2000000000000000ULL
273#define TX4939_PCFG_I2CMODE 0x1000000000000000ULL
274#define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL
275#define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL
276#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
277#define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL
278#define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL
279#define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL
280#define TX4939_PCFG_DMASEL3 0x0004000000000000ULL
281#define TX4939_PCFG_DMASEL3_SIO0 0x0004000000000000ULL
282#define TX4939_PCFG_DMASEL3_NDFC 0x0000000000000000ULL
283#define TX4939_PCFG_VSSMODE 0x0000200000000000ULL
284#define TX4939_PCFG_VPSMODE 0x0000100000000000ULL
285#define TX4939_PCFG_ET1MODE 0x0000080000000000ULL
286#define TX4939_PCFG_ET0MODE 0x0000040000000000ULL
287#define TX4939_PCFG_ATA1MODE 0x0000020000000000ULL
288#define TX4939_PCFG_ATA0MODE 0x0000010000000000ULL
289#define TX4939_PCFG_BP_PLL 0x0000000100000000ULL
290
291#define TX4939_PCFG_SYSCLKEN 0x08000000
292#define TX4939_PCFG_PCICLKEN_ALL 0x000f0000
293#define TX4939_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
294#define TX4939_PCFG_SPEED1 0x00002000
295#define TX4939_PCFG_SPEED0 0x00001000
296#define TX4939_PCFG_ITMODE 0x00000300
297#define TX4939_PCFG_DMASEL_ALL (0x00000007 | TX4939_PCFG_DMASEL3)
298#define TX4939_PCFG_DMASEL2 0x00000004
299#define TX4939_PCFG_DMASEL2_DRQ2 0x00000000
300#define TX4939_PCFG_DMASEL2_SIO0 0x00000004
301#define TX4939_PCFG_DMASEL1 0x00000002
302#define TX4939_PCFG_DMASEL1_DRQ1 0x00000000
303#define TX4939_PCFG_DMASEL0 0x00000001
304#define TX4939_PCFG_DMASEL0_DRQ0 0x00000000
305
306/* CLKCTR : Clock Control */
307#define TX4939_CLKCTR_IOSCKD 0x8000000000000000ULL
308#define TX4939_CLKCTR_SYSCKD 0x4000000000000000ULL
309#define TX4939_CLKCTR_TM5CKD 0x2000000000000000ULL
310#define TX4939_CLKCTR_TM4CKD 0x1000000000000000ULL
311#define TX4939_CLKCTR_TM3CKD 0x0800000000000000ULL
312#define TX4939_CLKCTR_CIRCKD 0x0400000000000000ULL
313#define TX4939_CLKCTR_SIO3CKD 0x0200000000000000ULL
314#define TX4939_CLKCTR_SIO2CKD 0x0100000000000000ULL
315#define TX4939_CLKCTR_SIO1CKD 0x0080000000000000ULL
316#define TX4939_CLKCTR_VPCCKD 0x0040000000000000ULL
317#define TX4939_CLKCTR_EPCICKD 0x0020000000000000ULL
318#define TX4939_CLKCTR_ETH1CKD 0x0008000000000000ULL
319#define TX4939_CLKCTR_ATA1CKD 0x0004000000000000ULL
320#define TX4939_CLKCTR_BROMCKD 0x0002000000000000ULL
321#define TX4939_CLKCTR_NDCCKD 0x0001000000000000ULL
322#define TX4939_CLKCTR_I2CCKD 0x0000800000000000ULL
323#define TX4939_CLKCTR_ETH0CKD 0x0000400000000000ULL
324#define TX4939_CLKCTR_SPICKD 0x0000200000000000ULL
325#define TX4939_CLKCTR_SRAMCKD 0x0000100000000000ULL
326#define TX4939_CLKCTR_PCI1CKD 0x0000080000000000ULL
327#define TX4939_CLKCTR_DMA1CKD 0x0000040000000000ULL
328#define TX4939_CLKCTR_ACLCKD 0x0000020000000000ULL
329#define TX4939_CLKCTR_ATA0CKD 0x0000010000000000ULL
330#define TX4939_CLKCTR_DMA0CKD 0x0000008000000000ULL
331#define TX4939_CLKCTR_PCICCKD 0x0000004000000000ULL
332#define TX4939_CLKCTR_I2SCKD 0x0000002000000000ULL
333#define TX4939_CLKCTR_TM0CKD 0x0000001000000000ULL
334#define TX4939_CLKCTR_TM1CKD 0x0000000800000000ULL
335#define TX4939_CLKCTR_TM2CKD 0x0000000400000000ULL
336#define TX4939_CLKCTR_SIO0CKD 0x0000000200000000ULL
337#define TX4939_CLKCTR_CYPCKD 0x0000000100000000ULL
338#define TX4939_CLKCTR_IOSRST 0x80000000
339#define TX4939_CLKCTR_SYSRST 0x40000000
340#define TX4939_CLKCTR_TM5RST 0x20000000
341#define TX4939_CLKCTR_TM4RST 0x10000000
342#define TX4939_CLKCTR_TM3RST 0x08000000
343#define TX4939_CLKCTR_CIRRST 0x04000000
344#define TX4939_CLKCTR_SIO3RST 0x02000000
345#define TX4939_CLKCTR_SIO2RST 0x01000000
346#define TX4939_CLKCTR_SIO1RST 0x00800000
347#define TX4939_CLKCTR_VPCRST 0x00400000
348#define TX4939_CLKCTR_EPCIRST 0x00200000
349#define TX4939_CLKCTR_ETH1RST 0x00080000
350#define TX4939_CLKCTR_ATA1RST 0x00040000
351#define TX4939_CLKCTR_BROMRST 0x00020000
352#define TX4939_CLKCTR_NDCRST 0x00010000
353#define TX4939_CLKCTR_I2CRST 0x00008000
354#define TX4939_CLKCTR_ETH0RST 0x00004000
355#define TX4939_CLKCTR_SPIRST 0x00002000
356#define TX4939_CLKCTR_SRAMRST 0x00001000
357#define TX4939_CLKCTR_PCI1RST 0x00000800
358#define TX4939_CLKCTR_DMA1RST 0x00000400
359#define TX4939_CLKCTR_ACLRST 0x00000200
360#define TX4939_CLKCTR_ATA0RST 0x00000100
361#define TX4939_CLKCTR_DMA0RST 0x00000080
362#define TX4939_CLKCTR_PCICRST 0x00000040
363#define TX4939_CLKCTR_I2SRST 0x00000020
364#define TX4939_CLKCTR_TM0RST 0x00000010
365#define TX4939_CLKCTR_TM1RST 0x00000008
366#define TX4939_CLKCTR_TM2RST 0x00000004
367#define TX4939_CLKCTR_SIO0RST 0x00000002
368#define TX4939_CLKCTR_CYPRST 0x00000001
369
370/*
371 * RTC
372 */
373#define TX4939_RTCCTL_ALME 0x00000080
374#define TX4939_RTCCTL_ALMD 0x00000040
375#define TX4939_RTCCTL_BUSY 0x00000020
376
377#define TX4939_RTCCTL_COMMAND 0x00000007
378#define TX4939_RTCCTL_COMMAND_NOP 0x00000000
379#define TX4939_RTCCTL_COMMAND_GETTIME 0x00000001
380#define TX4939_RTCCTL_COMMAND_SETTIME 0x00000002
381#define TX4939_RTCCTL_COMMAND_GETALARM 0x00000003
382#define TX4939_RTCCTL_COMMAND_SETALARM 0x00000004
383
384#define TX4939_RTCTBC_PM 0x00000080
385#define TX4939_RTCTBC_COMP 0x0000007f
386
387#define TX4939_RTC_REG_RAMSIZE 0x00000100
388#define TX4939_RTC_REG_RWBSIZE 0x00000006
389
390/*
391 * CRYPTO
392 */
393#define TX4939_CRYPTO_CSR_SAESO 0x08000000
394#define TX4939_CRYPTO_CSR_SAESI 0x04000000
395#define TX4939_CRYPTO_CSR_SDESO 0x02000000
396#define TX4939_CRYPTO_CSR_SDESI 0x01000000
397#define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000
398#define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20)
399#define TX4939_CRYPTO_CSR_TOINT 0x00080000
400#define TX4939_CRYPTO_CSR_DCINT 0x00040000
401#define TX4939_CRYPTO_CSR_GBINT 0x00010000
402#define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000
403#define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13)
404#define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800
405#define TX4939_CRYPTO_CSR_CSWAP_NONE 0x00000000
406#define TX4939_CRYPTO_CSR_CSWAP_IN 0x00000800
407#define TX4939_CRYPTO_CSR_CSWAP_OUT 0x00001000
408#define TX4939_CRYPTO_CSR_CSWAP_BOTH 0x00001800
409#define TX4939_CRYPTO_CSR_CDIV_MASK 0x00000600
410#define TX4939_CRYPTO_CSR_CDIV_DIV2 0x00000000
411#define TX4939_CRYPTO_CSR_CDIV_DIV1 0x00000200
412#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT 0x00000400
413#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT 0x00000600
414#define TX4939_CRYPTO_CSR_PDINT_MASK 0x000000c0
415#define TX4939_CRYPTO_CSR_PDINT_ALL 0x00000000
416#define TX4939_CRYPTO_CSR_PDINT_END 0x00000040
417#define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080
418#define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0
419#define TX4939_CRYPTO_CSR_GINTE 0x00000008
420#define TX4939_CRYPTO_CSR_RSTD 0x00000004
421#define TX4939_CRYPTO_CSR_RSTC 0x00000002
422#define TX4939_CRYPTO_CSR_ENCR 0x00000001
423
424/* bits for tx4939_crypto_reg.cdr.gen.ctrl */
425#define TX4939_CRYPTO_CTX_ENGINE_MASK 0x00000003
426#define TX4939_CRYPTO_CTX_ENGINE_DES 0x00000000
427#define TX4939_CRYPTO_CTX_ENGINE_AES 0x00000001
428#define TX4939_CRYPTO_CTX_ENGINE_MD5 0x00000002
429#define TX4939_CRYPTO_CTX_ENGINE_SHA1 0x00000003
430#define TX4939_CRYPTO_CTX_TDMS 0x00000010
431#define TX4939_CRYPTO_CTX_CMS 0x00000020
432#define TX4939_CRYPTO_CTX_DMS 0x00000040
433#define TX4939_CRYPTO_CTX_UPDATE 0x00000080
434
435/* bits for tx4939_crypto_desc.ctrl */
436#define TX4939_CRYPTO_DESC_OB_CNT_MASK 0xffe00000
437#define TX4939_CRYPTO_DESC_OB_CNT(cnt) ((cnt) << 21)
438#define TX4939_CRYPTO_DESC_IB_CNT_MASK 0x001ffc00
439#define TX4939_CRYPTO_DESC_IB_CNT(cnt) ((cnt) << 10)
440#define TX4939_CRYPTO_DESC_START 0x00000200
441#define TX4939_CRYPTO_DESC_END 0x00000100
442#define TX4939_CRYPTO_DESC_XOR 0x00000010
443#define TX4939_CRYPTO_DESC_LAST 0x00000008
444#define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006
445#define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000
446#define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002
447#define TX4939_CRYPTO_DESC_ERR_DIGEST 0x00000004
448#define TX4939_CRYPTO_DESC_OWN 0x00000001
449
450/* bits for tx4939_crypto_desc.index */
451#define TX4939_CRYPTO_DESC_HASH_IDX_MASK 0x00000070
452#define TX4939_CRYPTO_DESC_HASH_IDX(idx) ((idx) << 4)
453#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK 0x00000007
454#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx) ((idx) << 0)
455
456#define TX4939_CRYPTO_NR_SET 6
457
458#define TX4939_CRYPTO_RCSR_INTE 0x00000008
459#define TX4939_CRYPTO_RCSR_RST 0x00000004
460#define TX4939_CRYPTO_RCSR_FIN 0x00000002
461#define TX4939_CRYPTO_RCSR_ST 0x00000001
462
463/*
464 * VPC
465 */
466#define TX4939_VPC_CSR_GBINT 0x00010000
467#define TX4939_VPC_CSR_SWAPO 0x00000020
468#define TX4939_VPC_CSR_SWAPI 0x00000010
469#define TX4939_VPC_CSR_GINTE 0x00000008
470#define TX4939_VPC_CSR_RSTD 0x00000004
471#define TX4939_VPC_CSR_RSTVPC 0x00000002
472
473#define TX4939_VPC_CTRLA_VDPSN 0x00000200
474#define TX4939_VPC_CTRLA_PBUSY 0x00000100
475#define TX4939_VPC_CTRLA_DCINT 0x00000080
476#define TX4939_VPC_CTRLA_UOINT 0x00000040
477#define TX4939_VPC_CTRLA_PDINT_MASK 0x00000030
478#define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000
479#define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010
480#define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030
481#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
482#define TX4939_VPC_CTRLA_VDMODE 0x00000004
483#define TX4939_VPC_CTRLA_VDFOR 0x00000002
484#define TX4939_VPC_CTRLA_ENVPC 0x00000001
485
486/* bits for tx4939_vpc_desc.ctrl1 */
487#define TX4939_VPC_DESC_CTRL1_ERR_MASK 0x00000006
488#define TX4939_VPC_DESC_CTRL1_OWN 0x00000001
489
490#define tx4939_ddrcptr ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG)
491#define tx4939_ebuscptr tx4938_ebuscptr
492#define tx4939_ircptr \
493 ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG)
494#define tx4939_pcicptr tx4938_pcicptr
495#define tx4939_pcic1ptr tx4938_pcic1ptr
496#define tx4939_ccfgptr \
497 ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG)
498#define tx4939_sramcptr tx4938_sramcptr
499#define tx4939_rtcptr \
500 ((struct tx4939_rtc_reg __iomem *)TX4939_RTC_REG)
501#define tx4939_cryptoptr \
502 ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG)
503#define tx4939_vpcptr ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG)
504
505#define TX4939_REV_MAJ_MIN() \
506 ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff)
507#define TX4939_REV_PCODE() \
508 ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16)
509#define TX4939_CCFG_BCFG() \
510 ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
511 >> 32))
512
513#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
514#define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits)
515#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
516
517#define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
518#define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
519#define TX4939_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
520#define TX4939_EBUSC_WIDTH(ch) \
521 (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
522
523/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */
524#define TX4939_SCLK0(mst) \
525 ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
526
527void tx4939_wdt_init(void);
528void tx4939_add_memory_regions(void);
529void tx4939_setup(void);
530void tx4939_time_init(unsigned int tmrnr);
531void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
532void tx4939_spi_init(int busid);
533void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
534int tx4939_report_pciclk(void);
535void tx4939_report_pci1clk(void);
536struct pci_dev;
537int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
538int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
539void tx4939_setup_pcierr_irq(void);
540void tx4939_irq_init(void);
541int tx4939_irq(void);
542void tx4939_mtd_init(int ch);
543void tx4939_ata_init(void);
544
545#endif /* __ASM_TXX9_TX4939_H */
diff --git a/include/asm-mips/txx9irq.h b/arch/mips/include/asm/txx9irq.h
index 5620879be37f..5620879be37f 100644
--- a/include/asm-mips/txx9irq.h
+++ b/arch/mips/include/asm/txx9irq.h
diff --git a/include/asm-mips/txx9pio.h b/arch/mips/include/asm/txx9pio.h
index 3d6fa9f8d513..3d6fa9f8d513 100644
--- a/include/asm-mips/txx9pio.h
+++ b/arch/mips/include/asm/txx9pio.h
diff --git a/include/asm-mips/txx9tmr.h b/arch/mips/include/asm/txx9tmr.h
index 67f70a8f09bd..67f70a8f09bd 100644
--- a/include/asm-mips/txx9tmr.h
+++ b/arch/mips/include/asm/txx9tmr.h
diff --git a/include/asm-mips/types.h b/arch/mips/include/asm/types.h
index bcbb8d675af5..bcbb8d675af5 100644
--- a/include/asm-mips/types.h
+++ b/arch/mips/include/asm/types.h
diff --git a/include/asm-mips/uaccess.h b/arch/mips/include/asm/uaccess.h
index 66523d610950..09ff5bb17445 100644
--- a/include/asm-mips/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -13,7 +13,6 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/errno.h> 14#include <linux/errno.h>
15#include <linux/thread_info.h> 15#include <linux/thread_info.h>
16#include <asm-generic/uaccess.h>
17 16
18/* 17/*
19 * The fs value determines whether argument validity checking should be 18 * The fs value determines whether argument validity checking should be
@@ -224,7 +223,7 @@ do { \
224 223
225#define __get_user_nocheck(x, ptr, size) \ 224#define __get_user_nocheck(x, ptr, size) \
226({ \ 225({ \
227 long __gu_err; \ 226 int __gu_err; \
228 \ 227 \
229 __get_user_common((x), size, ptr); \ 228 __get_user_common((x), size, ptr); \
230 __gu_err; \ 229 __gu_err; \
@@ -232,7 +231,7 @@ do { \
232 231
233#define __get_user_check(x, ptr, size) \ 232#define __get_user_check(x, ptr, size) \
234({ \ 233({ \
235 long __gu_err = -EFAULT; \ 234 int __gu_err = -EFAULT; \
236 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ 235 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \
237 \ 236 \
238 if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ 237 if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \
@@ -304,7 +303,7 @@ do { \
304#define __put_user_nocheck(x, ptr, size) \ 303#define __put_user_nocheck(x, ptr, size) \
305({ \ 304({ \
306 __typeof__(*(ptr)) __pu_val; \ 305 __typeof__(*(ptr)) __pu_val; \
307 long __pu_err = 0; \ 306 int __pu_err = 0; \
308 \ 307 \
309 __pu_val = (x); \ 308 __pu_val = (x); \
310 switch (size) { \ 309 switch (size) { \
@@ -321,7 +320,7 @@ do { \
321({ \ 320({ \
322 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ 321 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
323 __typeof__(*(ptr)) __pu_val = (x); \ 322 __typeof__(*(ptr)) __pu_val = (x); \
324 long __pu_err = -EFAULT; \ 323 int __pu_err = -EFAULT; \
325 \ 324 \
326 if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \ 325 if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \
327 switch (size) { \ 326 switch (size) { \
@@ -374,6 +373,269 @@ do { \
374extern void __put_user_unknown(void); 373extern void __put_user_unknown(void);
375 374
376/* 375/*
376 * put_user_unaligned: - Write a simple value into user space.
377 * @x: Value to copy to user space.
378 * @ptr: Destination address, in user space.
379 *
380 * Context: User context only. This function may sleep.
381 *
382 * This macro copies a single simple value from kernel space to user
383 * space. It supports simple types like char and int, but not larger
384 * data types like structures or arrays.
385 *
386 * @ptr must have pointer-to-simple-variable type, and @x must be assignable
387 * to the result of dereferencing @ptr.
388 *
389 * Returns zero on success, or -EFAULT on error.
390 */
391#define put_user_unaligned(x,ptr) \
392 __put_user_unaligned_check((x),(ptr),sizeof(*(ptr)))
393
394/*
395 * get_user_unaligned: - Get a simple variable from user space.
396 * @x: Variable to store result.
397 * @ptr: Source address, in user space.
398 *
399 * Context: User context only. This function may sleep.
400 *
401 * This macro copies a single simple variable from user space to kernel
402 * space. It supports simple types like char and int, but not larger
403 * data types like structures or arrays.
404 *
405 * @ptr must have pointer-to-simple-variable type, and the result of
406 * dereferencing @ptr must be assignable to @x without a cast.
407 *
408 * Returns zero on success, or -EFAULT on error.
409 * On error, the variable @x is set to zero.
410 */
411#define get_user_unaligned(x,ptr) \
412 __get_user_unaligned_check((x),(ptr),sizeof(*(ptr)))
413
414/*
415 * __put_user_unaligned: - Write a simple value into user space, with less checking.
416 * @x: Value to copy to user space.
417 * @ptr: Destination address, in user space.
418 *
419 * Context: User context only. This function may sleep.
420 *
421 * This macro copies a single simple value from kernel space to user
422 * space. It supports simple types like char and int, but not larger
423 * data types like structures or arrays.
424 *
425 * @ptr must have pointer-to-simple-variable type, and @x must be assignable
426 * to the result of dereferencing @ptr.
427 *
428 * Caller must check the pointer with access_ok() before calling this
429 * function.
430 *
431 * Returns zero on success, or -EFAULT on error.
432 */
433#define __put_user_unaligned(x,ptr) \
434 __put_user_unaligned_nocheck((x),(ptr),sizeof(*(ptr)))
435
436/*
437 * __get_user_unaligned: - Get a simple variable from user space, with less checking.
438 * @x: Variable to store result.
439 * @ptr: Source address, in user space.
440 *
441 * Context: User context only. This function may sleep.
442 *
443 * This macro copies a single simple variable from user space to kernel
444 * space. It supports simple types like char and int, but not larger
445 * data types like structures or arrays.
446 *
447 * @ptr must have pointer-to-simple-variable type, and the result of
448 * dereferencing @ptr must be assignable to @x without a cast.
449 *
450 * Caller must check the pointer with access_ok() before calling this
451 * function.
452 *
453 * Returns zero on success, or -EFAULT on error.
454 * On error, the variable @x is set to zero.
455 */
456#define __get_user_unaligned(x,ptr) \
457 __get_user__unalignednocheck((x),(ptr),sizeof(*(ptr)))
458
459/*
460 * Yuck. We need two variants, one for 64bit operation and one
461 * for 32 bit mode and old iron.
462 */
463#ifdef CONFIG_32BIT
464#define __GET_USER_UNALIGNED_DW(val, ptr) \
465 __get_user_unaligned_asm_ll32(val, ptr)
466#endif
467#ifdef CONFIG_64BIT
468#define __GET_USER_UNALIGNED_DW(val, ptr) \
469 __get_user_unaligned_asm(val, "uld", ptr)
470#endif
471
472extern void __get_user_unaligned_unknown(void);
473
474#define __get_user_unaligned_common(val, size, ptr) \
475do { \
476 switch (size) { \
477 case 1: __get_user_asm(val, "lb", ptr); break; \
478 case 2: __get_user_unaligned_asm(val, "ulh", ptr); break; \
479 case 4: __get_user_unaligned_asm(val, "ulw", ptr); break; \
480 case 8: __GET_USER_UNALIGNED_DW(val, ptr); break; \
481 default: __get_user_unaligned_unknown(); break; \
482 } \
483} while (0)
484
485#define __get_user_unaligned_nocheck(x,ptr,size) \
486({ \
487 int __gu_err; \
488 \
489 __get_user_unaligned_common((x), size, ptr); \
490 __gu_err; \
491})
492
493#define __get_user_unaligned_check(x,ptr,size) \
494({ \
495 int __gu_err = -EFAULT; \
496 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \
497 \
498 if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \
499 __get_user_unaligned_common((x), size, __gu_ptr); \
500 \
501 __gu_err; \
502})
503
504#define __get_user_unaligned_asm(val, insn, addr) \
505{ \
506 long __gu_tmp; \
507 \
508 __asm__ __volatile__( \
509 "1: " insn " %1, %3 \n" \
510 "2: \n" \
511 " .section .fixup,\"ax\" \n" \
512 "3: li %0, %4 \n" \
513 " j 2b \n" \
514 " .previous \n" \
515 " .section __ex_table,\"a\" \n" \
516 " "__UA_ADDR "\t1b, 3b \n" \
517 " "__UA_ADDR "\t1b + 4, 3b \n" \
518 " .previous \n" \
519 : "=r" (__gu_err), "=r" (__gu_tmp) \
520 : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \
521 \
522 (val) = (__typeof__(*(addr))) __gu_tmp; \
523}
524
525/*
526 * Get a long long 64 using 32 bit registers.
527 */
528#define __get_user_unaligned_asm_ll32(val, addr) \
529{ \
530 unsigned long long __gu_tmp; \
531 \
532 __asm__ __volatile__( \
533 "1: ulw %1, (%3) \n" \
534 "2: ulw %D1, 4(%3) \n" \
535 " move %0, $0 \n" \
536 "3: .section .fixup,\"ax\" \n" \
537 "4: li %0, %4 \n" \
538 " move %1, $0 \n" \
539 " move %D1, $0 \n" \
540 " j 3b \n" \
541 " .previous \n" \
542 " .section __ex_table,\"a\" \n" \
543 " " __UA_ADDR " 1b, 4b \n" \
544 " " __UA_ADDR " 1b + 4, 4b \n" \
545 " " __UA_ADDR " 2b, 4b \n" \
546 " " __UA_ADDR " 2b + 4, 4b \n" \
547 " .previous \n" \
548 : "=r" (__gu_err), "=&r" (__gu_tmp) \
549 : "0" (0), "r" (addr), "i" (-EFAULT)); \
550 (val) = (__typeof__(*(addr))) __gu_tmp; \
551}
552
553/*
554 * Yuck. We need two variants, one for 64bit operation and one
555 * for 32 bit mode and old iron.
556 */
557#ifdef CONFIG_32BIT
558#define __PUT_USER_UNALIGNED_DW(ptr) __put_user_unaligned_asm_ll32(ptr)
559#endif
560#ifdef CONFIG_64BIT
561#define __PUT_USER_UNALIGNED_DW(ptr) __put_user_unaligned_asm("usd", ptr)
562#endif
563
564#define __put_user_unaligned_nocheck(x,ptr,size) \
565({ \
566 __typeof__(*(ptr)) __pu_val; \
567 int __pu_err = 0; \
568 \
569 __pu_val = (x); \
570 switch (size) { \
571 case 1: __put_user_asm("sb", ptr); break; \
572 case 2: __put_user_unaligned_asm("ush", ptr); break; \
573 case 4: __put_user_unaligned_asm("usw", ptr); break; \
574 case 8: __PUT_USER_UNALIGNED_DW(ptr); break; \
575 default: __put_user_unaligned_unknown(); break; \
576 } \
577 __pu_err; \
578})
579
580#define __put_user_unaligned_check(x,ptr,size) \
581({ \
582 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
583 __typeof__(*(ptr)) __pu_val = (x); \
584 int __pu_err = -EFAULT; \
585 \
586 if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \
587 switch (size) { \
588 case 1: __put_user_asm("sb", __pu_addr); break; \
589 case 2: __put_user_unaligned_asm("ush", __pu_addr); break; \
590 case 4: __put_user_unaligned_asm("usw", __pu_addr); break; \
591 case 8: __PUT_USER_UNALGINED_DW(__pu_addr); break; \
592 default: __put_user_unaligned_unknown(); break; \
593 } \
594 } \
595 __pu_err; \
596})
597
598#define __put_user_unaligned_asm(insn, ptr) \
599{ \
600 __asm__ __volatile__( \
601 "1: " insn " %z2, %3 # __put_user_unaligned_asm\n" \
602 "2: \n" \
603 " .section .fixup,\"ax\" \n" \
604 "3: li %0, %4 \n" \
605 " j 2b \n" \
606 " .previous \n" \
607 " .section __ex_table,\"a\" \n" \
608 " " __UA_ADDR " 1b, 3b \n" \
609 " .previous \n" \
610 : "=r" (__pu_err) \
611 : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)), \
612 "i" (-EFAULT)); \
613}
614
615#define __put_user_unaligned_asm_ll32(ptr) \
616{ \
617 __asm__ __volatile__( \
618 "1: sw %2, (%3) # __put_user_unaligned_asm_ll32 \n" \
619 "2: sw %D2, 4(%3) \n" \
620 "3: \n" \
621 " .section .fixup,\"ax\" \n" \
622 "4: li %0, %4 \n" \
623 " j 3b \n" \
624 " .previous \n" \
625 " .section __ex_table,\"a\" \n" \
626 " " __UA_ADDR " 1b, 4b \n" \
627 " " __UA_ADDR " 1b + 4, 4b \n" \
628 " " __UA_ADDR " 2b, 4b \n" \
629 " " __UA_ADDR " 2b + 4, 4b \n" \
630 " .previous" \
631 : "=r" (__pu_err) \
632 : "0" (0), "r" (__pu_val), "r" (ptr), \
633 "i" (-EFAULT)); \
634}
635
636extern void __put_user_unaligned_unknown(void);
637
638/*
377 * We're generating jump to subroutines which will be outside the range of 639 * We're generating jump to subroutines which will be outside the range of
378 * jump instructions 640 * jump instructions
379 */ 641 */
diff --git a/include/asm-mips/ucontext.h b/arch/mips/include/asm/ucontext.h
index 8a4b20e88b81..8a4b20e88b81 100644
--- a/include/asm-mips/ucontext.h
+++ b/arch/mips/include/asm/ucontext.h
diff --git a/include/asm-mips/unaligned.h b/arch/mips/include/asm/unaligned.h
index 792404948571..792404948571 100644
--- a/include/asm-mips/unaligned.h
+++ b/arch/mips/include/asm/unaligned.h
diff --git a/include/asm-mips/unistd.h b/arch/mips/include/asm/unistd.h
index a73e1531e151..a73e1531e151 100644
--- a/include/asm-mips/unistd.h
+++ b/arch/mips/include/asm/unistd.h
diff --git a/include/asm-mips/user.h b/arch/mips/include/asm/user.h
index afa83a4c1888..afa83a4c1888 100644
--- a/include/asm-mips/user.h
+++ b/arch/mips/include/asm/user.h
diff --git a/include/asm-mips/vga.h b/arch/mips/include/asm/vga.h
index f4cff7e4fa8a..f4cff7e4fa8a 100644
--- a/include/asm-mips/vga.h
+++ b/arch/mips/include/asm/vga.h
diff --git a/include/asm-mips/vpe.h b/arch/mips/include/asm/vpe.h
index c6e1b961537d..c6e1b961537d 100644
--- a/include/asm-mips/vpe.h
+++ b/arch/mips/include/asm/vpe.h
diff --git a/include/asm-mips/vr41xx/capcella.h b/arch/mips/include/asm/vr41xx/capcella.h
index e0ee05a3dfcc..e0ee05a3dfcc 100644
--- a/include/asm-mips/vr41xx/capcella.h
+++ b/arch/mips/include/asm/vr41xx/capcella.h
diff --git a/include/asm-mips/vr41xx/giu.h b/arch/mips/include/asm/vr41xx/giu.h
index 0bcdd3a5c256..0bcdd3a5c256 100644
--- a/include/asm-mips/vr41xx/giu.h
+++ b/arch/mips/include/asm/vr41xx/giu.h
diff --git a/include/asm-mips/vr41xx/irq.h b/arch/mips/include/asm/vr41xx/irq.h
index d315dfbc08f2..d315dfbc08f2 100644
--- a/include/asm-mips/vr41xx/irq.h
+++ b/arch/mips/include/asm/vr41xx/irq.h
diff --git a/include/asm-mips/vr41xx/mpc30x.h b/arch/mips/include/asm/vr41xx/mpc30x.h
index 1d67df843dc3..1d67df843dc3 100644
--- a/include/asm-mips/vr41xx/mpc30x.h
+++ b/arch/mips/include/asm/vr41xx/mpc30x.h
diff --git a/include/asm-mips/vr41xx/pci.h b/arch/mips/include/asm/vr41xx/pci.h
index 6fc01ce19777..6fc01ce19777 100644
--- a/include/asm-mips/vr41xx/pci.h
+++ b/arch/mips/include/asm/vr41xx/pci.h
diff --git a/include/asm-mips/vr41xx/siu.h b/arch/mips/include/asm/vr41xx/siu.h
index da9f6e373409..da9f6e373409 100644
--- a/include/asm-mips/vr41xx/siu.h
+++ b/arch/mips/include/asm/vr41xx/siu.h
diff --git a/include/asm-mips/vr41xx/tb0219.h b/arch/mips/include/asm/vr41xx/tb0219.h
index dc981b4be0a4..dc981b4be0a4 100644
--- a/include/asm-mips/vr41xx/tb0219.h
+++ b/arch/mips/include/asm/vr41xx/tb0219.h
diff --git a/include/asm-mips/vr41xx/tb0226.h b/arch/mips/include/asm/vr41xx/tb0226.h
index de527dcfa5f3..de527dcfa5f3 100644
--- a/include/asm-mips/vr41xx/tb0226.h
+++ b/arch/mips/include/asm/vr41xx/tb0226.h
diff --git a/include/asm-mips/vr41xx/tb0287.h b/arch/mips/include/asm/vr41xx/tb0287.h
index 61bead68abf0..61bead68abf0 100644
--- a/include/asm-mips/vr41xx/tb0287.h
+++ b/arch/mips/include/asm/vr41xx/tb0287.h
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/arch/mips/include/asm/vr41xx/vr41xx.h
index 22be64971cc6..22be64971cc6 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/arch/mips/include/asm/vr41xx/vr41xx.h
diff --git a/include/asm-mips/war.h b/arch/mips/include/asm/war.h
index 22361d5e3bf0..22361d5e3bf0 100644
--- a/include/asm-mips/war.h
+++ b/arch/mips/include/asm/war.h
diff --git a/arch/mips/include/asm/watch.h b/arch/mips/include/asm/watch.h
new file mode 100644
index 000000000000..20126ec79359
--- /dev/null
+++ b/arch/mips/include/asm/watch.h
@@ -0,0 +1,32 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 David Daney
7 */
8#ifndef _ASM_WATCH_H
9#define _ASM_WATCH_H
10
11#include <linux/bitops.h>
12
13#include <asm/mipsregs.h>
14
15void mips_install_watch_registers(void);
16void mips_read_watch_registers(void);
17void mips_clear_watch_registers(void);
18void mips_probe_watch_registers(struct cpuinfo_mips *c);
19
20#ifdef CONFIG_HARDWARE_WATCHPOINTS
21#define __restore_watch() do { \
22 if (unlikely(test_bit(TIF_LOAD_WATCH, \
23 &current_thread_info()->flags))) { \
24 mips_install_watch_registers(); \
25 } \
26} while (0)
27
28#else
29#define __restore_watch() do {} while (0)
30#endif
31
32#endif /* _ASM_WATCH_H */
diff --git a/include/asm-mips/wbflush.h b/arch/mips/include/asm/wbflush.h
index eadc0ac47e24..eadc0ac47e24 100644
--- a/include/asm-mips/wbflush.h
+++ b/arch/mips/include/asm/wbflush.h
diff --git a/include/asm-mips/xor.h b/arch/mips/include/asm/xor.h
index c82eb12a5b18..c82eb12a5b18 100644
--- a/include/asm-mips/xor.h
+++ b/arch/mips/include/asm/xor.h
diff --git a/include/asm-mips/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
index 79bac882a739..79bac882a739 100644
--- a/include/asm-mips/xtalk/xtalk.h
+++ b/arch/mips/include/asm/xtalk/xtalk.h
diff --git a/include/asm-mips/xtalk/xwidget.h b/arch/mips/include/asm/xtalk/xwidget.h
index b4a13d7405ee..b4a13d7405ee 100644
--- a/include/asm-mips/xtalk/xwidget.h
+++ b/arch/mips/include/asm/xtalk/xwidget.h
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 25775cb54000..d9da7112aaf8 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -6,7 +6,7 @@ extra-y := head.o init_task.o vmlinux.lds
6 6
7obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ 7obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
8 ptrace.o reset.o setup.o signal.o syscall.o \ 8 ptrace.o reset.o setup.o signal.o syscall.o \
9 time.o topology.o traps.o unaligned.o 9 time.o topology.o traps.o unaligned.o watch.o
10 10
11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o 11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
12obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o 12obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e621fda8ab37..0cf15457ecac 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -21,6 +21,7 @@
21#include <asm/fpu.h> 21#include <asm/fpu.h>
22#include <asm/mipsregs.h> 22#include <asm/mipsregs.h>
23#include <asm/system.h> 23#include <asm/system.h>
24#include <asm/watch.h>
24 25
25/* 26/*
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
@@ -677,6 +678,7 @@ static inline void spram_config(void) {}
677static inline void cpu_probe_mips(struct cpuinfo_mips *c) 678static inline void cpu_probe_mips(struct cpuinfo_mips *c)
678{ 679{
679 decode_configs(c); 680 decode_configs(c);
681 mips_probe_watch_registers(c);
680 switch (c->processor_id & 0xff00) { 682 switch (c->processor_id & 0xff00) {
681 case PRID_IMP_4KC: 683 case PRID_IMP_4KC:
682 c->cputype = CPU_4KC; 684 c->cputype = CPU_4KC;
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 01dcbe38fa01..757d48f0d80f 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -453,7 +453,11 @@ NESTED(nmi_handler, PT_SIZE, sp)
453 BUILD_HANDLER tr tr sti silent /* #13 */ 453 BUILD_HANDLER tr tr sti silent /* #13 */
454 BUILD_HANDLER fpe fpe fpe silent /* #15 */ 454 BUILD_HANDLER fpe fpe fpe silent /* #15 */
455 BUILD_HANDLER mdmx mdmx sti silent /* #22 */ 455 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
456#ifdef CONFIG_HARDWARE_WATCHPOINTS
457 BUILD_HANDLER watch watch sti silent /* #23 */
458#else
456 BUILD_HANDLER watch watch sti verbose /* #23 */ 459 BUILD_HANDLER watch watch sti verbose /* #23 */
460#endif
457 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ 461 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
458 BUILD_HANDLER mt mt sti silent /* #25 */ 462 BUILD_HANDLER mt mt sti silent /* #25 */
459 BUILD_HANDLER dsp dsp sti silent /* #26 */ 463 BUILD_HANDLER dsp dsp sti silent /* #26 */
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 36f065398243..75bb1300dd7a 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -23,6 +23,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
23 unsigned int version = cpu_data[n].processor_id; 23 unsigned int version = cpu_data[n].processor_id;
24 unsigned int fp_vers = cpu_data[n].fpu_id; 24 unsigned int fp_vers = cpu_data[n].fpu_id;
25 char fmt [64]; 25 char fmt [64];
26 int i;
26 27
27#ifdef CONFIG_SMP 28#ifdef CONFIG_SMP
28 if (!cpu_isset(n, cpu_online_map)) 29 if (!cpu_isset(n, cpu_online_map))
@@ -50,8 +51,16 @@ static int show_cpuinfo(struct seq_file *m, void *v)
50 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); 51 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
51 seq_printf(m, "extra interrupt vector\t: %s\n", 52 seq_printf(m, "extra interrupt vector\t: %s\n",
52 cpu_has_divec ? "yes" : "no"); 53 cpu_has_divec ? "yes" : "no");
53 seq_printf(m, "hardware watchpoint\t: %s\n", 54 seq_printf(m, "hardware watchpoint\t: %s",
54 cpu_has_watch ? "yes" : "no"); 55 cpu_has_watch ? "yes, " : "no\n");
56 if (cpu_has_watch) {
57 seq_printf(m, "count: %d, address/irw mask: [",
58 cpu_data[n].watch_reg_count);
59 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
60 seq_printf(m, "%s0x%04x", i ? ", " : "" ,
61 cpu_data[n].watch_reg_masks[i]);
62 seq_printf(m, "]\n");
63 }
55 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", 64 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
56 cpu_has_mips16 ? " mips16" : "", 65 cpu_has_mips16 ? " mips16" : "",
57 cpu_has_mdmx ? " mdmx" : "", 66 cpu_has_mdmx ? " mdmx" : "",
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 96ffc9c6d194..054861ccb4dd 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -46,7 +46,8 @@
46 */ 46 */
47void ptrace_disable(struct task_struct *child) 47void ptrace_disable(struct task_struct *child)
48{ 48{
49 /* Nothing to do.. */ 49 /* Don't load the watchpoint registers for the ex-child. */
50 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
50} 51}
51 52
52/* 53/*
@@ -167,6 +168,93 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
167 return 0; 168 return 0;
168} 169}
169 170
171int ptrace_get_watch_regs(struct task_struct *child,
172 struct pt_watch_regs __user *addr)
173{
174 enum pt_watch_style style;
175 int i;
176
177 if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
178 return -EIO;
179 if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
180 return -EIO;
181
182#ifdef CONFIG_32BIT
183 style = pt_watch_style_mips32;
184#define WATCH_STYLE mips32
185#else
186 style = pt_watch_style_mips64;
187#define WATCH_STYLE mips64
188#endif
189
190 __put_user(style, &addr->style);
191 __put_user(current_cpu_data.watch_reg_use_cnt,
192 &addr->WATCH_STYLE.num_valid);
193 for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
194 __put_user(child->thread.watch.mips3264.watchlo[i],
195 &addr->WATCH_STYLE.watchlo[i]);
196 __put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
197 &addr->WATCH_STYLE.watchhi[i]);
198 __put_user(current_cpu_data.watch_reg_masks[i],
199 &addr->WATCH_STYLE.watch_masks[i]);
200 }
201 for (; i < 8; i++) {
202 __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
203 __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
204 __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
205 }
206
207 return 0;
208}
209
210int ptrace_set_watch_regs(struct task_struct *child,
211 struct pt_watch_regs __user *addr)
212{
213 int i;
214 int watch_active = 0;
215 unsigned long lt[NUM_WATCH_REGS];
216 u16 ht[NUM_WATCH_REGS];
217
218 if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
219 return -EIO;
220 if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
221 return -EIO;
222 /* Check the values. */
223 for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
224 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
225#ifdef CONFIG_32BIT
226 if (lt[i] & __UA_LIMIT)
227 return -EINVAL;
228#else
229 if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
230 if (lt[i] & 0xffffffff80000000UL)
231 return -EINVAL;
232 } else {
233 if (lt[i] & __UA_LIMIT)
234 return -EINVAL;
235 }
236#endif
237 __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
238 if (ht[i] & ~0xff8)
239 return -EINVAL;
240 }
241 /* Install them. */
242 for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
243 if (lt[i] & 7)
244 watch_active = 1;
245 child->thread.watch.mips3264.watchlo[i] = lt[i];
246 /* Set the G bit. */
247 child->thread.watch.mips3264.watchhi[i] = ht[i];
248 }
249
250 if (watch_active)
251 set_tsk_thread_flag(child, TIF_LOAD_WATCH);
252 else
253 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
254
255 return 0;
256}
257
170long arch_ptrace(struct task_struct *child, long request, long addr, long data) 258long arch_ptrace(struct task_struct *child, long request, long addr, long data)
171{ 259{
172 int ret; 260 int ret;
@@ -440,6 +528,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
440 (unsigned long __user *) data); 528 (unsigned long __user *) data);
441 break; 529 break;
442 530
531 case PTRACE_GET_WATCH_REGS:
532 ret = ptrace_get_watch_regs(child,
533 (struct pt_watch_regs __user *) addr);
534 break;
535
536 case PTRACE_SET_WATCH_REGS:
537 ret = ptrace_set_watch_regs(child,
538 (struct pt_watch_regs __user *) addr);
539 break;
540
443 default: 541 default:
444 ret = ptrace_request(child, request, addr, data); 542 ret = ptrace_request(child, request, addr, data);
445 break; 543 break;
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 76818be6ba7c..1ca34104e593 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -15,6 +15,7 @@
15 * binaries. 15 * binaries.
16 */ 16 */
17#include <linux/compiler.h> 17#include <linux/compiler.h>
18#include <linux/compat.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/sched.h> 20#include <linux/sched.h>
20#include <linux/mm.h> 21#include <linux/mm.h>
@@ -36,47 +37,17 @@
36#include <asm/uaccess.h> 37#include <asm/uaccess.h>
37#include <asm/bootinfo.h> 38#include <asm/bootinfo.h>
38 39
39int ptrace_getregs(struct task_struct *child, __s64 __user *data);
40int ptrace_setregs(struct task_struct *child, __s64 __user *data);
41
42int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
43int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
44
45/* 40/*
46 * Tracing a 32-bit process with a 64-bit strace and vice versa will not 41 * Tracing a 32-bit process with a 64-bit strace and vice versa will not
47 * work. I don't know how to fix this. 42 * work. I don't know how to fix this.
48 */ 43 */
49asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) 44long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
45 compat_ulong_t caddr, compat_ulong_t cdata)
50{ 46{
51 struct task_struct *child; 47 int addr = caddr;
48 int data = cdata;
52 int ret; 49 int ret;
53 50
54#if 0
55 printk("ptrace(r=%d,pid=%d,addr=%08lx,data=%08lx)\n",
56 (int) request, (int) pid, (unsigned long) addr,
57 (unsigned long) data);
58#endif
59 lock_kernel();
60 if (request == PTRACE_TRACEME) {
61 ret = ptrace_traceme();
62 goto out;
63 }
64
65 child = ptrace_get_task_struct(pid);
66 if (IS_ERR(child)) {
67 ret = PTR_ERR(child);
68 goto out;
69 }
70
71 if (request == PTRACE_ATTACH) {
72 ret = ptrace_attach(child);
73 goto out_tsk;
74 }
75
76 ret = ptrace_check_attach(child, request == PTRACE_KILL);
77 if (ret < 0)
78 goto out_tsk;
79
80 switch (request) { 51 switch (request) {
81 /* when I and D space are separate, these will need to be fixed. */ 52 /* when I and D space are separate, these will need to be fixed. */
82 case PTRACE_PEEKTEXT: /* read word at location addr. */ 53 case PTRACE_PEEKTEXT: /* read word at location addr. */
@@ -214,7 +185,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
214 if (!cpu_has_dsp) { 185 if (!cpu_has_dsp) {
215 tmp = 0; 186 tmp = 0;
216 ret = -EIO; 187 ret = -EIO;
217 goto out_tsk; 188 goto out;
218 } 189 }
219 dregs = __get_dsp_regs(child); 190 dregs = __get_dsp_regs(child);
220 tmp = (unsigned long) (dregs[addr - DSP_BASE]); 191 tmp = (unsigned long) (dregs[addr - DSP_BASE]);
@@ -224,14 +195,14 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
224 if (!cpu_has_dsp) { 195 if (!cpu_has_dsp) {
225 tmp = 0; 196 tmp = 0;
226 ret = -EIO; 197 ret = -EIO;
227 goto out_tsk; 198 goto out;
228 } 199 }
229 tmp = child->thread.dsp.dspcontrol; 200 tmp = child->thread.dsp.dspcontrol;
230 break; 201 break;
231 default: 202 default:
232 tmp = 0; 203 tmp = 0;
233 ret = -EIO; 204 ret = -EIO;
234 goto out_tsk; 205 goto out;
235 } 206 }
236 ret = put_user(tmp, (unsigned __user *) (unsigned long) data); 207 ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
237 break; 208 break;
@@ -410,14 +381,20 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
410 (unsigned long __user *) (unsigned long) data); 381 (unsigned long __user *) (unsigned long) data);
411 break; 382 break;
412 383
384 case PTRACE_GET_WATCH_REGS:
385 ret = ptrace_get_watch_regs(child,
386 (struct pt_watch_regs __user *) (unsigned long) addr);
387 break;
388
389 case PTRACE_SET_WATCH_REGS:
390 ret = ptrace_set_watch_regs(child,
391 (struct pt_watch_regs __user *) (unsigned long) addr);
392 break;
393
413 default: 394 default:
414 ret = ptrace_request(child, request, addr, data); 395 ret = ptrace_request(child, request, addr, data);
415 break; 396 break;
416 } 397 }
417
418out_tsk:
419 put_task_struct(child);
420out: 398out:
421 unlock_kernel();
422 return ret; 399 return ret;
423} 400}
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index da7f1b6ea0fb..324c5499dec2 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -219,7 +219,7 @@ EXPORT(sysn32_call_table)
219 PTR compat_sys_getrusage 219 PTR compat_sys_getrusage
220 PTR compat_sys_sysinfo 220 PTR compat_sys_sysinfo
221 PTR compat_sys_times 221 PTR compat_sys_times
222 PTR sys32_ptrace 222 PTR compat_sys_ptrace
223 PTR sys_getuid /* 6100 */ 223 PTR sys_getuid /* 6100 */
224 PTR sys_syslog 224 PTR sys_syslog
225 PTR sys_getgid 225 PTR sys_getgid
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index d7cd1aac9ada..85fedac99a57 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -231,7 +231,7 @@ sys_call_table:
231 PTR sys_setuid 231 PTR sys_setuid
232 PTR sys_getuid 232 PTR sys_getuid
233 PTR compat_sys_stime /* 4025 */ 233 PTR compat_sys_stime /* 4025 */
234 PTR sys32_ptrace 234 PTR compat_sys_ptrace
235 PTR sys_alarm 235 PTR sys_alarm
236 PTR sys_ni_syscall /* was sys_fstat */ 236 PTR sys_ni_syscall /* was sys_fstat */
237 PTR sys_pause 237 PTR sys_pause
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 572c610db1b1..652709b353ad 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -482,6 +482,18 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
482 return err; 482 return err;
483} 483}
484 484
485int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
486{
487 memset(to, 0, sizeof *to);
488
489 if (copy_from_user(to, from, 3*sizeof(int)) ||
490 copy_from_user(to->_sifields._pad,
491 from->_sifields._pad, SI_PAD_SIZE32))
492 return -EFAULT;
493
494 return 0;
495}
496
485asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs) 497asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
486{ 498{
487 struct sigframe32 __user *frame; 499 struct sigframe32 __user *frame;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b602ac6eb47d..80b9e070c207 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -42,6 +42,7 @@
42#include <asm/tlbdebug.h> 42#include <asm/tlbdebug.h>
43#include <asm/traps.h> 43#include <asm/traps.h>
44#include <asm/uaccess.h> 44#include <asm/uaccess.h>
45#include <asm/watch.h>
45#include <asm/mmu_context.h> 46#include <asm/mmu_context.h>
46#include <asm/types.h> 47#include <asm/types.h>
47#include <asm/stacktrace.h> 48#include <asm/stacktrace.h>
@@ -912,13 +913,26 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
912 913
913asmlinkage void do_watch(struct pt_regs *regs) 914asmlinkage void do_watch(struct pt_regs *regs)
914{ 915{
916 u32 cause;
917
915 /* 918 /*
916 * We use the watch exception where available to detect stack 919 * Clear WP (bit 22) bit of cause register so we don't loop
917 * overflows. 920 * forever.
918 */ 921 */
919 dump_tlb_all(); 922 cause = read_c0_cause();
920 show_regs(regs); 923 cause &= ~(1 << 22);
921 panic("Caught WATCH exception - probably caused by stack overflow."); 924 write_c0_cause(cause);
925
926 /*
927 * If the current thread has the watch registers loaded, save
928 * their values and send SIGTRAP. Otherwise another thread
929 * left the registers set, clear them and continue.
930 */
931 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
932 mips_read_watch_registers();
933 force_sig(SIGTRAP, current);
934 } else
935 mips_clear_watch_registers();
922} 936}
923 937
924asmlinkage void do_mcheck(struct pt_regs *regs) 938asmlinkage void do_mcheck(struct pt_regs *regs)
diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
new file mode 100644
index 000000000000..c15406968030
--- /dev/null
+++ b/arch/mips/kernel/watch.c
@@ -0,0 +1,188 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 David Daney
7 */
8
9#include <linux/sched.h>
10
11#include <asm/processor.h>
12#include <asm/watch.h>
13
14/*
15 * Install the watch registers for the current thread. A maximum of
16 * four registers are installed although the machine may have more.
17 */
18void mips_install_watch_registers(void)
19{
20 struct mips3264_watch_reg_state *watches =
21 &current->thread.watch.mips3264;
22 switch (current_cpu_data.watch_reg_use_cnt) {
23 default:
24 BUG();
25 case 4:
26 write_c0_watchlo3(watches->watchlo[3]);
27 /* Write 1 to the I, R, and W bits to clear them, and
28 1 to G so all ASIDs are trapped. */
29 write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
30 case 3:
31 write_c0_watchlo2(watches->watchlo[2]);
32 write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
33 case 2:
34 write_c0_watchlo1(watches->watchlo[1]);
35 write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
36 case 1:
37 write_c0_watchlo0(watches->watchlo[0]);
38 write_c0_watchhi0(0x40000007 | watches->watchhi[0]);
39 }
40}
41
42/*
43 * Read back the watchhi registers so the user space debugger has
44 * access to the I, R, and W bits. A maximum of four registers are
45 * read although the machine may have more.
46 */
47void mips_read_watch_registers(void)
48{
49 struct mips3264_watch_reg_state *watches =
50 &current->thread.watch.mips3264;
51 switch (current_cpu_data.watch_reg_use_cnt) {
52 default:
53 BUG();
54 case 4:
55 watches->watchhi[3] = (read_c0_watchhi3() & 0x0fff);
56 case 3:
57 watches->watchhi[2] = (read_c0_watchhi2() & 0x0fff);
58 case 2:
59 watches->watchhi[1] = (read_c0_watchhi1() & 0x0fff);
60 case 1:
61 watches->watchhi[0] = (read_c0_watchhi0() & 0x0fff);
62 }
63 if (current_cpu_data.watch_reg_use_cnt == 1 &&
64 (watches->watchhi[0] & 7) == 0) {
65 /* Pathological case of release 1 architecture that
66 * doesn't set the condition bits. We assume that
67 * since we got here, the watch condition was met and
68 * signal that the conditions requested in watchlo
69 * were met. */
70 watches->watchhi[0] |= (watches->watchlo[0] & 7);
71 }
72 }
73
74/*
75 * Disable all watch registers. Although only four registers are
76 * installed, all are cleared to eliminate the possibility of endless
77 * looping in the watch handler.
78 */
79void mips_clear_watch_registers(void)
80{
81 switch (current_cpu_data.watch_reg_count) {
82 default:
83 BUG();
84 case 8:
85 write_c0_watchlo7(0);
86 case 7:
87 write_c0_watchlo6(0);
88 case 6:
89 write_c0_watchlo5(0);
90 case 5:
91 write_c0_watchlo4(0);
92 case 4:
93 write_c0_watchlo3(0);
94 case 3:
95 write_c0_watchlo2(0);
96 case 2:
97 write_c0_watchlo1(0);
98 case 1:
99 write_c0_watchlo0(0);
100 }
101}
102
103__cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
104{
105 unsigned int t;
106
107 if ((c->options & MIPS_CPU_WATCH) == 0)
108 return;
109 /*
110 * Check which of the I,R and W bits are supported, then
111 * disable the register.
112 */
113 write_c0_watchlo0(7);
114 t = read_c0_watchlo0();
115 write_c0_watchlo0(0);
116 c->watch_reg_masks[0] = t & 7;
117
118 /* Write the mask bits and read them back to determine which
119 * can be used. */
120 c->watch_reg_count = 1;
121 c->watch_reg_use_cnt = 1;
122 t = read_c0_watchhi0();
123 write_c0_watchhi0(t | 0xff8);
124 t = read_c0_watchhi0();
125 c->watch_reg_masks[0] |= (t & 0xff8);
126 if ((t & 0x80000000) == 0)
127 return;
128
129 write_c0_watchlo1(7);
130 t = read_c0_watchlo1();
131 write_c0_watchlo1(0);
132 c->watch_reg_masks[1] = t & 7;
133
134 c->watch_reg_count = 2;
135 c->watch_reg_use_cnt = 2;
136 t = read_c0_watchhi1();
137 write_c0_watchhi1(t | 0xff8);
138 t = read_c0_watchhi1();
139 c->watch_reg_masks[1] |= (t & 0xff8);
140 if ((t & 0x80000000) == 0)
141 return;
142
143 write_c0_watchlo2(7);
144 t = read_c0_watchlo2();
145 write_c0_watchlo2(0);
146 c->watch_reg_masks[2] = t & 7;
147
148 c->watch_reg_count = 3;
149 c->watch_reg_use_cnt = 3;
150 t = read_c0_watchhi2();
151 write_c0_watchhi2(t | 0xff8);
152 t = read_c0_watchhi2();
153 c->watch_reg_masks[2] |= (t & 0xff8);
154 if ((t & 0x80000000) == 0)
155 return;
156
157 write_c0_watchlo3(7);
158 t = read_c0_watchlo3();
159 write_c0_watchlo3(0);
160 c->watch_reg_masks[3] = t & 7;
161
162 c->watch_reg_count = 4;
163 c->watch_reg_use_cnt = 4;
164 t = read_c0_watchhi3();
165 write_c0_watchhi3(t | 0xff8);
166 t = read_c0_watchhi3();
167 c->watch_reg_masks[3] |= (t & 0xff8);
168 if ((t & 0x80000000) == 0)
169 return;
170
171 /* We use at most 4, but probe and report up to 8. */
172 c->watch_reg_count = 5;
173 t = read_c0_watchhi4();
174 if ((t & 0x80000000) == 0)
175 return;
176
177 c->watch_reg_count = 6;
178 t = read_c0_watchhi5();
179 if ((t & 0x80000000) == 0)
180 return;
181
182 c->watch_reg_count = 7;
183 t = read_c0_watchhi6();
184 if ((t & 0x80000000) == 0)
185 return;
186
187 c->watch_reg_count = 8;
188}
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index edac9892c51a..6b876ca299ee 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -55,20 +55,14 @@
55#define UNIT(unit) ((unit)*NBYTES) 55#define UNIT(unit) ((unit)*NBYTES)
56 56
57#define ADDC(sum,reg) \ 57#define ADDC(sum,reg) \
58 .set push; \
59 .set noat; \
60 ADD sum, reg; \ 58 ADD sum, reg; \
61 sltu v1, sum, reg; \ 59 sltu v1, sum, reg; \
62 ADD sum, v1; \ 60 ADD sum, v1; \
63 .set pop
64 61
65#define ADDC32(sum,reg) \ 62#define ADDC32(sum,reg) \
66 .set push; \
67 .set noat; \
68 addu sum, reg; \ 63 addu sum, reg; \
69 sltu v1, sum, reg; \ 64 sltu v1, sum, reg; \
70 addu sum, v1; \ 65 addu sum, v1; \
71 .set pop
72 66
73#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \ 67#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
74 LOAD _t0, (offset + UNIT(0))(src); \ 68 LOAD _t0, (offset + UNIT(0))(src); \
@@ -267,8 +261,6 @@ LEAF(csum_partial)
2671: ADDC(sum, t1) 2611: ADDC(sum, t1)
268 262
269 /* fold checksum */ 263 /* fold checksum */
270 .set push
271 .set noat
272#ifdef USE_DOUBLE 264#ifdef USE_DOUBLE
273 dsll32 v1, sum, 0 265 dsll32 v1, sum, 0
274 daddu sum, v1 266 daddu sum, v1
@@ -276,21 +268,22 @@ LEAF(csum_partial)
276 dsra32 sum, sum, 0 268 dsra32 sum, sum, 0
277 addu sum, v1 269 addu sum, v1
278#endif 270#endif
279 sll v1, sum, 16
280 addu sum, v1
281 sltu v1, sum, v1
282 srl sum, sum, 16
283 addu sum, v1
284 271
285 /* odd buffer alignment? */ 272 /* odd buffer alignment? */
286 beqz t7, 1f 273#ifdef CPU_MIPSR2
287 nop 274 wsbh v1, sum
288 sll v1, sum, 8 275 movn sum, v1, t7
276#else
277 beqz t7, 1f /* odd buffer alignment? */
278 lui v1, 0x00ff
279 addu v1, 0x00ff
280 and t0, sum, v1
281 sll t0, t0, 8
289 srl sum, sum, 8 282 srl sum, sum, 8
290 or sum, v1 283 and sum, sum, v1
291 andi sum, 0xffff 284 or sum, sum, t0
292 .set pop
2931: 2851:
286#endif
294 .set reorder 287 .set reorder
295 /* Add the passed partial csum. */ 288 /* Add the passed partial csum. */
296 ADDC32(sum, a2) 289 ADDC32(sum, a2)
@@ -669,8 +662,6 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
669 ADDC(sum, t2) 662 ADDC(sum, t2)
670.Ldone: 663.Ldone:
671 /* fold checksum */ 664 /* fold checksum */
672 .set push
673 .set noat
674#ifdef USE_DOUBLE 665#ifdef USE_DOUBLE
675 dsll32 v1, sum, 0 666 dsll32 v1, sum, 0
676 daddu sum, v1 667 daddu sum, v1
@@ -678,21 +669,21 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
678 dsra32 sum, sum, 0 669 dsra32 sum, sum, 0
679 addu sum, v1 670 addu sum, v1
680#endif 671#endif
681 sll v1, sum, 16
682 addu sum, v1
683 sltu v1, sum, v1
684 srl sum, sum, 16
685 addu sum, v1
686 672
687 /* odd buffer alignment? */ 673#ifdef CPU_MIPSR2
688 beqz odd, 1f 674 wsbh v1, sum
689 nop 675 movn sum, v1, odd
690 sll v1, sum, 8 676#else
677 beqz odd, 1f /* odd buffer alignment? */
678 lui v1, 0x00ff
679 addu v1, 0x00ff
680 and t0, sum, v1
681 sll t0, t0, 8
691 srl sum, sum, 8 682 srl sum, sum, 8
692 or sum, v1 683 and sum, sum, v1
693 andi sum, 0xffff 684 or sum, sum, t0
694 .set pop
6951: 6851:
686#endif
696 .set reorder 687 .set reorder
697 ADDC32(sum, psum) 688 ADDC32(sum, psum)
698 jr ra 689 jr ra
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c8c32f417b6c..b1886244cedf 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
45obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o 45obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o
46obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o 46obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
47obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o 47obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
48obj-$(CONFIG_SOC_TX4939) += pci-tx4939.o
48obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o 49obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
49obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o 50obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
50obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 51obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
index 60e2c52c2c5e..1ea257bc3b8f 100644
--- a/arch/mips/pci/pci-tx4938.c
+++ b/arch/mips/pci/pci-tx4938.c
@@ -114,7 +114,7 @@ int __init tx4938_pciclk66_setup(void)
114 return pciclk; 114 return pciclk;
115} 115}
116 116
117int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot) 117int __init tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
118{ 118{
119 if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) { 119 if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) {
120 switch (slot) { 120 switch (slot) {
diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c
new file mode 100644
index 000000000000..5fecf1cdc325
--- /dev/null
+++ b/arch/mips/pci/pci-tx4939.c
@@ -0,0 +1,109 @@
1/*
2 * linux/arch/mips/pci/pci-tx4939.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4939/setup.c,
5 * and RBTX49xx patch from CELF patch archive.
6 *
7 * Copyright 2001, 2003-2005 MontaVista Software Inc.
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <asm/txx9/generic.h>
20#include <asm/txx9/tx4939.h>
21
22int __init tx4939_report_pciclk(void)
23{
24 int pciclk = 0;
25
26 pr_info("PCIC --%s PCICLK:",
27 (__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66) ?
28 " PCI66" : "");
29 if (__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_PCICLKEN_ALL) {
30 pciclk = txx9_master_clock * 20 / 6;
31 if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
32 pciclk /= 2;
33 printk(KERN_CONT "Internal(%u.%uMHz)",
34 (pciclk + 50000) / 1000000,
35 ((pciclk + 50000) / 100000) % 10);
36 } else {
37 printk(KERN_CONT "External");
38 pciclk = -1;
39 }
40 printk(KERN_CONT "\n");
41 return pciclk;
42}
43
44void __init tx4939_report_pci1clk(void)
45{
46 unsigned int pciclk = txx9_master_clock * 20 / 6;
47
48 pr_info("PCIC1 -- PCICLK:%u.%uMHz\n",
49 (pciclk + 50000) / 1000000,
50 ((pciclk + 50000) / 100000) % 10);
51}
52
53int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
54{
55 if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {
56 switch (slot) {
57 case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
58 if (__raw_readq(&tx4939_ccfgptr->pcfg) &
59 TX4939_PCFG_ET0MODE)
60 return TXX9_IRQ_BASE + TX4939_IR_ETH(0);
61 break;
62 case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
63 if (__raw_readq(&tx4939_ccfgptr->pcfg) &
64 TX4939_PCFG_ET1MODE)
65 return TXX9_IRQ_BASE + TX4939_IR_ETH(1);
66 break;
67 }
68 return 0;
69 }
70 return -1;
71}
72
73int __init tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
74{
75 int irq = tx4939_pcic1_map_irq(dev, slot);
76
77 if (irq >= 0)
78 return irq;
79 irq = pin;
80 /* IRQ rotation */
81 irq--; /* 0-3 */
82 irq = (irq + 33 - slot) % 4;
83 irq++; /* 1-4 */
84
85 switch (irq) {
86 case 1:
87 irq = TXX9_IRQ_BASE + TX4939_IR_INTA;
88 break;
89 case 2:
90 irq = TXX9_IRQ_BASE + TX4939_IR_INTB;
91 break;
92 case 3:
93 irq = TXX9_IRQ_BASE + TX4939_IR_INTC;
94 break;
95 case 4:
96 irq = TXX9_IRQ_BASE + TX4939_IR_INTD;
97 break;
98 }
99 return irq;
100}
101
102void __init tx4939_setup_pcierr_irq(void)
103{
104 if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
105 tx4927_pcierr_interrupt,
106 IRQF_DISABLED, "PCI error",
107 (void *)TX4939_PCIC_REG))
108 pr_warning("Failed to request irq for PCIERR\n");
109}
diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile
index 4bba79c1cc79..e107f79b1491 100644
--- a/arch/mips/pmc-sierra/msp71xx/Makefile
+++ b/arch/mips/pmc-sierra/msp71xx/Makefile
@@ -3,6 +3,7 @@
3# 3#
4obj-y += msp_prom.o msp_setup.o msp_irq.o \ 4obj-y += msp_prom.o msp_setup.o msp_irq.o \
5 msp_time.o msp_serial.o msp_elb.o 5 msp_time.o msp_serial.o msp_elb.o
6obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o
6obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o 7obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
7obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o 8obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
8obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o 9obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o
diff --git a/arch/mips/pmc-sierra/msp71xx/gpio.c b/arch/mips/pmc-sierra/msp71xx/gpio.c
new file mode 100644
index 000000000000..69848c5813e2
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/gpio.c
@@ -0,0 +1,218 @@
1/*
2 * @file /arch/mips/pmc-sierra/msp71xx/gpio.c
3 *
4 * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two
5 * types of registers. The data register sets the output level when in output
6 * mode and when in input mode will contain the value at the input. The config
7 * register sets the various modes for each gpio.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * @author Patrick Glass <patrickglass@gmail.com>
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/spinlock.h>
21#include <linux/io.h>
22
23#define MSP71XX_CFG_OFFSET(gpio) (4 * (gpio))
24#define CONF_MASK 0x0F
25#define MSP71XX_GPIO_INPUT 0x01
26#define MSP71XX_GPIO_OUTPUT 0x08
27
28#define MSP71XX_GPIO_BASE 0x0B8400000L
29
30#define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip)
31
32static spinlock_t gpio_lock;
33
34/*
35 * struct msp71xx_gpio_chip - container for gpio chip and registers
36 * @chip: chip structure for the specified gpio bank
37 * @data_reg: register for reading and writing the gpio pin value
38 * @config_reg: register to set the mode for the gpio pin bank
39 * @out_drive_reg: register to set the output drive mode for the gpio pin bank
40 */
41struct msp71xx_gpio_chip {
42 struct gpio_chip chip;
43 void __iomem *data_reg;
44 void __iomem *config_reg;
45 void __iomem *out_drive_reg;
46};
47
48/*
49 * msp71xx_gpio_get() - return the chip's gpio value
50 * @chip: chip structure which controls the specified gpio
51 * @offset: gpio whose value will be returned
52 *
53 * It will return 0 if gpio value is low and other if high.
54 */
55static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset)
56{
57 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
58
59 return __raw_readl(msp_chip->data_reg) & (1 << offset);
60}
61
62/*
63 * msp71xx_gpio_set() - set the output value for the gpio
64 * @chip: chip structure who controls the specified gpio
65 * @offset: gpio whose value will be assigned
66 * @value: logic level to assign to the gpio initially
67 *
68 * This will set the gpio bit specified to the desired value. It will set the
69 * gpio pin low if value is 0 otherwise it will be high.
70 */
71static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
72{
73 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
74 unsigned long flags;
75 u32 data;
76
77 spin_lock_irqsave(&gpio_lock, flags);
78
79 data = __raw_readl(msp_chip->data_reg);
80 if (value)
81 data |= (1 << offset);
82 else
83 data &= ~(1 << offset);
84 __raw_writel(data, msp_chip->data_reg);
85
86 spin_unlock_irqrestore(&gpio_lock, flags);
87}
88
89/*
90 * msp71xx_set_gpio_mode() - declare the mode for a gpio
91 * @chip: chip structure which controls the specified gpio
92 * @offset: gpio whose value will be assigned
93 * @mode: desired configuration for the gpio (see datasheet)
94 *
95 * It will set the gpio pin config to the @mode value passed in.
96 */
97static int msp71xx_set_gpio_mode(struct gpio_chip *chip,
98 unsigned offset, int mode)
99{
100 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
101 const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset);
102 unsigned long flags;
103 u32 cfg;
104
105 spin_lock_irqsave(&gpio_lock, flags);
106
107 cfg = __raw_readl(msp_chip->config_reg);
108 cfg &= ~(CONF_MASK << bit_offset);
109 cfg |= (mode << bit_offset);
110 __raw_writel(cfg, msp_chip->config_reg);
111
112 spin_unlock_irqrestore(&gpio_lock, flags);
113
114 return 0;
115}
116
117/*
118 * msp71xx_direction_output() - declare the direction mode for a gpio
119 * @chip: chip structure which controls the specified gpio
120 * @offset: gpio whose value will be assigned
121 * @value: logic level to assign to the gpio initially
122 *
123 * This call will set the mode for the @gpio to output. It will set the
124 * gpio pin low if value is 0 otherwise it will be high.
125 */
126static int msp71xx_direction_output(struct gpio_chip *chip,
127 unsigned offset, int value)
128{
129 msp71xx_gpio_set(chip, offset, value);
130
131 return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT);
132}
133
134/*
135 * msp71xx_direction_input() - declare the direction mode for a gpio
136 * @chip: chip structure which controls the specified gpio
137 * @offset: gpio whose to which the value will be assigned
138 *
139 * This call will set the mode for the @gpio to input.
140 */
141static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset)
142{
143 return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT);
144}
145
146/*
147 * msp71xx_set_output_drive() - declare the output drive for the gpio line
148 * @gpio: gpio pin whose output drive you wish to modify
149 * @value: zero for active drain 1 for open drain drive
150 *
151 * This call will set the output drive mode for the @gpio to output.
152 */
153int msp71xx_set_output_drive(unsigned gpio, int value)
154{
155 unsigned long flags;
156 u32 data;
157
158 if (gpio > 15 || gpio < 0)
159 return -EINVAL;
160
161 spin_lock_irqsave(&gpio_lock, flags);
162
163 data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
164 if (value)
165 data |= (1 << gpio);
166 else
167 data &= ~(1 << gpio);
168 __raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
169
170 spin_unlock_irqrestore(&gpio_lock, flags);
171
172 return 0;
173}
174EXPORT_SYMBOL(msp71xx_set_output_drive);
175
176#define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \
177{ \
178 .chip = { \
179 .label = name, \
180 .direction_input = msp71xx_direction_input, \
181 .direction_output = msp71xx_direction_output, \
182 .get = msp71xx_gpio_get, \
183 .set = msp71xx_gpio_set, \
184 .base = base_gpio, \
185 .ngpio = num_gpio \
186 }, \
187 .data_reg = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \
188 .config_reg = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \
189 .out_drive_reg = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \
190}
191
192/*
193 * struct msp71xx_gpio_banks[] - container array of gpio banks
194 * @chip: chip structure for the specified gpio bank
195 * @data_reg: register for reading and writing the gpio pin value
196 * @config_reg: register to set the mode for the gpio pin bank
197 *
198 * This array structure defines the gpio banks for the PMC MIPS Processor.
199 * We specify the bank name, the data register, the config register, base
200 * starting gpio number, and the number of gpios exposed by the bank.
201 */
202static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = {
203
204 MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2),
205 MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4),
206 MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4),
207 MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6),
208};
209
210void __init msp71xx_init_gpio(void)
211{
212 int i;
213
214 spin_lock_init(&gpio_lock);
215
216 for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++)
217 gpiochip_add(&msp71xx_gpio_banks[i].chip);
218}
diff --git a/arch/mips/pmc-sierra/msp71xx/gpio_extended.c b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c
new file mode 100644
index 000000000000..fc6dbc6cf1c0
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c
@@ -0,0 +1,148 @@
1/*
2 * @file /arch/mips/pmc-sierra/msp71xx/gpio_extended.c
3 *
4 * Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is
5 * a set of hardware registers that have no need for explicit locking as
6 * it is handled by unique method of writing individual set/clr bits.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * @author Patrick Glass <patrickglass@gmail.com>
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/gpio.h>
19#include <linux/io.h>
20
21#define MSP71XX_DATA_OFFSET(gpio) (2 * (gpio))
22#define MSP71XX_READ_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 1)
23#define MSP71XX_CFG_OUT_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 16)
24#define MSP71XX_CFG_IN_OFFSET(gpio) (MSP71XX_CFG_OUT_OFFSET(gpio) + 1)
25
26#define MSP71XX_EXD_GPIO_BASE 0x0BC000000L
27
28#define to_msp71xx_exd_gpio_chip(c) \
29 container_of(c, struct msp71xx_exd_gpio_chip, chip)
30
31/*
32 * struct msp71xx_exd_gpio_chip - container for gpio chip and registers
33 * @chip: chip structure for the specified gpio bank
34 * @reg: register for control and data of gpio pin
35 */
36struct msp71xx_exd_gpio_chip {
37 struct gpio_chip chip;
38 void __iomem *reg;
39};
40
41/*
42 * msp71xx_exd_gpio_get() - return the chip's gpio value
43 * @chip: chip structure which controls the specified gpio
44 * @offset: gpio whose value will be returned
45 *
46 * It will return 0 if gpio value is low and other if high.
47 */
48static int msp71xx_exd_gpio_get(struct gpio_chip *chip, unsigned offset)
49{
50 struct msp71xx_exd_gpio_chip *msp71xx_chip =
51 to_msp71xx_exd_gpio_chip(chip);
52 const unsigned bit = MSP71XX_READ_OFFSET(offset);
53
54 return __raw_readl(msp71xx_chip->reg) & (1 << bit);
55}
56
57/*
58 * msp71xx_exd_gpio_set() - set the output value for the gpio
59 * @chip: chip structure who controls the specified gpio
60 * @offset: gpio whose value will be assigned
61 * @value: logic level to assign to the gpio initially
62 *
63 * This will set the gpio bit specified to the desired value. It will set the
64 * gpio pin low if value is 0 otherwise it will be high.
65 */
66static void msp71xx_exd_gpio_set(struct gpio_chip *chip,
67 unsigned offset, int value)
68{
69 struct msp71xx_exd_gpio_chip *msp71xx_chip =
70 to_msp71xx_exd_gpio_chip(chip);
71 const unsigned bit = MSP71XX_DATA_OFFSET(offset);
72
73 __raw_writel(1 << (bit + (value ? 1 : 0)), msp71xx_chip->reg);
74}
75
76/*
77 * msp71xx_exd_direction_output() - declare the direction mode for a gpio
78 * @chip: chip structure which controls the specified gpio
79 * @offset: gpio whose value will be assigned
80 * @value: logic level to assign to the gpio initially
81 *
82 * This call will set the mode for the @gpio to output. It will set the
83 * gpio pin low if value is 0 otherwise it will be high.
84 */
85static int msp71xx_exd_direction_output(struct gpio_chip *chip,
86 unsigned offset, int value)
87{
88 struct msp71xx_exd_gpio_chip *msp71xx_chip =
89 to_msp71xx_exd_gpio_chip(chip);
90
91 msp71xx_exd_gpio_set(chip, offset, value);
92 __raw_writel(1 << MSP71XX_CFG_OUT_OFFSET(offset), msp71xx_chip->reg);
93 return 0;
94}
95
96/*
97 * msp71xx_exd_direction_input() - declare the direction mode for a gpio
98 * @chip: chip structure which controls the specified gpio
99 * @offset: gpio whose to which the value will be assigned
100 *
101 * This call will set the mode for the @gpio to input.
102 */
103static int msp71xx_exd_direction_input(struct gpio_chip *chip, unsigned offset)
104{
105 struct msp71xx_exd_gpio_chip *msp71xx_chip =
106 to_msp71xx_exd_gpio_chip(chip);
107
108 __raw_writel(1 << MSP71XX_CFG_IN_OFFSET(offset), msp71xx_chip->reg);
109 return 0;
110}
111
112#define MSP71XX_EXD_GPIO_BANK(name, exd_reg, base_gpio, num_gpio) \
113{ \
114 .chip = { \
115 .label = name, \
116 .direction_input = msp71xx_exd_direction_input, \
117 .direction_output = msp71xx_exd_direction_output, \
118 .get = msp71xx_exd_gpio_get, \
119 .set = msp71xx_exd_gpio_set, \
120 .base = base_gpio, \
121 .ngpio = num_gpio, \
122 }, \
123 .reg = (void __iomem *)(MSP71XX_EXD_GPIO_BASE + exd_reg), \
124}
125
126/*
127 * struct msp71xx_exd_gpio_banks[] - container array of gpio banks
128 * @chip: chip structure for the specified gpio bank
129 * @reg: register for reading and writing the gpio pin value
130 *
131 * This array structure defines the extended gpio banks for the
132 * PMC MIPS Processor. We specify the bank name, the data/config
133 * register,the base starting gpio number, and the number of
134 * gpios exposed by the bank of gpios.
135 */
136static struct msp71xx_exd_gpio_chip msp71xx_exd_gpio_banks[] = {
137
138 MSP71XX_EXD_GPIO_BANK("GPIO_23_16", 0x188, 16, 8),
139 MSP71XX_EXD_GPIO_BANK("GPIO_27_24", 0x18C, 24, 4),
140};
141
142void __init msp71xx_init_gpio_extended(void)
143{
144 int i;
145
146 for (i = 0; i < ARRAY_SIZE(msp71xx_exd_gpio_banks); i++)
147 gpiochip_add(&msp71xx_exd_gpio_banks[i].chip);
148}
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 82ab395efa33..31619c601b11 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -34,21 +34,11 @@
34#include <asm/mach-rc32434/rb.h> 34#include <asm/mach-rc32434/rb.h>
35#include <asm/mach-rc32434/integ.h> 35#include <asm/mach-rc32434/integ.h>
36#include <asm/mach-rc32434/gpio.h> 36#include <asm/mach-rc32434/gpio.h>
37 37#include <asm/mach-rc32434/irq.h>
38#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
39#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
40#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
41#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
42 38
43#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET) 39#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
44#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET) 40#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
45 41
46/* NAND definitions */
47#define GPIO_RDY (1 << 0x08)
48#define GPIO_WPX (1 << 0x09)
49#define GPIO_ALE (1 << 0x0a)
50#define GPIO_CLE (1 << 0x0b)
51
52static struct resource korina_dev0_res[] = { 42static struct resource korina_dev0_res[] = {
53 { 43 {
54 .name = "korina_regs", 44 .name = "korina_regs",
@@ -94,15 +84,13 @@ static struct korina_device korina_dev0_data = {
94}; 84};
95 85
96static struct platform_device korina_dev0 = { 86static struct platform_device korina_dev0 = {
97 .id = 0, 87 .id = -1,
98 .name = "korina", 88 .name = "korina",
99 .dev.platform_data = &korina_dev0_data, 89 .dev.platform_data = &korina_dev0_data,
100 .resource = korina_dev0_res, 90 .resource = korina_dev0_res,
101 .num_resources = ARRAY_SIZE(korina_dev0_res), 91 .num_resources = ARRAY_SIZE(korina_dev0_res),
102}; 92};
103 93
104#define CF_GPIO_NUM 13
105
106static struct resource cf_slot0_res[] = { 94static struct resource cf_slot0_res[] = {
107 { 95 {
108 .name = "cf_membase", 96 .name = "cf_membase",
@@ -116,11 +104,11 @@ static struct resource cf_slot0_res[] = {
116}; 104};
117 105
118static struct cf_device cf_slot0_data = { 106static struct cf_device cf_slot0_data = {
119 .gpio_pin = 13 107 .gpio_pin = CF_GPIO_NUM
120}; 108};
121 109
122static struct platform_device cf_slot0 = { 110static struct platform_device cf_slot0 = {
123 .id = 0, 111 .id = -1,
124 .name = "pata-rb532-cf", 112 .name = "pata-rb532-cf",
125 .dev.platform_data = &cf_slot0_data, 113 .dev.platform_data = &cf_slot0_data,
126 .resource = cf_slot0_res, 114 .resource = cf_slot0_res,
@@ -185,7 +173,7 @@ static struct mtd_partition rb532_partition_info[] = {
185 173
186static struct platform_device rb532_led = { 174static struct platform_device rb532_led = {
187 .name = "rb532-led", 175 .name = "rb532-led",
188 .id = 0, 176 .id = -1,
189}; 177};
190 178
191static struct gpio_keys_button rb532_gpio_btn[] = { 179static struct gpio_keys_button rb532_gpio_btn[] = {
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 00a1c7877bf4..76a7fd96d564 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -27,28 +27,31 @@
27 */ 27 */
28 28
29#include <linux/kernel.h> 29#include <linux/kernel.h>
30#include <linux/gpio.h>
31#include <linux/init.h> 30#include <linux/init.h>
32#include <linux/types.h> 31#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/spinlock.h> 32#include <linux/spinlock.h>
35#include <linux/io.h>
36#include <linux/platform_device.h> 33#include <linux/platform_device.h>
37 34#include <linux/gpio.h>
38#include <asm/addrspace.h>
39 35
40#include <asm/mach-rc32434/rb.h> 36#include <asm/mach-rc32434/rb.h>
41 37#include <asm/mach-rc32434/gpio.h>
42struct rb532_gpio_reg __iomem *rb532_gpio_reg0; 38
43EXPORT_SYMBOL(rb532_gpio_reg0); 39struct rb532_gpio_chip {
40 struct gpio_chip chip;
41 void __iomem *regbase;
42 void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value);
43 int (*get_int_level)(struct gpio_chip *chip, unsigned offset);
44 void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value);
45 int (*get_int_status)(struct gpio_chip *chip, unsigned offset);
46};
44 47
45struct mpmc_device dev3; 48struct mpmc_device dev3;
46 49
47static struct resource rb532_gpio_reg0_res[] = { 50static struct resource rb532_gpio_reg0_res[] = {
48 { 51 {
49 .name = "gpio_reg0", 52 .name = "gpio_reg0",
50 .start = (u32)(IDT434_REG_BASE + GPIOBASE), 53 .start = REGBASE + GPIOBASE,
51 .end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)), 54 .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
52 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
53 } 56 }
54}; 57};
@@ -56,8 +59,8 @@ static struct resource rb532_gpio_reg0_res[] = {
56static struct resource rb532_dev3_ctl_res[] = { 59static struct resource rb532_dev3_ctl_res[] = {
57 { 60 {
58 .name = "dev3_ctl", 61 .name = "dev3_ctl",
59 .start = (u32)(IDT434_REG_BASE + DEV3BASE), 62 .start = REGBASE + DEV3BASE,
60 .end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)), 63 .end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
61 .flags = IORESOURCE_MEM, 64 .flags = IORESOURCE_MEM,
62 } 65 }
63}; 66};
@@ -70,7 +73,7 @@ void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
70 73
71 spin_lock_irqsave(&dev3.lock, flags); 74 spin_lock_irqsave(&dev3.lock, flags);
72 75
73 data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs); 76 data = readl(IDT434_REG_BASE + reg_offs);
74 for (i = 0; i != len; ++i) { 77 for (i = 0; i != len; ++i) {
75 if (val & (1 << i)) 78 if (val & (1 << i))
76 data |= (1 << (i + bit)); 79 data |= (1 << (i + bit));
@@ -108,108 +111,199 @@ unsigned char get_latch_u5(void)
108} 111}
109EXPORT_SYMBOL(get_latch_u5); 112EXPORT_SYMBOL(get_latch_u5);
110 113
111int rb532_gpio_get_value(unsigned gpio) 114/*
115 * Return GPIO level */
116static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
112{ 117{
113 return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio); 118 u32 mask = 1 << offset;
119 struct rb532_gpio_chip *gpch;
120
121 gpch = container_of(chip, struct rb532_gpio_chip, chip);
122 return readl(gpch->regbase + GPIOD) & mask;
114} 123}
115EXPORT_SYMBOL(rb532_gpio_get_value);
116 124
117void rb532_gpio_set_value(unsigned gpio, int value) 125/*
126 * Set output GPIO level
127 */
128static void rb532_gpio_set(struct gpio_chip *chip,
129 unsigned offset, int value)
118{ 130{
119 unsigned tmp; 131 unsigned long flags;
132 u32 mask = 1 << offset;
133 u32 tmp;
134 struct rb532_gpio_chip *gpch;
135 void __iomem *gpvr;
120 136
121 tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio); 137 gpch = container_of(chip, struct rb532_gpio_chip, chip);
122 if (value) 138 gpvr = gpch->regbase + GPIOD;
123 tmp |= 1 << gpio;
124 139
125 writel(tmp, (void *)&rb532_gpio_reg0->gpiod); 140 local_irq_save(flags);
141 tmp = readl(gpvr);
142 if (value)
143 tmp |= mask;
144 else
145 tmp &= ~mask;
146 writel(tmp, gpvr);
147 local_irq_restore(flags);
126} 148}
127EXPORT_SYMBOL(rb532_gpio_set_value);
128 149
129int rb532_gpio_direction_input(unsigned gpio) 150/*
151 * Set GPIO direction to input
152 */
153static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
130{ 154{
131 writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio), 155 unsigned long flags;
132 (void *)&rb532_gpio_reg0->gpiocfg); 156 u32 mask = 1 << offset;
157 u32 value;
158 struct rb532_gpio_chip *gpch;
159 void __iomem *gpdr;
133 160
134 return 0; 161 gpch = container_of(chip, struct rb532_gpio_chip, chip);
135} 162 gpdr = gpch->regbase + GPIOCFG;
136EXPORT_SYMBOL(rb532_gpio_direction_input);
137 163
138int rb532_gpio_direction_output(unsigned gpio, int value) 164 local_irq_save(flags);
139{ 165 value = readl(gpdr);
140 gpio_set_value(gpio, value); 166 value &= ~mask;
141 writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio), 167 writel(value, gpdr);
142 (void *)&rb532_gpio_reg0->gpiocfg); 168 local_irq_restore(flags);
143 169
144 return 0; 170 return 0;
145} 171}
146EXPORT_SYMBOL(rb532_gpio_direction_output);
147 172
148void rb532_gpio_set_int_level(unsigned gpio, int value) 173/*
174 * Set GPIO direction to output
175 */
176static int rb532_gpio_direction_output(struct gpio_chip *chip,
177 unsigned offset, int value)
149{ 178{
150 unsigned tmp; 179 unsigned long flags;
180 u32 mask = 1 << offset;
181 u32 tmp;
182 struct rb532_gpio_chip *gpch;
183 void __iomem *gpdr;
184
185 gpch = container_of(chip, struct rb532_gpio_chip, chip);
186 writel(mask, gpch->regbase + GPIOD);
187 gpdr = gpch->regbase + GPIOCFG;
188
189 local_irq_save(flags);
190 tmp = readl(gpdr);
191 tmp |= mask;
192 writel(tmp, gpdr);
193 local_irq_restore(flags);
151 194
152 tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio); 195 return 0;
153 if (value)
154 tmp |= 1 << gpio;
155 writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
156} 196}
157EXPORT_SYMBOL(rb532_gpio_set_int_level);
158 197
159int rb532_gpio_get_int_level(unsigned gpio) 198/*
199 * Set the GPIO interrupt level
200 */
201static void rb532_gpio_set_int_level(struct gpio_chip *chip,
202 unsigned offset, int value)
160{ 203{
161 return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio); 204 unsigned long flags;
162} 205 u32 mask = 1 << offset;
163EXPORT_SYMBOL(rb532_gpio_get_int_level); 206 u32 tmp;
207 struct rb532_gpio_chip *gpch;
208 void __iomem *gpil;
164 209
165void rb532_gpio_set_int_status(unsigned gpio, int value) 210 gpch = container_of(chip, struct rb532_gpio_chip, chip);
166{ 211 gpil = gpch->regbase + GPIOILEVEL;
167 unsigned tmp;
168 212
169 tmp = readl(&rb532_gpio_reg0->gpioistat); 213 local_irq_save(flags);
214 tmp = readl(gpil);
170 if (value) 215 if (value)
171 tmp |= 1 << gpio; 216 tmp |= mask;
172 writel(tmp, (void *)&rb532_gpio_reg0->gpioistat); 217 else
218 tmp &= ~mask;
219 writel(tmp, gpil);
220 local_irq_restore(flags);
173} 221}
174EXPORT_SYMBOL(rb532_gpio_set_int_status);
175 222
176int rb532_gpio_get_int_status(unsigned gpio) 223/*
224 * Get the GPIO interrupt level
225 */
226static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset)
177{ 227{
178 return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio); 228 u32 mask = 1 << offset;
229 struct rb532_gpio_chip *gpch;
230
231 gpch = container_of(chip, struct rb532_gpio_chip, chip);
232 return readl(gpch->regbase + GPIOILEVEL) & mask;
179} 233}
180EXPORT_SYMBOL(rb532_gpio_get_int_status);
181 234
182void rb532_gpio_set_func(unsigned gpio, int value) 235/*
236 * Set the GPIO interrupt status
237 */
238static void rb532_gpio_set_int_status(struct gpio_chip *chip,
239 unsigned offset, int value)
183{ 240{
184 unsigned tmp; 241 unsigned long flags;
242 u32 mask = 1 << offset;
243 u32 tmp;
244 struct rb532_gpio_chip *gpch;
245 void __iomem *gpis;
246
247 gpch = container_of(chip, struct rb532_gpio_chip, chip);
248 gpis = gpch->regbase + GPIOISTAT;
185 249
186 tmp = readl(&rb532_gpio_reg0->gpiofunc); 250 local_irq_save(flags);
251 tmp = readl(gpis);
187 if (value) 252 if (value)
188 tmp |= 1 << gpio; 253 tmp |= mask;
189 writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc); 254 else
255 tmp &= ~mask;
256 writel(tmp, gpis);
257 local_irq_restore(flags);
190} 258}
191EXPORT_SYMBOL(rb532_gpio_set_func);
192 259
193int rb532_gpio_get_func(unsigned gpio) 260/*
261 * Get the GPIO interrupt status
262 */
263static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset)
194{ 264{
195 return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio); 265 u32 mask = 1 << offset;
266 struct rb532_gpio_chip *gpch;
267
268 gpch = container_of(chip, struct rb532_gpio_chip, chip);
269 return readl(gpch->regbase + GPIOISTAT) & mask;
196} 270}
197EXPORT_SYMBOL(rb532_gpio_get_func); 271
272static struct rb532_gpio_chip rb532_gpio_chip[] = {
273 [0] = {
274 .chip = {
275 .label = "gpio0",
276 .direction_input = rb532_gpio_direction_input,
277 .direction_output = rb532_gpio_direction_output,
278 .get = rb532_gpio_get,
279 .set = rb532_gpio_set,
280 .base = 0,
281 .ngpio = 32,
282 },
283 .get_int_level = rb532_gpio_get_int_level,
284 .set_int_level = rb532_gpio_set_int_level,
285 .get_int_status = rb532_gpio_get_int_status,
286 .set_int_status = rb532_gpio_set_int_status,
287 },
288};
198 289
199int __init rb532_gpio_init(void) 290int __init rb532_gpio_init(void)
200{ 291{
201 rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start, 292 struct resource *r;
202 rb532_gpio_reg0_res[0].end -
203 rb532_gpio_reg0_res[0].start);
204 293
205 if (!rb532_gpio_reg0) { 294 r = rb532_gpio_reg0_res;
295 rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);
296
297 if (!rb532_gpio_chip->regbase) {
206 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n"); 298 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
207 return -ENXIO; 299 return -ENXIO;
208 } 300 }
209 301
210 dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start, 302 /* Register our GPIO chip */
211 rb532_dev3_ctl_res[0].end - 303 gpiochip_add(&rb532_gpio_chip->chip);
212 rb532_dev3_ctl_res[0].start); 304
305 r = rb532_dev3_ctl_res;
306 dev3.base = ioremap_nocache(r->start, r->end - r->start);
213 307
214 if (!dev3.base) { 308 if (!dev3.base) {
215 printk(KERN_ERR "rb532: cannot remap device controller 3\n"); 309 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index c0d0f950caf2..549b46d2fcee 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -45,7 +45,7 @@
45#include <asm/mipsregs.h> 45#include <asm/mipsregs.h>
46#include <asm/system.h> 46#include <asm/system.h>
47 47
48#include <asm/mach-rc32434/rc32434.h> 48#include <asm/mach-rc32434/irq.h>
49 49
50struct intr_group { 50struct intr_group {
51 u32 mask; /* mask of valid bits in pending/mask registers */ 51 u32 mask; /* mask of valid bits in pending/mask registers */
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index 1bc0af8febf4..46ca24dbcc2d 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -37,12 +37,8 @@
37#include <asm/mach-rc32434/ddr.h> 37#include <asm/mach-rc32434/ddr.h>
38#include <asm/mach-rc32434/prom.h> 38#include <asm/mach-rc32434/prom.h>
39 39
40extern void __init setup_serial_port(void);
41
42unsigned int idt_cpu_freq = 132000000; 40unsigned int idt_cpu_freq = 132000000;
43EXPORT_SYMBOL(idt_cpu_freq); 41EXPORT_SYMBOL(idt_cpu_freq);
44unsigned int gpio_bootup_state;
45EXPORT_SYMBOL(gpio_bootup_state);
46 42
47static struct resource ddr_reg[] = { 43static struct resource ddr_reg[] = {
48 { 44 {
@@ -108,9 +104,6 @@ void __init prom_setup_cmdline(void)
108 mips_machtype = MACH_MIKROTIK_RB532; 104 mips_machtype = MACH_MIKROTIK_RB532;
109 } 105 }
110 106
111 if (match_tag(prom_argv[i], GPIO_TAG))
112 gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
113
114 strcpy(cp, prom_argv[i]); 107 strcpy(cp, prom_argv[i]);
115 cp += strlen(prom_argv[i]); 108 cp += strlen(prom_argv[i]);
116 } 109 }
@@ -122,11 +115,6 @@ void __init prom_setup_cmdline(void)
122 strcpy(cp, arcs_cmdline); 115 strcpy(cp, arcs_cmdline);
123 cp += strlen(arcs_cmdline); 116 cp += strlen(arcs_cmdline);
124 } 117 }
125 if (gpio_bootup_state & 0x02)
126 strcpy(cp, GPIO_INIT_NOBUTTON);
127 else
128 strcpy(cp, GPIO_INIT_BUTTON);
129
130 cmd_line[CL_SIZE-1] = '\0'; 118 cmd_line[CL_SIZE-1] = '\0';
131 119
132 strcpy(arcs_cmdline, cmd_line); 120 strcpy(arcs_cmdline, cmd_line);
diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
index 1a05b5ddee09..3e0d7ec3a579 100644
--- a/arch/mips/rb532/serial.c
+++ b/arch/mips/rb532/serial.c
@@ -31,16 +31,16 @@
31#include <linux/serial_8250.h> 31#include <linux/serial_8250.h>
32 32
33#include <asm/serial.h> 33#include <asm/serial.h>
34#include <asm/mach-rc32434/rc32434.h> 34#include <asm/mach-rc32434/rb.h>
35 35
36extern unsigned int idt_cpu_freq; 36extern unsigned int idt_cpu_freq;
37 37
38static struct uart_port rb532_uart = { 38static struct uart_port rb532_uart = {
39 .type = PORT_16550A, 39 .type = PORT_16550A,
40 .line = 0, 40 .line = 0,
41 .irq = RC32434_UART0_IRQ, 41 .irq = UART0_IRQ,
42 .iotype = UPIO_MEM, 42 .iotype = UPIO_MEM,
43 .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE), 43 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
44 .regshift = 2 44 .regshift = 2
45}; 45};
46 46
diff --git a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c
index 7aafa95ac20b..50f530f5b602 100644
--- a/arch/mips/rb532/setup.c
+++ b/arch/mips/rb532/setup.c
@@ -9,7 +9,7 @@
9#include <asm/time.h> 9#include <asm/time.h>
10#include <linux/ioport.h> 10#include <linux/ioport.h>
11 11
12#include <asm/mach-rc32434/rc32434.h> 12#include <asm/mach-rc32434/rb.h>
13#include <asm/mach-rc32434/pci.h> 13#include <asm/mach-rc32434/pci.h>
14 14
15struct pci_reg __iomem *pci_reg; 15struct pci_reg __iomem *pci_reg;
@@ -27,7 +27,7 @@ static struct resource pci0_res[] = {
27static void rb_machine_restart(char *command) 27static void rb_machine_restart(char *command)
28{ 28{
29 /* just jump to the reset vector */ 29 /* just jump to the reset vector */
30 writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST)); 30 writel(0x80000001, IDT434_REG_BASE + RST);
31 ((void (*)(void)) KSEG1ADDR(0x1FC00000u))(); 31 ((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
32} 32}
33 33
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 840fe757c48d..17052db4161d 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -45,6 +45,14 @@ config TOSHIBA_RBTX4938
45 This Toshiba board is based on the TX4938 processor. Say Y here to 45 This Toshiba board is based on the TX4938 processor. Say Y here to
46 support this machine type 46 support this machine type
47 47
48config TOSHIBA_RBTX4939
49 bool "Toshiba RBTX4939 bobard"
50 depends on MACH_TX49XX
51 select SOC_TX4939
52 help
53 This Toshiba board is based on the TX4939 processor. Say Y here to
54 support this machine type
55
48config SOC_TX3927 56config SOC_TX3927
49 bool 57 bool
50 select CEVT_TXX9 58 select CEVT_TXX9
@@ -71,6 +79,13 @@ config SOC_TX4938
71 select PCI_TX4927 79 select PCI_TX4927
72 select GPIO_TXX9 80 select GPIO_TXX9
73 81
82config SOC_TX4939
83 bool
84 select CEVT_TXX9
85 select HAS_TXX9_SERIAL
86 select HW_HAS_PCI
87 select PCI_TX4927
88
74config TOSHIBA_FPCIB0 89config TOSHIBA_FPCIB0
75 bool "FPCIB0 Backplane Support" 90 bool "FPCIB0 Backplane Support"
76 depends on PCI && MACH_TXX9 91 depends on PCI && MACH_TXX9
@@ -94,16 +109,11 @@ config TOSHIBA_RBTX4938_MPLEX_NAND
94 bool "NAND" 109 bool "NAND"
95config TOSHIBA_RBTX4938_MPLEX_ATA 110config TOSHIBA_RBTX4938_MPLEX_ATA
96 bool "ATA" 111 bool "ATA"
112config TOSHIBA_RBTX4938_MPLEX_KEEP
113 bool "Keep firmware settings"
97 114
98endchoice 115endchoice
99 116
100config TX4938_NAND_BOOT
101 depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND
102 bool "NAND Boot Support (EXPERIMENTAL)"
103 help
104 This is only for Toshiba RBTX4938 reference board, which has NAND IPL.
105 Select this option if you need to use NAND boot.
106
107endif 117endif
108 118
109config PCI_TX4927 119config PCI_TX4927
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 9bb34af26b73..0030d23bef5b 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -7,6 +7,8 @@ obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o 7obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o
8obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o 8obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
9obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o 9obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
10obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
10obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 11obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
12obj-$(CONFIG_SPI) += spi_eeprom.o
11 13
12EXTRA_CFLAGS += -Werror 14EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index cbea1fdde82b..ad2870def8f1 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -30,8 +30,19 @@
30 30
31void __init tx4927_irq_init(void) 31void __init tx4927_irq_init(void)
32{ 32{
33 int i;
34
33 mips_cpu_irq_init(); 35 mips_cpu_irq_init();
34 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); 36 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, 37 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
36 handle_simple_irq); 38 handle_simple_irq);
39 /* raise priority for errors, timers, SIO */
40 txx9_irq_set_pri(TX4927_IR_ECCERR, 7);
41 txx9_irq_set_pri(TX4927_IR_WTOERR, 7);
42 txx9_irq_set_pri(TX4927_IR_PCIERR, 7);
43 txx9_irq_set_pri(TX4927_IR_PCIPME, 7);
44 for (i = 0; i < TX4927_NUM_IR_TMR; i++)
45 txx9_irq_set_pri(TX4927_IR_TMR(i), 6);
46 for (i = 0; i < TX4927_NUM_IR_SIO; i++)
47 txx9_irq_set_pri(TX4927_IR_SIO(i), 5);
37} 48}
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index 6eac684bf190..025ae11359a8 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -18,8 +18,19 @@
18 18
19void __init tx4938_irq_init(void) 19void __init tx4938_irq_init(void)
20{ 20{
21 int i;
22
21 mips_cpu_irq_init(); 23 mips_cpu_irq_init();
22 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); 24 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, 25 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
24 handle_simple_irq); 26 handle_simple_irq);
27 /* raise priority for errors, timers, SIO */
28 txx9_irq_set_pri(TX4938_IR_ECCERR, 7);
29 txx9_irq_set_pri(TX4938_IR_WTOERR, 7);
30 txx9_irq_set_pri(TX4938_IR_PCIERR, 7);
31 txx9_irq_set_pri(TX4938_IR_PCIPME, 7);
32 for (i = 0; i < TX4938_NUM_IR_TMR; i++)
33 txx9_irq_set_pri(TX4938_IR_TMR(i), 6);
34 for (i = 0; i < TX4938_NUM_IR_SIO; i++)
35 txx9_irq_set_pri(TX4938_IR_SIO(i), 5);
25} 36}
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
new file mode 100644
index 000000000000..013213a8706b
--- /dev/null
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -0,0 +1,215 @@
1/*
2 * TX4939 irq routines
3 * Based on linux/arch/mips/kernel/irq_txx9.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * Copyright 2001, 2003-2005 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ahennessy@mvista.com
9 * source@mvista.com
10 * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16/*
17 * TX4939 defines 64 IRQs.
18 * Similer to irq_txx9.c but different register layouts.
19 */
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/types.h>
23#include <asm/irq_cpu.h>
24#include <asm/txx9irq.h>
25#include <asm/txx9/tx4939.h>
26
27/* IRCER : Int. Control Enable */
28#define TXx9_IRCER_ICE 0x00000001
29
30/* IRCR : Int. Control */
31#define TXx9_IRCR_LOW 0x00000000
32#define TXx9_IRCR_HIGH 0x00000001
33#define TXx9_IRCR_DOWN 0x00000002
34#define TXx9_IRCR_UP 0x00000003
35#define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
36
37/* IRSCR : Int. Status Control */
38#define TXx9_IRSCR_EIClrE 0x00000100
39#define TXx9_IRSCR_EIClr_MASK 0x0000000f
40
41/* IRCSR : Int. Current Status */
42#define TXx9_IRCSR_IF 0x00010000
43
44#define irc_dlevel 0
45#define irc_elevel 1
46
47static struct {
48 unsigned char level;
49 unsigned char mode;
50} tx4939irq[TX4939_NUM_IR] __read_mostly;
51
52static void tx4939_irq_unmask(unsigned int irq)
53{
54 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
55 u32 __iomem *lvlp;
56 int ofs;
57 if (irq_nr < 32) {
58 irq_nr--;
59 lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
60 } else {
61 irq_nr -= 32;
62 lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
63 }
64 ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
65 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
66 | (tx4939irq[irq_nr].level << ofs),
67 lvlp);
68}
69
70static inline void tx4939_irq_mask(unsigned int irq)
71{
72 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
73 u32 __iomem *lvlp;
74 int ofs;
75 if (irq_nr < 32) {
76 irq_nr--;
77 lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
78 } else {
79 irq_nr -= 32;
80 lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
81 }
82 ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
83 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
84 | (irc_dlevel << ofs),
85 lvlp);
86 mmiowb();
87}
88
89static void tx4939_irq_mask_ack(unsigned int irq)
90{
91 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
92
93 tx4939_irq_mask(irq);
94 if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
95 irq_nr--;
96 /* clear edge detection */
97 __raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf))
98 << (irq_nr & 0x10),
99 &tx4939_ircptr->edc.r);
100 }
101}
102
103static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type)
104{
105 unsigned int irq_nr = irq - TXX9_IRQ_BASE;
106 u32 cr;
107 u32 __iomem *crp;
108 int ofs;
109 int mode;
110
111 if (flow_type & IRQF_TRIGGER_PROBE)
112 return 0;
113 switch (flow_type & IRQF_TRIGGER_MASK) {
114 case IRQF_TRIGGER_RISING:
115 mode = TXx9_IRCR_UP;
116 break;
117 case IRQF_TRIGGER_FALLING:
118 mode = TXx9_IRCR_DOWN;
119 break;
120 case IRQF_TRIGGER_HIGH:
121 mode = TXx9_IRCR_HIGH;
122 break;
123 case IRQF_TRIGGER_LOW:
124 mode = TXx9_IRCR_LOW;
125 break;
126 default:
127 return -EINVAL;
128 }
129 if (irq_nr < 32) {
130 irq_nr--;
131 crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r;
132 } else {
133 irq_nr -= 32;
134 crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r;
135 }
136 ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2;
137 cr = __raw_readl(crp);
138 cr &= ~(0x3 << ofs);
139 cr |= (mode & 0x3) << ofs;
140 __raw_writel(cr, crp);
141 tx4939irq[irq_nr].mode = mode;
142 return 0;
143}
144
145static struct irq_chip tx4939_irq_chip = {
146 .name = "TX4939",
147 .ack = tx4939_irq_mask_ack,
148 .mask = tx4939_irq_mask,
149 .mask_ack = tx4939_irq_mask_ack,
150 .unmask = tx4939_irq_unmask,
151 .set_type = tx4939_irq_set_type,
152};
153
154static int tx4939_irq_set_pri(int irc_irq, int new_pri)
155{
156 int old_pri;
157
158 if ((unsigned int)irc_irq >= TX4939_NUM_IR)
159 return 0;
160 old_pri = tx4939irq[irc_irq].level;
161 tx4939irq[irc_irq].level = new_pri;
162 return old_pri;
163}
164
165void __init tx4939_irq_init(void)
166{
167 int i;
168
169 mips_cpu_irq_init();
170 /* disable interrupt control */
171 __raw_writel(0, &tx4939_ircptr->den.r);
172 __raw_writel(0, &tx4939_ircptr->maskint.r);
173 __raw_writel(0, &tx4939_ircptr->maskext.r);
174 /* irq_base + 0 is not used */
175 for (i = 1; i < TX4939_NUM_IR; i++) {
176 tx4939irq[i].level = 4; /* middle level */
177 tx4939irq[i].mode = TXx9_IRCR_LOW;
178 set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
179 &tx4939_irq_chip, handle_level_irq);
180 }
181
182 /* mask all IRC interrupts */
183 __raw_writel(0, &tx4939_ircptr->msk.r);
184 for (i = 0; i < 16; i++)
185 __raw_writel(0, &tx4939_ircptr->lvl[i].r);
186 /* setup IRC interrupt mode (Low Active) */
187 for (i = 0; i < 2; i++)
188 __raw_writel(0, &tx4939_ircptr->dm[i].r);
189 for (i = 0; i < 2; i++)
190 __raw_writel(0, &tx4939_ircptr->dm2[i].r);
191 /* enable interrupt control */
192 __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
193 __raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
194
195 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
196 handle_simple_irq);
197
198 /* raise priority for errors, timers, sio */
199 tx4939_irq_set_pri(TX4939_IR_WTOERR, 7);
200 tx4939_irq_set_pri(TX4939_IR_PCIERR, 7);
201 tx4939_irq_set_pri(TX4939_IR_PCIPME, 7);
202 for (i = 0; i < TX4939_NUM_IR_TMR; i++)
203 tx4939_irq_set_pri(TX4939_IR_TMR(i), 6);
204 for (i = 0; i < TX4939_NUM_IR_SIO; i++)
205 tx4939_irq_set_pri(TX4939_IR_SIO(i), 5);
206}
207
208int tx4939_irq(void)
209{
210 u32 csr = __raw_readl(&tx4939_ircptr->cs.r);
211
212 if (likely(!(csr & TXx9_IRCSR_IF)))
213 return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1));
214 return -1;
215}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index fe6bee09cece..5526375010f8 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -22,11 +22,16 @@
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/serial_core.h> 24#include <linux/serial_core.h>
25#include <linux/mtd/physmap.h>
26#include <linux/leds.h>
25#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
26#include <asm/time.h> 28#include <asm/time.h>
27#include <asm/reboot.h> 29#include <asm/reboot.h>
30#include <asm/r4kcache.h>
31#include <asm/sections.h>
28#include <asm/txx9/generic.h> 32#include <asm/txx9/generic.h>
29#include <asm/txx9/pci.h> 33#include <asm/txx9/pci.h>
34#include <asm/txx9tmr.h>
30#ifdef CONFIG_CPU_TX49XX 35#ifdef CONFIG_CPU_TX49XX
31#include <asm/txx9/tx4938.h> 36#include <asm/txx9/tx4938.h>
32#endif 37#endif
@@ -67,7 +72,12 @@ unsigned int txx9_master_clock;
67unsigned int txx9_cpu_clock; 72unsigned int txx9_cpu_clock;
68unsigned int txx9_gbus_clock; 73unsigned int txx9_gbus_clock;
69 74
75#ifdef CONFIG_CPU_TX39XX
76/* don't enable by default - see errata */
77int txx9_ccfg_toeon __initdata;
78#else
70int txx9_ccfg_toeon __initdata = 1; 79int txx9_ccfg_toeon __initdata = 1;
80#endif
71 81
72/* Minimum CLK support */ 82/* Minimum CLK support */
73 83
@@ -119,39 +129,232 @@ int irq_to_gpio(unsigned irq)
119EXPORT_SYMBOL(irq_to_gpio); 129EXPORT_SYMBOL(irq_to_gpio);
120#endif 130#endif
121 131
122extern struct txx9_board_vec jmr3927_vec; 132#define BOARD_VEC(board) extern struct txx9_board_vec board;
123extern struct txx9_board_vec rbtx4927_vec; 133#include <asm/txx9/boards.h>
124extern struct txx9_board_vec rbtx4937_vec; 134#undef BOARD_VEC
125extern struct txx9_board_vec rbtx4938_vec;
126 135
127struct txx9_board_vec *txx9_board_vec __initdata; 136struct txx9_board_vec *txx9_board_vec __initdata;
128static char txx9_system_type[32]; 137static char txx9_system_type[32];
129 138
130void __init prom_init_cmdline(void) 139static struct txx9_board_vec *board_vecs[] __initdata = {
140#define BOARD_VEC(board) &board,
141#include <asm/txx9/boards.h>
142#undef BOARD_VEC
143};
144
145static struct txx9_board_vec *__init find_board_byname(const char *name)
146{
147 int i;
148
149 /* search board_vecs table */
150 for (i = 0; i < ARRAY_SIZE(board_vecs); i++) {
151 if (strstr(board_vecs[i]->system, name))
152 return board_vecs[i];
153 }
154 return NULL;
155}
156
157static void __init prom_init_cmdline(void)
131{ 158{
132 int argc = (int)fw_arg0; 159 int argc = (int)fw_arg0;
133 char **argv = (char **)fw_arg1; 160 int *argv32 = (int *)fw_arg1;
134 int i; /* Always ignore the "-c" at argv[0] */ 161 int i; /* Always ignore the "-c" at argv[0] */
135#ifdef CONFIG_64BIT 162 char builtin[CL_SIZE];
136 char *fixed_argv[32];
137 for (i = 0; i < argc; i++)
138 fixed_argv[i] = (char *)(long)(*((__s32 *)argv + i));
139 argv = fixed_argv;
140#endif
141 163
142 /* ignore all built-in args if any f/w args given */ 164 /* ignore all built-in args if any f/w args given */
143 if (argc > 1) 165 /*
144 *arcs_cmdline = '\0'; 166 * But if built-in strings was started with '+', append them
167 * to command line args. If built-in was started with '-',
168 * ignore all f/w args.
169 */
170 builtin[0] = '\0';
171 if (arcs_cmdline[0] == '+')
172 strcpy(builtin, arcs_cmdline + 1);
173 else if (arcs_cmdline[0] == '-') {
174 strcpy(builtin, arcs_cmdline + 1);
175 argc = 0;
176 } else if (argc <= 1)
177 strcpy(builtin, arcs_cmdline);
178 arcs_cmdline[0] = '\0';
145 179
146 for (i = 1; i < argc; i++) { 180 for (i = 1; i < argc; i++) {
181 char *str = (char *)(long)argv32[i];
147 if (i != 1) 182 if (i != 1)
148 strcat(arcs_cmdline, " "); 183 strcat(arcs_cmdline, " ");
149 strcat(arcs_cmdline, argv[i]); 184 if (strchr(str, ' ')) {
185 strcat(arcs_cmdline, "\"");
186 strcat(arcs_cmdline, str);
187 strcat(arcs_cmdline, "\"");
188 } else
189 strcat(arcs_cmdline, str);
190 }
191 /* append saved builtin args */
192 if (builtin[0]) {
193 if (arcs_cmdline[0])
194 strcat(arcs_cmdline, " ");
195 strcat(arcs_cmdline, builtin);
150 } 196 }
151} 197}
152 198
153void __init prom_init(void) 199static int txx9_ic_disable __initdata;
200static int txx9_dc_disable __initdata;
201
202#if defined(CONFIG_CPU_TX49XX)
203/* flush all cache on very early stage (before 4k_cache_init) */
204static void __init early_flush_dcache(void)
154{ 205{
206 unsigned int conf = read_c0_config();
207 unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6));
208 unsigned int linesz = 32;
209 unsigned long addr, end;
210
211 end = INDEX_BASE + dc_size / 4;
212 /* 4way, waybit=0 */
213 for (addr = INDEX_BASE; addr < end; addr += linesz) {
214 cache_op(Index_Writeback_Inv_D, addr | 0);
215 cache_op(Index_Writeback_Inv_D, addr | 1);
216 cache_op(Index_Writeback_Inv_D, addr | 2);
217 cache_op(Index_Writeback_Inv_D, addr | 3);
218 }
219}
220
221static void __init txx9_cache_fixup(void)
222{
223 unsigned int conf;
224
225 conf = read_c0_config();
226 /* flush and disable */
227 if (txx9_ic_disable) {
228 conf |= TX49_CONF_IC;
229 write_c0_config(conf);
230 }
231 if (txx9_dc_disable) {
232 early_flush_dcache();
233 conf |= TX49_CONF_DC;
234 write_c0_config(conf);
235 }
236
237 /* enable cache */
238 conf = read_c0_config();
239 if (!txx9_ic_disable)
240 conf &= ~TX49_CONF_IC;
241 if (!txx9_dc_disable)
242 conf &= ~TX49_CONF_DC;
243 write_c0_config(conf);
244
245 if (conf & TX49_CONF_IC)
246 pr_info("TX49XX I-Cache disabled.\n");
247 if (conf & TX49_CONF_DC)
248 pr_info("TX49XX D-Cache disabled.\n");
249}
250#elif defined(CONFIG_CPU_TX39XX)
251/* flush all cache on very early stage (before tx39_cache_init) */
252static void __init early_flush_dcache(void)
253{
254 unsigned int conf = read_c0_config();
255 unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >>
256 TX39_CONF_DCS_SHIFT));
257 unsigned int linesz = 16;
258 unsigned long addr, end;
259
260 end = INDEX_BASE + dc_size / 2;
261 /* 2way, waybit=0 */
262 for (addr = INDEX_BASE; addr < end; addr += linesz) {
263 cache_op(Index_Writeback_Inv_D, addr | 0);
264 cache_op(Index_Writeback_Inv_D, addr | 1);
265 }
266}
267
268static void __init txx9_cache_fixup(void)
269{
270 unsigned int conf;
271
272 conf = read_c0_config();
273 /* flush and disable */
274 if (txx9_ic_disable) {
275 conf &= ~TX39_CONF_ICE;
276 write_c0_config(conf);
277 }
278 if (txx9_dc_disable) {
279 early_flush_dcache();
280 conf &= ~TX39_CONF_DCE;
281 write_c0_config(conf);
282 }
283
284 /* enable cache */
285 conf = read_c0_config();
286 if (!txx9_ic_disable)
287 conf |= TX39_CONF_ICE;
288 if (!txx9_dc_disable)
289 conf |= TX39_CONF_DCE;
290 write_c0_config(conf);
291
292 if (!(conf & TX39_CONF_ICE))
293 pr_info("TX39XX I-Cache disabled.\n");
294 if (!(conf & TX39_CONF_DCE))
295 pr_info("TX39XX D-Cache disabled.\n");
296}
297#else
298static inline void txx9_cache_fixup(void)
299{
300}
301#endif
302
303static void __init preprocess_cmdline(void)
304{
305 char cmdline[CL_SIZE];
306 char *s;
307
308 strcpy(cmdline, arcs_cmdline);
309 s = cmdline;
310 arcs_cmdline[0] = '\0';
311 while (s && *s) {
312 char *str = strsep(&s, " ");
313 if (strncmp(str, "board=", 6) == 0) {
314 txx9_board_vec = find_board_byname(str + 6);
315 continue;
316 } else if (strncmp(str, "masterclk=", 10) == 0) {
317 unsigned long val;
318 if (strict_strtoul(str + 10, 10, &val) == 0)
319 txx9_master_clock = val;
320 continue;
321 } else if (strcmp(str, "icdisable") == 0) {
322 txx9_ic_disable = 1;
323 continue;
324 } else if (strcmp(str, "dcdisable") == 0) {
325 txx9_dc_disable = 1;
326 continue;
327 } else if (strcmp(str, "toeoff") == 0) {
328 txx9_ccfg_toeon = 0;
329 continue;
330 } else if (strcmp(str, "toeon") == 0) {
331 txx9_ccfg_toeon = 1;
332 continue;
333 }
334 if (arcs_cmdline[0])
335 strcat(arcs_cmdline, " ");
336 strcat(arcs_cmdline, str);
337 }
338
339 txx9_cache_fixup();
340}
341
342static void __init select_board(void)
343{
344 const char *envstr;
345
346 /* first, determine by "board=" argument in preprocess_cmdline() */
347 if (txx9_board_vec)
348 return;
349 /* next, determine by "board" envvar */
350 envstr = prom_getenv("board");
351 if (envstr) {
352 txx9_board_vec = find_board_byname(envstr);
353 if (txx9_board_vec)
354 return;
355 }
356
357 /* select "default" board */
155#ifdef CONFIG_CPU_TX39XX 358#ifdef CONFIG_CPU_TX39XX
156 txx9_board_vec = &jmr3927_vec; 359 txx9_board_vec = &jmr3927_vec;
157#endif 360#endif
@@ -170,8 +373,20 @@ void __init prom_init(void)
170 txx9_board_vec = &rbtx4938_vec; 373 txx9_board_vec = &rbtx4938_vec;
171 break; 374 break;
172#endif 375#endif
376#ifdef CONFIG_TOSHIBA_RBTX4939
377 case 0x4939:
378 txx9_board_vec = &rbtx4939_vec;
379 break;
380#endif
173 } 381 }
174#endif 382#endif
383}
384
385void __init prom_init(void)
386{
387 prom_init_cmdline();
388 preprocess_cmdline();
389 select_board();
175 390
176 strcpy(txx9_system_type, txx9_board_vec->system); 391 strcpy(txx9_system_type, txx9_board_vec->system);
177 392
@@ -180,6 +395,11 @@ void __init prom_init(void)
180 395
181void __init prom_free_prom_memory(void) 396void __init prom_free_prom_memory(void)
182{ 397{
398 unsigned long saddr = PAGE_SIZE;
399 unsigned long eaddr = __pa_symbol(&_text);
400
401 if (saddr < eaddr)
402 free_init_pages("prom memory", saddr, eaddr);
183} 403}
184 404
185const char *get_system_type(void) 405const char *get_system_type(void)
@@ -192,6 +412,21 @@ char * __init prom_getcmdline(void)
192 return &(arcs_cmdline[0]); 412 return &(arcs_cmdline[0]);
193} 413}
194 414
415const char *__init prom_getenv(const char *name)
416{
417 const s32 *str = (const s32 *)fw_arg2;
418
419 if (!str)
420 return NULL;
421 /* YAMON style ("name", "value" pairs) */
422 while (str[0] && str[1]) {
423 if (!strcmp((const char *)(unsigned long)str[0], name))
424 return (const char *)(unsigned long)str[1];
425 str += 2;
426 }
427 return NULL;
428}
429
195static void __noreturn txx9_machine_halt(void) 430static void __noreturn txx9_machine_halt(void)
196{ 431{
197 local_irq_disable(); 432 local_irq_disable();
@@ -222,6 +457,20 @@ void __init txx9_wdt_init(unsigned long base)
222 platform_device_register_simple("txx9wdt", -1, &res, 1); 457 platform_device_register_simple("txx9wdt", -1, &res, 1);
223} 458}
224 459
460void txx9_wdt_now(unsigned long base)
461{
462 struct txx9_tmr_reg __iomem *tmrptr =
463 ioremap(base, sizeof(struct txx9_tmr_reg));
464 /* disable watch dog timer */
465 __raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
466 __raw_writel(0, &tmrptr->tcr);
467 /* kick watchdog */
468 __raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
469 __raw_writel(1, &tmrptr->cpra); /* immediate */
470 __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
471 &tmrptr->tcr);
472}
473
225/* SPI support */ 474/* SPI support */
226void __init txx9_spi_init(int busid, unsigned long base, int irq) 475void __init txx9_spi_init(int busid, unsigned long base, int irq)
227{ 476{
@@ -372,3 +621,153 @@ static unsigned long __swizzle_addr_none(unsigned long port)
372unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none; 621unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
373EXPORT_SYMBOL(__swizzle_addr_b); 622EXPORT_SYMBOL(__swizzle_addr_b);
374#endif 623#endif
624
625void __init txx9_physmap_flash_init(int no, unsigned long addr,
626 unsigned long size,
627 const struct physmap_flash_data *pdata)
628{
629#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
630 struct resource res = {
631 .start = addr,
632 .end = addr + size - 1,
633 .flags = IORESOURCE_MEM,
634 };
635 struct platform_device *pdev;
636#ifdef CONFIG_MTD_PARTITIONS
637 static struct mtd_partition parts[2];
638 struct physmap_flash_data pdata_part;
639
640 /* If this area contained boot area, make separate partition */
641 if (pdata->nr_parts == 0 && !pdata->parts &&
642 addr < 0x1fc00000 && addr + size > 0x1fc00000 &&
643 !parts[0].name) {
644 parts[0].name = "boot";
645 parts[0].offset = 0x1fc00000 - addr;
646 parts[0].size = addr + size - 0x1fc00000;
647 parts[1].name = "user";
648 parts[1].offset = 0;
649 parts[1].size = 0x1fc00000 - addr;
650 pdata_part = *pdata;
651 pdata_part.nr_parts = ARRAY_SIZE(parts);
652 pdata_part.parts = parts;
653 pdata = &pdata_part;
654 }
655#endif
656 pdev = platform_device_alloc("physmap-flash", no);
657 if (!pdev ||
658 platform_device_add_resources(pdev, &res, 1) ||
659 platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
660 platform_device_add(pdev))
661 platform_device_put(pdev);
662#endif
663}
664
665#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
666static DEFINE_SPINLOCK(txx9_iocled_lock);
667
668#define TXX9_IOCLED_MAXLEDS 8
669
670struct txx9_iocled_data {
671 struct gpio_chip chip;
672 u8 cur_val;
673 void __iomem *mmioaddr;
674 struct gpio_led_platform_data pdata;
675 struct gpio_led leds[TXX9_IOCLED_MAXLEDS];
676 char names[TXX9_IOCLED_MAXLEDS][32];
677};
678
679static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset)
680{
681 struct txx9_iocled_data *data =
682 container_of(chip, struct txx9_iocled_data, chip);
683 return data->cur_val & (1 << offset);
684}
685
686static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
687 int value)
688{
689 struct txx9_iocled_data *data =
690 container_of(chip, struct txx9_iocled_data, chip);
691 unsigned long flags;
692 spin_lock_irqsave(&txx9_iocled_lock, flags);
693 if (value)
694 data->cur_val |= 1 << offset;
695 else
696 data->cur_val &= ~(1 << offset);
697 writeb(data->cur_val, data->mmioaddr);
698 mmiowb();
699 spin_unlock_irqrestore(&txx9_iocled_lock, flags);
700}
701
702static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
703{
704 return 0;
705}
706
707static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset,
708 int value)
709{
710 txx9_iocled_set(chip, offset, value);
711 return 0;
712}
713
714void __init txx9_iocled_init(unsigned long baseaddr,
715 int basenum, unsigned int num, int lowactive,
716 const char *color, char **deftriggers)
717{
718 struct txx9_iocled_data *iocled;
719 struct platform_device *pdev;
720 int i;
721 static char *default_triggers[] __initdata = {
722 "heartbeat",
723 "ide-disk",
724 "nand-disk",
725 NULL,
726 };
727
728 if (!deftriggers)
729 deftriggers = default_triggers;
730 iocled = kzalloc(sizeof(*iocled), GFP_KERNEL);
731 if (!iocled)
732 return;
733 iocled->mmioaddr = ioremap(baseaddr, 1);
734 if (!iocled->mmioaddr)
735 return;
736 iocled->chip.get = txx9_iocled_get;
737 iocled->chip.set = txx9_iocled_set;
738 iocled->chip.direction_input = txx9_iocled_dir_in;
739 iocled->chip.direction_output = txx9_iocled_dir_out;
740 iocled->chip.label = "iocled";
741 iocled->chip.base = basenum;
742 iocled->chip.ngpio = num;
743 if (gpiochip_add(&iocled->chip))
744 return;
745 if (basenum < 0)
746 basenum = iocled->chip.base;
747
748 pdev = platform_device_alloc("leds-gpio", basenum);
749 if (!pdev)
750 return;
751 iocled->pdata.num_leds = num;
752 iocled->pdata.leds = iocled->leds;
753 for (i = 0; i < num; i++) {
754 struct gpio_led *led = &iocled->leds[i];
755 snprintf(iocled->names[i], sizeof(iocled->names[i]),
756 "iocled:%s:%u", color, i);
757 led->name = iocled->names[i];
758 led->gpio = basenum + i;
759 led->active_low = lowactive;
760 if (deftriggers && *deftriggers)
761 led->default_trigger = *deftriggers++;
762 }
763 pdev->dev.platform_data = &iocled->pdata;
764 if (platform_device_add(pdev))
765 platform_device_put(pdev);
766}
767#else /* CONFIG_LEDS_GPIO */
768void __init txx9_iocled_init(unsigned long baseaddr,
769 int basenum, unsigned int num, int lowactive,
770 const char *color, char **deftriggers)
771{
772}
773#endif /* CONFIG_LEDS_GPIO */
diff --git a/arch/mips/txx9/generic/setup_tx3927.c b/arch/mips/txx9/generic/setup_tx3927.c
index 7bd963d37fc3..9505d58454c8 100644
--- a/arch/mips/txx9/generic/setup_tx3927.c
+++ b/arch/mips/txx9/generic/setup_tx3927.c
@@ -15,6 +15,7 @@
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/param.h> 16#include <linux/param.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/mtd/physmap.h>
18#include <asm/mipsregs.h> 19#include <asm/mipsregs.h>
19#include <asm/txx9irq.h> 20#include <asm/txx9irq.h>
20#include <asm/txx9tmr.h> 21#include <asm/txx9tmr.h>
@@ -32,11 +33,6 @@ void __init tx3927_setup(void)
32 int i; 33 int i;
33 unsigned int conf; 34 unsigned int conf;
34 35
35 /* don't enable - see errata */
36 txx9_ccfg_toeon = 0;
37 if (strstr(prom_getcmdline(), "toeon") != NULL)
38 txx9_ccfg_toeon = 1;
39
40 txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE, 36 txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE,
41 TX3927_REG_SIZE); 37 TX3927_REG_SIZE);
42 38
@@ -99,16 +95,14 @@ void __init tx3927_setup(void)
99 txx9_gpio_init(TX3927_PIO_REG, 0, 16); 95 txx9_gpio_init(TX3927_PIO_REG, 0, 16);
100 96
101 conf = read_c0_conf(); 97 conf = read_c0_conf();
102 if (!(conf & TX39_CONF_ICE)) 98 if (conf & TX39_CONF_DCE) {
103 printk(KERN_INFO "TX3927 I-Cache disabled.\n"); 99 if (!(conf & TX39_CONF_WBON))
104 if (!(conf & TX39_CONF_DCE)) 100 pr_info("TX3927 D-Cache WriteThrough.\n");
105 printk(KERN_INFO "TX3927 D-Cache disabled.\n"); 101 else if (!(conf & TX39_CONF_CWFON))
106 else if (!(conf & TX39_CONF_WBON)) 102 pr_info("TX3927 D-Cache WriteBack.\n");
107 printk(KERN_INFO "TX3927 D-Cache WriteThrough.\n"); 103 else
108 else if (!(conf & TX39_CONF_CWFON)) 104 pr_info("TX3927 D-Cache WriteBack (CWF) .\n");
109 printk(KERN_INFO "TX3927 D-Cache WriteBack.\n"); 105 }
110 else
111 printk(KERN_INFO "TX3927 D-Cache WriteBack (CWF) .\n");
112} 106}
113 107
114void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr) 108void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)
@@ -128,3 +122,16 @@ void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask)
128 TXX9_IRQ_BASE + TX3927_IR_SIO(i), 122 TXX9_IRQ_BASE + TX3927_IR_SIO(i),
129 i, sclk, (1 << i) & cts_mask); 123 i, sclk, (1 << i) & cts_mask);
130} 124}
125
126void __init tx3927_mtd_init(int ch)
127{
128 struct physmap_flash_data pdata = {
129 .width = TX3927_ROMC_WIDTH(ch) / 8,
130 };
131 unsigned long start = txx9_ce_res[ch].start;
132 unsigned long size = txx9_ce_res[ch].end - start + 1;
133
134 if (!(tx3927_romcptr->cr[ch] & 0x8))
135 return; /* disabled */
136 txx9_physmap_flash_init(ch, start, size, &pdata);
137}
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
index f80d4b7a694d..914e93c62639 100644
--- a/arch/mips/txx9/generic/setup_tx4927.c
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -14,6 +14,10 @@
14#include <linux/ioport.h> 14#include <linux/ioport.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/param.h> 16#include <linux/param.h>
17#include <linux/ptrace.h>
18#include <linux/mtd/physmap.h>
19#include <asm/reboot.h>
20#include <asm/traps.h>
17#include <asm/txx9irq.h> 21#include <asm/txx9irq.h>
18#include <asm/txx9tmr.h> 22#include <asm/txx9tmr.h>
19#include <asm/txx9pio.h> 23#include <asm/txx9pio.h>
@@ -22,6 +26,10 @@
22 26
23static void __init tx4927_wdr_init(void) 27static void __init tx4927_wdr_init(void)
24{ 28{
29 /* report watchdog reset status */
30 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST)
31 pr_warning("Watchdog reset detected at 0x%lx\n",
32 read_c0_errorepc());
25 /* clear WatchDogReset (W1C) */ 33 /* clear WatchDogReset (W1C) */
26 tx4927_ccfg_set(TX4927_CCFG_WDRST); 34 tx4927_ccfg_set(TX4927_CCFG_WDRST);
27 /* do reset on watchdog */ 35 /* do reset on watchdog */
@@ -33,6 +41,47 @@ void __init tx4927_wdt_init(void)
33 txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); 41 txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
34} 42}
35 43
44static void tx4927_machine_restart(char *command)
45{
46 local_irq_disable();
47 pr_emerg("Rebooting (with %s watchdog reset)...\n",
48 (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) ?
49 "external" : "internal");
50 /* clear watchdog status */
51 tx4927_ccfg_set(TX4927_CCFG_WDRST); /* W1C */
52 txx9_wdt_now(TX4927_TMR_REG(2) & 0xfffffffffULL);
53 while (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST))
54 ;
55 mdelay(10);
56 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) {
57 pr_emerg("Rebooting (with internal watchdog reset)...\n");
58 /* External WDRST failed. Do internal watchdog reset */
59 tx4927_ccfg_clear(TX4927_CCFG_WDREXEN);
60 }
61 /* fallback */
62 (*_machine_halt)();
63}
64
65void show_registers(struct pt_regs *regs);
66static int tx4927_be_handler(struct pt_regs *regs, int is_fixup)
67{
68 int data = regs->cp0_cause & 4;
69 console_verbose();
70 pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
71 pr_err("ccfg:%llx, toea:%llx\n",
72 (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
73 (unsigned long long)____raw_readq(&tx4927_ccfgptr->toea));
74#ifdef CONFIG_PCI
75 tx4927_report_pcic_status();
76#endif
77 show_registers(regs);
78 panic("BusError!");
79}
80static void __init tx4927_be_init(void)
81{
82 board_be_handler = tx4927_be_handler;
83}
84
36static struct resource tx4927_sdram_resource[4]; 85static struct resource tx4927_sdram_resource[4];
37 86
38void __init tx4927_setup(void) 87void __init tx4927_setup(void)
@@ -44,6 +93,7 @@ void __init tx4927_setup(void)
44 93
45 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE, 94 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
46 TX4927_REG_SIZE); 95 TX4927_REG_SIZE);
96 set_c0_config(TX49_CONF_CWFON);
47 97
48 /* SDRAMC,EBUSC are configured by PROM */ 98 /* SDRAMC,EBUSC are configured by PROM */
49 for (i = 0; i < 8; i++) { 99 for (i = 0; i < 8; i++) {
@@ -167,6 +217,9 @@ void __init tx4927_setup(void)
167 txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO); 217 txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
168 __raw_writel(0, &tx4927_pioptr->maskcpu); 218 __raw_writel(0, &tx4927_pioptr->maskcpu);
169 __raw_writel(0, &tx4927_pioptr->maskext); 219 __raw_writel(0, &tx4927_pioptr->maskext);
220
221 _machine_restart = tx4927_machine_restart;
222 board_be_init = tx4927_be_init;
170} 223}
171 224
172void __init tx4927_time_init(unsigned int tmrnr) 225void __init tx4927_time_init(unsigned int tmrnr)
@@ -186,3 +239,47 @@ void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
186 TXX9_IRQ_BASE + TX4927_IR_SIO(i), 239 TXX9_IRQ_BASE + TX4927_IR_SIO(i),
187 i, sclk, (1 << i) & cts_mask); 240 i, sclk, (1 << i) & cts_mask);
188} 241}
242
243void __init tx4927_mtd_init(int ch)
244{
245 struct physmap_flash_data pdata = {
246 .width = TX4927_EBUSC_WIDTH(ch) / 8,
247 };
248 unsigned long start = txx9_ce_res[ch].start;
249 unsigned long size = txx9_ce_res[ch].end - start + 1;
250
251 if (!(TX4927_EBUSC_CR(ch) & 0x8))
252 return; /* disabled */
253 txx9_physmap_flash_init(ch, start, size, &pdata);
254}
255
256static void __init tx4927_stop_unused_modules(void)
257{
258 __u64 pcfg, rst = 0, ckd = 0;
259 char buf[128];
260
261 buf[0] = '\0';
262 local_irq_disable();
263 pcfg = ____raw_readq(&tx4927_ccfgptr->pcfg);
264 if (!(pcfg & TX4927_PCFG_SEL2)) {
265 rst |= TX4927_CLKCTR_ACLRST;
266 ckd |= TX4927_CLKCTR_ACLCKD;
267 strcat(buf, " ACLC");
268 }
269 if (rst | ckd) {
270 txx9_set64(&tx4927_ccfgptr->clkctr, rst);
271 txx9_set64(&tx4927_ccfgptr->clkctr, ckd);
272 }
273 local_irq_enable();
274 if (buf[0])
275 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
276}
277
278static int __init tx4927_late_init(void)
279{
280 if (txx9_pcode != 0x4927)
281 return -ENODEV;
282 tx4927_stop_unused_modules();
283 return 0;
284}
285late_initcall(tx4927_late_init);
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index f3040b9ba059..af724e53ef91 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -14,6 +14,10 @@
14#include <linux/ioport.h> 14#include <linux/ioport.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/param.h> 16#include <linux/param.h>
17#include <linux/ptrace.h>
18#include <linux/mtd/physmap.h>
19#include <asm/reboot.h>
20#include <asm/traps.h>
17#include <asm/txx9irq.h> 21#include <asm/txx9irq.h>
18#include <asm/txx9tmr.h> 22#include <asm/txx9tmr.h>
19#include <asm/txx9pio.h> 23#include <asm/txx9pio.h>
@@ -22,6 +26,10 @@
22 26
23static void __init tx4938_wdr_init(void) 27static void __init tx4938_wdr_init(void)
24{ 28{
29 /* report watchdog reset status */
30 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST)
31 pr_warning("Watchdog reset detected at 0x%lx\n",
32 read_c0_errorepc());
25 /* clear WatchDogReset (W1C) */ 33 /* clear WatchDogReset (W1C) */
26 tx4938_ccfg_set(TX4938_CCFG_WDRST); 34 tx4938_ccfg_set(TX4938_CCFG_WDRST);
27 /* do reset on watchdog */ 35 /* do reset on watchdog */
@@ -33,6 +41,47 @@ void __init tx4938_wdt_init(void)
33 txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); 41 txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
34} 42}
35 43
44static void tx4938_machine_restart(char *command)
45{
46 local_irq_disable();
47 pr_emerg("Rebooting (with %s watchdog reset)...\n",
48 (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) ?
49 "external" : "internal");
50 /* clear watchdog status */
51 tx4938_ccfg_set(TX4938_CCFG_WDRST); /* W1C */
52 txx9_wdt_now(TX4938_TMR_REG(2) & 0xfffffffffULL);
53 while (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST))
54 ;
55 mdelay(10);
56 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) {
57 pr_emerg("Rebooting (with internal watchdog reset)...\n");
58 /* External WDRST failed. Do internal watchdog reset */
59 tx4938_ccfg_clear(TX4938_CCFG_WDREXEN);
60 }
61 /* fallback */
62 (*_machine_halt)();
63}
64
65void show_registers(struct pt_regs *regs);
66static int tx4938_be_handler(struct pt_regs *regs, int is_fixup)
67{
68 int data = regs->cp0_cause & 4;
69 console_verbose();
70 pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
71 pr_err("ccfg:%llx, toea:%llx\n",
72 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
73 (unsigned long long)____raw_readq(&tx4938_ccfgptr->toea));
74#ifdef CONFIG_PCI
75 tx4927_report_pcic_status();
76#endif
77 show_registers(regs);
78 panic("BusError!");
79}
80static void __init tx4938_be_init(void)
81{
82 board_be_handler = tx4938_be_handler;
83}
84
36static struct resource tx4938_sdram_resource[4]; 85static struct resource tx4938_sdram_resource[4];
37static struct resource tx4938_sram_resource; 86static struct resource tx4938_sram_resource;
38 87
@@ -47,6 +96,7 @@ void __init tx4938_setup(void)
47 96
48 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE, 97 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
49 TX4938_REG_SIZE); 98 TX4938_REG_SIZE);
99 set_c0_config(TX49_CONF_CWFON);
50 100
51 /* SDRAMC,EBUSC are configured by PROM */ 101 /* SDRAMC,EBUSC are configured by PROM */
52 for (i = 0; i < 8; i++) { 102 for (i = 0; i < 8; i++) {
@@ -227,6 +277,9 @@ void __init tx4938_setup(void)
227 TX4938_CLKCTR_ETH1CKD); 277 TX4938_CLKCTR_ETH1CKD);
228 } 278 }
229 } 279 }
280
281 _machine_restart = tx4938_machine_restart;
282 board_be_init = tx4938_be_init;
230} 283}
231 284
232void __init tx4938_time_init(unsigned int tmrnr) 285void __init tx4938_time_init(unsigned int tmrnr)
@@ -268,3 +321,72 @@ void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
268 if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL)) 321 if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
269 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1); 322 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
270} 323}
324
325void __init tx4938_mtd_init(int ch)
326{
327 struct physmap_flash_data pdata = {
328 .width = TX4938_EBUSC_WIDTH(ch) / 8,
329 };
330 unsigned long start = txx9_ce_res[ch].start;
331 unsigned long size = txx9_ce_res[ch].end - start + 1;
332
333 if (!(TX4938_EBUSC_CR(ch) & 0x8))
334 return; /* disabled */
335 txx9_physmap_flash_init(ch, start, size, &pdata);
336}
337
338static void __init tx4938_stop_unused_modules(void)
339{
340 __u64 pcfg, rst = 0, ckd = 0;
341 char buf[128];
342
343 buf[0] = '\0';
344 local_irq_disable();
345 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
346 switch (txx9_pcode) {
347 case 0x4937:
348 if (!(pcfg & TX4938_PCFG_SEL2)) {
349 rst |= TX4938_CLKCTR_ACLRST;
350 ckd |= TX4938_CLKCTR_ACLCKD;
351 strcat(buf, " ACLC");
352 }
353 break;
354 case 0x4938:
355 if (!(pcfg & TX4938_PCFG_SEL2) ||
356 (pcfg & TX4938_PCFG_ETH0_SEL)) {
357 rst |= TX4938_CLKCTR_ACLRST;
358 ckd |= TX4938_CLKCTR_ACLCKD;
359 strcat(buf, " ACLC");
360 }
361 if ((pcfg &
362 (TX4938_PCFG_ATA_SEL | TX4938_PCFG_ISA_SEL |
363 TX4938_PCFG_NDF_SEL))
364 != TX4938_PCFG_NDF_SEL) {
365 rst |= TX4938_CLKCTR_NDFRST;
366 ckd |= TX4938_CLKCTR_NDFCKD;
367 strcat(buf, " NDFMC");
368 }
369 if (!(pcfg & TX4938_PCFG_SPI_SEL)) {
370 rst |= TX4938_CLKCTR_SPIRST;
371 ckd |= TX4938_CLKCTR_SPICKD;
372 strcat(buf, " SPI");
373 }
374 break;
375 }
376 if (rst | ckd) {
377 txx9_set64(&tx4938_ccfgptr->clkctr, rst);
378 txx9_set64(&tx4938_ccfgptr->clkctr, ckd);
379 }
380 local_irq_enable();
381 if (buf[0])
382 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
383}
384
385static int __init tx4938_late_init(void)
386{
387 if (txx9_pcode != 0x4937 && txx9_pcode != 0x4938)
388 return -ENODEV;
389 tx4938_stop_unused_modules();
390 return 0;
391}
392late_initcall(tx4938_late_init);
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
new file mode 100644
index 000000000000..6c0049a5bbc1
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -0,0 +1,506 @@
1/*
2 * TX4939 setup routines
3 * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/netdevice.h>
17#include <linux/notifier.h>
18#include <linux/sysdev.h>
19#include <linux/ethtool.h>
20#include <linux/param.h>
21#include <linux/ptrace.h>
22#include <linux/mtd/physmap.h>
23#include <linux/platform_device.h>
24#include <asm/bootinfo.h>
25#include <asm/reboot.h>
26#include <asm/traps.h>
27#include <asm/txx9irq.h>
28#include <asm/txx9tmr.h>
29#include <asm/txx9/generic.h>
30#include <asm/txx9/tx4939.h>
31
32static void __init tx4939_wdr_init(void)
33{
34 /* report watchdog reset status */
35 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
36 pr_warning("Watchdog reset detected at 0x%lx\n",
37 read_c0_errorepc());
38 /* clear WatchDogReset (W1C) */
39 tx4939_ccfg_set(TX4939_CCFG_WDRST);
40 /* do reset on watchdog */
41 tx4939_ccfg_set(TX4939_CCFG_WR);
42}
43
44void __init tx4939_wdt_init(void)
45{
46 txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
47}
48
49static void tx4939_machine_restart(char *command)
50{
51 local_irq_disable();
52 pr_emerg("Rebooting (with %s watchdog reset)...\n",
53 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
54 "external" : "internal");
55 /* clear watchdog status */
56 tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
57 txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
58 while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
59 ;
60 mdelay(10);
61 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
62 pr_emerg("Rebooting (with internal watchdog reset)...\n");
63 /* External WDRST failed. Do internal watchdog reset */
64 tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
65 }
66 /* fallback */
67 (*_machine_halt)();
68}
69
70void show_registers(struct pt_regs *regs);
71static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
72{
73 int data = regs->cp0_cause & 4;
74 console_verbose();
75 pr_err("%cBE exception at %#lx\n",
76 data ? 'D' : 'I', regs->cp0_epc);
77 pr_err("ccfg:%llx, toea:%llx\n",
78 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
79 (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
80#ifdef CONFIG_PCI
81 tx4927_report_pcic_status();
82#endif
83 show_registers(regs);
84 panic("BusError!");
85}
86static void __init tx4939_be_init(void)
87{
88 board_be_handler = tx4939_be_handler;
89}
90
91static struct resource tx4939_sdram_resource[4];
92static struct resource tx4939_sram_resource;
93#define TX4939_SRAM_SIZE 0x800
94
95void __init tx4939_add_memory_regions(void)
96{
97 int i;
98 unsigned long start, size;
99 u64 win;
100
101 for (i = 0; i < 4; i++) {
102 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
103 continue;
104 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
105 start = (unsigned long)(win >> 48);
106 size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
107 add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
108 }
109}
110
111void __init tx4939_setup(void)
112{
113 int i;
114 __u32 divmode;
115 __u64 pcfg;
116 int cpuclk = 0;
117
118 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
119 TX4939_REG_SIZE);
120 set_c0_config(TX49_CONF_CWFON);
121
122 /* SDRAMC,EBUSC are configured by PROM */
123 for (i = 0; i < 4; i++) {
124 if (!(TX4939_EBUSC_CR(i) & 0x8))
125 continue; /* disabled */
126 txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
127 txx9_ce_res[i].end =
128 txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
129 request_resource(&iomem_resource, &txx9_ce_res[i]);
130 }
131
132 /* clocks */
133 if (txx9_master_clock) {
134 /* calculate cpu_clock from master_clock */
135 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
136 TX4939_CCFG_MULCLK_MASK;
137 cpuclk = txx9_master_clock * 20 / 2;
138 switch (divmode) {
139 case TX4939_CCFG_MULCLK_8:
140 cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
141 case TX4939_CCFG_MULCLK_9:
142 cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
143 case TX4939_CCFG_MULCLK_10:
144 cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
145 case TX4939_CCFG_MULCLK_11:
146 cpuclk = cpuclk / 6 * 11; break;
147 case TX4939_CCFG_MULCLK_12:
148 cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
149 case TX4939_CCFG_MULCLK_13:
150 cpuclk = cpuclk / 6 * 13; break;
151 case TX4939_CCFG_MULCLK_14:
152 cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
153 case TX4939_CCFG_MULCLK_15:
154 cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
155 }
156 txx9_cpu_clock = cpuclk;
157 } else {
158 if (txx9_cpu_clock == 0)
159 txx9_cpu_clock = 400000000; /* 400MHz */
160 /* calculate master_clock from cpu_clock */
161 cpuclk = txx9_cpu_clock;
162 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
163 TX4939_CCFG_MULCLK_MASK;
164 switch (divmode) {
165 case TX4939_CCFG_MULCLK_8:
166 txx9_master_clock = cpuclk * 6 / 8; break;
167 case TX4939_CCFG_MULCLK_9:
168 txx9_master_clock = cpuclk * 6 / 9; break;
169 case TX4939_CCFG_MULCLK_10:
170 txx9_master_clock = cpuclk * 6 / 10; break;
171 case TX4939_CCFG_MULCLK_11:
172 txx9_master_clock = cpuclk * 6 / 11; break;
173 case TX4939_CCFG_MULCLK_12:
174 txx9_master_clock = cpuclk * 6 / 12; break;
175 case TX4939_CCFG_MULCLK_13:
176 txx9_master_clock = cpuclk * 6 / 13; break;
177 case TX4939_CCFG_MULCLK_14:
178 txx9_master_clock = cpuclk * 6 / 14; break;
179 case TX4939_CCFG_MULCLK_15:
180 txx9_master_clock = cpuclk * 6 / 15; break;
181 }
182 txx9_master_clock /= 10; /* * 2 / 20 */
183 }
184 /* calculate gbus_clock from cpu_clock */
185 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
186 TX4939_CCFG_YDIVMODE_MASK;
187 txx9_gbus_clock = txx9_cpu_clock;
188 switch (divmode) {
189 case TX4939_CCFG_YDIVMODE_2:
190 txx9_gbus_clock /= 2; break;
191 case TX4939_CCFG_YDIVMODE_3:
192 txx9_gbus_clock /= 3; break;
193 case TX4939_CCFG_YDIVMODE_5:
194 txx9_gbus_clock /= 5; break;
195 case TX4939_CCFG_YDIVMODE_6:
196 txx9_gbus_clock /= 6; break;
197 }
198 /* change default value to udelay/mdelay take reasonable time */
199 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
200
201 /* CCFG */
202 tx4939_wdr_init();
203 /* clear BusErrorOnWrite flag (W1C) */
204 tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
205 /* enable Timeout BusError */
206 if (txx9_ccfg_toeon)
207 tx4939_ccfg_set(TX4939_CCFG_TOE);
208
209 /* DMA selection */
210 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
211
212 /* Use external clock for external arbiter */
213 if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
214 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
215
216 pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
217 txx9_pcode_str,
218 (cpuclk + 500000) / 1000000,
219 (txx9_master_clock + 500000) / 1000000,
220 (txx9_gbus_clock + 500000) / 1000000,
221 (__u32)____raw_readq(&tx4939_ccfgptr->crir),
222 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
223 (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
224
225 pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
226 (__u32)____raw_readq(&tx4939_ddrcptr->winen));
227 for (i = 0; i < 4; i++) {
228 __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
229 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
230 continue; /* disabled */
231 printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
232 tx4939_sdram_resource[i].name = "DDR SDRAM";
233 tx4939_sdram_resource[i].start =
234 (unsigned long)(win >> 48) << 20;
235 tx4939_sdram_resource[i].end =
236 ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
237 20) - 1;
238 tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
239 request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
240 }
241 printk(KERN_CONT "\n");
242
243 /* SRAM */
244 if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
245 unsigned int size = TX4939_SRAM_SIZE;
246 tx4939_sram_resource.name = "SRAM";
247 tx4939_sram_resource.start =
248 (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
249 & ~(size - 1);
250 tx4939_sram_resource.end =
251 tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
252 tx4939_sram_resource.flags = IORESOURCE_MEM;
253 request_resource(&iomem_resource, &tx4939_sram_resource);
254 }
255
256 /* TMR */
257 /* disable all timers */
258 for (i = 0; i < TX4939_NR_TMR; i++)
259 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
260
261 /* DMA */
262 for (i = 0; i < 2; i++)
263 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
264 (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
265
266 /* set PCIC1 reset (required to prevent hangup on BIST) */
267 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
268 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
269 if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
270 mdelay(1); /* at least 128 cpu clock */
271 /* clear PCIC1 reset */
272 txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
273 } else {
274 pr_info("%s: stop PCIC1\n", txx9_pcode_str);
275 /* stop PCIC1 */
276 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
277 }
278 if (!(pcfg & TX4939_PCFG_ET0MODE)) {
279 pr_info("%s: stop ETH0\n", txx9_pcode_str);
280 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
281 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
282 }
283 if (!(pcfg & TX4939_PCFG_ET1MODE)) {
284 pr_info("%s: stop ETH1\n", txx9_pcode_str);
285 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
286 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
287 }
288
289 _machine_restart = tx4939_machine_restart;
290 board_be_init = tx4939_be_init;
291}
292
293void __init tx4939_time_init(unsigned int tmrnr)
294{
295 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
296 txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
297 TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
298 TXX9_IMCLK);
299}
300
301void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
302{
303 int i;
304 unsigned int ch_mask = 0;
305 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
306
307 cts_mask |= ~1; /* only SIO0 have RTS/CTS */
308 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
309 cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
310 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
311 ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
312 if (pcfg & TX4939_PCFG_SIO3MODE)
313 ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
314 for (i = 0; i < 4; i++) {
315 if ((1 << i) & ch_mask)
316 continue;
317 txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
318 TXX9_IRQ_BASE + TX4939_IR_SIO(i),
319 i, sclk, (1 << i) & cts_mask);
320 }
321}
322
323#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
324static int tx4939_get_eth_speed(struct net_device *dev)
325{
326 struct ethtool_cmd cmd = { ETHTOOL_GSET };
327 int speed = 100; /* default 100Mbps */
328 int err;
329 if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings)
330 return speed;
331 err = dev->ethtool_ops->get_settings(dev, &cmd);
332 if (err < 0)
333 return speed;
334 speed = cmd.speed == SPEED_100 ? 100 : 10;
335 return speed;
336}
337static int tx4939_netdev_event(struct notifier_block *this,
338 unsigned long event,
339 void *ptr)
340{
341 struct net_device *dev = ptr;
342 if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
343 __u64 bit = 0;
344 if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
345 bit = TX4939_PCFG_SPEED0;
346 else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
347 bit = TX4939_PCFG_SPEED1;
348 if (bit) {
349 int speed = tx4939_get_eth_speed(dev);
350 if (speed == 100)
351 txx9_set64(&tx4939_ccfgptr->pcfg, bit);
352 else
353 txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
354 }
355 }
356 return NOTIFY_DONE;
357}
358
359static struct notifier_block tx4939_netdev_notifier = {
360 .notifier_call = tx4939_netdev_event,
361 .priority = 1,
362};
363
364void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
365{
366 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
367
368 if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
369 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
370 if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
371 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
372 register_netdevice_notifier(&tx4939_netdev_notifier);
373}
374#else
375void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
376{
377}
378#endif
379
380void __init tx4939_mtd_init(int ch)
381{
382 struct physmap_flash_data pdata = {
383 .width = TX4939_EBUSC_WIDTH(ch) / 8,
384 };
385 unsigned long start = txx9_ce_res[ch].start;
386 unsigned long size = txx9_ce_res[ch].end - start + 1;
387
388 if (!(TX4939_EBUSC_CR(ch) & 0x8))
389 return; /* disabled */
390 txx9_physmap_flash_init(ch, start, size, &pdata);
391}
392
393#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
394void __init tx4939_ata_init(void)
395{
396 static struct resource ata0_res[] = {
397 {
398 .start = TX4939_ATA_REG_PHYS(0),
399 .end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
400 .flags = IORESOURCE_MEM,
401 }, {
402 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
403 .flags = IORESOURCE_IRQ,
404 },
405 };
406 static struct resource ata1_res[] = {
407 {
408 .start = TX4939_ATA_REG_PHYS(1),
409 .end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
410 .flags = IORESOURCE_MEM,
411 }, {
412 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
413 .flags = IORESOURCE_IRQ,
414 },
415 };
416 static struct platform_device ata0_dev = {
417 .name = "tx4939ide",
418 .id = 0,
419 .num_resources = ARRAY_SIZE(ata0_res),
420 .resource = ata0_res,
421 };
422 static struct platform_device ata1_dev = {
423 .name = "tx4939ide",
424 .id = 1,
425 .num_resources = ARRAY_SIZE(ata1_res),
426 .resource = ata1_res,
427 };
428 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
429
430 if (pcfg & TX4939_PCFG_ATA0MODE)
431 platform_device_register(&ata0_dev);
432 if ((pcfg & (TX4939_PCFG_ATA1MODE |
433 TX4939_PCFG_ET1MODE |
434 TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
435 platform_device_register(&ata1_dev);
436}
437
438static void __init tx4939_stop_unused_modules(void)
439{
440 __u64 pcfg, rst = 0, ckd = 0;
441 char buf[128];
442
443 buf[0] = '\0';
444 local_irq_disable();
445 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
446 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
447 TX4939_PCFG_I2SMODE_ACLC) {
448 rst |= TX4939_CLKCTR_ACLRST;
449 ckd |= TX4939_CLKCTR_ACLCKD;
450 strcat(buf, " ACLC");
451 }
452 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
453 TX4939_PCFG_I2SMODE_I2S &&
454 (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
455 TX4939_PCFG_I2SMODE_I2S_ALT) {
456 rst |= TX4939_CLKCTR_I2SRST;
457 ckd |= TX4939_CLKCTR_I2SCKD;
458 strcat(buf, " I2S");
459 }
460 if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
461 rst |= TX4939_CLKCTR_ATA0RST;
462 ckd |= TX4939_CLKCTR_ATA0CKD;
463 strcat(buf, " ATA0");
464 }
465 if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
466 rst |= TX4939_CLKCTR_ATA1RST;
467 ckd |= TX4939_CLKCTR_ATA1CKD;
468 strcat(buf, " ATA1");
469 }
470 if (pcfg & TX4939_PCFG_SPIMODE) {
471 rst |= TX4939_CLKCTR_SPIRST;
472 ckd |= TX4939_CLKCTR_SPICKD;
473 strcat(buf, " SPI");
474 }
475 if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
476 rst |= TX4939_CLKCTR_VPCRST;
477 ckd |= TX4939_CLKCTR_VPCCKD;
478 strcat(buf, " VPC");
479 }
480 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
481 rst |= TX4939_CLKCTR_SIO2RST;
482 ckd |= TX4939_CLKCTR_SIO2CKD;
483 strcat(buf, " SIO2");
484 }
485 if (pcfg & TX4939_PCFG_SIO3MODE) {
486 rst |= TX4939_CLKCTR_SIO3RST;
487 ckd |= TX4939_CLKCTR_SIO3CKD;
488 strcat(buf, " SIO3");
489 }
490 if (rst | ckd) {
491 txx9_set64(&tx4939_ccfgptr->clkctr, rst);
492 txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
493 }
494 local_irq_enable();
495 if (buf[0])
496 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
497}
498
499static int __init tx4939_late_init(void)
500{
501 if (txx9_pcode != 0x4939)
502 return -ENODEV;
503 tx4939_stop_unused_modules();
504 return 0;
505}
506late_initcall(tx4939_late_init);
diff --git a/arch/mips/txx9/rbtx4938/spi_eeprom.c b/arch/mips/txx9/generic/spi_eeprom.c
index a7ea8b041c1d..75c347238f47 100644
--- a/arch/mips/txx9/rbtx4938/spi_eeprom.c
+++ b/arch/mips/txx9/generic/spi_eeprom.c
@@ -18,29 +18,31 @@
18#define AT250X0_PAGE_SIZE 8 18#define AT250X0_PAGE_SIZE 8
19 19
20/* register board information for at25 driver */ 20/* register board information for at25 driver */
21int __init spi_eeprom_register(int chipid) 21int __init spi_eeprom_register(int busid, int chipid, int size)
22{ 22{
23 static struct spi_eeprom eeprom = {
24 .name = "at250x0",
25 .byte_len = 128,
26 .page_size = AT250X0_PAGE_SIZE,
27 .flags = EE_ADDR1,
28 };
29 struct spi_board_info info = { 23 struct spi_board_info info = {
30 .modalias = "at25", 24 .modalias = "at25",
31 .max_speed_hz = 1500000, /* 1.5Mbps */ 25 .max_speed_hz = 1500000, /* 1.5Mbps */
32 .bus_num = 0, 26 .bus_num = busid,
33 .chip_select = chipid, 27 .chip_select = chipid,
34 .platform_data = &eeprom,
35 /* Mode 0: High-Active, Sample-Then-Shift */ 28 /* Mode 0: High-Active, Sample-Then-Shift */
36 }; 29 };
37 30 struct spi_eeprom *eeprom;
31 eeprom = kzalloc(sizeof(*eeprom), GFP_KERNEL);
32 if (!eeprom)
33 return -ENOMEM;
34 strcpy(eeprom->name, "at250x0");
35 eeprom->byte_len = size;
36 eeprom->page_size = AT250X0_PAGE_SIZE;
37 eeprom->flags = EE_ADDR1;
38 info.platform_data = eeprom;
38 return spi_register_board_info(&info, 1); 39 return spi_register_board_info(&info, 1);
39} 40}
40 41
41/* simple temporary spi driver to provide early access to seeprom. */ 42/* simple temporary spi driver to provide early access to seeprom. */
42 43
43static struct read_param { 44static struct read_param {
45 int busid;
44 int chipid; 46 int chipid;
45 int address; 47 int address;
46 unsigned char *buf; 48 unsigned char *buf;
@@ -57,7 +59,8 @@ static int __init early_seeprom_probe(struct spi_device *spi)
57 59
58 dev_info(&spi->dev, "spiclk %u KHz.\n", 60 dev_info(&spi->dev, "spiclk %u KHz.\n",
59 (spi->max_speed_hz + 500) / 1000); 61 (spi->max_speed_hz + 500) / 1000);
60 if (read_param->chipid != spi->chip_select) 62 if (read_param->busid != spi->master->bus_num ||
63 read_param->chipid != spi->chip_select)
61 return -ENODEV; 64 return -ENODEV;
62 while (len > 0) { 65 while (len > 0) {
63 /* spi_write_then_read can only work with small chunk */ 66 /* spi_write_then_read can only work with small chunk */
@@ -80,11 +83,12 @@ static struct spi_driver early_seeprom_driver __initdata = {
80 .probe = early_seeprom_probe, 83 .probe = early_seeprom_probe,
81}; 84};
82 85
83int __init spi_eeprom_read(int chipid, int address, 86int __init spi_eeprom_read(int busid, int chipid, int address,
84 unsigned char *buf, int len) 87 unsigned char *buf, int len)
85{ 88{
86 int ret; 89 int ret;
87 struct read_param param = { 90 struct read_param param = {
91 .busid = busid,
88 .chipid = chipid, 92 .chipid = chipid,
89 .address = address, 93 .address = address,
90 .buf = buf, 94 .buf = buf,
diff --git a/arch/mips/txx9/jmr3927/prom.c b/arch/mips/txx9/jmr3927/prom.c
index 70c4c8ec3e84..c899c0c087a0 100644
--- a/arch/mips/txx9/jmr3927/prom.c
+++ b/arch/mips/txx9/jmr3927/prom.c
@@ -47,7 +47,6 @@ void __init jmr3927_prom_init(void)
47 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) 47 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
48 printk(KERN_ERR "TX3927 TLB off\n"); 48 printk(KERN_ERR "TX3927 TLB off\n");
49 49
50 prom_init_cmdline();
51 add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); 50 add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
52 txx9_sio_putchar_init(TX3927_SIO_REG(1)); 51 txx9_sio_putchar_init(TX3927_SIO_REG(1));
53} 52}
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 87db41be8a56..25e50a7be387 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -62,7 +62,6 @@ static void __init jmr3927_time_init(void)
62} 62}
63 63
64#define DO_WRITE_THROUGH 64#define DO_WRITE_THROUGH
65#define DO_ENABLE_CACHE
66 65
67static void jmr3927_board_init(void); 66static void jmr3927_board_init(void);
68 67
@@ -77,11 +76,6 @@ static void __init jmr3927_mem_setup(void)
77 /* cache setup */ 76 /* cache setup */
78 { 77 {
79 unsigned int conf; 78 unsigned int conf;
80#ifdef DO_ENABLE_CACHE
81 int mips_ic_disable = 0, mips_dc_disable = 0;
82#else
83 int mips_ic_disable = 1, mips_dc_disable = 1;
84#endif
85#ifdef DO_WRITE_THROUGH 79#ifdef DO_WRITE_THROUGH
86 int mips_config_cwfon = 0; 80 int mips_config_cwfon = 0;
87 int mips_config_wbon = 0; 81 int mips_config_wbon = 0;
@@ -91,10 +85,7 @@ static void __init jmr3927_mem_setup(void)
91#endif 85#endif
92 86
93 conf = read_c0_conf(); 87 conf = read_c0_conf();
94 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | 88 conf &= ~(TX39_CONF_WBON | TX39_CONF_CWFON);
95 TX39_CONF_WBON | TX39_CONF_CWFON);
96 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
97 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
98 conf |= mips_config_wbon ? TX39_CONF_WBON : 0; 89 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
99 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; 90 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
100 91
@@ -199,11 +190,25 @@ static void __init jmr3927_rtc_init(void)
199 platform_device_register_simple("rtc-ds1742", -1, &res, 1); 190 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
200} 191}
201 192
193static void __init jmr3927_mtd_init(void)
194{
195 int i;
196
197 for (i = 0; i < 2; i++)
198 tx3927_mtd_init(i);
199}
200
202static void __init jmr3927_device_init(void) 201static void __init jmr3927_device_init(void)
203{ 202{
203 unsigned long iocled_base = JMR3927_IOC_LED_ADDR - IO_BASE;
204#ifdef __LITTLE_ENDIAN
205 iocled_base |= 1;
206#endif
204 __swizzle_addr_b = jmr3927_swizzle_addr_b; 207 __swizzle_addr_b = jmr3927_swizzle_addr_b;
205 jmr3927_rtc_init(); 208 jmr3927_rtc_init();
206 tx3927_wdt_init(); 209 tx3927_wdt_init();
210 jmr3927_mtd_init();
211 txx9_iocled_init(iocled_base, -1, 8, 1, "green", NULL);
207} 212}
208 213
209struct txx9_board_vec jmr3927_vec __initdata = { 214struct txx9_board_vec jmr3927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 00cd5231da30..9c14ebb26cb4 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -133,15 +133,20 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq)
133 u8 level3; 133 u8 level3;
134 134
135 level3 = readb(rbtx4927_imstat_addr) & 0x1f; 135 level3 = readb(rbtx4927_imstat_addr) & 0x1f;
136 if (level3) 136 if (unlikely(!level3))
137 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; 137 return -1;
138 return sw_irq; 138 return RBTX4927_IRQ_IOC + __fls8(level3);
139} 139}
140 140
141static void __init toshiba_rbtx4927_irq_ioc_init(void) 141static void __init toshiba_rbtx4927_irq_ioc_init(void)
142{ 142{
143 int i; 143 int i;
144 144
145 /* mask all IOC interrupts */
146 writeb(0, rbtx4927_imask_addr);
147 /* clear SoftInt interrupts */
148 writeb(0, rbtx4927_softint_addr);
149
145 for (i = RBTX4927_IRQ_IOC; 150 for (i = RBTX4927_IRQ_IOC;
146 i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) 151 i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
147 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, 152 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c
index 1dc0a5b1956b..cc97c6a6011b 100644
--- a/arch/mips/txx9/rbtx4927/prom.c
+++ b/arch/mips/txx9/rbtx4927/prom.c
@@ -36,7 +36,6 @@
36 36
37void __init rbtx4927_prom_init(void) 37void __init rbtx4927_prom_init(void)
38{ 38{
39 prom_init_cmdline();
40 add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM); 39 add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM);
41 txx9_sio_putchar_init(TX4927_SIO_REG(0) & 0xfffffffffULL); 40 txx9_sio_putchar_init(TX4927_SIO_REG(0) & 0xfffffffffULL);
42} 41}
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 0d39bafea794..4a74423b2ba8 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -48,6 +48,7 @@
48#include <linux/ioport.h> 48#include <linux/ioport.h>
49#include <linux/platform_device.h> 49#include <linux/platform_device.h>
50#include <linux/delay.h> 50#include <linux/delay.h>
51#include <linux/gpio.h>
51#include <asm/io.h> 52#include <asm/io.h>
52#include <asm/reboot.h> 53#include <asm/reboot.h>
53#include <asm/txx9/generic.h> 54#include <asm/txx9/generic.h>
@@ -185,14 +186,8 @@ static void __init rbtx4937_clock_init(void);
185 186
186static void __init rbtx4927_mem_setup(void) 187static void __init rbtx4927_mem_setup(void)
187{ 188{
188 u32 cp0_config;
189 char *argptr; 189 char *argptr;
190 190
191 /* enable caches -- HCP5 does this, pmon does not */
192 cp0_config = read_c0_config();
193 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
194 write_c0_config(cp0_config);
195
196 if (TX4927_REV_PCODE() == 0x4927) { 191 if (TX4927_REV_PCODE() == 0x4927) {
197 rbtx4927_clock_init(); 192 rbtx4927_clock_init();
198 tx4927_setup(); 193 tx4927_setup();
@@ -212,6 +207,14 @@ static void __init rbtx4927_mem_setup(void)
212 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); 207 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
213#endif 208#endif
214 209
210 /* TX4927-SIO DTR on (PIO[15]) */
211 gpio_request(15, "sio-dtr");
212 gpio_direction_output(15, 1);
213 gpio_request(0, "led");
214 gpio_direction_output(0, 1);
215 gpio_request(1, "led");
216 gpio_direction_output(1, 1);
217
215 tx4927_sio_init(0, 0); 218 tx4927_sio_init(0, 0);
216#ifdef CONFIG_SERIAL_TXX9_CONSOLE 219#ifdef CONFIG_SERIAL_TXX9_CONSOLE
217 argptr = prom_getcmdline(); 220 argptr = prom_getcmdline();
@@ -304,11 +307,21 @@ static void __init rbtx4927_ne_init(void)
304 platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res)); 307 platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
305} 308}
306 309
310static void __init rbtx4927_mtd_init(void)
311{
312 int i;
313
314 for (i = 0; i < 2; i++)
315 tx4927_mtd_init(i);
316}
317
307static void __init rbtx4927_device_init(void) 318static void __init rbtx4927_device_init(void)
308{ 319{
309 toshiba_rbtx4927_rtc_init(); 320 toshiba_rbtx4927_rtc_init();
310 rbtx4927_ne_init(); 321 rbtx4927_ne_init();
311 tx4927_wdt_init(); 322 tx4927_wdt_init();
323 rbtx4927_mtd_init();
324 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
312} 325}
313 326
314struct txx9_board_vec rbtx4927_vec __initdata = { 327struct txx9_board_vec rbtx4927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4938/Makefile b/arch/mips/txx9/rbtx4938/Makefile
index 9dcc52ae5b9d..f3e1f597b4f1 100644
--- a/arch/mips/txx9/rbtx4938/Makefile
+++ b/arch/mips/txx9/rbtx4938/Makefile
@@ -1,3 +1,3 @@
1obj-y += prom.o setup.o irq.o spi_eeprom.o 1obj-y += prom.o setup.o irq.o
2 2
3EXTRA_CFLAGS += -Werror 3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index ca2f8306ce93..7d21befb8932 100644
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -85,10 +85,10 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq)
85 u8 level3; 85 u8 level3;
86 86
87 level3 = readb(rbtx4938_imstat_addr); 87 level3 = readb(rbtx4938_imstat_addr);
88 if (level3) 88 if (unlikely(!level3))
89 /* must use fls so onboard ATA has priority */ 89 return -1;
90 sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1; 90 /* must use fls so onboard ATA has priority */
91 return sw_irq; 91 return RBTX4938_IRQ_IOC + __fls8(level3);
92} 92}
93 93
94static void __init 94static void __init
diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c
index d73123cd2ab9..bcb469247e8c 100644
--- a/arch/mips/txx9/rbtx4938/prom.c
+++ b/arch/mips/txx9/rbtx4938/prom.c
@@ -18,9 +18,6 @@
18 18
19void __init rbtx4938_prom_init(void) 19void __init rbtx4938_prom_init(void)
20{ 20{
21#ifndef CONFIG_TX4938_NAND_BOOT
22 prom_init_cmdline();
23#endif
24 add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM); 21 add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM);
25 txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL); 22 txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL);
26} 23}
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index 9ab48dec0fe8..e077cc4d3a59 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -15,6 +15,7 @@
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/mtd/physmap.h>
18 19
19#include <asm/reboot.h> 20#include <asm/reboot.h>
20#include <asm/io.h> 21#include <asm/io.h>
@@ -110,6 +111,7 @@ static void __init rbtx4938_pci_setup(void)
110#define SEEPROM2_CS 0 /* IOC */ 111#define SEEPROM2_CS 0 /* IOC */
111#define SEEPROM3_CS 1 /* IOC */ 112#define SEEPROM3_CS 1 /* IOC */
112#define SRTC_CS 2 /* IOC */ 113#define SRTC_CS 2 /* IOC */
114#define SPI_BUSNO 0
113 115
114static int __init rbtx4938_ethaddr_init(void) 116static int __init rbtx4938_ethaddr_init(void)
115{ 117{
@@ -119,7 +121,7 @@ static int __init rbtx4938_ethaddr_init(void)
119 int i; 121 int i;
120 122
121 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ 123 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
122 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) { 124 if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
123 printk(KERN_ERR "seeprom: read error.\n"); 125 printk(KERN_ERR "seeprom: read error.\n");
124 return -ENODEV; 126 return -ENODEV;
125 } else { 127 } else {
@@ -173,23 +175,30 @@ static void __init rbtx4938_mem_setup(void)
173#endif 175#endif
174 176
175#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 177#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
176 printk(KERN_INFO "PIOSEL: disabling both ata and nand selection\n"); 178 pr_info("PIOSEL: disabling both ATA and NAND selection\n");
177 txx9_clear64(&tx4938_ccfgptr->pcfg, 179 txx9_clear64(&tx4938_ccfgptr->pcfg,
178 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); 180 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
179#endif 181#endif
180 182
181#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND 183#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
182 printk(KERN_INFO "PIOSEL: enabling nand selection\n"); 184 pr_info("PIOSEL: enabling NAND selection\n");
183 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); 185 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
184 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); 186 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
185#endif 187#endif
186 188
187#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA 189#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
188 printk(KERN_INFO "PIOSEL: enabling ata selection\n"); 190 pr_info("PIOSEL: enabling ATA selection\n");
189 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); 191 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
190 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); 192 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
191#endif 193#endif
192 194
195#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
196 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
197 pr_info("PIOSEL: NAND %s, ATA %s\n",
198 (pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
199 (pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
200#endif
201
193 rbtx4938_spi_setup(); 202 rbtx4938_spi_setup();
194 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */ 203 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
195 /* fixup piosel */ 204 /* fixup piosel */
@@ -279,9 +288,9 @@ static int __init rbtx4938_spi_init(void)
279 .mode = SPI_MODE_1 | SPI_CS_HIGH, 288 .mode = SPI_MODE_1 | SPI_CS_HIGH,
280 }; 289 };
281 spi_register_board_info(&srtc_info, 1); 290 spi_register_board_info(&srtc_info, 1);
282 spi_eeprom_register(SEEPROM1_CS); 291 spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
283 spi_eeprom_register(16 + SEEPROM2_CS); 292 spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
284 spi_eeprom_register(16 + SEEPROM3_CS); 293 spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
285 gpio_request(16 + SRTC_CS, "rtc-rs5c348"); 294 gpio_request(16 + SRTC_CS, "rtc-rs5c348");
286 gpio_direction_output(16 + SRTC_CS, 0); 295 gpio_direction_output(16 + SRTC_CS, 0);
287 gpio_request(SEEPROM1_CS, "seeprom1"); 296 gpio_request(SEEPROM1_CS, "seeprom1");
@@ -290,10 +299,46 @@ static int __init rbtx4938_spi_init(void)
290 gpio_direction_output(16 + SEEPROM2_CS, 1); 299 gpio_direction_output(16 + SEEPROM2_CS, 1);
291 gpio_request(16 + SEEPROM3_CS, "seeprom3"); 300 gpio_request(16 + SEEPROM3_CS, "seeprom3");
292 gpio_direction_output(16 + SEEPROM3_CS, 1); 301 gpio_direction_output(16 + SEEPROM3_CS, 1);
293 tx4938_spi_init(0); 302 tx4938_spi_init(SPI_BUSNO);
294 return 0; 303 return 0;
295} 304}
296 305
306static void __init rbtx4938_mtd_init(void)
307{
308 struct physmap_flash_data pdata = {
309 .width = 4,
310 };
311
312 switch (readb(rbtx4938_bdipsw_addr) & 7) {
313 case 0:
314 /* Boot */
315 txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
316 /* System */
317 txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
318 break;
319 case 1:
320 /* System */
321 txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
322 /* Boot */
323 txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
324 break;
325 case 2:
326 /* Ext */
327 txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
328 /* System */
329 txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
330 /* Boot */
331 txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
332 break;
333 case 3:
334 /* Boot */
335 txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
336 /* System */
337 txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
338 break;
339 }
340}
341
297static void __init rbtx4938_arch_init(void) 342static void __init rbtx4938_arch_init(void)
298{ 343{
299 gpiochip_add(&rbtx4938_spi_gpio_chip); 344 gpiochip_add(&rbtx4938_spi_gpio_chip);
@@ -306,6 +351,8 @@ static void __init rbtx4938_device_init(void)
306 rbtx4938_ethaddr_init(); 351 rbtx4938_ethaddr_init();
307 rbtx4938_ne_init(); 352 rbtx4938_ne_init();
308 tx4938_wdt_init(); 353 tx4938_wdt_init();
354 rbtx4938_mtd_init();
355 txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
309} 356}
310 357
311struct txx9_board_vec rbtx4938_vec __initdata = { 358struct txx9_board_vec rbtx4938_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4939/Makefile b/arch/mips/txx9/rbtx4939/Makefile
new file mode 100644
index 000000000000..3232cd03a7d6
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/Makefile
@@ -0,0 +1,3 @@
1obj-y += irq.o setup.o prom.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c
new file mode 100644
index 000000000000..500cc0a908e6
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/irq.c
@@ -0,0 +1,96 @@
1/*
2 * Toshiba RBTX4939 interrupt routines
3 * Based on linux/arch/mips/txx9/rbtx4938/irq.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <asm/mipsregs.h>
15#include <asm/txx9/rbtx4939.h>
16
17/*
18 * RBTX4939 IOC controller definition
19 */
20
21static void rbtx4939_ioc_irq_unmask(unsigned int irq)
22{
23 int ioc_nr = irq - RBTX4939_IRQ_IOC;
24
25 writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr);
26}
27
28static void rbtx4939_ioc_irq_mask(unsigned int irq)
29{
30 int ioc_nr = irq - RBTX4939_IRQ_IOC;
31
32 writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
33 mmiowb();
34}
35
36static struct irq_chip rbtx4939_ioc_irq_chip = {
37 .name = "IOC",
38 .ack = rbtx4939_ioc_irq_mask,
39 .mask = rbtx4939_ioc_irq_mask,
40 .mask_ack = rbtx4939_ioc_irq_mask,
41 .unmask = rbtx4939_ioc_irq_unmask,
42};
43
44
45static inline int rbtx4939_ioc_irqroute(void)
46{
47 unsigned char istat = readb(rbtx4939_ifac2_addr);
48
49 if (unlikely(istat == 0))
50 return -1;
51 return RBTX4939_IRQ_IOC + __fls8(istat);
52}
53
54static int rbtx4939_irq_dispatch(int pending)
55{
56 int irq;
57
58 if (pending & CAUSEF_IP7)
59 return MIPS_CPU_IRQ_BASE + 7;
60 irq = tx4939_irq();
61 if (likely(irq >= 0)) {
62 /* redirect IOC interrupts */
63 switch (irq) {
64 case RBTX4939_IRQ_IOCINT:
65 irq = rbtx4939_ioc_irqroute();
66 break;
67 }
68 } else if (pending & CAUSEF_IP0)
69 irq = MIPS_CPU_IRQ_BASE + 0;
70 else if (pending & CAUSEF_IP1)
71 irq = MIPS_CPU_IRQ_BASE + 1;
72 else
73 irq = -1;
74 return irq;
75}
76
77void __init rbtx4939_irq_setup(void)
78{
79 int i;
80
81 /* mask all IOC interrupts */
82 writeb(0, rbtx4939_ien_addr);
83
84 /* clear SoftInt interrupts */
85 writeb(0, rbtx4939_softint_addr);
86
87 txx9_irq_dispatch = rbtx4939_irq_dispatch;
88
89 tx4939_irq_init();
90 for (i = RBTX4939_IRQ_IOC;
91 i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
92 set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
93 handle_level_irq);
94
95 set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
96}
diff --git a/arch/mips/txx9/rbtx4939/prom.c b/arch/mips/txx9/rbtx4939/prom.c
new file mode 100644
index 000000000000..bd277ecb4ad6
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/prom.c
@@ -0,0 +1,17 @@
1/*
2 * rbtx4939 specific prom routines
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 */
8
9#include <linux/init.h>
10#include <asm/txx9/generic.h>
11#include <asm/txx9/rbtx4939.h>
12
13void __init rbtx4939_prom_init(void)
14{
15 tx4939_add_memory_regions();
16 txx9_sio_putchar_init(TX4939_SIO_REG(0) & 0xfffffffffULL);
17}
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
new file mode 100644
index 000000000000..9855d7bccc20
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -0,0 +1,307 @@
1/*
2 * Toshiba RBTX4939 setup routines.
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/platform_device.h>
16#include <linux/leds.h>
17#include <asm/reboot.h>
18#include <asm/txx9/generic.h>
19#include <asm/txx9/pci.h>
20#include <asm/txx9/rbtx4939.h>
21
22static void rbtx4939_machine_restart(char *command)
23{
24 local_irq_disable();
25 writeb(1, rbtx4939_reseten_addr);
26 writeb(1, rbtx4939_softreset_addr);
27 while (1)
28 ;
29}
30
31static void __init rbtx4939_time_init(void)
32{
33 tx4939_time_init(0);
34}
35
36static void __init rbtx4939_pci_setup(void)
37{
38#ifdef CONFIG_PCI
39 int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
40 struct pci_controller *c = &txx9_primary_pcic;
41
42 register_pci_controller(c);
43
44 tx4939_report_pciclk();
45 tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
46 if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
47 (__raw_readq(&tx4939_ccfgptr->pcfg) &
48 (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
49 tx4939_report_pci1clk();
50
51 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
52 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
53 register_pci_controller(c);
54 tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
55 }
56
57 tx4939_setup_pcierr_irq();
58#endif /* CONFIG_PCI */
59}
60
61static unsigned long long default_ebccr[] __initdata = {
62 0x01c0000000007608ULL, /* 64M ROM */
63 0x017f000000007049ULL, /* 1M IOC */
64 0x0180000000408608ULL, /* ISA */
65 0,
66};
67
68static void __init rbtx4939_ebusc_setup(void)
69{
70 int i;
71 unsigned int sp;
72
73 /* use user-configured speed */
74 sp = TX4939_EBUSC_CR(0) & 0x30;
75 default_ebccr[0] |= sp;
76 default_ebccr[1] |= sp;
77 default_ebccr[2] |= sp;
78 /* initialise by myself */
79 for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
80 if (default_ebccr[i])
81 ____raw_writeq(default_ebccr[i],
82 &tx4939_ebuscptr->cr[i]);
83 else
84 ____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
85 & ~8,
86 &tx4939_ebuscptr->cr[i]);
87 }
88}
89
90static void __init rbtx4939_update_ioc_pen(void)
91{
92 __u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
93 __u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
94 __u8 pe1 = readb(rbtx4939_pe1_addr);
95 __u8 pe2 = readb(rbtx4939_pe2_addr);
96 __u8 pe3 = readb(rbtx4939_pe3_addr);
97 if (pcfg & TX4939_PCFG_ATA0MODE)
98 pe1 |= RBTX4939_PE1_ATA(0);
99 else
100 pe1 &= ~RBTX4939_PE1_ATA(0);
101 if (pcfg & TX4939_PCFG_ATA1MODE) {
102 pe1 |= RBTX4939_PE1_ATA(1);
103 pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1));
104 } else {
105 pe1 &= ~RBTX4939_PE1_ATA(1);
106 if (pcfg & TX4939_PCFG_ET0MODE)
107 pe1 |= RBTX4939_PE1_RMII(0);
108 else
109 pe1 &= ~RBTX4939_PE1_RMII(0);
110 if (pcfg & TX4939_PCFG_ET1MODE)
111 pe1 |= RBTX4939_PE1_RMII(1);
112 else
113 pe1 &= ~RBTX4939_PE1_RMII(1);
114 }
115 if (ccfg & TX4939_CCFG_PTSEL)
116 pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
117 RBTX4939_PE3_VP_S);
118 else {
119 __u64 vmode = pcfg &
120 (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE);
121 if (vmode == 0)
122 pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
123 RBTX4939_PE3_VP_S);
124 else if (vmode == TX4939_PCFG_VPSMODE) {
125 pe3 |= RBTX4939_PE3_VP_P;
126 pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S);
127 } else if (vmode == TX4939_PCFG_VSSMODE) {
128 pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S;
129 pe3 &= ~RBTX4939_PE3_VP_P;
130 } else {
131 pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P;
132 pe3 &= ~RBTX4939_PE3_VP_S;
133 }
134 }
135 if (pcfg & TX4939_PCFG_SPIMODE) {
136 if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
137 pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0);
138 else {
139 if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
140 pe2 |= RBTX4939_PE2_SIO2;
141 pe2 &= ~RBTX4939_PE2_SIO0;
142 } else {
143 pe2 |= RBTX4939_PE2_SIO0;
144 pe2 &= ~RBTX4939_PE2_SIO2;
145 }
146 }
147 if (pcfg & TX4939_PCFG_SIO3MODE)
148 pe2 |= RBTX4939_PE2_SIO3;
149 else
150 pe2 &= ~RBTX4939_PE2_SIO3;
151 pe2 &= ~RBTX4939_PE2_SPI;
152 } else {
153 pe2 |= RBTX4939_PE2_SPI;
154 pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 |
155 RBTX4939_PE2_SIO0);
156 }
157 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
158 pe2 |= RBTX4939_PE2_GPIO;
159 else
160 pe2 &= ~RBTX4939_PE2_GPIO;
161 writeb(pe1, rbtx4939_pe1_addr);
162 writeb(pe2, rbtx4939_pe2_addr);
163 writeb(pe3, rbtx4939_pe3_addr);
164}
165
166#define RBTX4939_MAX_7SEGLEDS 8
167
168#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
169static u8 led_val[RBTX4939_MAX_7SEGLEDS];
170struct rbtx4939_led_data {
171 struct led_classdev cdev;
172 char name[32];
173 unsigned int num;
174};
175
176/* Use "dot" in 7seg LEDs */
177static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
178 enum led_brightness value)
179{
180 struct rbtx4939_led_data *led_dat =
181 container_of(led_cdev, struct rbtx4939_led_data, cdev);
182 unsigned int num = led_dat->num;
183 unsigned long flags;
184
185 local_irq_save(flags);
186 led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0);
187 writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
188 local_irq_restore(flags);
189}
190
191static int __init rbtx4939_led_probe(struct platform_device *pdev)
192{
193 struct rbtx4939_led_data *leds_data;
194 int i;
195 static char *default_triggers[] __initdata = {
196 "heartbeat",
197 "ide-disk",
198 "nand-disk",
199 };
200
201 leds_data = kzalloc(sizeof(*leds_data) * RBTX4939_MAX_7SEGLEDS,
202 GFP_KERNEL);
203 if (!leds_data)
204 return -ENOMEM;
205 for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
206 int rc;
207 struct rbtx4939_led_data *led_dat = &leds_data[i];
208
209 led_dat->num = i;
210 led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
211 sprintf(led_dat->name, "rbtx4939:amber:%u", i);
212 led_dat->cdev.name = led_dat->name;
213 if (i < ARRAY_SIZE(default_triggers))
214 led_dat->cdev.default_trigger = default_triggers[i];
215 rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
216 if (rc < 0)
217 return rc;
218 led_dat->cdev.brightness_set(&led_dat->cdev, 0);
219 }
220 return 0;
221
222}
223
224static struct platform_driver rbtx4939_led_driver = {
225 .driver = {
226 .name = "rbtx4939-led",
227 .owner = THIS_MODULE,
228 },
229};
230
231static void __init rbtx4939_led_setup(void)
232{
233 platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
234 platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
235}
236#else
237static inline void rbtx4939_led_setup(void)
238{
239}
240#endif
241
242static void __init rbtx4939_arch_init(void)
243{
244 rbtx4939_pci_setup();
245}
246
247static void __init rbtx4939_device_init(void)
248{
249#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
250 int i, j;
251 unsigned char ethaddr[2][6];
252 for (i = 0; i < 2; i++) {
253 unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
254 if (readb(rbtx4939_bdipsw_addr) & 8) {
255 u16 buf[3];
256 area -= 0x03000000;
257 for (j = 0; j < 3; j++)
258 buf[j] = le16_to_cpup((u16 *)(area + j * 2));
259 memcpy(ethaddr[i], buf, 6);
260 } else
261 memcpy(ethaddr[i], (void *)area, 6);
262 }
263 tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
264#endif
265 rbtx4939_led_setup();
266 tx4939_wdt_init();
267 tx4939_ata_init();
268}
269
270static void __init rbtx4939_setup(void)
271{
272 rbtx4939_ebusc_setup();
273 /* always enable ATA0 */
274 txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
275 rbtx4939_update_ioc_pen();
276 if (txx9_master_clock == 0)
277 txx9_master_clock = 20000000;
278 tx4939_setup();
279
280 _machine_restart = rbtx4939_machine_restart;
281
282 pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
283 readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
284 readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
285
286#ifdef CONFIG_PCI
287 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
288 txx9_board_pcibios_setup = tx4927_pcibios_setup;
289#else
290 set_io_port_base(RBTX4939_ETHER_BASE);
291#endif
292
293 tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
294}
295
296struct txx9_board_vec rbtx4939_vec __initdata = {
297 .system = "Tothiba RBTX4939",
298 .prom_init = rbtx4939_prom_init,
299 .mem_setup = rbtx4939_setup,
300 .irq_setup = rbtx4939_irq_setup,
301 .time_init = rbtx4939_time_init,
302 .device_init = rbtx4939_device_init,
303 .arch_init = rbtx4939_arch_init,
304#ifdef CONFIG_PCI
305 .pci_map_irq = tx4939_pci_map_irq,
306#endif
307};
diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
deleted file mode 100644
index cb9e4725f5dc..000000000000
--- a/include/asm-mips/mach-rc32434/irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ASM_RC32434_IRQ_H
2#define __ASM_RC32434_IRQ_H
3
4#define NR_IRQS 256
5
6#include <asm/mach-generic/irq.h>
7
8#endif /* __ASM_RC32434_IRQ_H */
diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h
deleted file mode 100644
index c4a02145104e..000000000000
--- a/include/asm-mips/mach-rc32434/rc32434.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Definitions for IDT RC323434 CPU.
3 */
4
5#ifndef _ASM_RC32434_RC32434_H_
6#define _ASM_RC32434_RC32434_H_
7
8#include <linux/delay.h>
9#include <linux/io.h>
10
11#define RC32434_REG_BASE 0x18000000
12#define RC32434_RST (1 << 15)
13
14#define IDT_CLOCK_MULT 2
15#define MIPS_CPU_TIMER_IRQ 7
16
17/* Interrupt Controller */
18#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
19#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
20#define IC_GROUP_OFFSET 0x0C
21
22#define NUM_INTR_GROUPS 5
23
24/* 16550 UARTs */
25#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
26 /* GRP3 IRQ numbers start here */
27#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
28 /* GRP4 IRQ numbers start here */
29#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
30 /* GRP5 IRQ numbers start here */
31#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
32#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
33
34
35#ifdef __MIPSEB__
36#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
37#else
38#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
39#endif
40
41#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0)
42
43/* cpu pipeline flush */
44static inline void rc32434_sync(void)
45{
46 __asm__ volatile ("sync");
47}
48
49static inline void rc32434_sync_udelay(int us)
50{
51 __asm__ volatile ("sync");
52 udelay(us);
53}
54
55static inline void rc32434_sync_delay(int ms)
56{
57 __asm__ volatile ("sync");
58 mdelay(ms);
59}
60
61#endif /* _ASM_RC32434_RC32434_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 03:15:18 -0500