diff options
author | David Daney <ddaney@caviumnetworks.com> | 2009-05-05 20:35:21 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2009-06-17 06:06:30 -0400 |
commit | 80ff0fd3ab6451407a20c19b80c1643c4a6d6434 (patch) | |
tree | 2d7021ac34269f0bce3ac18f7347bf6946640f36 | |
parent | 38295fb2a09264671c82d490ce77c17d492378e0 (diff) |
Staging: Add octeon-ethernet driver files.
The octeon-ethernet driver supports the sgmii, rgmii, spi, and xaui
ports present on the Cavium OCTEON family of SOCs. These SOCs are
multi-core mips64 processors with existing support over in arch/mips.
The driver files can be categorized into three basic groups:
1) Register definitions, these are named cvmx-*-defs.h
2) Main driver code, these have names that don't start cvmx-.
3) Interface specific functions and other utility code, names starting
with cvmx-
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
76 files changed, 26149 insertions, 0 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index d0fcf36c2ab2..925657889f0f 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig | |||
@@ -117,5 +117,7 @@ source "drivers/staging/serqt_usb/Kconfig" | |||
117 | 117 | ||
118 | source "drivers/gpu/drm/radeon/Kconfig" | 118 | source "drivers/gpu/drm/radeon/Kconfig" |
119 | 119 | ||
120 | source "drivers/staging/octeon/Kconfig" | ||
121 | |||
120 | endif # !STAGING_EXCLUDE_BUILD | 122 | endif # !STAGING_EXCLUDE_BUILD |
121 | endif # STAGING | 123 | endif # STAGING |
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 47dfd5b4288b..6da9c74c1840 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile | |||
@@ -40,3 +40,4 @@ obj-$(CONFIG_PLAN9AUTH) += p9auth/ | |||
40 | obj-$(CONFIG_HECI) += heci/ | 40 | obj-$(CONFIG_HECI) += heci/ |
41 | obj-$(CONFIG_LINE6_USB) += line6/ | 41 | obj-$(CONFIG_LINE6_USB) += line6/ |
42 | obj-$(CONFIG_USB_SERIAL_QUATECH_ESU100) += serqt_usb/ | 42 | obj-$(CONFIG_USB_SERIAL_QUATECH_ESU100) += serqt_usb/ |
43 | obj-$(CONFIG_OCTEON_ETHERNET) += octeon/ | ||
diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig new file mode 100644 index 000000000000..536e2382de54 --- /dev/null +++ b/drivers/staging/octeon/Kconfig | |||
@@ -0,0 +1,12 @@ | |||
1 | config OCTEON_ETHERNET | ||
2 | tristate "Cavium Networks Octeon Ethernet support" | ||
3 | depends on CPU_CAVIUM_OCTEON | ||
4 | select MII | ||
5 | help | ||
6 | This driver supports the builtin ethernet ports on Cavium | ||
7 | Networks' products in the Octeon family. This driver supports the | ||
8 | CN3XXX and CN5XXX Octeon processors. | ||
9 | |||
10 | To compile this driver as a module, choose M here. The module | ||
11 | will be called octeon-ethernet. | ||
12 | |||
diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile new file mode 100644 index 000000000000..3c839e37d37f --- /dev/null +++ b/drivers/staging/octeon/Makefile | |||
@@ -0,0 +1,30 @@ | |||
1 | # This file is subject to the terms and conditions of the GNU General Public | ||
2 | # License. See the file "COPYING" in the main directory of this archive | ||
3 | # for more details. | ||
4 | # | ||
5 | # Copyright (C) 2005-2009 Cavium Networks | ||
6 | # | ||
7 | |||
8 | # | ||
9 | # Makefile for Cavium OCTEON on-board ethernet driver | ||
10 | # | ||
11 | |||
12 | obj-${CONFIG_OCTEON_ETHERNET} := octeon-ethernet.o | ||
13 | |||
14 | octeon-ethernet-objs := ethernet.o | ||
15 | octeon-ethernet-objs += ethernet-common.o | ||
16 | octeon-ethernet-objs += ethernet-mdio.o | ||
17 | octeon-ethernet-objs += ethernet-mem.o | ||
18 | octeon-ethernet-objs += ethernet-proc.o | ||
19 | octeon-ethernet-objs += ethernet-rgmii.o | ||
20 | octeon-ethernet-objs += ethernet-rx.o | ||
21 | octeon-ethernet-objs += ethernet-sgmii.o | ||
22 | octeon-ethernet-objs += ethernet-spi.o | ||
23 | octeon-ethernet-objs += ethernet-tx.o | ||
24 | octeon-ethernet-objs += ethernet-xaui.o | ||
25 | octeon-ethernet-objs += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ | ||
26 | cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ | ||
27 | cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ | ||
28 | cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ | ||
29 | cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o | ||
30 | |||
diff --git a/drivers/staging/octeon/cvmx-address.h b/drivers/staging/octeon/cvmx-address.h new file mode 100644 index 000000000000..3c74d826e2e6 --- /dev/null +++ b/drivers/staging/octeon/cvmx-address.h | |||
@@ -0,0 +1,274 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2009 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * Typedefs and defines for working with Octeon physical addresses. | ||
30 | * | ||
31 | */ | ||
32 | #ifndef __CVMX_ADDRESS_H__ | ||
33 | #define __CVMX_ADDRESS_H__ | ||
34 | |||
35 | #if 0 | ||
36 | typedef enum { | ||
37 | CVMX_MIPS_SPACE_XKSEG = 3LL, | ||
38 | CVMX_MIPS_SPACE_XKPHYS = 2LL, | ||
39 | CVMX_MIPS_SPACE_XSSEG = 1LL, | ||
40 | CVMX_MIPS_SPACE_XUSEG = 0LL | ||
41 | } cvmx_mips_space_t; | ||
42 | #endif | ||
43 | |||
44 | typedef enum { | ||
45 | CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, | ||
46 | CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, | ||
47 | CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, | ||
48 | CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL | ||
49 | } cvmx_mips_xkseg_space_t; | ||
50 | |||
51 | /* decodes <14:13> of a kseg3 window address */ | ||
52 | typedef enum { | ||
53 | CVMX_ADD_WIN_SCR = 0L, | ||
54 | /* see cvmx_add_win_dma_dec_t for further decode */ | ||
55 | CVMX_ADD_WIN_DMA = 1L, | ||
56 | CVMX_ADD_WIN_UNUSED = 2L, | ||
57 | CVMX_ADD_WIN_UNUSED2 = 3L | ||
58 | } cvmx_add_win_dec_t; | ||
59 | |||
60 | /* decode within DMA space */ | ||
61 | typedef enum { | ||
62 | /* | ||
63 | * Add store data to the write buffer entry, allocating it if | ||
64 | * necessary. | ||
65 | */ | ||
66 | CVMX_ADD_WIN_DMA_ADD = 0L, | ||
67 | /* send out the write buffer entry to DRAM */ | ||
68 | CVMX_ADD_WIN_DMA_SENDMEM = 1L, | ||
69 | /* store data must be normal DRAM memory space address in this case */ | ||
70 | /* send out the write buffer entry as an IOBDMA command */ | ||
71 | CVMX_ADD_WIN_DMA_SENDDMA = 2L, | ||
72 | /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ | ||
73 | /* send out the write buffer entry as an IO write */ | ||
74 | CVMX_ADD_WIN_DMA_SENDIO = 3L, | ||
75 | /* store data must be normal IO space address in this case */ | ||
76 | /* send out a single-tick command on the NCB bus */ | ||
77 | CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, | ||
78 | /* no write buffer data needed/used */ | ||
79 | } cvmx_add_win_dma_dec_t; | ||
80 | |||
81 | /* | ||
82 | * Physical Address Decode | ||
83 | * | ||
84 | * Octeon-I HW never interprets this X (<39:36> reserved | ||
85 | * for future expansion), software should set to 0. | ||
86 | * | ||
87 | * - 0x0 XXX0 0000 0000 to DRAM Cached | ||
88 | * - 0x0 XXX0 0FFF FFFF | ||
89 | * | ||
90 | * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 | ||
91 | * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) | ||
92 | * | ||
93 | * - 0x0 XXX0 2000 0000 to DRAM Cached | ||
94 | * - 0x0 XXXF FFFF FFFF | ||
95 | * | ||
96 | * - 0x1 00X0 0000 0000 to Boot Bus Uncached | ||
97 | * - 0x1 00XF FFFF FFFF | ||
98 | * | ||
99 | * - 0x1 01X0 0000 0000 to Other NCB Uncached | ||
100 | * - 0x1 FFXF FFFF FFFF devices | ||
101 | * | ||
102 | * Decode of all Octeon addresses | ||
103 | */ | ||
104 | typedef union { | ||
105 | |||
106 | uint64_t u64; | ||
107 | /* mapped or unmapped virtual address */ | ||
108 | struct { | ||
109 | uint64_t R:2; | ||
110 | uint64_t offset:62; | ||
111 | } sva; | ||
112 | |||
113 | /* mapped USEG virtual addresses (typically) */ | ||
114 | struct { | ||
115 | uint64_t zeroes:33; | ||
116 | uint64_t offset:31; | ||
117 | } suseg; | ||
118 | |||
119 | /* mapped or unmapped virtual address */ | ||
120 | struct { | ||
121 | uint64_t ones:33; | ||
122 | uint64_t sp:2; | ||
123 | uint64_t offset:29; | ||
124 | } sxkseg; | ||
125 | |||
126 | /* | ||
127 | * physical address accessed through xkphys unmapped virtual | ||
128 | * address. | ||
129 | */ | ||
130 | struct { | ||
131 | uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ | ||
132 | uint64_t cca:3; /* ignored by octeon */ | ||
133 | uint64_t mbz:10; | ||
134 | uint64_t pa:49; /* physical address */ | ||
135 | } sxkphys; | ||
136 | |||
137 | /* physical address */ | ||
138 | struct { | ||
139 | uint64_t mbz:15; | ||
140 | /* if set, the address is uncached and resides on MCB bus */ | ||
141 | uint64_t is_io:1; | ||
142 | /* | ||
143 | * the hardware ignores this field when is_io==0, else | ||
144 | * device ID. | ||
145 | */ | ||
146 | uint64_t did:8; | ||
147 | /* the hardware ignores <39:36> in Octeon I */ | ||
148 | uint64_t unaddr:4; | ||
149 | uint64_t offset:36; | ||
150 | } sphys; | ||
151 | |||
152 | /* physical mem address */ | ||
153 | struct { | ||
154 | /* techically, <47:40> are dont-cares */ | ||
155 | uint64_t zeroes:24; | ||
156 | /* the hardware ignores <39:36> in Octeon I */ | ||
157 | uint64_t unaddr:4; | ||
158 | uint64_t offset:36; | ||
159 | } smem; | ||
160 | |||
161 | /* physical IO address */ | ||
162 | struct { | ||
163 | uint64_t mem_region:2; | ||
164 | uint64_t mbz:13; | ||
165 | /* 1 in this case */ | ||
166 | uint64_t is_io:1; | ||
167 | /* | ||
168 | * The hardware ignores this field when is_io==0, else | ||
169 | * device ID. | ||
170 | */ | ||
171 | uint64_t did:8; | ||
172 | /* the hardware ignores <39:36> in Octeon I */ | ||
173 | uint64_t unaddr:4; | ||
174 | uint64_t offset:36; | ||
175 | } sio; | ||
176 | |||
177 | /* | ||
178 | * Scratchpad virtual address - accessed through a window at | ||
179 | * the end of kseg3 | ||
180 | */ | ||
181 | struct { | ||
182 | uint64_t ones:49; | ||
183 | /* CVMX_ADD_WIN_SCR (0) in this case */ | ||
184 | cvmx_add_win_dec_t csrdec:2; | ||
185 | uint64_t addr:13; | ||
186 | } sscr; | ||
187 | |||
188 | /* there should only be stores to IOBDMA space, no loads */ | ||
189 | /* | ||
190 | * IOBDMA virtual address - accessed through a window at the | ||
191 | * end of kseg3 | ||
192 | */ | ||
193 | struct { | ||
194 | uint64_t ones:49; | ||
195 | uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */ | ||
196 | uint64_t unused2:3; | ||
197 | uint64_t type:3; | ||
198 | uint64_t addr:7; | ||
199 | } sdma; | ||
200 | |||
201 | struct { | ||
202 | uint64_t didspace:24; | ||
203 | uint64_t unused:40; | ||
204 | } sfilldidspace; | ||
205 | |||
206 | } cvmx_addr_t; | ||
207 | |||
208 | /* These macros for used by 32 bit applications */ | ||
209 | |||
210 | #define CVMX_MIPS32_SPACE_KSEG0 1l | ||
211 | #define CVMX_ADD_SEG32(segment, add) \ | ||
212 | (((int32_t)segment << 31) | (int32_t)(add)) | ||
213 | |||
214 | /* | ||
215 | * Currently all IOs are performed using XKPHYS addressing. Linux uses | ||
216 | * the CvmMemCtl register to enable XKPHYS addressing to IO space from | ||
217 | * user mode. Future OSes may need to change the upper bits of IO | ||
218 | * addresses. The following define controls the upper two bits for all | ||
219 | * IO addresses generated by the simple executive library. | ||
220 | */ | ||
221 | #define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS | ||
222 | |||
223 | /* These macros simplify the process of creating common IO addresses */ | ||
224 | #define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) | ||
225 | #ifndef CVMX_ADD_IO_SEG | ||
226 | #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) | ||
227 | #endif | ||
228 | #define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) | ||
229 | #define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) | ||
230 | #define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid)) | ||
231 | |||
232 | /* from include/ncb_rsl_id.v */ | ||
233 | #define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ | ||
234 | #define CVMX_OCT_DID_GMX0 1ULL | ||
235 | #define CVMX_OCT_DID_GMX1 2ULL | ||
236 | #define CVMX_OCT_DID_PCI 3ULL | ||
237 | #define CVMX_OCT_DID_KEY 4ULL | ||
238 | #define CVMX_OCT_DID_FPA 5ULL | ||
239 | #define CVMX_OCT_DID_DFA 6ULL | ||
240 | #define CVMX_OCT_DID_ZIP 7ULL | ||
241 | #define CVMX_OCT_DID_RNG 8ULL | ||
242 | #define CVMX_OCT_DID_IPD 9ULL | ||
243 | #define CVMX_OCT_DID_PKT 10ULL | ||
244 | #define CVMX_OCT_DID_TIM 11ULL | ||
245 | #define CVMX_OCT_DID_TAG 12ULL | ||
246 | /* the rest are not on the IO bus */ | ||
247 | #define CVMX_OCT_DID_L2C 16ULL | ||
248 | #define CVMX_OCT_DID_LMC 17ULL | ||
249 | #define CVMX_OCT_DID_SPX0 18ULL | ||
250 | #define CVMX_OCT_DID_SPX1 19ULL | ||
251 | #define CVMX_OCT_DID_PIP 20ULL | ||
252 | #define CVMX_OCT_DID_ASX0 22ULL | ||
253 | #define CVMX_OCT_DID_ASX1 23ULL | ||
254 | #define CVMX_OCT_DID_IOB 30ULL | ||
255 | |||
256 | #define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) | ||
257 | #define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) | ||
258 | #define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) | ||
259 | #define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) | ||
260 | #define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) | ||
261 | #define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) | ||
262 | #define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) | ||
263 | #define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) | ||
264 | #define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) | ||
265 | #define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) | ||
266 | #define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) | ||
267 | #define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) | ||
268 | #define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) | ||
269 | #define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) | ||
270 | #define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) | ||
271 | #define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) | ||
272 | #define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) | ||
273 | |||
274 | #endif /* __CVMX_ADDRESS_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/drivers/staging/octeon/cvmx-asxx-defs.h new file mode 100644 index 000000000000..91415a85e8d2 --- /dev/null +++ b/drivers/staging/octeon/cvmx-asxx-defs.h | |||
@@ -0,0 +1,475 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_ASXX_DEFS_H__ | ||
29 | #define __CVMX_ASXX_DEFS_H__ | ||
30 | |||
31 | #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \ | ||
32 | CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull)) | ||
33 | #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \ | ||
34 | CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull)) | ||
35 | #define CVMX_ASXX_INT_EN(block_id) \ | ||
36 | CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull)) | ||
37 | #define CVMX_ASXX_INT_REG(block_id) \ | ||
38 | CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull)) | ||
39 | #define CVMX_ASXX_MII_RX_DAT_SET(block_id) \ | ||
40 | CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull)) | ||
41 | #define CVMX_ASXX_PRT_LOOP(block_id) \ | ||
42 | CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull)) | ||
43 | #define CVMX_ASXX_RLD_BYPASS(block_id) \ | ||
44 | CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull)) | ||
45 | #define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \ | ||
46 | CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull)) | ||
47 | #define CVMX_ASXX_RLD_COMP(block_id) \ | ||
48 | CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull)) | ||
49 | #define CVMX_ASXX_RLD_DATA_DRV(block_id) \ | ||
50 | CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull)) | ||
51 | #define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \ | ||
52 | CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull)) | ||
53 | #define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \ | ||
54 | CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull)) | ||
55 | #define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \ | ||
56 | CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull)) | ||
57 | #define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \ | ||
58 | CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull)) | ||
59 | #define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \ | ||
60 | CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull)) | ||
61 | #define CVMX_ASXX_RLD_SETTING(block_id) \ | ||
62 | CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull)) | ||
63 | #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \ | ||
64 | CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
65 | #define CVMX_ASXX_RX_PRT_EN(block_id) \ | ||
66 | CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull)) | ||
67 | #define CVMX_ASXX_RX_WOL(block_id) \ | ||
68 | CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull)) | ||
69 | #define CVMX_ASXX_RX_WOL_MSK(block_id) \ | ||
70 | CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull)) | ||
71 | #define CVMX_ASXX_RX_WOL_POWOK(block_id) \ | ||
72 | CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull)) | ||
73 | #define CVMX_ASXX_RX_WOL_SIG(block_id) \ | ||
74 | CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull)) | ||
75 | #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \ | ||
76 | CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
77 | #define CVMX_ASXX_TX_COMP_BYP(block_id) \ | ||
78 | CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull)) | ||
79 | #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \ | ||
80 | CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
81 | #define CVMX_ASXX_TX_PRT_EN(block_id) \ | ||
82 | CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull)) | ||
83 | |||
84 | union cvmx_asxx_gmii_rx_clk_set { | ||
85 | uint64_t u64; | ||
86 | struct cvmx_asxx_gmii_rx_clk_set_s { | ||
87 | uint64_t reserved_5_63:59; | ||
88 | uint64_t setting:5; | ||
89 | } s; | ||
90 | struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; | ||
91 | struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; | ||
92 | struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; | ||
93 | }; | ||
94 | |||
95 | union cvmx_asxx_gmii_rx_dat_set { | ||
96 | uint64_t u64; | ||
97 | struct cvmx_asxx_gmii_rx_dat_set_s { | ||
98 | uint64_t reserved_5_63:59; | ||
99 | uint64_t setting:5; | ||
100 | } s; | ||
101 | struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; | ||
102 | struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; | ||
103 | struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; | ||
104 | }; | ||
105 | |||
106 | union cvmx_asxx_int_en { | ||
107 | uint64_t u64; | ||
108 | struct cvmx_asxx_int_en_s { | ||
109 | uint64_t reserved_12_63:52; | ||
110 | uint64_t txpsh:4; | ||
111 | uint64_t txpop:4; | ||
112 | uint64_t ovrflw:4; | ||
113 | } s; | ||
114 | struct cvmx_asxx_int_en_cn30xx { | ||
115 | uint64_t reserved_11_63:53; | ||
116 | uint64_t txpsh:3; | ||
117 | uint64_t reserved_7_7:1; | ||
118 | uint64_t txpop:3; | ||
119 | uint64_t reserved_3_3:1; | ||
120 | uint64_t ovrflw:3; | ||
121 | } cn30xx; | ||
122 | struct cvmx_asxx_int_en_cn30xx cn31xx; | ||
123 | struct cvmx_asxx_int_en_s cn38xx; | ||
124 | struct cvmx_asxx_int_en_s cn38xxp2; | ||
125 | struct cvmx_asxx_int_en_cn30xx cn50xx; | ||
126 | struct cvmx_asxx_int_en_s cn58xx; | ||
127 | struct cvmx_asxx_int_en_s cn58xxp1; | ||
128 | }; | ||
129 | |||
130 | union cvmx_asxx_int_reg { | ||
131 | uint64_t u64; | ||
132 | struct cvmx_asxx_int_reg_s { | ||
133 | uint64_t reserved_12_63:52; | ||
134 | uint64_t txpsh:4; | ||
135 | uint64_t txpop:4; | ||
136 | uint64_t ovrflw:4; | ||
137 | } s; | ||
138 | struct cvmx_asxx_int_reg_cn30xx { | ||
139 | uint64_t reserved_11_63:53; | ||
140 | uint64_t txpsh:3; | ||
141 | uint64_t reserved_7_7:1; | ||
142 | uint64_t txpop:3; | ||
143 | uint64_t reserved_3_3:1; | ||
144 | uint64_t ovrflw:3; | ||
145 | } cn30xx; | ||
146 | struct cvmx_asxx_int_reg_cn30xx cn31xx; | ||
147 | struct cvmx_asxx_int_reg_s cn38xx; | ||
148 | struct cvmx_asxx_int_reg_s cn38xxp2; | ||
149 | struct cvmx_asxx_int_reg_cn30xx cn50xx; | ||
150 | struct cvmx_asxx_int_reg_s cn58xx; | ||
151 | struct cvmx_asxx_int_reg_s cn58xxp1; | ||
152 | }; | ||
153 | |||
154 | union cvmx_asxx_mii_rx_dat_set { | ||
155 | uint64_t u64; | ||
156 | struct cvmx_asxx_mii_rx_dat_set_s { | ||
157 | uint64_t reserved_5_63:59; | ||
158 | uint64_t setting:5; | ||
159 | } s; | ||
160 | struct cvmx_asxx_mii_rx_dat_set_s cn30xx; | ||
161 | struct cvmx_asxx_mii_rx_dat_set_s cn50xx; | ||
162 | }; | ||
163 | |||
164 | union cvmx_asxx_prt_loop { | ||
165 | uint64_t u64; | ||
166 | struct cvmx_asxx_prt_loop_s { | ||
167 | uint64_t reserved_8_63:56; | ||
168 | uint64_t ext_loop:4; | ||
169 | uint64_t int_loop:4; | ||
170 | } s; | ||
171 | struct cvmx_asxx_prt_loop_cn30xx { | ||
172 | uint64_t reserved_7_63:57; | ||
173 | uint64_t ext_loop:3; | ||
174 | uint64_t reserved_3_3:1; | ||
175 | uint64_t int_loop:3; | ||
176 | } cn30xx; | ||
177 | struct cvmx_asxx_prt_loop_cn30xx cn31xx; | ||
178 | struct cvmx_asxx_prt_loop_s cn38xx; | ||
179 | struct cvmx_asxx_prt_loop_s cn38xxp2; | ||
180 | struct cvmx_asxx_prt_loop_cn30xx cn50xx; | ||
181 | struct cvmx_asxx_prt_loop_s cn58xx; | ||
182 | struct cvmx_asxx_prt_loop_s cn58xxp1; | ||
183 | }; | ||
184 | |||
185 | union cvmx_asxx_rld_bypass { | ||
186 | uint64_t u64; | ||
187 | struct cvmx_asxx_rld_bypass_s { | ||
188 | uint64_t reserved_1_63:63; | ||
189 | uint64_t bypass:1; | ||
190 | } s; | ||
191 | struct cvmx_asxx_rld_bypass_s cn38xx; | ||
192 | struct cvmx_asxx_rld_bypass_s cn38xxp2; | ||
193 | struct cvmx_asxx_rld_bypass_s cn58xx; | ||
194 | struct cvmx_asxx_rld_bypass_s cn58xxp1; | ||
195 | }; | ||
196 | |||
197 | union cvmx_asxx_rld_bypass_setting { | ||
198 | uint64_t u64; | ||
199 | struct cvmx_asxx_rld_bypass_setting_s { | ||
200 | uint64_t reserved_5_63:59; | ||
201 | uint64_t setting:5; | ||
202 | } s; | ||
203 | struct cvmx_asxx_rld_bypass_setting_s cn38xx; | ||
204 | struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; | ||
205 | struct cvmx_asxx_rld_bypass_setting_s cn58xx; | ||
206 | struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; | ||
207 | }; | ||
208 | |||
209 | union cvmx_asxx_rld_comp { | ||
210 | uint64_t u64; | ||
211 | struct cvmx_asxx_rld_comp_s { | ||
212 | uint64_t reserved_9_63:55; | ||
213 | uint64_t pctl:5; | ||
214 | uint64_t nctl:4; | ||
215 | } s; | ||
216 | struct cvmx_asxx_rld_comp_cn38xx { | ||
217 | uint64_t reserved_8_63:56; | ||
218 | uint64_t pctl:4; | ||
219 | uint64_t nctl:4; | ||
220 | } cn38xx; | ||
221 | struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; | ||
222 | struct cvmx_asxx_rld_comp_s cn58xx; | ||
223 | struct cvmx_asxx_rld_comp_s cn58xxp1; | ||
224 | }; | ||
225 | |||
226 | union cvmx_asxx_rld_data_drv { | ||
227 | uint64_t u64; | ||
228 | struct cvmx_asxx_rld_data_drv_s { | ||
229 | uint64_t reserved_8_63:56; | ||
230 | uint64_t pctl:4; | ||
231 | uint64_t nctl:4; | ||
232 | } s; | ||
233 | struct cvmx_asxx_rld_data_drv_s cn38xx; | ||
234 | struct cvmx_asxx_rld_data_drv_s cn38xxp2; | ||
235 | struct cvmx_asxx_rld_data_drv_s cn58xx; | ||
236 | struct cvmx_asxx_rld_data_drv_s cn58xxp1; | ||
237 | }; | ||
238 | |||
239 | union cvmx_asxx_rld_fcram_mode { | ||
240 | uint64_t u64; | ||
241 | struct cvmx_asxx_rld_fcram_mode_s { | ||
242 | uint64_t reserved_1_63:63; | ||
243 | uint64_t mode:1; | ||
244 | } s; | ||
245 | struct cvmx_asxx_rld_fcram_mode_s cn38xx; | ||
246 | struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; | ||
247 | }; | ||
248 | |||
249 | union cvmx_asxx_rld_nctl_strong { | ||
250 | uint64_t u64; | ||
251 | struct cvmx_asxx_rld_nctl_strong_s { | ||
252 | uint64_t reserved_5_63:59; | ||
253 | uint64_t nctl:5; | ||
254 | } s; | ||
255 | struct cvmx_asxx_rld_nctl_strong_s cn38xx; | ||
256 | struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; | ||
257 | struct cvmx_asxx_rld_nctl_strong_s cn58xx; | ||
258 | struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; | ||
259 | }; | ||
260 | |||
261 | union cvmx_asxx_rld_nctl_weak { | ||
262 | uint64_t u64; | ||
263 | struct cvmx_asxx_rld_nctl_weak_s { | ||
264 | uint64_t reserved_5_63:59; | ||
265 | uint64_t nctl:5; | ||
266 | } s; | ||
267 | struct cvmx_asxx_rld_nctl_weak_s cn38xx; | ||
268 | struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; | ||
269 | struct cvmx_asxx_rld_nctl_weak_s cn58xx; | ||
270 | struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; | ||
271 | }; | ||
272 | |||
273 | union cvmx_asxx_rld_pctl_strong { | ||
274 | uint64_t u64; | ||
275 | struct cvmx_asxx_rld_pctl_strong_s { | ||
276 | uint64_t reserved_5_63:59; | ||
277 | uint64_t pctl:5; | ||
278 | } s; | ||
279 | struct cvmx_asxx_rld_pctl_strong_s cn38xx; | ||
280 | struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; | ||
281 | struct cvmx_asxx_rld_pctl_strong_s cn58xx; | ||
282 | struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; | ||
283 | }; | ||
284 | |||
285 | union cvmx_asxx_rld_pctl_weak { | ||
286 | uint64_t u64; | ||
287 | struct cvmx_asxx_rld_pctl_weak_s { | ||
288 | uint64_t reserved_5_63:59; | ||
289 | uint64_t pctl:5; | ||
290 | } s; | ||
291 | struct cvmx_asxx_rld_pctl_weak_s cn38xx; | ||
292 | struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; | ||
293 | struct cvmx_asxx_rld_pctl_weak_s cn58xx; | ||
294 | struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; | ||
295 | }; | ||
296 | |||
297 | union cvmx_asxx_rld_setting { | ||
298 | uint64_t u64; | ||
299 | struct cvmx_asxx_rld_setting_s { | ||
300 | uint64_t reserved_13_63:51; | ||
301 | uint64_t dfaset:5; | ||
302 | uint64_t dfalag:1; | ||
303 | uint64_t dfalead:1; | ||
304 | uint64_t dfalock:1; | ||
305 | uint64_t setting:5; | ||
306 | } s; | ||
307 | struct cvmx_asxx_rld_setting_cn38xx { | ||
308 | uint64_t reserved_5_63:59; | ||
309 | uint64_t setting:5; | ||
310 | } cn38xx; | ||
311 | struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; | ||
312 | struct cvmx_asxx_rld_setting_s cn58xx; | ||
313 | struct cvmx_asxx_rld_setting_s cn58xxp1; | ||
314 | }; | ||
315 | |||
316 | union cvmx_asxx_rx_clk_setx { | ||
317 | uint64_t u64; | ||
318 | struct cvmx_asxx_rx_clk_setx_s { | ||
319 | uint64_t reserved_5_63:59; | ||
320 | uint64_t setting:5; | ||
321 | } s; | ||
322 | struct cvmx_asxx_rx_clk_setx_s cn30xx; | ||
323 | struct cvmx_asxx_rx_clk_setx_s cn31xx; | ||
324 | struct cvmx_asxx_rx_clk_setx_s cn38xx; | ||
325 | struct cvmx_asxx_rx_clk_setx_s cn38xxp2; | ||
326 | struct cvmx_asxx_rx_clk_setx_s cn50xx; | ||
327 | struct cvmx_asxx_rx_clk_setx_s cn58xx; | ||
328 | struct cvmx_asxx_rx_clk_setx_s cn58xxp1; | ||
329 | }; | ||
330 | |||
331 | union cvmx_asxx_rx_prt_en { | ||
332 | uint64_t u64; | ||
333 | struct cvmx_asxx_rx_prt_en_s { | ||
334 | uint64_t reserved_4_63:60; | ||
335 | uint64_t prt_en:4; | ||
336 | } s; | ||
337 | struct cvmx_asxx_rx_prt_en_cn30xx { | ||
338 | uint64_t reserved_3_63:61; | ||
339 | uint64_t prt_en:3; | ||
340 | } cn30xx; | ||
341 | struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; | ||
342 | struct cvmx_asxx_rx_prt_en_s cn38xx; | ||
343 | struct cvmx_asxx_rx_prt_en_s cn38xxp2; | ||
344 | struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; | ||
345 | struct cvmx_asxx_rx_prt_en_s cn58xx; | ||
346 | struct cvmx_asxx_rx_prt_en_s cn58xxp1; | ||
347 | }; | ||
348 | |||
349 | union cvmx_asxx_rx_wol { | ||
350 | uint64_t u64; | ||
351 | struct cvmx_asxx_rx_wol_s { | ||
352 | uint64_t reserved_2_63:62; | ||
353 | uint64_t status:1; | ||
354 | uint64_t enable:1; | ||
355 | } s; | ||
356 | struct cvmx_asxx_rx_wol_s cn38xx; | ||
357 | struct cvmx_asxx_rx_wol_s cn38xxp2; | ||
358 | }; | ||
359 | |||
360 | union cvmx_asxx_rx_wol_msk { | ||
361 | uint64_t u64; | ||
362 | struct cvmx_asxx_rx_wol_msk_s { | ||
363 | uint64_t msk:64; | ||
364 | } s; | ||
365 | struct cvmx_asxx_rx_wol_msk_s cn38xx; | ||
366 | struct cvmx_asxx_rx_wol_msk_s cn38xxp2; | ||
367 | }; | ||
368 | |||
369 | union cvmx_asxx_rx_wol_powok { | ||
370 | uint64_t u64; | ||
371 | struct cvmx_asxx_rx_wol_powok_s { | ||
372 | uint64_t reserved_1_63:63; | ||
373 | uint64_t powerok:1; | ||
374 | } s; | ||
375 | struct cvmx_asxx_rx_wol_powok_s cn38xx; | ||
376 | struct cvmx_asxx_rx_wol_powok_s cn38xxp2; | ||
377 | }; | ||
378 | |||
379 | union cvmx_asxx_rx_wol_sig { | ||
380 | uint64_t u64; | ||
381 | struct cvmx_asxx_rx_wol_sig_s { | ||
382 | uint64_t reserved_32_63:32; | ||
383 | uint64_t sig:32; | ||
384 | } s; | ||
385 | struct cvmx_asxx_rx_wol_sig_s cn38xx; | ||
386 | struct cvmx_asxx_rx_wol_sig_s cn38xxp2; | ||
387 | }; | ||
388 | |||
389 | union cvmx_asxx_tx_clk_setx { | ||
390 | uint64_t u64; | ||
391 | struct cvmx_asxx_tx_clk_setx_s { | ||
392 | uint64_t reserved_5_63:59; | ||
393 | uint64_t setting:5; | ||
394 | } s; | ||
395 | struct cvmx_asxx_tx_clk_setx_s cn30xx; | ||
396 | struct cvmx_asxx_tx_clk_setx_s cn31xx; | ||
397 | struct cvmx_asxx_tx_clk_setx_s cn38xx; | ||
398 | struct cvmx_asxx_tx_clk_setx_s cn38xxp2; | ||
399 | struct cvmx_asxx_tx_clk_setx_s cn50xx; | ||
400 | struct cvmx_asxx_tx_clk_setx_s cn58xx; | ||
401 | struct cvmx_asxx_tx_clk_setx_s cn58xxp1; | ||
402 | }; | ||
403 | |||
404 | union cvmx_asxx_tx_comp_byp { | ||
405 | uint64_t u64; | ||
406 | struct cvmx_asxx_tx_comp_byp_s { | ||
407 | uint64_t reserved_0_63:64; | ||
408 | } s; | ||
409 | struct cvmx_asxx_tx_comp_byp_cn30xx { | ||
410 | uint64_t reserved_9_63:55; | ||
411 | uint64_t bypass:1; | ||
412 | uint64_t pctl:4; | ||
413 | uint64_t nctl:4; | ||
414 | } cn30xx; | ||
415 | struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; | ||
416 | struct cvmx_asxx_tx_comp_byp_cn38xx { | ||
417 | uint64_t reserved_8_63:56; | ||
418 | uint64_t pctl:4; | ||
419 | uint64_t nctl:4; | ||
420 | } cn38xx; | ||
421 | struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; | ||
422 | struct cvmx_asxx_tx_comp_byp_cn50xx { | ||
423 | uint64_t reserved_17_63:47; | ||
424 | uint64_t bypass:1; | ||
425 | uint64_t reserved_13_15:3; | ||
426 | uint64_t pctl:5; | ||
427 | uint64_t reserved_5_7:3; | ||
428 | uint64_t nctl:5; | ||
429 | } cn50xx; | ||
430 | struct cvmx_asxx_tx_comp_byp_cn58xx { | ||
431 | uint64_t reserved_13_63:51; | ||
432 | uint64_t pctl:5; | ||
433 | uint64_t reserved_5_7:3; | ||
434 | uint64_t nctl:5; | ||
435 | } cn58xx; | ||
436 | struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; | ||
437 | }; | ||
438 | |||
439 | union cvmx_asxx_tx_hi_waterx { | ||
440 | uint64_t u64; | ||
441 | struct cvmx_asxx_tx_hi_waterx_s { | ||
442 | uint64_t reserved_4_63:60; | ||
443 | uint64_t mark:4; | ||
444 | } s; | ||
445 | struct cvmx_asxx_tx_hi_waterx_cn30xx { | ||
446 | uint64_t reserved_3_63:61; | ||
447 | uint64_t mark:3; | ||
448 | } cn30xx; | ||
449 | struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; | ||
450 | struct cvmx_asxx_tx_hi_waterx_s cn38xx; | ||
451 | struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; | ||
452 | struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; | ||
453 | struct cvmx_asxx_tx_hi_waterx_s cn58xx; | ||
454 | struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; | ||
455 | }; | ||
456 | |||
457 | union cvmx_asxx_tx_prt_en { | ||
458 | uint64_t u64; | ||
459 | struct cvmx_asxx_tx_prt_en_s { | ||
460 | uint64_t reserved_4_63:60; | ||
461 | uint64_t prt_en:4; | ||
462 | } s; | ||
463 | struct cvmx_asxx_tx_prt_en_cn30xx { | ||
464 | uint64_t reserved_3_63:61; | ||
465 | uint64_t prt_en:3; | ||
466 | } cn30xx; | ||
467 | struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; | ||
468 | struct cvmx_asxx_tx_prt_en_s cn38xx; | ||
469 | struct cvmx_asxx_tx_prt_en_s cn38xxp2; | ||
470 | struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; | ||
471 | struct cvmx_asxx_tx_prt_en_s cn58xx; | ||
472 | struct cvmx_asxx_tx_prt_en_s cn58xxp1; | ||
473 | }; | ||
474 | |||
475 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/drivers/staging/octeon/cvmx-cmd-queue.c new file mode 100644 index 000000000000..976227b01273 --- /dev/null +++ b/drivers/staging/octeon/cvmx-cmd-queue.c | |||
@@ -0,0 +1,306 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Support functions for managing command queues used for | ||
30 | * various hardware blocks. | ||
31 | */ | ||
32 | |||
33 | #include <linux/kernel.h> | ||
34 | |||
35 | #include <asm/octeon/octeon.h> | ||
36 | |||
37 | #include "cvmx-config.h" | ||
38 | #include "cvmx-fpa.h" | ||
39 | #include "cvmx-cmd-queue.h" | ||
40 | |||
41 | #include <asm/octeon/cvmx-npei-defs.h> | ||
42 | #include <asm/octeon/cvmx-pexp-defs.h> | ||
43 | #include "cvmx-pko-defs.h" | ||
44 | |||
45 | /** | ||
46 | * This application uses this pointer to access the global queue | ||
47 | * state. It points to a bootmem named block. | ||
48 | */ | ||
49 | __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr; | ||
50 | |||
51 | /** | ||
52 | * Initialize the Global queue state pointer. | ||
53 | * | ||
54 | * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code | ||
55 | */ | ||
56 | static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void) | ||
57 | { | ||
58 | char *alloc_name = "cvmx_cmd_queues"; | ||
59 | #if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32 | ||
60 | extern uint64_t octeon_reserve32_memory; | ||
61 | #endif | ||
62 | |||
63 | if (likely(__cvmx_cmd_queue_state_ptr)) | ||
64 | return CVMX_CMD_QUEUE_SUCCESS; | ||
65 | |||
66 | #if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32 | ||
67 | if (octeon_reserve32_memory) | ||
68 | __cvmx_cmd_queue_state_ptr = | ||
69 | cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr), | ||
70 | octeon_reserve32_memory, | ||
71 | octeon_reserve32_memory + | ||
72 | (CONFIG_CAVIUM_RESERVE32 << | ||
73 | 20) - 1, 128, alloc_name); | ||
74 | else | ||
75 | #endif | ||
76 | __cvmx_cmd_queue_state_ptr = | ||
77 | cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr), | ||
78 | 128, | ||
79 | alloc_name); | ||
80 | if (__cvmx_cmd_queue_state_ptr) | ||
81 | memset(__cvmx_cmd_queue_state_ptr, 0, | ||
82 | sizeof(*__cvmx_cmd_queue_state_ptr)); | ||
83 | else { | ||
84 | struct cvmx_bootmem_named_block_desc *block_desc = | ||
85 | cvmx_bootmem_find_named_block(alloc_name); | ||
86 | if (block_desc) | ||
87 | __cvmx_cmd_queue_state_ptr = | ||
88 | cvmx_phys_to_ptr(block_desc->base_addr); | ||
89 | else { | ||
90 | cvmx_dprintf | ||
91 | ("ERROR: cvmx_cmd_queue_initialize: Unable to get named block %s.\n", | ||
92 | alloc_name); | ||
93 | return CVMX_CMD_QUEUE_NO_MEMORY; | ||
94 | } | ||
95 | } | ||
96 | return CVMX_CMD_QUEUE_SUCCESS; | ||
97 | } | ||
98 | |||
99 | /** | ||
100 | * Initialize a command queue for use. The initial FPA buffer is | ||
101 | * allocated and the hardware unit is configured to point to the | ||
102 | * new command queue. | ||
103 | * | ||
104 | * @queue_id: Hardware command queue to initialize. | ||
105 | * @max_depth: Maximum outstanding commands that can be queued. | ||
106 | * @fpa_pool: FPA pool the command queues should come from. | ||
107 | * @pool_size: Size of each buffer in the FPA pool (bytes) | ||
108 | * | ||
109 | * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code | ||
110 | */ | ||
111 | cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, | ||
112 | int max_depth, int fpa_pool, | ||
113 | int pool_size) | ||
114 | { | ||
115 | __cvmx_cmd_queue_state_t *qstate; | ||
116 | cvmx_cmd_queue_result_t result = __cvmx_cmd_queue_init_state_ptr(); | ||
117 | if (result != CVMX_CMD_QUEUE_SUCCESS) | ||
118 | return result; | ||
119 | |||
120 | qstate = __cvmx_cmd_queue_get_state(queue_id); | ||
121 | if (qstate == NULL) | ||
122 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
123 | |||
124 | /* | ||
125 | * We artificially limit max_depth to 1<<20 words. It is an | ||
126 | * arbitrary limit. | ||
127 | */ | ||
128 | if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH) { | ||
129 | if ((max_depth < 0) || (max_depth > 1 << 20)) | ||
130 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
131 | } else if (max_depth != 0) | ||
132 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
133 | |||
134 | if ((fpa_pool < 0) || (fpa_pool > 7)) | ||
135 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
136 | if ((pool_size < 128) || (pool_size > 65536)) | ||
137 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
138 | |||
139 | /* See if someone else has already initialized the queue */ | ||
140 | if (qstate->base_ptr_div128) { | ||
141 | if (max_depth != (int)qstate->max_depth) { | ||
142 | cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " | ||
143 | "Queue already initalized with different " | ||
144 | "max_depth (%d).\n", | ||
145 | (int)qstate->max_depth); | ||
146 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
147 | } | ||
148 | if (fpa_pool != qstate->fpa_pool) { | ||
149 | cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " | ||
150 | "Queue already initalized with different " | ||
151 | "FPA pool (%u).\n", | ||
152 | qstate->fpa_pool); | ||
153 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
154 | } | ||
155 | if ((pool_size >> 3) - 1 != qstate->pool_size_m1) { | ||
156 | cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " | ||
157 | "Queue already initalized with different " | ||
158 | "FPA pool size (%u).\n", | ||
159 | (qstate->pool_size_m1 + 1) << 3); | ||
160 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
161 | } | ||
162 | CVMX_SYNCWS; | ||
163 | return CVMX_CMD_QUEUE_ALREADY_SETUP; | ||
164 | } else { | ||
165 | union cvmx_fpa_ctl_status status; | ||
166 | void *buffer; | ||
167 | |||
168 | status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); | ||
169 | if (!status.s.enb) { | ||
170 | cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " | ||
171 | "FPA is not enabled.\n"); | ||
172 | return CVMX_CMD_QUEUE_NO_MEMORY; | ||
173 | } | ||
174 | buffer = cvmx_fpa_alloc(fpa_pool); | ||
175 | if (buffer == NULL) { | ||
176 | cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " | ||
177 | "Unable to allocate initial buffer.\n"); | ||
178 | return CVMX_CMD_QUEUE_NO_MEMORY; | ||
179 | } | ||
180 | |||
181 | memset(qstate, 0, sizeof(*qstate)); | ||
182 | qstate->max_depth = max_depth; | ||
183 | qstate->fpa_pool = fpa_pool; | ||
184 | qstate->pool_size_m1 = (pool_size >> 3) - 1; | ||
185 | qstate->base_ptr_div128 = cvmx_ptr_to_phys(buffer) / 128; | ||
186 | /* | ||
187 | * We zeroed the now serving field so we need to also | ||
188 | * zero the ticket. | ||
189 | */ | ||
190 | __cvmx_cmd_queue_state_ptr-> | ||
191 | ticket[__cvmx_cmd_queue_get_index(queue_id)] = 0; | ||
192 | CVMX_SYNCWS; | ||
193 | return CVMX_CMD_QUEUE_SUCCESS; | ||
194 | } | ||
195 | } | ||
196 | |||
197 | /** | ||
198 | * Shutdown a queue a free it's command buffers to the FPA. The | ||
199 | * hardware connected to the queue must be stopped before this | ||
200 | * function is called. | ||
201 | * | ||
202 | * @queue_id: Queue to shutdown | ||
203 | * | ||
204 | * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code | ||
205 | */ | ||
206 | cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id) | ||
207 | { | ||
208 | __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); | ||
209 | if (qptr == NULL) { | ||
210 | cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to " | ||
211 | "get queue information.\n"); | ||
212 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
213 | } | ||
214 | |||
215 | if (cvmx_cmd_queue_length(queue_id) > 0) { | ||
216 | cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still " | ||
217 | "has data in it.\n"); | ||
218 | return CVMX_CMD_QUEUE_FULL; | ||
219 | } | ||
220 | |||
221 | __cvmx_cmd_queue_lock(queue_id, qptr); | ||
222 | if (qptr->base_ptr_div128) { | ||
223 | cvmx_fpa_free(cvmx_phys_to_ptr | ||
224 | ((uint64_t) qptr->base_ptr_div128 << 7), | ||
225 | qptr->fpa_pool, 0); | ||
226 | qptr->base_ptr_div128 = 0; | ||
227 | } | ||
228 | __cvmx_cmd_queue_unlock(qptr); | ||
229 | |||
230 | return CVMX_CMD_QUEUE_SUCCESS; | ||
231 | } | ||
232 | |||
233 | /** | ||
234 | * Return the number of command words pending in the queue. This | ||
235 | * function may be relatively slow for some hardware units. | ||
236 | * | ||
237 | * @queue_id: Hardware command queue to query | ||
238 | * | ||
239 | * Returns Number of outstanding commands | ||
240 | */ | ||
241 | int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) | ||
242 | { | ||
243 | if (CVMX_ENABLE_PARAMETER_CHECKING) { | ||
244 | if (__cvmx_cmd_queue_get_state(queue_id) == NULL) | ||
245 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
246 | } | ||
247 | |||
248 | /* | ||
249 | * The cast is here so gcc with check that all values in the | ||
250 | * cvmx_cmd_queue_id_t enumeration are here. | ||
251 | */ | ||
252 | switch ((cvmx_cmd_queue_id_t) (queue_id & 0xff0000)) { | ||
253 | case CVMX_CMD_QUEUE_PKO_BASE: | ||
254 | /* | ||
255 | * FIXME: Need atomic lock on | ||
256 | * CVMX_PKO_REG_READ_IDX. Right now we are normally | ||
257 | * called with the queue lock, so that is a SLIGHT | ||
258 | * amount of protection. | ||
259 | */ | ||
260 | cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff); | ||
261 | if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { | ||
262 | union cvmx_pko_mem_debug9 debug9; | ||
263 | debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); | ||
264 | return debug9.cn38xx.doorbell; | ||
265 | } else { | ||
266 | union cvmx_pko_mem_debug8 debug8; | ||
267 | debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); | ||
268 | return debug8.cn58xx.doorbell; | ||
269 | } | ||
270 | case CVMX_CMD_QUEUE_ZIP: | ||
271 | case CVMX_CMD_QUEUE_DFA: | ||
272 | case CVMX_CMD_QUEUE_RAID: | ||
273 | /* FIXME: Implement other lengths */ | ||
274 | return 0; | ||
275 | case CVMX_CMD_QUEUE_DMA_BASE: | ||
276 | { | ||
277 | union cvmx_npei_dmax_counts dmax_counts; | ||
278 | dmax_counts.u64 = | ||
279 | cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS | ||
280 | (queue_id & 0x7)); | ||
281 | return dmax_counts.s.dbell; | ||
282 | } | ||
283 | case CVMX_CMD_QUEUE_END: | ||
284 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
285 | } | ||
286 | return CVMX_CMD_QUEUE_INVALID_PARAM; | ||
287 | } | ||
288 | |||
289 | /** | ||
290 | * Return the command buffer to be written to. The purpose of this | ||
291 | * function is to allow CVMX routine access t othe low level buffer | ||
292 | * for initial hardware setup. User applications should not call this | ||
293 | * function directly. | ||
294 | * | ||
295 | * @queue_id: Command queue to query | ||
296 | * | ||
297 | * Returns Command buffer or NULL on failure | ||
298 | */ | ||
299 | void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id) | ||
300 | { | ||
301 | __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); | ||
302 | if (qptr && qptr->base_ptr_div128) | ||
303 | return cvmx_phys_to_ptr((uint64_t) qptr->base_ptr_div128 << 7); | ||
304 | else | ||
305 | return NULL; | ||
306 | } | ||
diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/drivers/staging/octeon/cvmx-cmd-queue.h new file mode 100644 index 000000000000..f0cb20ffa39a --- /dev/null +++ b/drivers/staging/octeon/cvmx-cmd-queue.h | |||
@@ -0,0 +1,617 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * | ||
30 | * Support functions for managing command queues used for | ||
31 | * various hardware blocks. | ||
32 | * | ||
33 | * The common command queue infrastructure abstracts out the | ||
34 | * software necessary for adding to Octeon's chained queue | ||
35 | * structures. These structures are used for commands to the | ||
36 | * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each | ||
37 | * hardware unit takes commands and CSRs of different types, | ||
38 | * they all use basic linked command buffers to store the | ||
39 | * pending request. In general, users of the CVMX API don't | ||
40 | * call cvmx-cmd-queue functions directly. Instead the hardware | ||
41 | * unit specific wrapper should be used. The wrappers perform | ||
42 | * unit specific validation and CSR writes to submit the | ||
43 | * commands. | ||
44 | * | ||
45 | * Even though most software will never directly interact with | ||
46 | * cvmx-cmd-queue, knowledge of its internal working can help | ||
47 | * in diagnosing performance problems and help with debugging. | ||
48 | * | ||
49 | * Command queue pointers are stored in a global named block | ||
50 | * called "cvmx_cmd_queues". Except for the PKO queues, each | ||
51 | * hardware queue is stored in its own cache line to reduce SMP | ||
52 | * contention on spin locks. The PKO queues are stored such that | ||
53 | * every 16th queue is next to each other in memory. This scheme | ||
54 | * allows for queues being in separate cache lines when there | ||
55 | * are low number of queues per port. With 16 queues per port, | ||
56 | * the first queue for each port is in the same cache area. The | ||
57 | * second queues for each port are in another area, etc. This | ||
58 | * allows software to implement very efficient lockless PKO with | ||
59 | * 16 queues per port using a minimum of cache lines per core. | ||
60 | * All queues for a given core will be isolated in the same | ||
61 | * cache area. | ||
62 | * | ||
63 | * In addition to the memory pointer layout, cvmx-cmd-queue | ||
64 | * provides an optimized fair ll/sc locking mechanism for the | ||
65 | * queues. The lock uses a "ticket / now serving" model to | ||
66 | * maintain fair order on contended locks. In addition, it uses | ||
67 | * predicted locking time to limit cache contention. When a core | ||
68 | * know it must wait in line for a lock, it spins on the | ||
69 | * internal cycle counter to completely eliminate any causes of | ||
70 | * bus traffic. | ||
71 | * | ||
72 | */ | ||
73 | |||
74 | #ifndef __CVMX_CMD_QUEUE_H__ | ||
75 | #define __CVMX_CMD_QUEUE_H__ | ||
76 | |||
77 | #include <linux/prefetch.h> | ||
78 | |||
79 | #include "cvmx-fpa.h" | ||
80 | /** | ||
81 | * By default we disable the max depth support. Most programs | ||
82 | * don't use it and it slows down the command queue processing | ||
83 | * significantly. | ||
84 | */ | ||
85 | #ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH | ||
86 | #define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0 | ||
87 | #endif | ||
88 | |||
89 | /** | ||
90 | * Enumeration representing all hardware blocks that use command | ||
91 | * queues. Each hardware block has up to 65536 sub identifiers for | ||
92 | * multiple command queues. Not all chips support all hardware | ||
93 | * units. | ||
94 | */ | ||
95 | typedef enum { | ||
96 | CVMX_CMD_QUEUE_PKO_BASE = 0x00000, | ||
97 | |||
98 | #define CVMX_CMD_QUEUE_PKO(queue) \ | ||
99 | ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue)))) | ||
100 | |||
101 | CVMX_CMD_QUEUE_ZIP = 0x10000, | ||
102 | CVMX_CMD_QUEUE_DFA = 0x20000, | ||
103 | CVMX_CMD_QUEUE_RAID = 0x30000, | ||
104 | CVMX_CMD_QUEUE_DMA_BASE = 0x40000, | ||
105 | |||
106 | #define CVMX_CMD_QUEUE_DMA(queue) \ | ||
107 | ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue)))) | ||
108 | |||
109 | CVMX_CMD_QUEUE_END = 0x50000, | ||
110 | } cvmx_cmd_queue_id_t; | ||
111 | |||
112 | /** | ||
113 | * Command write operations can fail if the comamnd queue needs | ||
114 | * a new buffer and the associated FPA pool is empty. It can also | ||
115 | * fail if the number of queued command words reaches the maximum | ||
116 | * set at initialization. | ||
117 | */ | ||
118 | typedef enum { | ||
119 | CVMX_CMD_QUEUE_SUCCESS = 0, | ||
120 | CVMX_CMD_QUEUE_NO_MEMORY = -1, | ||
121 | CVMX_CMD_QUEUE_FULL = -2, | ||
122 | CVMX_CMD_QUEUE_INVALID_PARAM = -3, | ||
123 | CVMX_CMD_QUEUE_ALREADY_SETUP = -4, | ||
124 | } cvmx_cmd_queue_result_t; | ||
125 | |||
126 | typedef struct { | ||
127 | /* You have lock when this is your ticket */ | ||
128 | uint8_t now_serving; | ||
129 | uint64_t unused1:24; | ||
130 | /* Maximum outstanding command words */ | ||
131 | uint32_t max_depth; | ||
132 | /* FPA pool buffers come from */ | ||
133 | uint64_t fpa_pool:3; | ||
134 | /* Top of command buffer pointer shifted 7 */ | ||
135 | uint64_t base_ptr_div128:29; | ||
136 | uint64_t unused2:6; | ||
137 | /* FPA buffer size in 64bit words minus 1 */ | ||
138 | uint64_t pool_size_m1:13; | ||
139 | /* Number of comamnds already used in buffer */ | ||
140 | uint64_t index:13; | ||
141 | } __cvmx_cmd_queue_state_t; | ||
142 | |||
143 | /** | ||
144 | * This structure contains the global state of all comamnd queues. | ||
145 | * It is stored in a bootmem named block and shared by all | ||
146 | * applications running on Octeon. Tickets are stored in a differnet | ||
147 | * cahce line that queue information to reduce the contention on the | ||
148 | * ll/sc used to get a ticket. If this is not the case, the update | ||
149 | * of queue state causes the ll/sc to fail quite often. | ||
150 | */ | ||
151 | typedef struct { | ||
152 | uint64_t ticket[(CVMX_CMD_QUEUE_END >> 16) * 256]; | ||
153 | __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256]; | ||
154 | } __cvmx_cmd_queue_all_state_t; | ||
155 | |||
156 | /** | ||
157 | * Initialize a command queue for use. The initial FPA buffer is | ||
158 | * allocated and the hardware unit is configured to point to the | ||
159 | * new command queue. | ||
160 | * | ||
161 | * @queue_id: Hardware command queue to initialize. | ||
162 | * @max_depth: Maximum outstanding commands that can be queued. | ||
163 | * @fpa_pool: FPA pool the command queues should come from. | ||
164 | * @pool_size: Size of each buffer in the FPA pool (bytes) | ||
165 | * | ||
166 | * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code | ||
167 | */ | ||
168 | cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, | ||
169 | int max_depth, int fpa_pool, | ||
170 | int pool_size); | ||
171 | |||
172 | /** | ||
173 | * Shutdown a queue a free it's command buffers to the FPA. The | ||
174 | * hardware connected to the queue must be stopped before this | ||
175 | * function is called. | ||
176 | * | ||
177 | * @queue_id: Queue to shutdown | ||
178 | * | ||
179 | * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code | ||
180 | */ | ||
181 | cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id); | ||
182 | |||
183 | /** | ||
184 | * Return the number of command words pending in the queue. This | ||
185 | * function may be relatively slow for some hardware units. | ||
186 | * | ||
187 | * @queue_id: Hardware command queue to query | ||
188 | * | ||
189 | * Returns Number of outstanding commands | ||
190 | */ | ||
191 | int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id); | ||
192 | |||
193 | /** | ||
194 | * Return the command buffer to be written to. The purpose of this | ||
195 | * function is to allow CVMX routine access t othe low level buffer | ||
196 | * for initial hardware setup. User applications should not call this | ||
197 | * function directly. | ||
198 | * | ||
199 | * @queue_id: Command queue to query | ||
200 | * | ||
201 | * Returns Command buffer or NULL on failure | ||
202 | */ | ||
203 | void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id); | ||
204 | |||
205 | /** | ||
206 | * Get the index into the state arrays for the supplied queue id. | ||
207 | * | ||
208 | * @queue_id: Queue ID to get an index for | ||
209 | * | ||
210 | * Returns Index into the state arrays | ||
211 | */ | ||
212 | static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id) | ||
213 | { | ||
214 | /* | ||
215 | * Warning: This code currently only works with devices that | ||
216 | * have 256 queues or less. Devices with more than 16 queues | ||
217 | * are layed out in memory to allow cores quick access to | ||
218 | * every 16th queue. This reduces cache thrashing when you are | ||
219 | * running 16 queues per port to support lockless operation. | ||
220 | */ | ||
221 | int unit = queue_id >> 16; | ||
222 | int q = (queue_id >> 4) & 0xf; | ||
223 | int core = queue_id & 0xf; | ||
224 | return unit * 256 + core * 16 + q; | ||
225 | } | ||
226 | |||
227 | /** | ||
228 | * Lock the supplied queue so nobody else is updating it at the same | ||
229 | * time as us. | ||
230 | * | ||
231 | * @queue_id: Queue ID to lock | ||
232 | * @qptr: Pointer to the queue's global state | ||
233 | */ | ||
234 | static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, | ||
235 | __cvmx_cmd_queue_state_t *qptr) | ||
236 | { | ||
237 | extern __cvmx_cmd_queue_all_state_t | ||
238 | *__cvmx_cmd_queue_state_ptr; | ||
239 | int tmp; | ||
240 | int my_ticket; | ||
241 | prefetch(qptr); | ||
242 | asm volatile ( | ||
243 | ".set push\n" | ||
244 | ".set noreorder\n" | ||
245 | "1:\n" | ||
246 | /* Atomic add one to ticket_ptr */ | ||
247 | "ll %[my_ticket], %[ticket_ptr]\n" | ||
248 | /* and store the original value */ | ||
249 | "li %[ticket], 1\n" | ||
250 | /* in my_ticket */ | ||
251 | "baddu %[ticket], %[my_ticket]\n" | ||
252 | "sc %[ticket], %[ticket_ptr]\n" | ||
253 | "beqz %[ticket], 1b\n" | ||
254 | " nop\n" | ||
255 | /* Load the current now_serving ticket */ | ||
256 | "lbu %[ticket], %[now_serving]\n" | ||
257 | "2:\n" | ||
258 | /* Jump out if now_serving == my_ticket */ | ||
259 | "beq %[ticket], %[my_ticket], 4f\n" | ||
260 | /* Find out how many tickets are in front of me */ | ||
261 | " subu %[ticket], %[my_ticket], %[ticket]\n" | ||
262 | /* Use tickets in front of me minus one to delay */ | ||
263 | "subu %[ticket], 1\n" | ||
264 | /* Delay will be ((tickets in front)-1)*32 loops */ | ||
265 | "cins %[ticket], %[ticket], 5, 7\n" | ||
266 | "3:\n" | ||
267 | /* Loop here until our ticket might be up */ | ||
268 | "bnez %[ticket], 3b\n" | ||
269 | " subu %[ticket], 1\n" | ||
270 | /* Jump back up to check out ticket again */ | ||
271 | "b 2b\n" | ||
272 | /* Load the current now_serving ticket */ | ||
273 | " lbu %[ticket], %[now_serving]\n" | ||
274 | "4:\n" | ||
275 | ".set pop\n" : | ||
276 | [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]), | ||
277 | [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp), | ||
278 | [my_ticket] "=r"(my_ticket) | ||
279 | ); | ||
280 | } | ||
281 | |||
282 | /** | ||
283 | * Unlock the queue, flushing all writes. | ||
284 | * | ||
285 | * @qptr: Queue to unlock | ||
286 | */ | ||
287 | static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr) | ||
288 | { | ||
289 | qptr->now_serving++; | ||
290 | CVMX_SYNCWS; | ||
291 | } | ||
292 | |||
293 | /** | ||
294 | * Get the queue state structure for the given queue id | ||
295 | * | ||
296 | * @queue_id: Queue id to get | ||
297 | * | ||
298 | * Returns Queue structure or NULL on failure | ||
299 | */ | ||
300 | static inline __cvmx_cmd_queue_state_t | ||
301 | *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id) | ||
302 | { | ||
303 | extern __cvmx_cmd_queue_all_state_t | ||
304 | *__cvmx_cmd_queue_state_ptr; | ||
305 | return &__cvmx_cmd_queue_state_ptr-> | ||
306 | state[__cvmx_cmd_queue_get_index(queue_id)]; | ||
307 | } | ||
308 | |||
309 | /** | ||
310 | * Write an arbitrary number of command words to a command queue. | ||
311 | * This is a generic function; the fixed number of comamnd word | ||
312 | * functions yield higher performance. | ||
313 | * | ||
314 | * @queue_id: Hardware command queue to write to | ||
315 | * @use_locking: | ||
316 | * Use internal locking to ensure exclusive access for queue | ||
317 | * updates. If you don't use this locking you must ensure | ||
318 | * exclusivity some other way. Locking is strongly recommended. | ||
319 | * @cmd_count: Number of command words to write | ||
320 | * @cmds: Array of comamnds to write | ||
321 | * | ||
322 | * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code | ||
323 | */ | ||
324 | static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t | ||
325 | queue_id, | ||
326 | int use_locking, | ||
327 | int cmd_count, | ||
328 | uint64_t *cmds) | ||
329 | { | ||
330 | __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); | ||
331 | |||
332 | /* Make sure nobody else is updating the same queue */ | ||
333 | if (likely(use_locking)) | ||
334 | __cvmx_cmd_queue_lock(queue_id, qptr); | ||
335 | |||
336 | /* | ||
337 | * If a max queue length was specified then make sure we don't | ||
338 | * exceed it. If any part of the command would be below the | ||
339 | * limit we allow it. | ||
340 | */ | ||
341 | if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { | ||
342 | if (unlikely | ||
343 | (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { | ||
344 | if (likely(use_locking)) | ||
345 | __cvmx_cmd_queue_unlock(qptr); | ||
346 | return CVMX_CMD_QUEUE_FULL; | ||
347 | } | ||
348 | } | ||
349 | |||
350 | /* | ||
351 | * Normally there is plenty of room in the current buffer for | ||
352 | * the command. | ||
353 | */ | ||
354 | if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) { | ||
355 | uint64_t *ptr = | ||
356 | (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> | ||
357 | base_ptr_div128 << 7); | ||
358 | ptr += qptr->index; | ||
359 | qptr->index += cmd_count; | ||
360 | while (cmd_count--) | ||
361 | *ptr++ = *cmds++; | ||
362 | } else { | ||
363 | uint64_t *ptr; | ||
364 | int count; | ||
365 | /* | ||
366 | * We need a new comamnd buffer. Fail if there isn't | ||
367 | * one available. | ||
368 | */ | ||
369 | uint64_t *new_buffer = | ||
370 | (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); | ||
371 | if (unlikely(new_buffer == NULL)) { | ||
372 | if (likely(use_locking)) | ||
373 | __cvmx_cmd_queue_unlock(qptr); | ||
374 | return CVMX_CMD_QUEUE_NO_MEMORY; | ||
375 | } | ||
376 | ptr = | ||
377 | (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> | ||
378 | base_ptr_div128 << 7); | ||
379 | /* | ||
380 | * Figure out how many command words will fit in this | ||
381 | * buffer. One location will be needed for the next | ||
382 | * buffer pointer. | ||
383 | */ | ||
384 | count = qptr->pool_size_m1 - qptr->index; | ||
385 | ptr += qptr->index; | ||
386 | cmd_count -= count; | ||
387 | while (count--) | ||
388 | *ptr++ = *cmds++; | ||
389 | *ptr = cvmx_ptr_to_phys(new_buffer); | ||
390 | /* | ||
391 | * The current buffer is full and has a link to the | ||
392 | * next buffer. Time to write the rest of the commands | ||
393 | * into the new buffer. | ||
394 | */ | ||
395 | qptr->base_ptr_div128 = *ptr >> 7; | ||
396 | qptr->index = cmd_count; | ||
397 | ptr = new_buffer; | ||
398 | while (cmd_count--) | ||
399 | *ptr++ = *cmds++; | ||
400 | } | ||
401 | |||
402 | /* All updates are complete. Release the lock and return */ | ||
403 | if (likely(use_locking)) | ||
404 | __cvmx_cmd_queue_unlock(qptr); | ||
405 | return CVMX_CMD_QUEUE_SUCCESS; | ||
406 | } | ||
407 | |||
408 | /** | ||
409 | * Simple function to write two command words to a command | ||
410 | * queue. | ||
411 | * | ||
412 | * @queue_id: Hardware command queue to write to | ||
413 | * @use_locking: | ||
414 | * Use internal locking to ensure exclusive access for queue | ||
415 | * updates. If you don't use this locking you must ensure | ||
416 | * exclusivity some other way. Locking is strongly recommended. | ||
417 | * @cmd1: Command | ||
418 | * @cmd2: Command | ||
419 | * | ||
420 | * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code | ||
421 | */ | ||
422 | static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t | ||
423 | queue_id, | ||
424 | int use_locking, | ||
425 | uint64_t cmd1, | ||
426 | uint64_t cmd2) | ||
427 | { | ||
428 | __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); | ||
429 | |||
430 | /* Make sure nobody else is updating the same queue */ | ||
431 | if (likely(use_locking)) | ||
432 | __cvmx_cmd_queue_lock(queue_id, qptr); | ||
433 | |||
434 | /* | ||
435 | * If a max queue length was specified then make sure we don't | ||
436 | * exceed it. If any part of the command would be below the | ||
437 | * limit we allow it. | ||
438 | */ | ||
439 | if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { | ||
440 | if (unlikely | ||
441 | (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { | ||
442 | if (likely(use_locking)) | ||
443 | __cvmx_cmd_queue_unlock(qptr); | ||
444 | return CVMX_CMD_QUEUE_FULL; | ||
445 | } | ||
446 | } | ||
447 | |||
448 | /* | ||
449 | * Normally there is plenty of room in the current buffer for | ||
450 | * the command. | ||
451 | */ | ||
452 | if (likely(qptr->index + 2 < qptr->pool_size_m1)) { | ||
453 | uint64_t *ptr = | ||
454 | (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> | ||
455 | base_ptr_div128 << 7); | ||
456 | ptr += qptr->index; | ||
457 | qptr->index += 2; | ||
458 | ptr[0] = cmd1; | ||
459 | ptr[1] = cmd2; | ||
460 | } else { | ||
461 | uint64_t *ptr; | ||
462 | /* | ||
463 | * Figure out how many command words will fit in this | ||
464 | * buffer. One location will be needed for the next | ||
465 | * buffer pointer. | ||
466 | */ | ||
467 | int count = qptr->pool_size_m1 - qptr->index; | ||
468 | /* | ||
469 | * We need a new comamnd buffer. Fail if there isn't | ||
470 | * one available. | ||
471 | */ | ||
472 | uint64_t *new_buffer = | ||
473 | (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); | ||
474 | if (unlikely(new_buffer == NULL)) { | ||
475 | if (likely(use_locking)) | ||
476 | __cvmx_cmd_queue_unlock(qptr); | ||
477 | return CVMX_CMD_QUEUE_NO_MEMORY; | ||
478 | } | ||
479 | count--; | ||
480 | ptr = | ||
481 | (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> | ||
482 | base_ptr_div128 << 7); | ||
483 | ptr += qptr->index; | ||
484 | *ptr++ = cmd1; | ||
485 | if (likely(count)) | ||
486 | *ptr++ = cmd2; | ||
487 | *ptr = cvmx_ptr_to_phys(new_buffer); | ||
488 | /* | ||
489 | * The current buffer is full and has a link to the | ||
490 | * next buffer. Time to write the rest of the commands | ||
491 | * into the new buffer. | ||
492 | */ | ||
493 | qptr->base_ptr_div128 = *ptr >> 7; | ||
494 | qptr->index = 0; | ||
495 | if (unlikely(count == 0)) { | ||
496 | qptr->index = 1; | ||
497 | new_buffer[0] = cmd2; | ||
498 | } | ||
499 | } | ||
500 | |||
501 | /* All updates are complete. Release the lock and return */ | ||
502 | if (likely(use_locking)) | ||
503 | __cvmx_cmd_queue_unlock(qptr); | ||
504 | return CVMX_CMD_QUEUE_SUCCESS; | ||
505 | } | ||
506 | |||
507 | /** | ||
508 | * Simple function to write three command words to a command | ||
509 | * queue. | ||
510 | * | ||
511 | * @queue_id: Hardware command queue to write to | ||
512 | * @use_locking: | ||
513 | * Use internal locking to ensure exclusive access for queue | ||
514 | * updates. If you don't use this locking you must ensure | ||
515 | * exclusivity some other way. Locking is strongly recommended. | ||
516 | * @cmd1: Command | ||
517 | * @cmd2: Command | ||
518 | * @cmd3: Command | ||
519 | * | ||
520 | * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code | ||
521 | */ | ||
522 | static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t | ||
523 | queue_id, | ||
524 | int use_locking, | ||
525 | uint64_t cmd1, | ||
526 | uint64_t cmd2, | ||
527 | uint64_t cmd3) | ||
528 | { | ||
529 | __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); | ||
530 | |||
531 | /* Make sure nobody else is updating the same queue */ | ||
532 | if (likely(use_locking)) | ||
533 | __cvmx_cmd_queue_lock(queue_id, qptr); | ||
534 | |||
535 | /* | ||
536 | * If a max queue length was specified then make sure we don't | ||
537 | * exceed it. If any part of the command would be below the | ||
538 | * limit we allow it. | ||
539 | */ | ||
540 | if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { | ||
541 | if (unlikely | ||
542 | (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { | ||
543 | if (likely(use_locking)) | ||
544 | __cvmx_cmd_queue_unlock(qptr); | ||
545 | return CVMX_CMD_QUEUE_FULL; | ||
546 | } | ||
547 | } | ||
548 | |||
549 | /* | ||
550 | * Normally there is plenty of room in the current buffer for | ||
551 | * the command. | ||
552 | */ | ||
553 | if (likely(qptr->index + 3 < qptr->pool_size_m1)) { | ||
554 | uint64_t *ptr = | ||
555 | (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> | ||
556 | base_ptr_div128 << 7); | ||
557 | ptr += qptr->index; | ||
558 | qptr->index += 3; | ||
559 | ptr[0] = cmd1; | ||
560 | ptr[1] = cmd2; | ||
561 | ptr[2] = cmd3; | ||
562 | } else { | ||
563 | uint64_t *ptr; | ||
564 | /* | ||
565 | * Figure out how many command words will fit in this | ||
566 | * buffer. One location will be needed for the next | ||
567 | * buffer pointer | ||
568 | */ | ||
569 | int count = qptr->pool_size_m1 - qptr->index; | ||
570 | /* | ||
571 | * We need a new comamnd buffer. Fail if there isn't | ||
572 | * one available | ||
573 | */ | ||
574 | uint64_t *new_buffer = | ||
575 | (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); | ||
576 | if (unlikely(new_buffer == NULL)) { | ||
577 | if (likely(use_locking)) | ||
578 | __cvmx_cmd_queue_unlock(qptr); | ||
579 | return CVMX_CMD_QUEUE_NO_MEMORY; | ||
580 | } | ||
581 | count--; | ||
582 | ptr = | ||
583 | (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> | ||
584 | base_ptr_div128 << 7); | ||
585 | ptr += qptr->index; | ||
586 | *ptr++ = cmd1; | ||
587 | if (count) { | ||
588 | *ptr++ = cmd2; | ||
589 | if (count > 1) | ||
590 | *ptr++ = cmd3; | ||
591 | } | ||
592 | *ptr = cvmx_ptr_to_phys(new_buffer); | ||
593 | /* | ||
594 | * The current buffer is full and has a link to the | ||
595 | * next buffer. Time to write the rest of the commands | ||
596 | * into the new buffer. | ||
597 | */ | ||
598 | qptr->base_ptr_div128 = *ptr >> 7; | ||
599 | qptr->index = 0; | ||
600 | ptr = new_buffer; | ||
601 | if (count == 0) { | ||
602 | *ptr++ = cmd2; | ||
603 | qptr->index++; | ||
604 | } | ||
605 | if (count < 2) { | ||
606 | *ptr++ = cmd3; | ||
607 | qptr->index++; | ||
608 | } | ||
609 | } | ||
610 | |||
611 | /* All updates are complete. Release the lock and return */ | ||
612 | if (likely(use_locking)) | ||
613 | __cvmx_cmd_queue_unlock(qptr); | ||
614 | return CVMX_CMD_QUEUE_SUCCESS; | ||
615 | } | ||
616 | |||
617 | #endif /* __CVMX_CMD_QUEUE_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-config.h b/drivers/staging/octeon/cvmx-config.h new file mode 100644 index 000000000000..078a520481cf --- /dev/null +++ b/drivers/staging/octeon/cvmx-config.h | |||
@@ -0,0 +1,169 @@ | |||
1 | #ifndef __CVMX_CONFIG_H__ | ||
2 | #define __CVMX_CONFIG_H__ | ||
3 | |||
4 | /************************* Config Specific Defines ************************/ | ||
5 | #define CVMX_LLM_NUM_PORTS 1 | ||
6 | #define CVMX_NULL_POINTER_PROTECT 1 | ||
7 | #define CVMX_ENABLE_DEBUG_PRINTS 1 | ||
8 | /* PKO queues per port for interface 0 (ports 0-15) */ | ||
9 | #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 | ||
10 | /* PKO queues per port for interface 1 (ports 16-31) */ | ||
11 | #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 | ||
12 | /* Limit on the number of PKO ports enabled for interface 0 */ | ||
13 | #define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 | ||
14 | /* Limit on the number of PKO ports enabled for interface 1 */ | ||
15 | #define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 | ||
16 | /* PKO queues per port for PCI (ports 32-35) */ | ||
17 | #define CVMX_PKO_QUEUES_PER_PORT_PCI 1 | ||
18 | /* PKO queues per port for Loop devices (ports 36-39) */ | ||
19 | #define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 | ||
20 | |||
21 | /************************* FPA allocation *********************************/ | ||
22 | /* Pool sizes in bytes, must be multiple of a cache line */ | ||
23 | #define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE) | ||
24 | #define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE) | ||
25 | #define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE) | ||
26 | #define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE) | ||
27 | #define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE) | ||
28 | #define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE) | ||
29 | #define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE) | ||
30 | #define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE) | ||
31 | |||
32 | /* Pools in use */ | ||
33 | /* Packet buffers */ | ||
34 | #define CVMX_FPA_PACKET_POOL (0) | ||
35 | #define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE | ||
36 | /* Work queue entrys */ | ||
37 | #define CVMX_FPA_WQE_POOL (1) | ||
38 | #define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE | ||
39 | /* PKO queue command buffers */ | ||
40 | #define CVMX_FPA_OUTPUT_BUFFER_POOL (2) | ||
41 | #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE | ||
42 | |||
43 | /************************* FAU allocation ********************************/ | ||
44 | /* The fetch and add registers are allocated here. They are arranged | ||
45 | * in order of descending size so that all alignment constraints are | ||
46 | * automatically met. The enums are linked so that the following enum | ||
47 | * continues allocating where the previous one left off, so the | ||
48 | * numbering within each enum always starts with zero. The macros | ||
49 | * take care of the address increment size, so the values entered | ||
50 | * always increase by 1. FAU registers are accessed with byte | ||
51 | * addresses. | ||
52 | */ | ||
53 | |||
54 | #define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START) | ||
55 | typedef enum { | ||
56 | CVMX_FAU_REG_64_START = 0, | ||
57 | CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0), | ||
58 | } cvmx_fau_reg_64_t; | ||
59 | |||
60 | #define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START) | ||
61 | typedef enum { | ||
62 | CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END, | ||
63 | CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0), | ||
64 | } cvmx_fau_reg_32_t; | ||
65 | |||
66 | #define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START) | ||
67 | typedef enum { | ||
68 | CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END, | ||
69 | CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0), | ||
70 | } cvmx_fau_reg_16_t; | ||
71 | |||
72 | #define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START) | ||
73 | typedef enum { | ||
74 | CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END, | ||
75 | CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0), | ||
76 | } cvmx_fau_reg_8_t; | ||
77 | |||
78 | /* | ||
79 | * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first | ||
80 | * available FAU address that is not allocated in cvmx-config.h. This | ||
81 | * is 64 bit aligned. | ||
82 | */ | ||
83 | #define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL)) | ||
84 | #define CVMX_FAU_REG_END (2048) | ||
85 | |||
86 | /********************** scratch memory allocation *************************/ | ||
87 | /* Scratchpad memory allocation. Note that these are byte memory | ||
88 | * addresses. Some uses of scratchpad (IOBDMA for example) require | ||
89 | * the use of 8-byte aligned addresses, so proper alignment needs to | ||
90 | * be taken into account. | ||
91 | */ | ||
92 | /* Generic scratch iobdma area */ | ||
93 | #define CVMX_SCR_SCRATCH (0) | ||
94 | /* First location available after cvmx-config.h allocated region. */ | ||
95 | #define CVMX_SCR_REG_AVAIL_BASE (8) | ||
96 | |||
97 | /* | ||
98 | * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve | ||
99 | * before the beginning of the packet. If necessary, override the | ||
100 | * default here. See the IPD section of the hardware manual for MBUFF | ||
101 | * SKIP details. | ||
102 | */ | ||
103 | #define CVMX_HELPER_FIRST_MBUFF_SKIP 184 | ||
104 | |||
105 | /* | ||
106 | * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve | ||
107 | * in each chained packet element. If necessary, override the default | ||
108 | * here. | ||
109 | */ | ||
110 | #define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0 | ||
111 | |||
112 | /* | ||
113 | * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is | ||
114 | * enabled for all input ports. This controls if IPD sends | ||
115 | * backpressure to all ports if Octeon's FPA pools don't have enough | ||
116 | * packet or work queue entries. Even when this is off, it is still | ||
117 | * possible to get backpressure from individual hardware ports. When | ||
118 | * configuring backpressure, also check | ||
119 | * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override | ||
120 | * the default here. | ||
121 | */ | ||
122 | #define CVMX_HELPER_ENABLE_BACK_PRESSURE 1 | ||
123 | |||
124 | /* | ||
125 | * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper | ||
126 | * function. Once it is enabled the hardware starts accepting | ||
127 | * packets. You might want to skip the IPD enable if configuration | ||
128 | * changes are need from the default helper setup. If necessary, | ||
129 | * override the default here. | ||
130 | */ | ||
131 | #define CVMX_HELPER_ENABLE_IPD 0 | ||
132 | |||
133 | /* | ||
134 | * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns | ||
135 | * to incoming packets. | ||
136 | */ | ||
137 | #define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED | ||
138 | |||
139 | #define CVMX_ENABLE_PARAMETER_CHECKING 0 | ||
140 | |||
141 | /* | ||
142 | * The following select which fields are used by the PIP to generate | ||
143 | * the tag on INPUT | ||
144 | * 0: don't include | ||
145 | * 1: include | ||
146 | */ | ||
147 | #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0 | ||
148 | #define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 | ||
149 | #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 | ||
150 | #define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 | ||
151 | #define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 | ||
152 | #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0 | ||
153 | #define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 | ||
154 | #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 | ||
155 | #define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 | ||
156 | #define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0 | ||
157 | #define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1 | ||
158 | |||
159 | /* Select skip mode for input ports */ | ||
160 | #define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2 | ||
161 | |||
162 | /* | ||
163 | * Force backpressure to be disabled. This overrides all other | ||
164 | * backpressure configuration. | ||
165 | */ | ||
166 | #define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0 | ||
167 | |||
168 | #endif /* __CVMX_CONFIG_H__ */ | ||
169 | |||
diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/drivers/staging/octeon/cvmx-dbg-defs.h new file mode 100644 index 000000000000..abbf42d05e5a --- /dev/null +++ b/drivers/staging/octeon/cvmx-dbg-defs.h | |||
@@ -0,0 +1,72 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_DBG_DEFS_H__ | ||
29 | #define __CVMX_DBG_DEFS_H__ | ||
30 | |||
31 | #define CVMX_DBG_DATA \ | ||
32 | CVMX_ADD_IO_SEG(0x00011F00000001E8ull) | ||
33 | |||
34 | union cvmx_dbg_data { | ||
35 | uint64_t u64; | ||
36 | struct cvmx_dbg_data_s { | ||
37 | uint64_t reserved_23_63:41; | ||
38 | uint64_t c_mul:5; | ||
39 | uint64_t dsel_ext:1; | ||
40 | uint64_t data:17; | ||
41 | } s; | ||
42 | struct cvmx_dbg_data_cn30xx { | ||
43 | uint64_t reserved_31_63:33; | ||
44 | uint64_t pll_mul:3; | ||
45 | uint64_t reserved_23_27:5; | ||
46 | uint64_t c_mul:5; | ||
47 | uint64_t dsel_ext:1; | ||
48 | uint64_t data:17; | ||
49 | } cn30xx; | ||
50 | struct cvmx_dbg_data_cn30xx cn31xx; | ||
51 | struct cvmx_dbg_data_cn38xx { | ||
52 | uint64_t reserved_29_63:35; | ||
53 | uint64_t d_mul:4; | ||
54 | uint64_t dclk_mul2:1; | ||
55 | uint64_t cclk_div2:1; | ||
56 | uint64_t c_mul:5; | ||
57 | uint64_t dsel_ext:1; | ||
58 | uint64_t data:17; | ||
59 | } cn38xx; | ||
60 | struct cvmx_dbg_data_cn38xx cn38xxp2; | ||
61 | struct cvmx_dbg_data_cn30xx cn50xx; | ||
62 | struct cvmx_dbg_data_cn58xx { | ||
63 | uint64_t reserved_29_63:35; | ||
64 | uint64_t rem:6; | ||
65 | uint64_t c_mul:5; | ||
66 | uint64_t dsel_ext:1; | ||
67 | uint64_t data:17; | ||
68 | } cn58xx; | ||
69 | struct cvmx_dbg_data_cn58xx cn58xxp1; | ||
70 | }; | ||
71 | |||
72 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-fau.h b/drivers/staging/octeon/cvmx-fau.h new file mode 100644 index 000000000000..29bdce66cdf8 --- /dev/null +++ b/drivers/staging/octeon/cvmx-fau.h | |||
@@ -0,0 +1,597 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Interface to the hardware Fetch and Add Unit. | ||
30 | */ | ||
31 | |||
32 | #ifndef __CVMX_FAU_H__ | ||
33 | #define __CVMX_FAU_H__ | ||
34 | |||
35 | /* | ||
36 | * Octeon Fetch and Add Unit (FAU) | ||
37 | */ | ||
38 | |||
39 | #define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0) | ||
40 | #define CVMX_FAU_BITS_SCRADDR 63, 56 | ||
41 | #define CVMX_FAU_BITS_LEN 55, 48 | ||
42 | #define CVMX_FAU_BITS_INEVAL 35, 14 | ||
43 | #define CVMX_FAU_BITS_TAGWAIT 13, 13 | ||
44 | #define CVMX_FAU_BITS_NOADD 13, 13 | ||
45 | #define CVMX_FAU_BITS_SIZE 12, 11 | ||
46 | #define CVMX_FAU_BITS_REGISTER 10, 0 | ||
47 | |||
48 | typedef enum { | ||
49 | CVMX_FAU_OP_SIZE_8 = 0, | ||
50 | CVMX_FAU_OP_SIZE_16 = 1, | ||
51 | CVMX_FAU_OP_SIZE_32 = 2, | ||
52 | CVMX_FAU_OP_SIZE_64 = 3 | ||
53 | } cvmx_fau_op_size_t; | ||
54 | |||
55 | /** | ||
56 | * Tagwait return definition. If a timeout occurs, the error | ||
57 | * bit will be set. Otherwise the value of the register before | ||
58 | * the update will be returned. | ||
59 | */ | ||
60 | typedef struct { | ||
61 | uint64_t error:1; | ||
62 | int64_t value:63; | ||
63 | } cvmx_fau_tagwait64_t; | ||
64 | |||
65 | /** | ||
66 | * Tagwait return definition. If a timeout occurs, the error | ||
67 | * bit will be set. Otherwise the value of the register before | ||
68 | * the update will be returned. | ||
69 | */ | ||
70 | typedef struct { | ||
71 | uint64_t error:1; | ||
72 | int32_t value:31; | ||
73 | } cvmx_fau_tagwait32_t; | ||
74 | |||
75 | /** | ||
76 | * Tagwait return definition. If a timeout occurs, the error | ||
77 | * bit will be set. Otherwise the value of the register before | ||
78 | * the update will be returned. | ||
79 | */ | ||
80 | typedef struct { | ||
81 | uint64_t error:1; | ||
82 | int16_t value:15; | ||
83 | } cvmx_fau_tagwait16_t; | ||
84 | |||
85 | /** | ||
86 | * Tagwait return definition. If a timeout occurs, the error | ||
87 | * bit will be set. Otherwise the value of the register before | ||
88 | * the update will be returned. | ||
89 | */ | ||
90 | typedef struct { | ||
91 | uint64_t error:1; | ||
92 | int8_t value:7; | ||
93 | } cvmx_fau_tagwait8_t; | ||
94 | |||
95 | /** | ||
96 | * Asynchronous tagwait return definition. If a timeout occurs, | ||
97 | * the error bit will be set. Otherwise the value of the | ||
98 | * register before the update will be returned. | ||
99 | */ | ||
100 | typedef union { | ||
101 | uint64_t u64; | ||
102 | struct { | ||
103 | uint64_t invalid:1; | ||
104 | uint64_t data:63; /* unpredictable if invalid is set */ | ||
105 | } s; | ||
106 | } cvmx_fau_async_tagwait_result_t; | ||
107 | |||
108 | /** | ||
109 | * Builds a store I/O address for writing to the FAU | ||
110 | * | ||
111 | * @noadd: 0 = Store value is atomically added to the current value | ||
112 | * 1 = Store value is atomically written over the current value | ||
113 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
114 | * - Step by 2 for 16 bit access. | ||
115 | * - Step by 4 for 32 bit access. | ||
116 | * - Step by 8 for 64 bit access. | ||
117 | * Returns Address to store for atomic update | ||
118 | */ | ||
119 | static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) | ||
120 | { | ||
121 | return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | | ||
122 | cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) | | ||
123 | cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); | ||
124 | } | ||
125 | |||
126 | /** | ||
127 | * Builds a I/O address for accessing the FAU | ||
128 | * | ||
129 | * @tagwait: Should the atomic add wait for the current tag switch | ||
130 | * operation to complete. | ||
131 | * - 0 = Don't wait | ||
132 | * - 1 = Wait for tag switch to complete | ||
133 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
134 | * - Step by 2 for 16 bit access. | ||
135 | * - Step by 4 for 32 bit access. | ||
136 | * - Step by 8 for 64 bit access. | ||
137 | * @value: Signed value to add. | ||
138 | * Note: When performing 32 and 64 bit access, only the low | ||
139 | * 22 bits are available. | ||
140 | * Returns Address to read from for atomic update | ||
141 | */ | ||
142 | static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, | ||
143 | int64_t value) | ||
144 | { | ||
145 | return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | | ||
146 | cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | | ||
147 | cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | | ||
148 | cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); | ||
149 | } | ||
150 | |||
151 | /** | ||
152 | * Perform an atomic 64 bit add | ||
153 | * | ||
154 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
155 | * - Step by 8 for 64 bit access. | ||
156 | * @value: Signed value to add. | ||
157 | * Note: Only the low 22 bits are available. | ||
158 | * Returns Value of the register before the update | ||
159 | */ | ||
160 | static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, | ||
161 | int64_t value) | ||
162 | { | ||
163 | return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); | ||
164 | } | ||
165 | |||
166 | /** | ||
167 | * Perform an atomic 32 bit add | ||
168 | * | ||
169 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
170 | * - Step by 4 for 32 bit access. | ||
171 | * @value: Signed value to add. | ||
172 | * Note: Only the low 22 bits are available. | ||
173 | * Returns Value of the register before the update | ||
174 | */ | ||
175 | static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, | ||
176 | int32_t value) | ||
177 | { | ||
178 | return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); | ||
179 | } | ||
180 | |||
181 | /** | ||
182 | * Perform an atomic 16 bit add | ||
183 | * | ||
184 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
185 | * - Step by 2 for 16 bit access. | ||
186 | * @value: Signed value to add. | ||
187 | * Returns Value of the register before the update | ||
188 | */ | ||
189 | static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, | ||
190 | int16_t value) | ||
191 | { | ||
192 | return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); | ||
193 | } | ||
194 | |||
195 | /** | ||
196 | * Perform an atomic 8 bit add | ||
197 | * | ||
198 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
199 | * @value: Signed value to add. | ||
200 | * Returns Value of the register before the update | ||
201 | */ | ||
202 | static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) | ||
203 | { | ||
204 | return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); | ||
205 | } | ||
206 | |||
207 | /** | ||
208 | * Perform an atomic 64 bit add after the current tag switch | ||
209 | * completes | ||
210 | * | ||
211 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
212 | * - Step by 8 for 64 bit access. | ||
213 | * @value: Signed value to add. | ||
214 | * Note: Only the low 22 bits are available. | ||
215 | * Returns If a timeout occurs, the error bit will be set. Otherwise | ||
216 | * the value of the register before the update will be | ||
217 | * returned | ||
218 | */ | ||
219 | static inline cvmx_fau_tagwait64_t | ||
220 | cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) | ||
221 | { | ||
222 | union { | ||
223 | uint64_t i64; | ||
224 | cvmx_fau_tagwait64_t t; | ||
225 | } result; | ||
226 | result.i64 = | ||
227 | cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); | ||
228 | return result.t; | ||
229 | } | ||
230 | |||
231 | /** | ||
232 | * Perform an atomic 32 bit add after the current tag switch | ||
233 | * completes | ||
234 | * | ||
235 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
236 | * - Step by 4 for 32 bit access. | ||
237 | * @value: Signed value to add. | ||
238 | * Note: Only the low 22 bits are available. | ||
239 | * Returns If a timeout occurs, the error bit will be set. Otherwise | ||
240 | * the value of the register before the update will be | ||
241 | * returned | ||
242 | */ | ||
243 | static inline cvmx_fau_tagwait32_t | ||
244 | cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) | ||
245 | { | ||
246 | union { | ||
247 | uint64_t i32; | ||
248 | cvmx_fau_tagwait32_t t; | ||
249 | } result; | ||
250 | result.i32 = | ||
251 | cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); | ||
252 | return result.t; | ||
253 | } | ||
254 | |||
255 | /** | ||
256 | * Perform an atomic 16 bit add after the current tag switch | ||
257 | * completes | ||
258 | * | ||
259 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
260 | * - Step by 2 for 16 bit access. | ||
261 | * @value: Signed value to add. | ||
262 | * Returns If a timeout occurs, the error bit will be set. Otherwise | ||
263 | * the value of the register before the update will be | ||
264 | * returned | ||
265 | */ | ||
266 | static inline cvmx_fau_tagwait16_t | ||
267 | cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) | ||
268 | { | ||
269 | union { | ||
270 | uint64_t i16; | ||
271 | cvmx_fau_tagwait16_t t; | ||
272 | } result; | ||
273 | result.i16 = | ||
274 | cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); | ||
275 | return result.t; | ||
276 | } | ||
277 | |||
278 | /** | ||
279 | * Perform an atomic 8 bit add after the current tag switch | ||
280 | * completes | ||
281 | * | ||
282 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
283 | * @value: Signed value to add. | ||
284 | * Returns If a timeout occurs, the error bit will be set. Otherwise | ||
285 | * the value of the register before the update will be | ||
286 | * returned | ||
287 | */ | ||
288 | static inline cvmx_fau_tagwait8_t | ||
289 | cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) | ||
290 | { | ||
291 | union { | ||
292 | uint64_t i8; | ||
293 | cvmx_fau_tagwait8_t t; | ||
294 | } result; | ||
295 | result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); | ||
296 | return result.t; | ||
297 | } | ||
298 | |||
299 | /** | ||
300 | * Builds I/O data for async operations | ||
301 | * | ||
302 | * @scraddr: Scratch pad byte addres to write to. Must be 8 byte aligned | ||
303 | * @value: Signed value to add. | ||
304 | * Note: When performing 32 and 64 bit access, only the low | ||
305 | * 22 bits are available. | ||
306 | * @tagwait: Should the atomic add wait for the current tag switch | ||
307 | * operation to complete. | ||
308 | * - 0 = Don't wait | ||
309 | * - 1 = Wait for tag switch to complete | ||
310 | * @size: The size of the operation: | ||
311 | * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits | ||
312 | * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits | ||
313 | * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits | ||
314 | * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits | ||
315 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
316 | * - Step by 2 for 16 bit access. | ||
317 | * - Step by 4 for 32 bit access. | ||
318 | * - Step by 8 for 64 bit access. | ||
319 | * Returns Data to write using cvmx_send_single | ||
320 | */ | ||
321 | static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, | ||
322 | uint64_t tagwait, | ||
323 | cvmx_fau_op_size_t size, | ||
324 | uint64_t reg) | ||
325 | { | ||
326 | return CVMX_FAU_LOAD_IO_ADDRESS | | ||
327 | cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) | | ||
328 | cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) | | ||
329 | cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | | ||
330 | cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | | ||
331 | cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) | | ||
332 | cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); | ||
333 | } | ||
334 | |||
335 | /** | ||
336 | * Perform an async atomic 64 bit add. The old value is | ||
337 | * placed in the scratch memory at byte address scraddr. | ||
338 | * | ||
339 | * @scraddr: Scratch memory byte address to put response in. | ||
340 | * Must be 8 byte aligned. | ||
341 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
342 | * - Step by 8 for 64 bit access. | ||
343 | * @value: Signed value to add. | ||
344 | * Note: Only the low 22 bits are available. | ||
345 | * Returns Placed in the scratch pad register | ||
346 | */ | ||
347 | static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, | ||
348 | cvmx_fau_reg_64_t reg, | ||
349 | int64_t value) | ||
350 | { | ||
351 | cvmx_send_single(__cvmx_fau_iobdma_data | ||
352 | (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg)); | ||
353 | } | ||
354 | |||
355 | /** | ||
356 | * Perform an async atomic 32 bit add. The old value is | ||
357 | * placed in the scratch memory at byte address scraddr. | ||
358 | * | ||
359 | * @scraddr: Scratch memory byte address to put response in. | ||
360 | * Must be 8 byte aligned. | ||
361 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
362 | * - Step by 4 for 32 bit access. | ||
363 | * @value: Signed value to add. | ||
364 | * Note: Only the low 22 bits are available. | ||
365 | * Returns Placed in the scratch pad register | ||
366 | */ | ||
367 | static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, | ||
368 | cvmx_fau_reg_32_t reg, | ||
369 | int32_t value) | ||
370 | { | ||
371 | cvmx_send_single(__cvmx_fau_iobdma_data | ||
372 | (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg)); | ||
373 | } | ||
374 | |||
375 | /** | ||
376 | * Perform an async atomic 16 bit add. The old value is | ||
377 | * placed in the scratch memory at byte address scraddr. | ||
378 | * | ||
379 | * @scraddr: Scratch memory byte address to put response in. | ||
380 | * Must be 8 byte aligned. | ||
381 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
382 | * - Step by 2 for 16 bit access. | ||
383 | * @value: Signed value to add. | ||
384 | * Returns Placed in the scratch pad register | ||
385 | */ | ||
386 | static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, | ||
387 | cvmx_fau_reg_16_t reg, | ||
388 | int16_t value) | ||
389 | { | ||
390 | cvmx_send_single(__cvmx_fau_iobdma_data | ||
391 | (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg)); | ||
392 | } | ||
393 | |||
394 | /** | ||
395 | * Perform an async atomic 8 bit add. The old value is | ||
396 | * placed in the scratch memory at byte address scraddr. | ||
397 | * | ||
398 | * @scraddr: Scratch memory byte address to put response in. | ||
399 | * Must be 8 byte aligned. | ||
400 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
401 | * @value: Signed value to add. | ||
402 | * Returns Placed in the scratch pad register | ||
403 | */ | ||
404 | static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, | ||
405 | cvmx_fau_reg_8_t reg, | ||
406 | int8_t value) | ||
407 | { | ||
408 | cvmx_send_single(__cvmx_fau_iobdma_data | ||
409 | (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg)); | ||
410 | } | ||
411 | |||
412 | /** | ||
413 | * Perform an async atomic 64 bit add after the current tag | ||
414 | * switch completes. | ||
415 | * | ||
416 | * @scraddr: Scratch memory byte address to put response in. Must be | ||
417 | * 8 byte aligned. If a timeout occurs, the error bit (63) | ||
418 | * will be set. Otherwise the value of the register before | ||
419 | * the update will be returned | ||
420 | * | ||
421 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
422 | * - Step by 8 for 64 bit access. | ||
423 | * @value: Signed value to add. | ||
424 | * Note: Only the low 22 bits are available. | ||
425 | * Returns Placed in the scratch pad register | ||
426 | */ | ||
427 | static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, | ||
428 | cvmx_fau_reg_64_t reg, | ||
429 | int64_t value) | ||
430 | { | ||
431 | cvmx_send_single(__cvmx_fau_iobdma_data | ||
432 | (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); | ||
433 | } | ||
434 | |||
435 | /** | ||
436 | * Perform an async atomic 32 bit add after the current tag | ||
437 | * switch completes. | ||
438 | * | ||
439 | * @scraddr: Scratch memory byte address to put response in. Must be | ||
440 | * 8 byte aligned. If a timeout occurs, the error bit (63) | ||
441 | * will be set. Otherwise the value of the register before | ||
442 | * the update will be returned | ||
443 | * | ||
444 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
445 | * - Step by 4 for 32 bit access. | ||
446 | * @value: Signed value to add. | ||
447 | * Note: Only the low 22 bits are available. | ||
448 | * Returns Placed in the scratch pad register | ||
449 | */ | ||
450 | static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, | ||
451 | cvmx_fau_reg_32_t reg, | ||
452 | int32_t value) | ||
453 | { | ||
454 | cvmx_send_single(__cvmx_fau_iobdma_data | ||
455 | (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); | ||
456 | } | ||
457 | |||
458 | /** | ||
459 | * Perform an async atomic 16 bit add after the current tag | ||
460 | * switch completes. | ||
461 | * | ||
462 | * @scraddr: Scratch memory byte address to put response in. Must be | ||
463 | * 8 byte aligned. If a timeout occurs, the error bit (63) | ||
464 | * will be set. Otherwise the value of the register before | ||
465 | * the update will be returned | ||
466 | * | ||
467 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
468 | * - Step by 2 for 16 bit access. | ||
469 | * @value: Signed value to add. | ||
470 | * | ||
471 | * Returns Placed in the scratch pad register | ||
472 | */ | ||
473 | static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, | ||
474 | cvmx_fau_reg_16_t reg, | ||
475 | int16_t value) | ||
476 | { | ||
477 | cvmx_send_single(__cvmx_fau_iobdma_data | ||
478 | (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); | ||
479 | } | ||
480 | |||
481 | /** | ||
482 | * Perform an async atomic 8 bit add after the current tag | ||
483 | * switch completes. | ||
484 | * | ||
485 | * @scraddr: Scratch memory byte address to put response in. Must be | ||
486 | * 8 byte aligned. If a timeout occurs, the error bit (63) | ||
487 | * will be set. Otherwise the value of the register before | ||
488 | * the update will be returned | ||
489 | * | ||
490 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
491 | * @value: Signed value to add. | ||
492 | * | ||
493 | * Returns Placed in the scratch pad register | ||
494 | */ | ||
495 | static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, | ||
496 | cvmx_fau_reg_8_t reg, | ||
497 | int8_t value) | ||
498 | { | ||
499 | cvmx_send_single(__cvmx_fau_iobdma_data | ||
500 | (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); | ||
501 | } | ||
502 | |||
503 | /** | ||
504 | * Perform an atomic 64 bit add | ||
505 | * | ||
506 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
507 | * - Step by 8 for 64 bit access. | ||
508 | * @value: Signed value to add. | ||
509 | */ | ||
510 | static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) | ||
511 | { | ||
512 | cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value); | ||
513 | } | ||
514 | |||
515 | /** | ||
516 | * Perform an atomic 32 bit add | ||
517 | * | ||
518 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
519 | * - Step by 4 for 32 bit access. | ||
520 | * @value: Signed value to add. | ||
521 | */ | ||
522 | static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) | ||
523 | { | ||
524 | cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); | ||
525 | } | ||
526 | |||
527 | /** | ||
528 | * Perform an atomic 16 bit add | ||
529 | * | ||
530 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
531 | * - Step by 2 for 16 bit access. | ||
532 | * @value: Signed value to add. | ||
533 | */ | ||
534 | static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) | ||
535 | { | ||
536 | cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); | ||
537 | } | ||
538 | |||
539 | /** | ||
540 | * Perform an atomic 8 bit add | ||
541 | * | ||
542 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
543 | * @value: Signed value to add. | ||
544 | */ | ||
545 | static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) | ||
546 | { | ||
547 | cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); | ||
548 | } | ||
549 | |||
550 | /** | ||
551 | * Perform an atomic 64 bit write | ||
552 | * | ||
553 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
554 | * - Step by 8 for 64 bit access. | ||
555 | * @value: Signed value to write. | ||
556 | */ | ||
557 | static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) | ||
558 | { | ||
559 | cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); | ||
560 | } | ||
561 | |||
562 | /** | ||
563 | * Perform an atomic 32 bit write | ||
564 | * | ||
565 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
566 | * - Step by 4 for 32 bit access. | ||
567 | * @value: Signed value to write. | ||
568 | */ | ||
569 | static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) | ||
570 | { | ||
571 | cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); | ||
572 | } | ||
573 | |||
574 | /** | ||
575 | * Perform an atomic 16 bit write | ||
576 | * | ||
577 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
578 | * - Step by 2 for 16 bit access. | ||
579 | * @value: Signed value to write. | ||
580 | */ | ||
581 | static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) | ||
582 | { | ||
583 | cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); | ||
584 | } | ||
585 | |||
586 | /** | ||
587 | * Perform an atomic 8 bit write | ||
588 | * | ||
589 | * @reg: FAU atomic register to access. 0 <= reg < 2048. | ||
590 | * @value: Signed value to write. | ||
591 | */ | ||
592 | static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) | ||
593 | { | ||
594 | cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); | ||
595 | } | ||
596 | |||
597 | #endif /* __CVMX_FAU_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/drivers/staging/octeon/cvmx-fpa-defs.h new file mode 100644 index 000000000000..bf5546b90110 --- /dev/null +++ b/drivers/staging/octeon/cvmx-fpa-defs.h | |||
@@ -0,0 +1,403 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_FPA_DEFS_H__ | ||
29 | #define __CVMX_FPA_DEFS_H__ | ||
30 | |||
31 | #define CVMX_FPA_BIST_STATUS \ | ||
32 | CVMX_ADD_IO_SEG(0x00011800280000E8ull) | ||
33 | #define CVMX_FPA_CTL_STATUS \ | ||
34 | CVMX_ADD_IO_SEG(0x0001180028000050ull) | ||
35 | #define CVMX_FPA_FPF0_MARKS \ | ||
36 | CVMX_ADD_IO_SEG(0x0001180028000000ull) | ||
37 | #define CVMX_FPA_FPF0_SIZE \ | ||
38 | CVMX_ADD_IO_SEG(0x0001180028000058ull) | ||
39 | #define CVMX_FPA_FPF1_MARKS \ | ||
40 | CVMX_ADD_IO_SEG(0x0001180028000008ull) | ||
41 | #define CVMX_FPA_FPF2_MARKS \ | ||
42 | CVMX_ADD_IO_SEG(0x0001180028000010ull) | ||
43 | #define CVMX_FPA_FPF3_MARKS \ | ||
44 | CVMX_ADD_IO_SEG(0x0001180028000018ull) | ||
45 | #define CVMX_FPA_FPF4_MARKS \ | ||
46 | CVMX_ADD_IO_SEG(0x0001180028000020ull) | ||
47 | #define CVMX_FPA_FPF5_MARKS \ | ||
48 | CVMX_ADD_IO_SEG(0x0001180028000028ull) | ||
49 | #define CVMX_FPA_FPF6_MARKS \ | ||
50 | CVMX_ADD_IO_SEG(0x0001180028000030ull) | ||
51 | #define CVMX_FPA_FPF7_MARKS \ | ||
52 | CVMX_ADD_IO_SEG(0x0001180028000038ull) | ||
53 | #define CVMX_FPA_FPFX_MARKS(offset) \ | ||
54 | CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1) | ||
55 | #define CVMX_FPA_FPFX_SIZE(offset) \ | ||
56 | CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1) | ||
57 | #define CVMX_FPA_INT_ENB \ | ||
58 | CVMX_ADD_IO_SEG(0x0001180028000048ull) | ||
59 | #define CVMX_FPA_INT_SUM \ | ||
60 | CVMX_ADD_IO_SEG(0x0001180028000040ull) | ||
61 | #define CVMX_FPA_QUE0_PAGE_INDEX \ | ||
62 | CVMX_ADD_IO_SEG(0x00011800280000F0ull) | ||
63 | #define CVMX_FPA_QUE1_PAGE_INDEX \ | ||
64 | CVMX_ADD_IO_SEG(0x00011800280000F8ull) | ||
65 | #define CVMX_FPA_QUE2_PAGE_INDEX \ | ||
66 | CVMX_ADD_IO_SEG(0x0001180028000100ull) | ||
67 | #define CVMX_FPA_QUE3_PAGE_INDEX \ | ||
68 | CVMX_ADD_IO_SEG(0x0001180028000108ull) | ||
69 | #define CVMX_FPA_QUE4_PAGE_INDEX \ | ||
70 | CVMX_ADD_IO_SEG(0x0001180028000110ull) | ||
71 | #define CVMX_FPA_QUE5_PAGE_INDEX \ | ||
72 | CVMX_ADD_IO_SEG(0x0001180028000118ull) | ||
73 | #define CVMX_FPA_QUE6_PAGE_INDEX \ | ||
74 | CVMX_ADD_IO_SEG(0x0001180028000120ull) | ||
75 | #define CVMX_FPA_QUE7_PAGE_INDEX \ | ||
76 | CVMX_ADD_IO_SEG(0x0001180028000128ull) | ||
77 | #define CVMX_FPA_QUEX_AVAILABLE(offset) \ | ||
78 | CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8)) | ||
79 | #define CVMX_FPA_QUEX_PAGE_INDEX(offset) \ | ||
80 | CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8)) | ||
81 | #define CVMX_FPA_QUE_ACT \ | ||
82 | CVMX_ADD_IO_SEG(0x0001180028000138ull) | ||
83 | #define CVMX_FPA_QUE_EXP \ | ||
84 | CVMX_ADD_IO_SEG(0x0001180028000130ull) | ||
85 | #define CVMX_FPA_WART_CTL \ | ||
86 | CVMX_ADD_IO_SEG(0x00011800280000D8ull) | ||
87 | #define CVMX_FPA_WART_STATUS \ | ||
88 | CVMX_ADD_IO_SEG(0x00011800280000E0ull) | ||
89 | |||
90 | union cvmx_fpa_bist_status { | ||
91 | uint64_t u64; | ||
92 | struct cvmx_fpa_bist_status_s { | ||
93 | uint64_t reserved_5_63:59; | ||
94 | uint64_t frd:1; | ||
95 | uint64_t fpf0:1; | ||
96 | uint64_t fpf1:1; | ||
97 | uint64_t ffr:1; | ||
98 | uint64_t fdr:1; | ||
99 | } s; | ||
100 | struct cvmx_fpa_bist_status_s cn30xx; | ||
101 | struct cvmx_fpa_bist_status_s cn31xx; | ||
102 | struct cvmx_fpa_bist_status_s cn38xx; | ||
103 | struct cvmx_fpa_bist_status_s cn38xxp2; | ||
104 | struct cvmx_fpa_bist_status_s cn50xx; | ||
105 | struct cvmx_fpa_bist_status_s cn52xx; | ||
106 | struct cvmx_fpa_bist_status_s cn52xxp1; | ||
107 | struct cvmx_fpa_bist_status_s cn56xx; | ||
108 | struct cvmx_fpa_bist_status_s cn56xxp1; | ||
109 | struct cvmx_fpa_bist_status_s cn58xx; | ||
110 | struct cvmx_fpa_bist_status_s cn58xxp1; | ||
111 | }; | ||
112 | |||
113 | union cvmx_fpa_ctl_status { | ||
114 | uint64_t u64; | ||
115 | struct cvmx_fpa_ctl_status_s { | ||
116 | uint64_t reserved_18_63:46; | ||
117 | uint64_t reset:1; | ||
118 | uint64_t use_ldt:1; | ||
119 | uint64_t use_stt:1; | ||
120 | uint64_t enb:1; | ||
121 | uint64_t mem1_err:7; | ||
122 | uint64_t mem0_err:7; | ||
123 | } s; | ||
124 | struct cvmx_fpa_ctl_status_s cn30xx; | ||
125 | struct cvmx_fpa_ctl_status_s cn31xx; | ||
126 | struct cvmx_fpa_ctl_status_s cn38xx; | ||
127 | struct cvmx_fpa_ctl_status_s cn38xxp2; | ||
128 | struct cvmx_fpa_ctl_status_s cn50xx; | ||
129 | struct cvmx_fpa_ctl_status_s cn52xx; | ||
130 | struct cvmx_fpa_ctl_status_s cn52xxp1; | ||
131 | struct cvmx_fpa_ctl_status_s cn56xx; | ||
132 | struct cvmx_fpa_ctl_status_s cn56xxp1; | ||
133 | struct cvmx_fpa_ctl_status_s cn58xx; | ||
134 | struct cvmx_fpa_ctl_status_s cn58xxp1; | ||
135 | }; | ||
136 | |||
137 | union cvmx_fpa_fpfx_marks { | ||
138 | uint64_t u64; | ||
139 | struct cvmx_fpa_fpfx_marks_s { | ||
140 | uint64_t reserved_22_63:42; | ||
141 | uint64_t fpf_wr:11; | ||
142 | uint64_t fpf_rd:11; | ||
143 | } s; | ||
144 | struct cvmx_fpa_fpfx_marks_s cn38xx; | ||
145 | struct cvmx_fpa_fpfx_marks_s cn38xxp2; | ||
146 | struct cvmx_fpa_fpfx_marks_s cn56xx; | ||
147 | struct cvmx_fpa_fpfx_marks_s cn56xxp1; | ||
148 | struct cvmx_fpa_fpfx_marks_s cn58xx; | ||
149 | struct cvmx_fpa_fpfx_marks_s cn58xxp1; | ||
150 | }; | ||
151 | |||
152 | union cvmx_fpa_fpfx_size { | ||
153 | uint64_t u64; | ||
154 | struct cvmx_fpa_fpfx_size_s { | ||
155 | uint64_t reserved_11_63:53; | ||
156 | uint64_t fpf_siz:11; | ||
157 | } s; | ||
158 | struct cvmx_fpa_fpfx_size_s cn38xx; | ||
159 | struct cvmx_fpa_fpfx_size_s cn38xxp2; | ||
160 | struct cvmx_fpa_fpfx_size_s cn56xx; | ||
161 | struct cvmx_fpa_fpfx_size_s cn56xxp1; | ||
162 | struct cvmx_fpa_fpfx_size_s cn58xx; | ||
163 | struct cvmx_fpa_fpfx_size_s cn58xxp1; | ||
164 | }; | ||
165 | |||
166 | union cvmx_fpa_fpf0_marks { | ||
167 | uint64_t u64; | ||
168 | struct cvmx_fpa_fpf0_marks_s { | ||
169 | uint64_t reserved_24_63:40; | ||
170 | uint64_t fpf_wr:12; | ||
171 | uint64_t fpf_rd:12; | ||
172 | } s; | ||
173 | struct cvmx_fpa_fpf0_marks_s cn38xx; | ||
174 | struct cvmx_fpa_fpf0_marks_s cn38xxp2; | ||
175 | struct cvmx_fpa_fpf0_marks_s cn56xx; | ||
176 | struct cvmx_fpa_fpf0_marks_s cn56xxp1; | ||
177 | struct cvmx_fpa_fpf0_marks_s cn58xx; | ||
178 | struct cvmx_fpa_fpf0_marks_s cn58xxp1; | ||
179 | }; | ||
180 | |||
181 | union cvmx_fpa_fpf0_size { | ||
182 | uint64_t u64; | ||
183 | struct cvmx_fpa_fpf0_size_s { | ||
184 | uint64_t reserved_12_63:52; | ||
185 | uint64_t fpf_siz:12; | ||
186 | } s; | ||
187 | struct cvmx_fpa_fpf0_size_s cn38xx; | ||
188 | struct cvmx_fpa_fpf0_size_s cn38xxp2; | ||
189 | struct cvmx_fpa_fpf0_size_s cn56xx; | ||
190 | struct cvmx_fpa_fpf0_size_s cn56xxp1; | ||
191 | struct cvmx_fpa_fpf0_size_s cn58xx; | ||
192 | struct cvmx_fpa_fpf0_size_s cn58xxp1; | ||
193 | }; | ||
194 | |||
195 | union cvmx_fpa_int_enb { | ||
196 | uint64_t u64; | ||
197 | struct cvmx_fpa_int_enb_s { | ||
198 | uint64_t reserved_28_63:36; | ||
199 | uint64_t q7_perr:1; | ||
200 | uint64_t q7_coff:1; | ||
201 | uint64_t q7_und:1; | ||
202 | uint64_t q6_perr:1; | ||
203 | uint64_t q6_coff:1; | ||
204 | uint64_t q6_und:1; | ||
205 | uint64_t q5_perr:1; | ||
206 | uint64_t q5_coff:1; | ||
207 | uint64_t q5_und:1; | ||
208 | uint64_t q4_perr:1; | ||
209 | uint64_t q4_coff:1; | ||
210 | uint64_t q4_und:1; | ||
211 | uint64_t q3_perr:1; | ||
212 | uint64_t q3_coff:1; | ||
213 | uint64_t q3_und:1; | ||
214 | uint64_t q2_perr:1; | ||
215 | uint64_t q2_coff:1; | ||
216 | uint64_t q2_und:1; | ||
217 | uint64_t q1_perr:1; | ||
218 | uint64_t q1_coff:1; | ||
219 | uint64_t q1_und:1; | ||
220 | uint64_t q0_perr:1; | ||
221 | uint64_t q0_coff:1; | ||
222 | uint64_t q0_und:1; | ||
223 | uint64_t fed1_dbe:1; | ||
224 | uint64_t fed1_sbe:1; | ||
225 | uint64_t fed0_dbe:1; | ||
226 | uint64_t fed0_sbe:1; | ||
227 | } s; | ||
228 | struct cvmx_fpa_int_enb_s cn30xx; | ||
229 | struct cvmx_fpa_int_enb_s cn31xx; | ||
230 | struct cvmx_fpa_int_enb_s cn38xx; | ||
231 | struct cvmx_fpa_int_enb_s cn38xxp2; | ||
232 | struct cvmx_fpa_int_enb_s cn50xx; | ||
233 | struct cvmx_fpa_int_enb_s cn52xx; | ||
234 | struct cvmx_fpa_int_enb_s cn52xxp1; | ||
235 | struct cvmx_fpa_int_enb_s cn56xx; | ||
236 | struct cvmx_fpa_int_enb_s cn56xxp1; | ||
237 | struct cvmx_fpa_int_enb_s cn58xx; | ||
238 | struct cvmx_fpa_int_enb_s cn58xxp1; | ||
239 | }; | ||
240 | |||
241 | union cvmx_fpa_int_sum { | ||
242 | uint64_t u64; | ||
243 | struct cvmx_fpa_int_sum_s { | ||
244 | uint64_t reserved_28_63:36; | ||
245 | uint64_t q7_perr:1; | ||
246 | uint64_t q7_coff:1; | ||
247 | uint64_t q7_und:1; | ||
248 | uint64_t q6_perr:1; | ||
249 | uint64_t q6_coff:1; | ||
250 | uint64_t q6_und:1; | ||
251 | uint64_t q5_perr:1; | ||
252 | uint64_t q5_coff:1; | ||
253 | uint64_t q5_und:1; | ||
254 | uint64_t q4_perr:1; | ||
255 | uint64_t q4_coff:1; | ||
256 | uint64_t q4_und:1; | ||
257 | uint64_t q3_perr:1; | ||
258 | uint64_t q3_coff:1; | ||
259 | uint64_t q3_und:1; | ||
260 | uint64_t q2_perr:1; | ||
261 | uint64_t q2_coff:1; | ||
262 | uint64_t q2_und:1; | ||
263 | uint64_t q1_perr:1; | ||
264 | uint64_t q1_coff:1; | ||
265 | uint64_t q1_und:1; | ||
266 | uint64_t q0_perr:1; | ||
267 | uint64_t q0_coff:1; | ||
268 | uint64_t q0_und:1; | ||
269 | uint64_t fed1_dbe:1; | ||
270 | uint64_t fed1_sbe:1; | ||
271 | uint64_t fed0_dbe:1; | ||
272 | uint64_t fed0_sbe:1; | ||
273 | } s; | ||
274 | struct cvmx_fpa_int_sum_s cn30xx; | ||
275 | struct cvmx_fpa_int_sum_s cn31xx; | ||
276 | struct cvmx_fpa_int_sum_s cn38xx; | ||
277 | struct cvmx_fpa_int_sum_s cn38xxp2; | ||
278 | struct cvmx_fpa_int_sum_s cn50xx; | ||
279 | struct cvmx_fpa_int_sum_s cn52xx; | ||
280 | struct cvmx_fpa_int_sum_s cn52xxp1; | ||
281 | struct cvmx_fpa_int_sum_s cn56xx; | ||
282 | struct cvmx_fpa_int_sum_s cn56xxp1; | ||
283 | struct cvmx_fpa_int_sum_s cn58xx; | ||
284 | struct cvmx_fpa_int_sum_s cn58xxp1; | ||
285 | }; | ||
286 | |||
287 | union cvmx_fpa_quex_available { | ||
288 | uint64_t u64; | ||
289 | struct cvmx_fpa_quex_available_s { | ||
290 | uint64_t reserved_29_63:35; | ||
291 | uint64_t que_siz:29; | ||
292 | } s; | ||
293 | struct cvmx_fpa_quex_available_s cn30xx; | ||
294 | struct cvmx_fpa_quex_available_s cn31xx; | ||
295 | struct cvmx_fpa_quex_available_s cn38xx; | ||
296 | struct cvmx_fpa_quex_available_s cn38xxp2; | ||
297 | struct cvmx_fpa_quex_available_s cn50xx; | ||
298 | struct cvmx_fpa_quex_available_s cn52xx; | ||
299 | struct cvmx_fpa_quex_available_s cn52xxp1; | ||
300 | struct cvmx_fpa_quex_available_s cn56xx; | ||
301 | struct cvmx_fpa_quex_available_s cn56xxp1; | ||
302 | struct cvmx_fpa_quex_available_s cn58xx; | ||
303 | struct cvmx_fpa_quex_available_s cn58xxp1; | ||
304 | }; | ||
305 | |||
306 | union cvmx_fpa_quex_page_index { | ||
307 | uint64_t u64; | ||
308 | struct cvmx_fpa_quex_page_index_s { | ||
309 | uint64_t reserved_25_63:39; | ||
310 | uint64_t pg_num:25; | ||
311 | } s; | ||
312 | struct cvmx_fpa_quex_page_index_s cn30xx; | ||
313 | struct cvmx_fpa_quex_page_index_s cn31xx; | ||
314 | struct cvmx_fpa_quex_page_index_s cn38xx; | ||
315 | struct cvmx_fpa_quex_page_index_s cn38xxp2; | ||
316 | struct cvmx_fpa_quex_page_index_s cn50xx; | ||
317 | struct cvmx_fpa_quex_page_index_s cn52xx; | ||
318 | struct cvmx_fpa_quex_page_index_s cn52xxp1; | ||
319 | struct cvmx_fpa_quex_page_index_s cn56xx; | ||
320 | struct cvmx_fpa_quex_page_index_s cn56xxp1; | ||
321 | struct cvmx_fpa_quex_page_index_s cn58xx; | ||
322 | struct cvmx_fpa_quex_page_index_s cn58xxp1; | ||
323 | }; | ||
324 | |||
325 | union cvmx_fpa_que_act { | ||
326 | uint64_t u64; | ||
327 | struct cvmx_fpa_que_act_s { | ||
328 | uint64_t reserved_29_63:35; | ||
329 | uint64_t act_que:3; | ||
330 | uint64_t act_indx:26; | ||
331 | } s; | ||
332 | struct cvmx_fpa_que_act_s cn30xx; | ||
333 | struct cvmx_fpa_que_act_s cn31xx; | ||
334 | struct cvmx_fpa_que_act_s cn38xx; | ||
335 | struct cvmx_fpa_que_act_s cn38xxp2; | ||
336 | struct cvmx_fpa_que_act_s cn50xx; | ||
337 | struct cvmx_fpa_que_act_s cn52xx; | ||
338 | struct cvmx_fpa_que_act_s cn52xxp1; | ||
339 | struct cvmx_fpa_que_act_s cn56xx; | ||
340 | struct cvmx_fpa_que_act_s cn56xxp1; | ||
341 | struct cvmx_fpa_que_act_s cn58xx; | ||
342 | struct cvmx_fpa_que_act_s cn58xxp1; | ||
343 | }; | ||
344 | |||
345 | union cvmx_fpa_que_exp { | ||
346 | uint64_t u64; | ||
347 | struct cvmx_fpa_que_exp_s { | ||
348 | uint64_t reserved_29_63:35; | ||
349 | uint64_t exp_que:3; | ||
350 | uint64_t exp_indx:26; | ||
351 | } s; | ||
352 | struct cvmx_fpa_que_exp_s cn30xx; | ||
353 | struct cvmx_fpa_que_exp_s cn31xx; | ||
354 | struct cvmx_fpa_que_exp_s cn38xx; | ||
355 | struct cvmx_fpa_que_exp_s cn38xxp2; | ||
356 | struct cvmx_fpa_que_exp_s cn50xx; | ||
357 | struct cvmx_fpa_que_exp_s cn52xx; | ||
358 | struct cvmx_fpa_que_exp_s cn52xxp1; | ||
359 | struct cvmx_fpa_que_exp_s cn56xx; | ||
360 | struct cvmx_fpa_que_exp_s cn56xxp1; | ||
361 | struct cvmx_fpa_que_exp_s cn58xx; | ||
362 | struct cvmx_fpa_que_exp_s cn58xxp1; | ||
363 | }; | ||
364 | |||
365 | union cvmx_fpa_wart_ctl { | ||
366 | uint64_t u64; | ||
367 | struct cvmx_fpa_wart_ctl_s { | ||
368 | uint64_t reserved_16_63:48; | ||
369 | uint64_t ctl:16; | ||
370 | } s; | ||
371 | struct cvmx_fpa_wart_ctl_s cn30xx; | ||
372 | struct cvmx_fpa_wart_ctl_s cn31xx; | ||
373 | struct cvmx_fpa_wart_ctl_s cn38xx; | ||
374 | struct cvmx_fpa_wart_ctl_s cn38xxp2; | ||
375 | struct cvmx_fpa_wart_ctl_s cn50xx; | ||
376 | struct cvmx_fpa_wart_ctl_s cn52xx; | ||
377 | struct cvmx_fpa_wart_ctl_s cn52xxp1; | ||
378 | struct cvmx_fpa_wart_ctl_s cn56xx; | ||
379 | struct cvmx_fpa_wart_ctl_s cn56xxp1; | ||
380 | struct cvmx_fpa_wart_ctl_s cn58xx; | ||
381 | struct cvmx_fpa_wart_ctl_s cn58xxp1; | ||
382 | }; | ||
383 | |||
384 | union cvmx_fpa_wart_status { | ||
385 | uint64_t u64; | ||
386 | struct cvmx_fpa_wart_status_s { | ||
387 | uint64_t reserved_32_63:32; | ||
388 | uint64_t status:32; | ||
389 | } s; | ||
390 | struct cvmx_fpa_wart_status_s cn30xx; | ||
391 | struct cvmx_fpa_wart_status_s cn31xx; | ||
392 | struct cvmx_fpa_wart_status_s cn38xx; | ||
393 | struct cvmx_fpa_wart_status_s cn38xxp2; | ||
394 | struct cvmx_fpa_wart_status_s cn50xx; | ||
395 | struct cvmx_fpa_wart_status_s cn52xx; | ||
396 | struct cvmx_fpa_wart_status_s cn52xxp1; | ||
397 | struct cvmx_fpa_wart_status_s cn56xx; | ||
398 | struct cvmx_fpa_wart_status_s cn56xxp1; | ||
399 | struct cvmx_fpa_wart_status_s cn58xx; | ||
400 | struct cvmx_fpa_wart_status_s cn58xxp1; | ||
401 | }; | ||
402 | |||
403 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-fpa.c b/drivers/staging/octeon/cvmx-fpa.c new file mode 100644 index 000000000000..55d9147acc85 --- /dev/null +++ b/drivers/staging/octeon/cvmx-fpa.c | |||
@@ -0,0 +1,183 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * | ||
31 | * Support library for the hardware Free Pool Allocator. | ||
32 | * | ||
33 | * | ||
34 | */ | ||
35 | |||
36 | #include "cvmx-config.h" | ||
37 | #include "cvmx.h" | ||
38 | #include "cvmx-fpa.h" | ||
39 | #include "cvmx-ipd.h" | ||
40 | |||
41 | /** | ||
42 | * Current state of all the pools. Use access functions | ||
43 | * instead of using it directly. | ||
44 | */ | ||
45 | CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; | ||
46 | |||
47 | /** | ||
48 | * Setup a FPA pool to control a new block of memory. The | ||
49 | * buffer pointer must be a physical address. | ||
50 | * | ||
51 | * @pool: Pool to initialize | ||
52 | * 0 <= pool < 8 | ||
53 | * @name: Constant character string to name this pool. | ||
54 | * String is not copied. | ||
55 | * @buffer: Pointer to the block of memory to use. This must be | ||
56 | * accessable by all processors and external hardware. | ||
57 | * @block_size: Size for each block controlled by the FPA | ||
58 | * @num_blocks: Number of blocks | ||
59 | * | ||
60 | * Returns 0 on Success, | ||
61 | * -1 on failure | ||
62 | */ | ||
63 | int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, | ||
64 | uint64_t block_size, uint64_t num_blocks) | ||
65 | { | ||
66 | char *ptr; | ||
67 | if (!buffer) { | ||
68 | cvmx_dprintf | ||
69 | ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n"); | ||
70 | return -1; | ||
71 | } | ||
72 | if (pool >= CVMX_FPA_NUM_POOLS) { | ||
73 | cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n"); | ||
74 | return -1; | ||
75 | } | ||
76 | |||
77 | if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) { | ||
78 | cvmx_dprintf | ||
79 | ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n"); | ||
80 | return -1; | ||
81 | } | ||
82 | |||
83 | if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) { | ||
84 | cvmx_dprintf | ||
85 | ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n"); | ||
86 | return -1; | ||
87 | } | ||
88 | |||
89 | cvmx_fpa_pool_info[pool].name = name; | ||
90 | cvmx_fpa_pool_info[pool].size = block_size; | ||
91 | cvmx_fpa_pool_info[pool].starting_element_count = num_blocks; | ||
92 | cvmx_fpa_pool_info[pool].base = buffer; | ||
93 | |||
94 | ptr = (char *)buffer; | ||
95 | while (num_blocks--) { | ||
96 | cvmx_fpa_free(ptr, pool, 0); | ||
97 | ptr += block_size; | ||
98 | } | ||
99 | return 0; | ||
100 | } | ||
101 | |||
102 | /** | ||
103 | * Shutdown a Memory pool and validate that it had all of | ||
104 | * the buffers originally placed in it. | ||
105 | * | ||
106 | * @pool: Pool to shutdown | ||
107 | * Returns Zero on success | ||
108 | * - Positive is count of missing buffers | ||
109 | * - Negative is too many buffers or corrupted pointers | ||
110 | */ | ||
111 | uint64_t cvmx_fpa_shutdown_pool(uint64_t pool) | ||
112 | { | ||
113 | uint64_t errors = 0; | ||
114 | uint64_t count = 0; | ||
115 | uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base); | ||
116 | uint64_t finish = | ||
117 | base + | ||
118 | cvmx_fpa_pool_info[pool].size * | ||
119 | cvmx_fpa_pool_info[pool].starting_element_count; | ||
120 | void *ptr; | ||
121 | uint64_t address; | ||
122 | |||
123 | count = 0; | ||
124 | do { | ||
125 | ptr = cvmx_fpa_alloc(pool); | ||
126 | if (ptr) | ||
127 | address = cvmx_ptr_to_phys(ptr); | ||
128 | else | ||
129 | address = 0; | ||
130 | if (address) { | ||
131 | if ((address >= base) && (address < finish) && | ||
132 | (((address - | ||
133 | base) % cvmx_fpa_pool_info[pool].size) == 0)) { | ||
134 | count++; | ||
135 | } else { | ||
136 | cvmx_dprintf | ||
137 | ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n", | ||
138 | (unsigned long long)address, | ||
139 | cvmx_fpa_pool_info[pool].name, (int)pool); | ||
140 | errors++; | ||
141 | } | ||
142 | } | ||
143 | } while (address); | ||
144 | |||
145 | #ifdef CVMX_ENABLE_PKO_FUNCTIONS | ||
146 | if (pool == 0) | ||
147 | cvmx_ipd_free_ptr(); | ||
148 | #endif | ||
149 | |||
150 | if (errors) { | ||
151 | cvmx_dprintf | ||
152 | ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n", | ||
153 | cvmx_fpa_pool_info[pool].name, (int)pool, | ||
154 | (unsigned long long)base, (unsigned long long)finish, | ||
155 | (unsigned long long)cvmx_fpa_pool_info[pool].size); | ||
156 | return -errors; | ||
157 | } else | ||
158 | return 0; | ||
159 | } | ||
160 | |||
161 | uint64_t cvmx_fpa_get_block_size(uint64_t pool) | ||
162 | { | ||
163 | switch (pool) { | ||
164 | case 0: | ||
165 | return CVMX_FPA_POOL_0_SIZE; | ||
166 | case 1: | ||
167 | return CVMX_FPA_POOL_1_SIZE; | ||
168 | case 2: | ||
169 | return CVMX_FPA_POOL_2_SIZE; | ||
170 | case 3: | ||
171 | return CVMX_FPA_POOL_3_SIZE; | ||
172 | case 4: | ||
173 | return CVMX_FPA_POOL_4_SIZE; | ||
174 | case 5: | ||
175 | return CVMX_FPA_POOL_5_SIZE; | ||
176 | case 6: | ||
177 | return CVMX_FPA_POOL_6_SIZE; | ||
178 | case 7: | ||
179 | return CVMX_FPA_POOL_7_SIZE; | ||
180 | default: | ||
181 | return 0; | ||
182 | } | ||
183 | } | ||
diff --git a/drivers/staging/octeon/cvmx-fpa.h b/drivers/staging/octeon/cvmx-fpa.h new file mode 100644 index 000000000000..1d7788fe09f2 --- /dev/null +++ b/drivers/staging/octeon/cvmx-fpa.h | |||
@@ -0,0 +1,299 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * | ||
31 | * Interface to the hardware Free Pool Allocator. | ||
32 | * | ||
33 | * | ||
34 | */ | ||
35 | |||
36 | #ifndef __CVMX_FPA_H__ | ||
37 | #define __CVMX_FPA_H__ | ||
38 | |||
39 | #include "cvmx-address.h" | ||
40 | #include "cvmx-fpa-defs.h" | ||
41 | |||
42 | #define CVMX_FPA_NUM_POOLS 8 | ||
43 | #define CVMX_FPA_MIN_BLOCK_SIZE 128 | ||
44 | #define CVMX_FPA_ALIGNMENT 128 | ||
45 | |||
46 | /** | ||
47 | * Structure describing the data format used for stores to the FPA. | ||
48 | */ | ||
49 | typedef union { | ||
50 | uint64_t u64; | ||
51 | struct { | ||
52 | /* | ||
53 | * the (64-bit word) location in scratchpad to write | ||
54 | * to (if len != 0) | ||
55 | */ | ||
56 | uint64_t scraddr:8; | ||
57 | /* the number of words in the response (0 => no response) */ | ||
58 | uint64_t len:8; | ||
59 | /* the ID of the device on the non-coherent bus */ | ||
60 | uint64_t did:8; | ||
61 | /* | ||
62 | * the address that will appear in the first tick on | ||
63 | * the NCB bus. | ||
64 | */ | ||
65 | uint64_t addr:40; | ||
66 | } s; | ||
67 | } cvmx_fpa_iobdma_data_t; | ||
68 | |||
69 | /** | ||
70 | * Structure describing the current state of a FPA pool. | ||
71 | */ | ||
72 | typedef struct { | ||
73 | /* Name it was created under */ | ||
74 | const char *name; | ||
75 | /* Size of each block */ | ||
76 | uint64_t size; | ||
77 | /* The base memory address of whole block */ | ||
78 | void *base; | ||
79 | /* The number of elements in the pool at creation */ | ||
80 | uint64_t starting_element_count; | ||
81 | } cvmx_fpa_pool_info_t; | ||
82 | |||
83 | /** | ||
84 | * Current state of all the pools. Use access functions | ||
85 | * instead of using it directly. | ||
86 | */ | ||
87 | extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; | ||
88 | |||
89 | /* CSR typedefs have been moved to cvmx-csr-*.h */ | ||
90 | |||
91 | /** | ||
92 | * Return the name of the pool | ||
93 | * | ||
94 | * @pool: Pool to get the name of | ||
95 | * Returns The name | ||
96 | */ | ||
97 | static inline const char *cvmx_fpa_get_name(uint64_t pool) | ||
98 | { | ||
99 | return cvmx_fpa_pool_info[pool].name; | ||
100 | } | ||
101 | |||
102 | /** | ||
103 | * Return the base of the pool | ||
104 | * | ||
105 | * @pool: Pool to get the base of | ||
106 | * Returns The base | ||
107 | */ | ||
108 | static inline void *cvmx_fpa_get_base(uint64_t pool) | ||
109 | { | ||
110 | return cvmx_fpa_pool_info[pool].base; | ||
111 | } | ||
112 | |||
113 | /** | ||
114 | * Check if a pointer belongs to an FPA pool. Return non-zero | ||
115 | * if the supplied pointer is inside the memory controlled by | ||
116 | * an FPA pool. | ||
117 | * | ||
118 | * @pool: Pool to check | ||
119 | * @ptr: Pointer to check | ||
120 | * Returns Non-zero if pointer is in the pool. Zero if not | ||
121 | */ | ||
122 | static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr) | ||
123 | { | ||
124 | return ((ptr >= cvmx_fpa_pool_info[pool].base) && | ||
125 | ((char *)ptr < | ||
126 | ((char *)(cvmx_fpa_pool_info[pool].base)) + | ||
127 | cvmx_fpa_pool_info[pool].size * | ||
128 | cvmx_fpa_pool_info[pool].starting_element_count)); | ||
129 | } | ||
130 | |||
131 | /** | ||
132 | * Enable the FPA for use. Must be performed after any CSR | ||
133 | * configuration but before any other FPA functions. | ||
134 | */ | ||
135 | static inline void cvmx_fpa_enable(void) | ||
136 | { | ||
137 | union cvmx_fpa_ctl_status status; | ||
138 | |||
139 | status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); | ||
140 | if (status.s.enb) { | ||
141 | cvmx_dprintf | ||
142 | ("Warning: Enabling FPA when FPA already enabled.\n"); | ||
143 | } | ||
144 | |||
145 | /* | ||
146 | * Do runtime check as we allow pass1 compiled code to run on | ||
147 | * pass2 chips. | ||
148 | */ | ||
149 | if (cvmx_octeon_is_pass1()) { | ||
150 | union cvmx_fpa_fpfx_marks marks; | ||
151 | int i; | ||
152 | for (i = 1; i < 8; i++) { | ||
153 | marks.u64 = | ||
154 | cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull); | ||
155 | marks.s.fpf_wr = 0xe0; | ||
156 | cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull, | ||
157 | marks.u64); | ||
158 | } | ||
159 | |||
160 | /* Enforce a 10 cycle delay between config and enable */ | ||
161 | cvmx_wait(10); | ||
162 | } | ||
163 | |||
164 | /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */ | ||
165 | status.u64 = 0; | ||
166 | status.s.enb = 1; | ||
167 | cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64); | ||
168 | } | ||
169 | |||
170 | /** | ||
171 | * Get a new block from the FPA | ||
172 | * | ||
173 | * @pool: Pool to get the block from | ||
174 | * Returns Pointer to the block or NULL on failure | ||
175 | */ | ||
176 | static inline void *cvmx_fpa_alloc(uint64_t pool) | ||
177 | { | ||
178 | uint64_t address = | ||
179 | cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool))); | ||
180 | if (address) | ||
181 | return cvmx_phys_to_ptr(address); | ||
182 | else | ||
183 | return NULL; | ||
184 | } | ||
185 | |||
186 | /** | ||
187 | * Asynchronously get a new block from the FPA | ||
188 | * | ||
189 | * @scr_addr: Local scratch address to put response in. This is a byte address, | ||
190 | * but must be 8 byte aligned. | ||
191 | * @pool: Pool to get the block from | ||
192 | */ | ||
193 | static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool) | ||
194 | { | ||
195 | cvmx_fpa_iobdma_data_t data; | ||
196 | |||
197 | /* | ||
198 | * Hardware only uses 64 bit alligned locations, so convert | ||
199 | * from byte address to 64-bit index | ||
200 | */ | ||
201 | data.s.scraddr = scr_addr >> 3; | ||
202 | data.s.len = 1; | ||
203 | data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool); | ||
204 | data.s.addr = 0; | ||
205 | cvmx_send_single(data.u64); | ||
206 | } | ||
207 | |||
208 | /** | ||
209 | * Free a block allocated with a FPA pool. Does NOT provide memory | ||
210 | * ordering in cases where the memory block was modified by the core. | ||
211 | * | ||
212 | * @ptr: Block to free | ||
213 | * @pool: Pool to put it in | ||
214 | * @num_cache_lines: | ||
215 | * Cache lines to invalidate | ||
216 | */ | ||
217 | static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool, | ||
218 | uint64_t num_cache_lines) | ||
219 | { | ||
220 | cvmx_addr_t newptr; | ||
221 | newptr.u64 = cvmx_ptr_to_phys(ptr); | ||
222 | newptr.sfilldidspace.didspace = | ||
223 | CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); | ||
224 | /* Prevent GCC from reordering around free */ | ||
225 | barrier(); | ||
226 | /* value written is number of cache lines not written back */ | ||
227 | cvmx_write_io(newptr.u64, num_cache_lines); | ||
228 | } | ||
229 | |||
230 | /** | ||
231 | * Free a block allocated with a FPA pool. Provides required memory | ||
232 | * ordering in cases where memory block was modified by core. | ||
233 | * | ||
234 | * @ptr: Block to free | ||
235 | * @pool: Pool to put it in | ||
236 | * @num_cache_lines: | ||
237 | * Cache lines to invalidate | ||
238 | */ | ||
239 | static inline void cvmx_fpa_free(void *ptr, uint64_t pool, | ||
240 | uint64_t num_cache_lines) | ||
241 | { | ||
242 | cvmx_addr_t newptr; | ||
243 | newptr.u64 = cvmx_ptr_to_phys(ptr); | ||
244 | newptr.sfilldidspace.didspace = | ||
245 | CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); | ||
246 | /* | ||
247 | * Make sure that any previous writes to memory go out before | ||
248 | * we free this buffer. This also serves as a barrier to | ||
249 | * prevent GCC from reordering operations to after the | ||
250 | * free. | ||
251 | */ | ||
252 | CVMX_SYNCWS; | ||
253 | /* value written is number of cache lines not written back */ | ||
254 | cvmx_write_io(newptr.u64, num_cache_lines); | ||
255 | } | ||
256 | |||
257 | /** | ||
258 | * Setup a FPA pool to control a new block of memory. | ||
259 | * This can only be called once per pool. Make sure proper | ||
260 | * locking enforces this. | ||
261 | * | ||
262 | * @pool: Pool to initialize | ||
263 | * 0 <= pool < 8 | ||
264 | * @name: Constant character string to name this pool. | ||
265 | * String is not copied. | ||
266 | * @buffer: Pointer to the block of memory to use. This must be | ||
267 | * accessable by all processors and external hardware. | ||
268 | * @block_size: Size for each block controlled by the FPA | ||
269 | * @num_blocks: Number of blocks | ||
270 | * | ||
271 | * Returns 0 on Success, | ||
272 | * -1 on failure | ||
273 | */ | ||
274 | extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, | ||
275 | uint64_t block_size, uint64_t num_blocks); | ||
276 | |||
277 | /** | ||
278 | * Shutdown a Memory pool and validate that it had all of | ||
279 | * the buffers originally placed in it. This should only be | ||
280 | * called by one processor after all hardware has finished | ||
281 | * using the pool. | ||
282 | * | ||
283 | * @pool: Pool to shutdown | ||
284 | * Returns Zero on success | ||
285 | * - Positive is count of missing buffers | ||
286 | * - Negative is too many buffers or corrupted pointers | ||
287 | */ | ||
288 | extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool); | ||
289 | |||
290 | /** | ||
291 | * Get the size of blocks controlled by the pool | ||
292 | * This is resolved to a constant at compile time. | ||
293 | * | ||
294 | * @pool: Pool to access | ||
295 | * Returns Size of the block in bytes | ||
296 | */ | ||
297 | uint64_t cvmx_fpa_get_block_size(uint64_t pool); | ||
298 | |||
299 | #endif /* __CVM_FPA_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/drivers/staging/octeon/cvmx-gmxx-defs.h new file mode 100644 index 000000000000..946a43a73fd7 --- /dev/null +++ b/drivers/staging/octeon/cvmx-gmxx-defs.h | |||
@@ -0,0 +1,2529 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_GMXX_DEFS_H__ | ||
29 | #define __CVMX_GMXX_DEFS_H__ | ||
30 | |||
31 | #define CVMX_GMXX_BAD_REG(block_id) \ | ||
32 | CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull)) | ||
33 | #define CVMX_GMXX_BIST(block_id) \ | ||
34 | CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull)) | ||
35 | #define CVMX_GMXX_CLK_EN(block_id) \ | ||
36 | CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull)) | ||
37 | #define CVMX_GMXX_HG2_CONTROL(block_id) \ | ||
38 | CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull)) | ||
39 | #define CVMX_GMXX_INF_MODE(block_id) \ | ||
40 | CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull)) | ||
41 | #define CVMX_GMXX_NXA_ADR(block_id) \ | ||
42 | CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull)) | ||
43 | #define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \ | ||
44 | CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
45 | #define CVMX_GMXX_PRTX_CFG(offset, block_id) \ | ||
46 | CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
47 | #define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \ | ||
48 | CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
49 | #define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \ | ||
50 | CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
51 | #define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \ | ||
52 | CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
53 | #define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \ | ||
54 | CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
55 | #define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \ | ||
56 | CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
57 | #define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \ | ||
58 | CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
59 | #define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \ | ||
60 | CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
61 | #define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \ | ||
62 | CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
63 | #define CVMX_GMXX_RXX_DECISION(offset, block_id) \ | ||
64 | CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
65 | #define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \ | ||
66 | CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
67 | #define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \ | ||
68 | CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
69 | #define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \ | ||
70 | CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
71 | #define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \ | ||
72 | CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
73 | #define CVMX_GMXX_RXX_IFG(offset, block_id) \ | ||
74 | CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
75 | #define CVMX_GMXX_RXX_INT_EN(offset, block_id) \ | ||
76 | CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
77 | #define CVMX_GMXX_RXX_INT_REG(offset, block_id) \ | ||
78 | CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
79 | #define CVMX_GMXX_RXX_JABBER(offset, block_id) \ | ||
80 | CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
81 | #define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \ | ||
82 | CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
83 | #define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \ | ||
84 | CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
85 | #define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \ | ||
86 | CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
87 | #define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \ | ||
88 | CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
89 | #define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \ | ||
90 | CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
91 | #define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \ | ||
92 | CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
93 | #define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \ | ||
94 | CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
95 | #define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \ | ||
96 | CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
97 | #define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \ | ||
98 | CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
99 | #define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \ | ||
100 | CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
101 | #define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \ | ||
102 | CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
103 | #define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \ | ||
104 | CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
105 | #define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \ | ||
106 | CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
107 | #define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \ | ||
108 | CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
109 | #define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \ | ||
110 | CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
111 | #define CVMX_GMXX_RX_BP_ONX(offset, block_id) \ | ||
112 | CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
113 | #define CVMX_GMXX_RX_HG2_STATUS(block_id) \ | ||
114 | CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull)) | ||
115 | #define CVMX_GMXX_RX_PASS_EN(block_id) \ | ||
116 | CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull)) | ||
117 | #define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \ | ||
118 | CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
119 | #define CVMX_GMXX_RX_PRTS(block_id) \ | ||
120 | CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull)) | ||
121 | #define CVMX_GMXX_RX_PRT_INFO(block_id) \ | ||
122 | CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull)) | ||
123 | #define CVMX_GMXX_RX_TX_STATUS(block_id) \ | ||
124 | CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull)) | ||
125 | #define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \ | ||
126 | CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull)) | ||
127 | #define CVMX_GMXX_RX_XAUI_CTL(block_id) \ | ||
128 | CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull)) | ||
129 | #define CVMX_GMXX_SMACX(offset, block_id) \ | ||
130 | CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
131 | #define CVMX_GMXX_STAT_BP(block_id) \ | ||
132 | CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull)) | ||
133 | #define CVMX_GMXX_TXX_APPEND(offset, block_id) \ | ||
134 | CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
135 | #define CVMX_GMXX_TXX_BURST(offset, block_id) \ | ||
136 | CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
137 | #define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \ | ||
138 | CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
139 | #define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \ | ||
140 | CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
141 | #define CVMX_GMXX_TXX_CLK(offset, block_id) \ | ||
142 | CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
143 | #define CVMX_GMXX_TXX_CTL(offset, block_id) \ | ||
144 | CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
145 | #define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \ | ||
146 | CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
147 | #define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \ | ||
148 | CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
149 | #define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \ | ||
150 | CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
151 | #define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \ | ||
152 | CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
153 | #define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \ | ||
154 | CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
155 | #define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \ | ||
156 | CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
157 | #define CVMX_GMXX_TXX_SLOT(offset, block_id) \ | ||
158 | CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
159 | #define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \ | ||
160 | CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
161 | #define CVMX_GMXX_TXX_STAT0(offset, block_id) \ | ||
162 | CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
163 | #define CVMX_GMXX_TXX_STAT1(offset, block_id) \ | ||
164 | CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
165 | #define CVMX_GMXX_TXX_STAT2(offset, block_id) \ | ||
166 | CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
167 | #define CVMX_GMXX_TXX_STAT3(offset, block_id) \ | ||
168 | CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
169 | #define CVMX_GMXX_TXX_STAT4(offset, block_id) \ | ||
170 | CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
171 | #define CVMX_GMXX_TXX_STAT5(offset, block_id) \ | ||
172 | CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
173 | #define CVMX_GMXX_TXX_STAT6(offset, block_id) \ | ||
174 | CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
175 | #define CVMX_GMXX_TXX_STAT7(offset, block_id) \ | ||
176 | CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
177 | #define CVMX_GMXX_TXX_STAT8(offset, block_id) \ | ||
178 | CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
179 | #define CVMX_GMXX_TXX_STAT9(offset, block_id) \ | ||
180 | CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
181 | #define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \ | ||
182 | CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
183 | #define CVMX_GMXX_TXX_THRESH(offset, block_id) \ | ||
184 | CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) | ||
185 | #define CVMX_GMXX_TX_BP(block_id) \ | ||
186 | CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull)) | ||
187 | #define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \ | ||
188 | CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull)) | ||
189 | #define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \ | ||
190 | CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull)) | ||
191 | #define CVMX_GMXX_TX_CORRUPT(block_id) \ | ||
192 | CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull)) | ||
193 | #define CVMX_GMXX_TX_HG2_REG1(block_id) \ | ||
194 | CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull)) | ||
195 | #define CVMX_GMXX_TX_HG2_REG2(block_id) \ | ||
196 | CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull)) | ||
197 | #define CVMX_GMXX_TX_IFG(block_id) \ | ||
198 | CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull)) | ||
199 | #define CVMX_GMXX_TX_INT_EN(block_id) \ | ||
200 | CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull)) | ||
201 | #define CVMX_GMXX_TX_INT_REG(block_id) \ | ||
202 | CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull)) | ||
203 | #define CVMX_GMXX_TX_JAM(block_id) \ | ||
204 | CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull)) | ||
205 | #define CVMX_GMXX_TX_LFSR(block_id) \ | ||
206 | CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull)) | ||
207 | #define CVMX_GMXX_TX_OVR_BP(block_id) \ | ||
208 | CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull)) | ||
209 | #define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \ | ||
210 | CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull)) | ||
211 | #define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \ | ||
212 | CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull)) | ||
213 | #define CVMX_GMXX_TX_PRTS(block_id) \ | ||
214 | CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull)) | ||
215 | #define CVMX_GMXX_TX_SPI_CTL(block_id) \ | ||
216 | CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull)) | ||
217 | #define CVMX_GMXX_TX_SPI_DRAIN(block_id) \ | ||
218 | CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull)) | ||
219 | #define CVMX_GMXX_TX_SPI_MAX(block_id) \ | ||
220 | CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull)) | ||
221 | #define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \ | ||
222 | CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
223 | #define CVMX_GMXX_TX_SPI_THRESH(block_id) \ | ||
224 | CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull)) | ||
225 | #define CVMX_GMXX_TX_XAUI_CTL(block_id) \ | ||
226 | CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull)) | ||
227 | #define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \ | ||
228 | CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull)) | ||
229 | |||
230 | union cvmx_gmxx_bad_reg { | ||
231 | uint64_t u64; | ||
232 | struct cvmx_gmxx_bad_reg_s { | ||
233 | uint64_t reserved_31_63:33; | ||
234 | uint64_t inb_nxa:4; | ||
235 | uint64_t statovr:1; | ||
236 | uint64_t loststat:4; | ||
237 | uint64_t reserved_18_21:4; | ||
238 | uint64_t out_ovr:16; | ||
239 | uint64_t ncb_ovr:1; | ||
240 | uint64_t out_col:1; | ||
241 | } s; | ||
242 | struct cvmx_gmxx_bad_reg_cn30xx { | ||
243 | uint64_t reserved_31_63:33; | ||
244 | uint64_t inb_nxa:4; | ||
245 | uint64_t statovr:1; | ||
246 | uint64_t reserved_25_25:1; | ||
247 | uint64_t loststat:3; | ||
248 | uint64_t reserved_5_21:17; | ||
249 | uint64_t out_ovr:3; | ||
250 | uint64_t reserved_0_1:2; | ||
251 | } cn30xx; | ||
252 | struct cvmx_gmxx_bad_reg_cn30xx cn31xx; | ||
253 | struct cvmx_gmxx_bad_reg_s cn38xx; | ||
254 | struct cvmx_gmxx_bad_reg_s cn38xxp2; | ||
255 | struct cvmx_gmxx_bad_reg_cn30xx cn50xx; | ||
256 | struct cvmx_gmxx_bad_reg_cn52xx { | ||
257 | uint64_t reserved_31_63:33; | ||
258 | uint64_t inb_nxa:4; | ||
259 | uint64_t statovr:1; | ||
260 | uint64_t loststat:4; | ||
261 | uint64_t reserved_6_21:16; | ||
262 | uint64_t out_ovr:4; | ||
263 | uint64_t reserved_0_1:2; | ||
264 | } cn52xx; | ||
265 | struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1; | ||
266 | struct cvmx_gmxx_bad_reg_cn52xx cn56xx; | ||
267 | struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1; | ||
268 | struct cvmx_gmxx_bad_reg_s cn58xx; | ||
269 | struct cvmx_gmxx_bad_reg_s cn58xxp1; | ||
270 | }; | ||
271 | |||
272 | union cvmx_gmxx_bist { | ||
273 | uint64_t u64; | ||
274 | struct cvmx_gmxx_bist_s { | ||
275 | uint64_t reserved_17_63:47; | ||
276 | uint64_t status:17; | ||
277 | } s; | ||
278 | struct cvmx_gmxx_bist_cn30xx { | ||
279 | uint64_t reserved_10_63:54; | ||
280 | uint64_t status:10; | ||
281 | } cn30xx; | ||
282 | struct cvmx_gmxx_bist_cn30xx cn31xx; | ||
283 | struct cvmx_gmxx_bist_cn30xx cn38xx; | ||
284 | struct cvmx_gmxx_bist_cn30xx cn38xxp2; | ||
285 | struct cvmx_gmxx_bist_cn50xx { | ||
286 | uint64_t reserved_12_63:52; | ||
287 | uint64_t status:12; | ||
288 | } cn50xx; | ||
289 | struct cvmx_gmxx_bist_cn52xx { | ||
290 | uint64_t reserved_16_63:48; | ||
291 | uint64_t status:16; | ||
292 | } cn52xx; | ||
293 | struct cvmx_gmxx_bist_cn52xx cn52xxp1; | ||
294 | struct cvmx_gmxx_bist_cn52xx cn56xx; | ||
295 | struct cvmx_gmxx_bist_cn52xx cn56xxp1; | ||
296 | struct cvmx_gmxx_bist_s cn58xx; | ||
297 | struct cvmx_gmxx_bist_s cn58xxp1; | ||
298 | }; | ||
299 | |||
300 | union cvmx_gmxx_clk_en { | ||
301 | uint64_t u64; | ||
302 | struct cvmx_gmxx_clk_en_s { | ||
303 | uint64_t reserved_1_63:63; | ||
304 | uint64_t clk_en:1; | ||
305 | } s; | ||
306 | struct cvmx_gmxx_clk_en_s cn52xx; | ||
307 | struct cvmx_gmxx_clk_en_s cn52xxp1; | ||
308 | struct cvmx_gmxx_clk_en_s cn56xx; | ||
309 | struct cvmx_gmxx_clk_en_s cn56xxp1; | ||
310 | }; | ||
311 | |||
312 | union cvmx_gmxx_hg2_control { | ||
313 | uint64_t u64; | ||
314 | struct cvmx_gmxx_hg2_control_s { | ||
315 | uint64_t reserved_19_63:45; | ||
316 | uint64_t hg2tx_en:1; | ||
317 | uint64_t hg2rx_en:1; | ||
318 | uint64_t phys_en:1; | ||
319 | uint64_t logl_en:16; | ||
320 | } s; | ||
321 | struct cvmx_gmxx_hg2_control_s cn52xx; | ||
322 | struct cvmx_gmxx_hg2_control_s cn52xxp1; | ||
323 | struct cvmx_gmxx_hg2_control_s cn56xx; | ||
324 | }; | ||
325 | |||
326 | union cvmx_gmxx_inf_mode { | ||
327 | uint64_t u64; | ||
328 | struct cvmx_gmxx_inf_mode_s { | ||
329 | uint64_t reserved_10_63:54; | ||
330 | uint64_t speed:2; | ||
331 | uint64_t reserved_6_7:2; | ||
332 | uint64_t mode:2; | ||
333 | uint64_t reserved_3_3:1; | ||
334 | uint64_t p0mii:1; | ||
335 | uint64_t en:1; | ||
336 | uint64_t type:1; | ||
337 | } s; | ||
338 | struct cvmx_gmxx_inf_mode_cn30xx { | ||
339 | uint64_t reserved_3_63:61; | ||
340 | uint64_t p0mii:1; | ||
341 | uint64_t en:1; | ||
342 | uint64_t type:1; | ||
343 | } cn30xx; | ||
344 | struct cvmx_gmxx_inf_mode_cn31xx { | ||
345 | uint64_t reserved_2_63:62; | ||
346 | uint64_t en:1; | ||
347 | uint64_t type:1; | ||
348 | } cn31xx; | ||
349 | struct cvmx_gmxx_inf_mode_cn31xx cn38xx; | ||
350 | struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2; | ||
351 | struct cvmx_gmxx_inf_mode_cn30xx cn50xx; | ||
352 | struct cvmx_gmxx_inf_mode_cn52xx { | ||
353 | uint64_t reserved_10_63:54; | ||
354 | uint64_t speed:2; | ||
355 | uint64_t reserved_6_7:2; | ||
356 | uint64_t mode:2; | ||
357 | uint64_t reserved_2_3:2; | ||
358 | uint64_t en:1; | ||
359 | uint64_t type:1; | ||
360 | } cn52xx; | ||
361 | struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1; | ||
362 | struct cvmx_gmxx_inf_mode_cn52xx cn56xx; | ||
363 | struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1; | ||
364 | struct cvmx_gmxx_inf_mode_cn31xx cn58xx; | ||
365 | struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1; | ||
366 | }; | ||
367 | |||
368 | union cvmx_gmxx_nxa_adr { | ||
369 | uint64_t u64; | ||
370 | struct cvmx_gmxx_nxa_adr_s { | ||
371 | uint64_t reserved_6_63:58; | ||
372 | uint64_t prt:6; | ||
373 | } s; | ||
374 | struct cvmx_gmxx_nxa_adr_s cn30xx; | ||
375 | struct cvmx_gmxx_nxa_adr_s cn31xx; | ||
376 | struct cvmx_gmxx_nxa_adr_s cn38xx; | ||
377 | struct cvmx_gmxx_nxa_adr_s cn38xxp2; | ||
378 | struct cvmx_gmxx_nxa_adr_s cn50xx; | ||
379 | struct cvmx_gmxx_nxa_adr_s cn52xx; | ||
380 | struct cvmx_gmxx_nxa_adr_s cn52xxp1; | ||
381 | struct cvmx_gmxx_nxa_adr_s cn56xx; | ||
382 | struct cvmx_gmxx_nxa_adr_s cn56xxp1; | ||
383 | struct cvmx_gmxx_nxa_adr_s cn58xx; | ||
384 | struct cvmx_gmxx_nxa_adr_s cn58xxp1; | ||
385 | }; | ||
386 | |||
387 | union cvmx_gmxx_prtx_cbfc_ctl { | ||
388 | uint64_t u64; | ||
389 | struct cvmx_gmxx_prtx_cbfc_ctl_s { | ||
390 | uint64_t phys_en:16; | ||
391 | uint64_t logl_en:16; | ||
392 | uint64_t phys_bp:16; | ||
393 | uint64_t reserved_4_15:12; | ||
394 | uint64_t bck_en:1; | ||
395 | uint64_t drp_en:1; | ||
396 | uint64_t tx_en:1; | ||
397 | uint64_t rx_en:1; | ||
398 | } s; | ||
399 | struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx; | ||
400 | struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx; | ||
401 | }; | ||
402 | |||
403 | union cvmx_gmxx_prtx_cfg { | ||
404 | uint64_t u64; | ||
405 | struct cvmx_gmxx_prtx_cfg_s { | ||
406 | uint64_t reserved_14_63:50; | ||
407 | uint64_t tx_idle:1; | ||
408 | uint64_t rx_idle:1; | ||
409 | uint64_t reserved_9_11:3; | ||
410 | uint64_t speed_msb:1; | ||
411 | uint64_t reserved_4_7:4; | ||
412 | uint64_t slottime:1; | ||
413 | uint64_t duplex:1; | ||
414 | uint64_t speed:1; | ||
415 | uint64_t en:1; | ||
416 | } s; | ||
417 | struct cvmx_gmxx_prtx_cfg_cn30xx { | ||
418 | uint64_t reserved_4_63:60; | ||
419 | uint64_t slottime:1; | ||
420 | uint64_t duplex:1; | ||
421 | uint64_t speed:1; | ||
422 | uint64_t en:1; | ||
423 | } cn30xx; | ||
424 | struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx; | ||
425 | struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx; | ||
426 | struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2; | ||
427 | struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx; | ||
428 | struct cvmx_gmxx_prtx_cfg_s cn52xx; | ||
429 | struct cvmx_gmxx_prtx_cfg_s cn52xxp1; | ||
430 | struct cvmx_gmxx_prtx_cfg_s cn56xx; | ||
431 | struct cvmx_gmxx_prtx_cfg_s cn56xxp1; | ||
432 | struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx; | ||
433 | struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1; | ||
434 | }; | ||
435 | |||
436 | union cvmx_gmxx_rxx_adr_cam0 { | ||
437 | uint64_t u64; | ||
438 | struct cvmx_gmxx_rxx_adr_cam0_s { | ||
439 | uint64_t adr:64; | ||
440 | } s; | ||
441 | struct cvmx_gmxx_rxx_adr_cam0_s cn30xx; | ||
442 | struct cvmx_gmxx_rxx_adr_cam0_s cn31xx; | ||
443 | struct cvmx_gmxx_rxx_adr_cam0_s cn38xx; | ||
444 | struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2; | ||
445 | struct cvmx_gmxx_rxx_adr_cam0_s cn50xx; | ||
446 | struct cvmx_gmxx_rxx_adr_cam0_s cn52xx; | ||
447 | struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1; | ||
448 | struct cvmx_gmxx_rxx_adr_cam0_s cn56xx; | ||
449 | struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1; | ||
450 | struct cvmx_gmxx_rxx_adr_cam0_s cn58xx; | ||
451 | struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1; | ||
452 | }; | ||
453 | |||
454 | union cvmx_gmxx_rxx_adr_cam1 { | ||
455 | uint64_t u64; | ||
456 | struct cvmx_gmxx_rxx_adr_cam1_s { | ||
457 | uint64_t adr:64; | ||
458 | } s; | ||
459 | struct cvmx_gmxx_rxx_adr_cam1_s cn30xx; | ||
460 | struct cvmx_gmxx_rxx_adr_cam1_s cn31xx; | ||
461 | struct cvmx_gmxx_rxx_adr_cam1_s cn38xx; | ||
462 | struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2; | ||
463 | struct cvmx_gmxx_rxx_adr_cam1_s cn50xx; | ||
464 | struct cvmx_gmxx_rxx_adr_cam1_s cn52xx; | ||
465 | struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1; | ||
466 | struct cvmx_gmxx_rxx_adr_cam1_s cn56xx; | ||
467 | struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1; | ||
468 | struct cvmx_gmxx_rxx_adr_cam1_s cn58xx; | ||
469 | struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1; | ||
470 | }; | ||
471 | |||
472 | union cvmx_gmxx_rxx_adr_cam2 { | ||
473 | uint64_t u64; | ||
474 | struct cvmx_gmxx_rxx_adr_cam2_s { | ||
475 | uint64_t adr:64; | ||
476 | } s; | ||
477 | struct cvmx_gmxx_rxx_adr_cam2_s cn30xx; | ||
478 | struct cvmx_gmxx_rxx_adr_cam2_s cn31xx; | ||
479 | struct cvmx_gmxx_rxx_adr_cam2_s cn38xx; | ||
480 | struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2; | ||
481 | struct cvmx_gmxx_rxx_adr_cam2_s cn50xx; | ||
482 | struct cvmx_gmxx_rxx_adr_cam2_s cn52xx; | ||
483 | struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1; | ||
484 | struct cvmx_gmxx_rxx_adr_cam2_s cn56xx; | ||
485 | struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1; | ||
486 | struct cvmx_gmxx_rxx_adr_cam2_s cn58xx; | ||
487 | struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1; | ||
488 | }; | ||
489 | |||
490 | union cvmx_gmxx_rxx_adr_cam3 { | ||
491 | uint64_t u64; | ||
492 | struct cvmx_gmxx_rxx_adr_cam3_s { | ||
493 | uint64_t adr:64; | ||
494 | } s; | ||
495 | struct cvmx_gmxx_rxx_adr_cam3_s cn30xx; | ||
496 | struct cvmx_gmxx_rxx_adr_cam3_s cn31xx; | ||
497 | struct cvmx_gmxx_rxx_adr_cam3_s cn38xx; | ||
498 | struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2; | ||
499 | struct cvmx_gmxx_rxx_adr_cam3_s cn50xx; | ||
500 | struct cvmx_gmxx_rxx_adr_cam3_s cn52xx; | ||
501 | struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1; | ||
502 | struct cvmx_gmxx_rxx_adr_cam3_s cn56xx; | ||
503 | struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1; | ||
504 | struct cvmx_gmxx_rxx_adr_cam3_s cn58xx; | ||
505 | struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1; | ||
506 | }; | ||
507 | |||
508 | union cvmx_gmxx_rxx_adr_cam4 { | ||
509 | uint64_t u64; | ||
510 | struct cvmx_gmxx_rxx_adr_cam4_s { | ||
511 | uint64_t adr:64; | ||
512 | } s; | ||
513 | struct cvmx_gmxx_rxx_adr_cam4_s cn30xx; | ||
514 | struct cvmx_gmxx_rxx_adr_cam4_s cn31xx; | ||
515 | struct cvmx_gmxx_rxx_adr_cam4_s cn38xx; | ||
516 | struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2; | ||
517 | struct cvmx_gmxx_rxx_adr_cam4_s cn50xx; | ||
518 | struct cvmx_gmxx_rxx_adr_cam4_s cn52xx; | ||
519 | struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1; | ||
520 | struct cvmx_gmxx_rxx_adr_cam4_s cn56xx; | ||
521 | struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1; | ||
522 | struct cvmx_gmxx_rxx_adr_cam4_s cn58xx; | ||
523 | struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1; | ||
524 | }; | ||
525 | |||
526 | union cvmx_gmxx_rxx_adr_cam5 { | ||
527 | uint64_t u64; | ||
528 | struct cvmx_gmxx_rxx_adr_cam5_s { | ||
529 | uint64_t adr:64; | ||
530 | } s; | ||
531 | struct cvmx_gmxx_rxx_adr_cam5_s cn30xx; | ||
532 | struct cvmx_gmxx_rxx_adr_cam5_s cn31xx; | ||
533 | struct cvmx_gmxx_rxx_adr_cam5_s cn38xx; | ||
534 | struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2; | ||
535 | struct cvmx_gmxx_rxx_adr_cam5_s cn50xx; | ||
536 | struct cvmx_gmxx_rxx_adr_cam5_s cn52xx; | ||
537 | struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1; | ||
538 | struct cvmx_gmxx_rxx_adr_cam5_s cn56xx; | ||
539 | struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1; | ||
540 | struct cvmx_gmxx_rxx_adr_cam5_s cn58xx; | ||
541 | struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1; | ||
542 | }; | ||
543 | |||
544 | union cvmx_gmxx_rxx_adr_cam_en { | ||
545 | uint64_t u64; | ||
546 | struct cvmx_gmxx_rxx_adr_cam_en_s { | ||
547 | uint64_t reserved_8_63:56; | ||
548 | uint64_t en:8; | ||
549 | } s; | ||
550 | struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx; | ||
551 | struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx; | ||
552 | struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx; | ||
553 | struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2; | ||
554 | struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx; | ||
555 | struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx; | ||
556 | struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1; | ||
557 | struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx; | ||
558 | struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1; | ||
559 | struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx; | ||
560 | struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1; | ||
561 | }; | ||
562 | |||
563 | union cvmx_gmxx_rxx_adr_ctl { | ||
564 | uint64_t u64; | ||
565 | struct cvmx_gmxx_rxx_adr_ctl_s { | ||
566 | uint64_t reserved_4_63:60; | ||
567 | uint64_t cam_mode:1; | ||
568 | uint64_t mcst:2; | ||
569 | uint64_t bcst:1; | ||
570 | } s; | ||
571 | struct cvmx_gmxx_rxx_adr_ctl_s cn30xx; | ||
572 | struct cvmx_gmxx_rxx_adr_ctl_s cn31xx; | ||
573 | struct cvmx_gmxx_rxx_adr_ctl_s cn38xx; | ||
574 | struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2; | ||
575 | struct cvmx_gmxx_rxx_adr_ctl_s cn50xx; | ||
576 | struct cvmx_gmxx_rxx_adr_ctl_s cn52xx; | ||
577 | struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1; | ||
578 | struct cvmx_gmxx_rxx_adr_ctl_s cn56xx; | ||
579 | struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1; | ||
580 | struct cvmx_gmxx_rxx_adr_ctl_s cn58xx; | ||
581 | struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1; | ||
582 | }; | ||
583 | |||
584 | union cvmx_gmxx_rxx_decision { | ||
585 | uint64_t u64; | ||
586 | struct cvmx_gmxx_rxx_decision_s { | ||
587 | uint64_t reserved_5_63:59; | ||
588 | uint64_t cnt:5; | ||
589 | } s; | ||
590 | struct cvmx_gmxx_rxx_decision_s cn30xx; | ||
591 | struct cvmx_gmxx_rxx_decision_s cn31xx; | ||
592 | struct cvmx_gmxx_rxx_decision_s cn38xx; | ||
593 | struct cvmx_gmxx_rxx_decision_s cn38xxp2; | ||
594 | struct cvmx_gmxx_rxx_decision_s cn50xx; | ||
595 | struct cvmx_gmxx_rxx_decision_s cn52xx; | ||
596 | struct cvmx_gmxx_rxx_decision_s cn52xxp1; | ||
597 | struct cvmx_gmxx_rxx_decision_s cn56xx; | ||
598 | struct cvmx_gmxx_rxx_decision_s cn56xxp1; | ||
599 | struct cvmx_gmxx_rxx_decision_s cn58xx; | ||
600 | struct cvmx_gmxx_rxx_decision_s cn58xxp1; | ||
601 | }; | ||
602 | |||
603 | union cvmx_gmxx_rxx_frm_chk { | ||
604 | uint64_t u64; | ||
605 | struct cvmx_gmxx_rxx_frm_chk_s { | ||
606 | uint64_t reserved_10_63:54; | ||
607 | uint64_t niberr:1; | ||
608 | uint64_t skperr:1; | ||
609 | uint64_t rcverr:1; | ||
610 | uint64_t lenerr:1; | ||
611 | uint64_t alnerr:1; | ||
612 | uint64_t fcserr:1; | ||
613 | uint64_t jabber:1; | ||
614 | uint64_t maxerr:1; | ||
615 | uint64_t carext:1; | ||
616 | uint64_t minerr:1; | ||
617 | } s; | ||
618 | struct cvmx_gmxx_rxx_frm_chk_s cn30xx; | ||
619 | struct cvmx_gmxx_rxx_frm_chk_s cn31xx; | ||
620 | struct cvmx_gmxx_rxx_frm_chk_s cn38xx; | ||
621 | struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2; | ||
622 | struct cvmx_gmxx_rxx_frm_chk_cn50xx { | ||
623 | uint64_t reserved_10_63:54; | ||
624 | uint64_t niberr:1; | ||
625 | uint64_t skperr:1; | ||
626 | uint64_t rcverr:1; | ||
627 | uint64_t reserved_6_6:1; | ||
628 | uint64_t alnerr:1; | ||
629 | uint64_t fcserr:1; | ||
630 | uint64_t jabber:1; | ||
631 | uint64_t reserved_2_2:1; | ||
632 | uint64_t carext:1; | ||
633 | uint64_t reserved_0_0:1; | ||
634 | } cn50xx; | ||
635 | struct cvmx_gmxx_rxx_frm_chk_cn52xx { | ||
636 | uint64_t reserved_9_63:55; | ||
637 | uint64_t skperr:1; | ||
638 | uint64_t rcverr:1; | ||
639 | uint64_t reserved_5_6:2; | ||
640 | uint64_t fcserr:1; | ||
641 | uint64_t jabber:1; | ||
642 | uint64_t reserved_2_2:1; | ||
643 | uint64_t carext:1; | ||
644 | uint64_t reserved_0_0:1; | ||
645 | } cn52xx; | ||
646 | struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1; | ||
647 | struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx; | ||
648 | struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1; | ||
649 | struct cvmx_gmxx_rxx_frm_chk_s cn58xx; | ||
650 | struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1; | ||
651 | }; | ||
652 | |||
653 | union cvmx_gmxx_rxx_frm_ctl { | ||
654 | uint64_t u64; | ||
655 | struct cvmx_gmxx_rxx_frm_ctl_s { | ||
656 | uint64_t reserved_11_63:53; | ||
657 | uint64_t null_dis:1; | ||
658 | uint64_t pre_align:1; | ||
659 | uint64_t pad_len:1; | ||
660 | uint64_t vlan_len:1; | ||
661 | uint64_t pre_free:1; | ||
662 | uint64_t ctl_smac:1; | ||
663 | uint64_t ctl_mcst:1; | ||
664 | uint64_t ctl_bck:1; | ||
665 | uint64_t ctl_drp:1; | ||
666 | uint64_t pre_strp:1; | ||
667 | uint64_t pre_chk:1; | ||
668 | } s; | ||
669 | struct cvmx_gmxx_rxx_frm_ctl_cn30xx { | ||
670 | uint64_t reserved_9_63:55; | ||
671 | uint64_t pad_len:1; | ||
672 | uint64_t vlan_len:1; | ||
673 | uint64_t pre_free:1; | ||
674 | uint64_t ctl_smac:1; | ||
675 | uint64_t ctl_mcst:1; | ||
676 | uint64_t ctl_bck:1; | ||
677 | uint64_t ctl_drp:1; | ||
678 | uint64_t pre_strp:1; | ||
679 | uint64_t pre_chk:1; | ||
680 | } cn30xx; | ||
681 | struct cvmx_gmxx_rxx_frm_ctl_cn31xx { | ||
682 | uint64_t reserved_8_63:56; | ||
683 | uint64_t vlan_len:1; | ||
684 | uint64_t pre_free:1; | ||
685 | uint64_t ctl_smac:1; | ||
686 | uint64_t ctl_mcst:1; | ||
687 | uint64_t ctl_bck:1; | ||
688 | uint64_t ctl_drp:1; | ||
689 | uint64_t pre_strp:1; | ||
690 | uint64_t pre_chk:1; | ||
691 | } cn31xx; | ||
692 | struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx; | ||
693 | struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2; | ||
694 | struct cvmx_gmxx_rxx_frm_ctl_cn50xx { | ||
695 | uint64_t reserved_11_63:53; | ||
696 | uint64_t null_dis:1; | ||
697 | uint64_t pre_align:1; | ||
698 | uint64_t reserved_7_8:2; | ||
699 | uint64_t pre_free:1; | ||
700 | uint64_t ctl_smac:1; | ||
701 | uint64_t ctl_mcst:1; | ||
702 | uint64_t ctl_bck:1; | ||
703 | uint64_t ctl_drp:1; | ||
704 | uint64_t pre_strp:1; | ||
705 | uint64_t pre_chk:1; | ||
706 | } cn50xx; | ||
707 | struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx; | ||
708 | struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1; | ||
709 | struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx; | ||
710 | struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { | ||
711 | uint64_t reserved_10_63:54; | ||
712 | uint64_t pre_align:1; | ||
713 | uint64_t reserved_7_8:2; | ||
714 | uint64_t pre_free:1; | ||
715 | uint64_t ctl_smac:1; | ||
716 | uint64_t ctl_mcst:1; | ||
717 | uint64_t ctl_bck:1; | ||
718 | uint64_t ctl_drp:1; | ||
719 | uint64_t pre_strp:1; | ||
720 | uint64_t pre_chk:1; | ||
721 | } cn56xxp1; | ||
722 | struct cvmx_gmxx_rxx_frm_ctl_s cn58xx; | ||
723 | struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1; | ||
724 | }; | ||
725 | |||
726 | union cvmx_gmxx_rxx_frm_max { | ||
727 | uint64_t u64; | ||
728 | struct cvmx_gmxx_rxx_frm_max_s { | ||
729 | uint64_t reserved_16_63:48; | ||
730 | uint64_t len:16; | ||
731 | } s; | ||
732 | struct cvmx_gmxx_rxx_frm_max_s cn30xx; | ||
733 | struct cvmx_gmxx_rxx_frm_max_s cn31xx; | ||
734 | struct cvmx_gmxx_rxx_frm_max_s cn38xx; | ||
735 | struct cvmx_gmxx_rxx_frm_max_s cn38xxp2; | ||
736 | struct cvmx_gmxx_rxx_frm_max_s cn58xx; | ||
737 | struct cvmx_gmxx_rxx_frm_max_s cn58xxp1; | ||
738 | }; | ||
739 | |||
740 | union cvmx_gmxx_rxx_frm_min { | ||
741 | uint64_t u64; | ||
742 | struct cvmx_gmxx_rxx_frm_min_s { | ||
743 | uint64_t reserved_16_63:48; | ||
744 | uint64_t len:16; | ||
745 | } s; | ||
746 | struct cvmx_gmxx_rxx_frm_min_s cn30xx; | ||
747 | struct cvmx_gmxx_rxx_frm_min_s cn31xx; | ||
748 | struct cvmx_gmxx_rxx_frm_min_s cn38xx; | ||
749 | struct cvmx_gmxx_rxx_frm_min_s cn38xxp2; | ||
750 | struct cvmx_gmxx_rxx_frm_min_s cn58xx; | ||
751 | struct cvmx_gmxx_rxx_frm_min_s cn58xxp1; | ||
752 | }; | ||
753 | |||
754 | union cvmx_gmxx_rxx_ifg { | ||
755 | uint64_t u64; | ||
756 | struct cvmx_gmxx_rxx_ifg_s { | ||
757 | uint64_t reserved_4_63:60; | ||
758 | uint64_t ifg:4; | ||
759 | } s; | ||
760 | struct cvmx_gmxx_rxx_ifg_s cn30xx; | ||
761 | struct cvmx_gmxx_rxx_ifg_s cn31xx; | ||
762 | struct cvmx_gmxx_rxx_ifg_s cn38xx; | ||
763 | struct cvmx_gmxx_rxx_ifg_s cn38xxp2; | ||
764 | struct cvmx_gmxx_rxx_ifg_s cn50xx; | ||
765 | struct cvmx_gmxx_rxx_ifg_s cn52xx; | ||
766 | struct cvmx_gmxx_rxx_ifg_s cn52xxp1; | ||
767 | struct cvmx_gmxx_rxx_ifg_s cn56xx; | ||
768 | struct cvmx_gmxx_rxx_ifg_s cn56xxp1; | ||
769 | struct cvmx_gmxx_rxx_ifg_s cn58xx; | ||
770 | struct cvmx_gmxx_rxx_ifg_s cn58xxp1; | ||
771 | }; | ||
772 | |||
773 | union cvmx_gmxx_rxx_int_en { | ||
774 | uint64_t u64; | ||
775 | struct cvmx_gmxx_rxx_int_en_s { | ||
776 | uint64_t reserved_29_63:35; | ||
777 | uint64_t hg2cc:1; | ||
778 | uint64_t hg2fld:1; | ||
779 | uint64_t undat:1; | ||
780 | uint64_t uneop:1; | ||
781 | uint64_t unsop:1; | ||
782 | uint64_t bad_term:1; | ||
783 | uint64_t bad_seq:1; | ||
784 | uint64_t rem_fault:1; | ||
785 | uint64_t loc_fault:1; | ||
786 | uint64_t pause_drp:1; | ||
787 | uint64_t phy_dupx:1; | ||
788 | uint64_t phy_spd:1; | ||
789 | uint64_t phy_link:1; | ||
790 | uint64_t ifgerr:1; | ||
791 | uint64_t coldet:1; | ||
792 | uint64_t falerr:1; | ||
793 | uint64_t rsverr:1; | ||
794 | uint64_t pcterr:1; | ||
795 | uint64_t ovrerr:1; | ||
796 | uint64_t niberr:1; | ||
797 | uint64_t skperr:1; | ||
798 | uint64_t rcverr:1; | ||
799 | uint64_t lenerr:1; | ||
800 | uint64_t alnerr:1; | ||
801 | uint64_t fcserr:1; | ||
802 | uint64_t jabber:1; | ||
803 | uint64_t maxerr:1; | ||
804 | uint64_t carext:1; | ||
805 | uint64_t minerr:1; | ||
806 | } s; | ||
807 | struct cvmx_gmxx_rxx_int_en_cn30xx { | ||
808 | uint64_t reserved_19_63:45; | ||
809 | uint64_t phy_dupx:1; | ||
810 | uint64_t phy_spd:1; | ||
811 | uint64_t phy_link:1; | ||
812 | uint64_t ifgerr:1; | ||
813 | uint64_t coldet:1; | ||
814 | uint64_t falerr:1; | ||
815 | uint64_t rsverr:1; | ||
816 | uint64_t pcterr:1; | ||
817 | uint64_t ovrerr:1; | ||
818 | uint64_t niberr:1; | ||
819 | uint64_t skperr:1; | ||
820 | uint64_t rcverr:1; | ||
821 | uint64_t lenerr:1; | ||
822 | uint64_t alnerr:1; | ||
823 | uint64_t fcserr:1; | ||
824 | uint64_t jabber:1; | ||
825 | uint64_t maxerr:1; | ||
826 | uint64_t carext:1; | ||
827 | uint64_t minerr:1; | ||
828 | } cn30xx; | ||
829 | struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx; | ||
830 | struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx; | ||
831 | struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2; | ||
832 | struct cvmx_gmxx_rxx_int_en_cn50xx { | ||
833 | uint64_t reserved_20_63:44; | ||
834 | uint64_t pause_drp:1; | ||
835 | uint64_t phy_dupx:1; | ||
836 | uint64_t phy_spd:1; | ||
837 | uint64_t phy_link:1; | ||
838 | uint64_t ifgerr:1; | ||
839 | uint64_t coldet:1; | ||
840 | uint64_t falerr:1; | ||
841 | uint64_t rsverr:1; | ||
842 | uint64_t pcterr:1; | ||
843 | uint64_t ovrerr:1; | ||
844 | uint64_t niberr:1; | ||
845 | uint64_t skperr:1; | ||
846 | uint64_t rcverr:1; | ||
847 | uint64_t reserved_6_6:1; | ||
848 | uint64_t alnerr:1; | ||
849 | uint64_t fcserr:1; | ||
850 | uint64_t jabber:1; | ||
851 | uint64_t reserved_2_2:1; | ||
852 | uint64_t carext:1; | ||
853 | uint64_t reserved_0_0:1; | ||
854 | } cn50xx; | ||
855 | struct cvmx_gmxx_rxx_int_en_cn52xx { | ||
856 | uint64_t reserved_29_63:35; | ||
857 | uint64_t hg2cc:1; | ||
858 | uint64_t hg2fld:1; | ||
859 | uint64_t undat:1; | ||
860 | uint64_t uneop:1; | ||
861 | uint64_t unsop:1; | ||
862 | uint64_t bad_term:1; | ||
863 | uint64_t bad_seq:1; | ||
864 | uint64_t rem_fault:1; | ||
865 | uint64_t loc_fault:1; | ||
866 | uint64_t pause_drp:1; | ||
867 | uint64_t reserved_16_18:3; | ||
868 | uint64_t ifgerr:1; | ||
869 | uint64_t coldet:1; | ||
870 | uint64_t falerr:1; | ||
871 | uint64_t rsverr:1; | ||
872 | uint64_t pcterr:1; | ||
873 | uint64_t ovrerr:1; | ||
874 | uint64_t reserved_9_9:1; | ||
875 | uint64_t skperr:1; | ||
876 | uint64_t rcverr:1; | ||
877 | uint64_t reserved_5_6:2; | ||
878 | uint64_t fcserr:1; | ||
879 | uint64_t jabber:1; | ||
880 | uint64_t reserved_2_2:1; | ||
881 | uint64_t carext:1; | ||
882 | uint64_t reserved_0_0:1; | ||
883 | } cn52xx; | ||
884 | struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1; | ||
885 | struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx; | ||
886 | struct cvmx_gmxx_rxx_int_en_cn56xxp1 { | ||
887 | uint64_t reserved_27_63:37; | ||
888 | uint64_t undat:1; | ||
889 | uint64_t uneop:1; | ||
890 | uint64_t unsop:1; | ||
891 | uint64_t bad_term:1; | ||
892 | uint64_t bad_seq:1; | ||
893 | uint64_t rem_fault:1; | ||
894 | uint64_t loc_fault:1; | ||
895 | uint64_t pause_drp:1; | ||
896 | uint64_t reserved_16_18:3; | ||
897 | uint64_t ifgerr:1; | ||
898 | uint64_t coldet:1; | ||
899 | uint64_t falerr:1; | ||
900 | uint64_t rsverr:1; | ||
901 | uint64_t pcterr:1; | ||
902 | uint64_t ovrerr:1; | ||
903 | uint64_t reserved_9_9:1; | ||
904 | uint64_t skperr:1; | ||
905 | uint64_t rcverr:1; | ||
906 | uint64_t reserved_5_6:2; | ||
907 | uint64_t fcserr:1; | ||
908 | uint64_t jabber:1; | ||
909 | uint64_t reserved_2_2:1; | ||
910 | uint64_t carext:1; | ||
911 | uint64_t reserved_0_0:1; | ||
912 | } cn56xxp1; | ||
913 | struct cvmx_gmxx_rxx_int_en_cn58xx { | ||
914 | uint64_t reserved_20_63:44; | ||
915 | uint64_t pause_drp:1; | ||
916 | uint64_t phy_dupx:1; | ||
917 | uint64_t phy_spd:1; | ||
918 | uint64_t phy_link:1; | ||
919 | uint64_t ifgerr:1; | ||
920 | uint64_t coldet:1; | ||
921 | uint64_t falerr:1; | ||
922 | uint64_t rsverr:1; | ||
923 | uint64_t pcterr:1; | ||
924 | uint64_t ovrerr:1; | ||
925 | uint64_t niberr:1; | ||
926 | uint64_t skperr:1; | ||
927 | uint64_t rcverr:1; | ||
928 | uint64_t lenerr:1; | ||
929 | uint64_t alnerr:1; | ||
930 | uint64_t fcserr:1; | ||
931 | uint64_t jabber:1; | ||
932 | uint64_t maxerr:1; | ||
933 | uint64_t carext:1; | ||
934 | uint64_t minerr:1; | ||
935 | } cn58xx; | ||
936 | struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1; | ||
937 | }; | ||
938 | |||
939 | union cvmx_gmxx_rxx_int_reg { | ||
940 | uint64_t u64; | ||
941 | struct cvmx_gmxx_rxx_int_reg_s { | ||
942 | uint64_t reserved_29_63:35; | ||
943 | uint64_t hg2cc:1; | ||
944 | uint64_t hg2fld:1; | ||
945 | uint64_t undat:1; | ||
946 | uint64_t uneop:1; | ||
947 | uint64_t unsop:1; | ||
948 | uint64_t bad_term:1; | ||
949 | uint64_t bad_seq:1; | ||
950 | uint64_t rem_fault:1; | ||
951 | uint64_t loc_fault:1; | ||
952 | uint64_t pause_drp:1; | ||
953 | uint64_t phy_dupx:1; | ||
954 | uint64_t phy_spd:1; | ||
955 | uint64_t phy_link:1; | ||
956 | uint64_t ifgerr:1; | ||
957 | uint64_t coldet:1; | ||
958 | uint64_t falerr:1; | ||
959 | uint64_t rsverr:1; | ||
960 | uint64_t pcterr:1; | ||
961 | uint64_t ovrerr:1; | ||
962 | uint64_t niberr:1; | ||
963 | uint64_t skperr:1; | ||
964 | uint64_t rcverr:1; | ||
965 | uint64_t lenerr:1; | ||
966 | uint64_t alnerr:1; | ||
967 | uint64_t fcserr:1; | ||
968 | uint64_t jabber:1; | ||
969 | uint64_t maxerr:1; | ||
970 | uint64_t carext:1; | ||
971 | uint64_t minerr:1; | ||
972 | } s; | ||
973 | struct cvmx_gmxx_rxx_int_reg_cn30xx { | ||
974 | uint64_t reserved_19_63:45; | ||
975 | uint64_t phy_dupx:1; | ||
976 | uint64_t phy_spd:1; | ||
977 | uint64_t phy_link:1; | ||
978 | uint64_t ifgerr:1; | ||
979 | uint64_t coldet:1; | ||
980 | uint64_t falerr:1; | ||
981 | uint64_t rsverr:1; | ||
982 | uint64_t pcterr:1; | ||
983 | uint64_t ovrerr:1; | ||
984 | uint64_t niberr:1; | ||
985 | uint64_t skperr:1; | ||
986 | uint64_t rcverr:1; | ||
987 | uint64_t lenerr:1; | ||
988 | uint64_t alnerr:1; | ||
989 | uint64_t fcserr:1; | ||
990 | uint64_t jabber:1; | ||
991 | uint64_t maxerr:1; | ||
992 | uint64_t carext:1; | ||
993 | uint64_t minerr:1; | ||
994 | } cn30xx; | ||
995 | struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx; | ||
996 | struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx; | ||
997 | struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2; | ||
998 | struct cvmx_gmxx_rxx_int_reg_cn50xx { | ||
999 | uint64_t reserved_20_63:44; | ||
1000 | uint64_t pause_drp:1; | ||
1001 | uint64_t phy_dupx:1; | ||
1002 | uint64_t phy_spd:1; | ||
1003 | uint64_t phy_link:1; | ||
1004 | uint64_t ifgerr:1; | ||
1005 | uint64_t coldet:1; | ||
1006 | uint64_t falerr:1; | ||
1007 | uint64_t rsverr:1; | ||
1008 | uint64_t pcterr:1; | ||
1009 | uint64_t ovrerr:1; | ||
1010 | uint64_t niberr:1; | ||
1011 | uint64_t skperr:1; | ||
1012 | uint64_t rcverr:1; | ||
1013 | uint64_t reserved_6_6:1; | ||
1014 | uint64_t alnerr:1; | ||
1015 | uint64_t fcserr:1; | ||
1016 | uint64_t jabber:1; | ||
1017 | uint64_t reserved_2_2:1; | ||
1018 | uint64_t carext:1; | ||
1019 | uint64_t reserved_0_0:1; | ||
1020 | } cn50xx; | ||
1021 | struct cvmx_gmxx_rxx_int_reg_cn52xx { | ||
1022 | uint64_t reserved_29_63:35; | ||
1023 | uint64_t hg2cc:1; | ||
1024 | uint64_t hg2fld:1; | ||
1025 | uint64_t undat:1; | ||
1026 | uint64_t uneop:1; | ||
1027 | uint64_t unsop:1; | ||
1028 | uint64_t bad_term:1; | ||
1029 | uint64_t bad_seq:1; | ||
1030 | uint64_t rem_fault:1; | ||
1031 | uint64_t loc_fault:1; | ||
1032 | uint64_t pause_drp:1; | ||
1033 | uint64_t reserved_16_18:3; | ||
1034 | uint64_t ifgerr:1; | ||
1035 | uint64_t coldet:1; | ||
1036 | uint64_t falerr:1; | ||
1037 | uint64_t rsverr:1; | ||
1038 | uint64_t pcterr:1; | ||
1039 | uint64_t ovrerr:1; | ||
1040 | uint64_t reserved_9_9:1; | ||
1041 | uint64_t skperr:1; | ||
1042 | uint64_t rcverr:1; | ||
1043 | uint64_t reserved_5_6:2; | ||
1044 | uint64_t fcserr:1; | ||
1045 | uint64_t jabber:1; | ||
1046 | uint64_t reserved_2_2:1; | ||
1047 | uint64_t carext:1; | ||
1048 | uint64_t reserved_0_0:1; | ||
1049 | } cn52xx; | ||
1050 | struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1; | ||
1051 | struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx; | ||
1052 | struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { | ||
1053 | uint64_t reserved_27_63:37; | ||
1054 | uint64_t undat:1; | ||
1055 | uint64_t uneop:1; | ||
1056 | uint64_t unsop:1; | ||
1057 | uint64_t bad_term:1; | ||
1058 | uint64_t bad_seq:1; | ||
1059 | uint64_t rem_fault:1; | ||
1060 | uint64_t loc_fault:1; | ||
1061 | uint64_t pause_drp:1; | ||
1062 | uint64_t reserved_16_18:3; | ||
1063 | uint64_t ifgerr:1; | ||
1064 | uint64_t coldet:1; | ||
1065 | uint64_t falerr:1; | ||
1066 | uint64_t rsverr:1; | ||
1067 | uint64_t pcterr:1; | ||
1068 | uint64_t ovrerr:1; | ||
1069 | uint64_t reserved_9_9:1; | ||
1070 | uint64_t skperr:1; | ||
1071 | uint64_t rcverr:1; | ||
1072 | uint64_t reserved_5_6:2; | ||
1073 | uint64_t fcserr:1; | ||
1074 | uint64_t jabber:1; | ||
1075 | uint64_t reserved_2_2:1; | ||
1076 | uint64_t carext:1; | ||
1077 | uint64_t reserved_0_0:1; | ||
1078 | } cn56xxp1; | ||
1079 | struct cvmx_gmxx_rxx_int_reg_cn58xx { | ||
1080 | uint64_t reserved_20_63:44; | ||
1081 | uint64_t pause_drp:1; | ||
1082 | uint64_t phy_dupx:1; | ||
1083 | uint64_t phy_spd:1; | ||
1084 | uint64_t phy_link:1; | ||
1085 | uint64_t ifgerr:1; | ||
1086 | uint64_t coldet:1; | ||
1087 | uint64_t falerr:1; | ||
1088 | uint64_t rsverr:1; | ||
1089 | uint64_t pcterr:1; | ||
1090 | uint64_t ovrerr:1; | ||
1091 | uint64_t niberr:1; | ||
1092 | uint64_t skperr:1; | ||
1093 | uint64_t rcverr:1; | ||
1094 | uint64_t lenerr:1; | ||
1095 | uint64_t alnerr:1; | ||
1096 | uint64_t fcserr:1; | ||
1097 | uint64_t jabber:1; | ||
1098 | uint64_t maxerr:1; | ||
1099 | uint64_t carext:1; | ||
1100 | uint64_t minerr:1; | ||
1101 | } cn58xx; | ||
1102 | struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1; | ||
1103 | }; | ||
1104 | |||
1105 | union cvmx_gmxx_rxx_jabber { | ||
1106 | uint64_t u64; | ||
1107 | struct cvmx_gmxx_rxx_jabber_s { | ||
1108 | uint64_t reserved_16_63:48; | ||
1109 | uint64_t cnt:16; | ||
1110 | } s; | ||
1111 | struct cvmx_gmxx_rxx_jabber_s cn30xx; | ||
1112 | struct cvmx_gmxx_rxx_jabber_s cn31xx; | ||
1113 | struct cvmx_gmxx_rxx_jabber_s cn38xx; | ||
1114 | struct cvmx_gmxx_rxx_jabber_s cn38xxp2; | ||
1115 | struct cvmx_gmxx_rxx_jabber_s cn50xx; | ||
1116 | struct cvmx_gmxx_rxx_jabber_s cn52xx; | ||
1117 | struct cvmx_gmxx_rxx_jabber_s cn52xxp1; | ||
1118 | struct cvmx_gmxx_rxx_jabber_s cn56xx; | ||
1119 | struct cvmx_gmxx_rxx_jabber_s cn56xxp1; | ||
1120 | struct cvmx_gmxx_rxx_jabber_s cn58xx; | ||
1121 | struct cvmx_gmxx_rxx_jabber_s cn58xxp1; | ||
1122 | }; | ||
1123 | |||
1124 | union cvmx_gmxx_rxx_pause_drop_time { | ||
1125 | uint64_t u64; | ||
1126 | struct cvmx_gmxx_rxx_pause_drop_time_s { | ||
1127 | uint64_t reserved_16_63:48; | ||
1128 | uint64_t status:16; | ||
1129 | } s; | ||
1130 | struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx; | ||
1131 | struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx; | ||
1132 | struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1; | ||
1133 | struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx; | ||
1134 | struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1; | ||
1135 | struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx; | ||
1136 | struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1; | ||
1137 | }; | ||
1138 | |||
1139 | union cvmx_gmxx_rxx_rx_inbnd { | ||
1140 | uint64_t u64; | ||
1141 | struct cvmx_gmxx_rxx_rx_inbnd_s { | ||
1142 | uint64_t reserved_4_63:60; | ||
1143 | uint64_t duplex:1; | ||
1144 | uint64_t speed:2; | ||
1145 | uint64_t status:1; | ||
1146 | } s; | ||
1147 | struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx; | ||
1148 | struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx; | ||
1149 | struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx; | ||
1150 | struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2; | ||
1151 | struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx; | ||
1152 | struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx; | ||
1153 | struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1; | ||
1154 | }; | ||
1155 | |||
1156 | union cvmx_gmxx_rxx_stats_ctl { | ||
1157 | uint64_t u64; | ||
1158 | struct cvmx_gmxx_rxx_stats_ctl_s { | ||
1159 | uint64_t reserved_1_63:63; | ||
1160 | uint64_t rd_clr:1; | ||
1161 | } s; | ||
1162 | struct cvmx_gmxx_rxx_stats_ctl_s cn30xx; | ||
1163 | struct cvmx_gmxx_rxx_stats_ctl_s cn31xx; | ||
1164 | struct cvmx_gmxx_rxx_stats_ctl_s cn38xx; | ||
1165 | struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2; | ||
1166 | struct cvmx_gmxx_rxx_stats_ctl_s cn50xx; | ||
1167 | struct cvmx_gmxx_rxx_stats_ctl_s cn52xx; | ||
1168 | struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1; | ||
1169 | struct cvmx_gmxx_rxx_stats_ctl_s cn56xx; | ||
1170 | struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1; | ||
1171 | struct cvmx_gmxx_rxx_stats_ctl_s cn58xx; | ||
1172 | struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1; | ||
1173 | }; | ||
1174 | |||
1175 | union cvmx_gmxx_rxx_stats_octs { | ||
1176 | uint64_t u64; | ||
1177 | struct cvmx_gmxx_rxx_stats_octs_s { | ||
1178 | uint64_t reserved_48_63:16; | ||
1179 | uint64_t cnt:48; | ||
1180 | } s; | ||
1181 | struct cvmx_gmxx_rxx_stats_octs_s cn30xx; | ||
1182 | struct cvmx_gmxx_rxx_stats_octs_s cn31xx; | ||
1183 | struct cvmx_gmxx_rxx_stats_octs_s cn38xx; | ||
1184 | struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2; | ||
1185 | struct cvmx_gmxx_rxx_stats_octs_s cn50xx; | ||
1186 | struct cvmx_gmxx_rxx_stats_octs_s cn52xx; | ||
1187 | struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1; | ||
1188 | struct cvmx_gmxx_rxx_stats_octs_s cn56xx; | ||
1189 | struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1; | ||
1190 | struct cvmx_gmxx_rxx_stats_octs_s cn58xx; | ||
1191 | struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1; | ||
1192 | }; | ||
1193 | |||
1194 | union cvmx_gmxx_rxx_stats_octs_ctl { | ||
1195 | uint64_t u64; | ||
1196 | struct cvmx_gmxx_rxx_stats_octs_ctl_s { | ||
1197 | uint64_t reserved_48_63:16; | ||
1198 | uint64_t cnt:48; | ||
1199 | } s; | ||
1200 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx; | ||
1201 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx; | ||
1202 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx; | ||
1203 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2; | ||
1204 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx; | ||
1205 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx; | ||
1206 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1; | ||
1207 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx; | ||
1208 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1; | ||
1209 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx; | ||
1210 | struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1; | ||
1211 | }; | ||
1212 | |||
1213 | union cvmx_gmxx_rxx_stats_octs_dmac { | ||
1214 | uint64_t u64; | ||
1215 | struct cvmx_gmxx_rxx_stats_octs_dmac_s { | ||
1216 | uint64_t reserved_48_63:16; | ||
1217 | uint64_t cnt:48; | ||
1218 | } s; | ||
1219 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx; | ||
1220 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx; | ||
1221 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx; | ||
1222 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2; | ||
1223 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx; | ||
1224 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx; | ||
1225 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1; | ||
1226 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx; | ||
1227 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1; | ||
1228 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx; | ||
1229 | struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1; | ||
1230 | }; | ||
1231 | |||
1232 | union cvmx_gmxx_rxx_stats_octs_drp { | ||
1233 | uint64_t u64; | ||
1234 | struct cvmx_gmxx_rxx_stats_octs_drp_s { | ||
1235 | uint64_t reserved_48_63:16; | ||
1236 | uint64_t cnt:48; | ||
1237 | } s; | ||
1238 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx; | ||
1239 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx; | ||
1240 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx; | ||
1241 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2; | ||
1242 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx; | ||
1243 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx; | ||
1244 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1; | ||
1245 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx; | ||
1246 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1; | ||
1247 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx; | ||
1248 | struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1; | ||
1249 | }; | ||
1250 | |||
1251 | union cvmx_gmxx_rxx_stats_pkts { | ||
1252 | uint64_t u64; | ||
1253 | struct cvmx_gmxx_rxx_stats_pkts_s { | ||
1254 | uint64_t reserved_32_63:32; | ||
1255 | uint64_t cnt:32; | ||
1256 | } s; | ||
1257 | struct cvmx_gmxx_rxx_stats_pkts_s cn30xx; | ||
1258 | struct cvmx_gmxx_rxx_stats_pkts_s cn31xx; | ||
1259 | struct cvmx_gmxx_rxx_stats_pkts_s cn38xx; | ||
1260 | struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2; | ||
1261 | struct cvmx_gmxx_rxx_stats_pkts_s cn50xx; | ||
1262 | struct cvmx_gmxx_rxx_stats_pkts_s cn52xx; | ||
1263 | struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1; | ||
1264 | struct cvmx_gmxx_rxx_stats_pkts_s cn56xx; | ||
1265 | struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1; | ||
1266 | struct cvmx_gmxx_rxx_stats_pkts_s cn58xx; | ||
1267 | struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1; | ||
1268 | }; | ||
1269 | |||
1270 | union cvmx_gmxx_rxx_stats_pkts_bad { | ||
1271 | uint64_t u64; | ||
1272 | struct cvmx_gmxx_rxx_stats_pkts_bad_s { | ||
1273 | uint64_t reserved_32_63:32; | ||
1274 | uint64_t cnt:32; | ||
1275 | } s; | ||
1276 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx; | ||
1277 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx; | ||
1278 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx; | ||
1279 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2; | ||
1280 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx; | ||
1281 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx; | ||
1282 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1; | ||
1283 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx; | ||
1284 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1; | ||
1285 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx; | ||
1286 | struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1; | ||
1287 | }; | ||
1288 | |||
1289 | union cvmx_gmxx_rxx_stats_pkts_ctl { | ||
1290 | uint64_t u64; | ||
1291 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s { | ||
1292 | uint64_t reserved_32_63:32; | ||
1293 | uint64_t cnt:32; | ||
1294 | } s; | ||
1295 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx; | ||
1296 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx; | ||
1297 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx; | ||
1298 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2; | ||
1299 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx; | ||
1300 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx; | ||
1301 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1; | ||
1302 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx; | ||
1303 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1; | ||
1304 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx; | ||
1305 | struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1; | ||
1306 | }; | ||
1307 | |||
1308 | union cvmx_gmxx_rxx_stats_pkts_dmac { | ||
1309 | uint64_t u64; | ||
1310 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s { | ||
1311 | uint64_t reserved_32_63:32; | ||
1312 | uint64_t cnt:32; | ||
1313 | } s; | ||
1314 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx; | ||
1315 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx; | ||
1316 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx; | ||
1317 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2; | ||
1318 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx; | ||
1319 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx; | ||
1320 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1; | ||
1321 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx; | ||
1322 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1; | ||
1323 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx; | ||
1324 | struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1; | ||
1325 | }; | ||
1326 | |||
1327 | union cvmx_gmxx_rxx_stats_pkts_drp { | ||
1328 | uint64_t u64; | ||
1329 | struct cvmx_gmxx_rxx_stats_pkts_drp_s { | ||
1330 | uint64_t reserved_32_63:32; | ||
1331 | uint64_t cnt:32; | ||
1332 | } s; | ||
1333 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx; | ||
1334 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx; | ||
1335 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx; | ||
1336 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2; | ||
1337 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx; | ||
1338 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx; | ||
1339 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1; | ||
1340 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx; | ||
1341 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1; | ||
1342 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx; | ||
1343 | struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1; | ||
1344 | }; | ||
1345 | |||
1346 | union cvmx_gmxx_rxx_udd_skp { | ||
1347 | uint64_t u64; | ||
1348 | struct cvmx_gmxx_rxx_udd_skp_s { | ||
1349 | uint64_t reserved_9_63:55; | ||
1350 | uint64_t fcssel:1; | ||
1351 | uint64_t reserved_7_7:1; | ||
1352 | uint64_t len:7; | ||
1353 | } s; | ||
1354 | struct cvmx_gmxx_rxx_udd_skp_s cn30xx; | ||
1355 | struct cvmx_gmxx_rxx_udd_skp_s cn31xx; | ||
1356 | struct cvmx_gmxx_rxx_udd_skp_s cn38xx; | ||
1357 | struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2; | ||
1358 | struct cvmx_gmxx_rxx_udd_skp_s cn50xx; | ||
1359 | struct cvmx_gmxx_rxx_udd_skp_s cn52xx; | ||
1360 | struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1; | ||
1361 | struct cvmx_gmxx_rxx_udd_skp_s cn56xx; | ||
1362 | struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1; | ||
1363 | struct cvmx_gmxx_rxx_udd_skp_s cn58xx; | ||
1364 | struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1; | ||
1365 | }; | ||
1366 | |||
1367 | union cvmx_gmxx_rx_bp_dropx { | ||
1368 | uint64_t u64; | ||
1369 | struct cvmx_gmxx_rx_bp_dropx_s { | ||
1370 | uint64_t reserved_6_63:58; | ||
1371 | uint64_t mark:6; | ||
1372 | } s; | ||
1373 | struct cvmx_gmxx_rx_bp_dropx_s cn30xx; | ||
1374 | struct cvmx_gmxx_rx_bp_dropx_s cn31xx; | ||
1375 | struct cvmx_gmxx_rx_bp_dropx_s cn38xx; | ||
1376 | struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2; | ||
1377 | struct cvmx_gmxx_rx_bp_dropx_s cn50xx; | ||
1378 | struct cvmx_gmxx_rx_bp_dropx_s cn52xx; | ||
1379 | struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1; | ||
1380 | struct cvmx_gmxx_rx_bp_dropx_s cn56xx; | ||
1381 | struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1; | ||
1382 | struct cvmx_gmxx_rx_bp_dropx_s cn58xx; | ||
1383 | struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1; | ||
1384 | }; | ||
1385 | |||
1386 | union cvmx_gmxx_rx_bp_offx { | ||
1387 | uint64_t u64; | ||
1388 | struct cvmx_gmxx_rx_bp_offx_s { | ||
1389 | uint64_t reserved_6_63:58; | ||
1390 | uint64_t mark:6; | ||
1391 | } s; | ||
1392 | struct cvmx_gmxx_rx_bp_offx_s cn30xx; | ||
1393 | struct cvmx_gmxx_rx_bp_offx_s cn31xx; | ||
1394 | struct cvmx_gmxx_rx_bp_offx_s cn38xx; | ||
1395 | struct cvmx_gmxx_rx_bp_offx_s cn38xxp2; | ||
1396 | struct cvmx_gmxx_rx_bp_offx_s cn50xx; | ||
1397 | struct cvmx_gmxx_rx_bp_offx_s cn52xx; | ||
1398 | struct cvmx_gmxx_rx_bp_offx_s cn52xxp1; | ||
1399 | struct cvmx_gmxx_rx_bp_offx_s cn56xx; | ||
1400 | struct cvmx_gmxx_rx_bp_offx_s cn56xxp1; | ||
1401 | struct cvmx_gmxx_rx_bp_offx_s cn58xx; | ||
1402 | struct cvmx_gmxx_rx_bp_offx_s cn58xxp1; | ||
1403 | }; | ||
1404 | |||
1405 | union cvmx_gmxx_rx_bp_onx { | ||
1406 | uint64_t u64; | ||
1407 | struct cvmx_gmxx_rx_bp_onx_s { | ||
1408 | uint64_t reserved_9_63:55; | ||
1409 | uint64_t mark:9; | ||
1410 | } s; | ||
1411 | struct cvmx_gmxx_rx_bp_onx_s cn30xx; | ||
1412 | struct cvmx_gmxx_rx_bp_onx_s cn31xx; | ||
1413 | struct cvmx_gmxx_rx_bp_onx_s cn38xx; | ||
1414 | struct cvmx_gmxx_rx_bp_onx_s cn38xxp2; | ||
1415 | struct cvmx_gmxx_rx_bp_onx_s cn50xx; | ||
1416 | struct cvmx_gmxx_rx_bp_onx_s cn52xx; | ||
1417 | struct cvmx_gmxx_rx_bp_onx_s cn52xxp1; | ||
1418 | struct cvmx_gmxx_rx_bp_onx_s cn56xx; | ||
1419 | struct cvmx_gmxx_rx_bp_onx_s cn56xxp1; | ||
1420 | struct cvmx_gmxx_rx_bp_onx_s cn58xx; | ||
1421 | struct cvmx_gmxx_rx_bp_onx_s cn58xxp1; | ||
1422 | }; | ||
1423 | |||
1424 | union cvmx_gmxx_rx_hg2_status { | ||
1425 | uint64_t u64; | ||
1426 | struct cvmx_gmxx_rx_hg2_status_s { | ||
1427 | uint64_t reserved_48_63:16; | ||
1428 | uint64_t phtim2go:16; | ||
1429 | uint64_t xof:16; | ||
1430 | uint64_t lgtim2go:16; | ||
1431 | } s; | ||
1432 | struct cvmx_gmxx_rx_hg2_status_s cn52xx; | ||
1433 | struct cvmx_gmxx_rx_hg2_status_s cn52xxp1; | ||
1434 | struct cvmx_gmxx_rx_hg2_status_s cn56xx; | ||
1435 | }; | ||
1436 | |||
1437 | union cvmx_gmxx_rx_pass_en { | ||
1438 | uint64_t u64; | ||
1439 | struct cvmx_gmxx_rx_pass_en_s { | ||
1440 | uint64_t reserved_16_63:48; | ||
1441 | uint64_t en:16; | ||
1442 | } s; | ||
1443 | struct cvmx_gmxx_rx_pass_en_s cn38xx; | ||
1444 | struct cvmx_gmxx_rx_pass_en_s cn38xxp2; | ||
1445 | struct cvmx_gmxx_rx_pass_en_s cn58xx; | ||
1446 | struct cvmx_gmxx_rx_pass_en_s cn58xxp1; | ||
1447 | }; | ||
1448 | |||
1449 | union cvmx_gmxx_rx_pass_mapx { | ||
1450 | uint64_t u64; | ||
1451 | struct cvmx_gmxx_rx_pass_mapx_s { | ||
1452 | uint64_t reserved_4_63:60; | ||
1453 | uint64_t dprt:4; | ||
1454 | } s; | ||
1455 | struct cvmx_gmxx_rx_pass_mapx_s cn38xx; | ||
1456 | struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2; | ||
1457 | struct cvmx_gmxx_rx_pass_mapx_s cn58xx; | ||
1458 | struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1; | ||
1459 | }; | ||
1460 | |||
1461 | union cvmx_gmxx_rx_prt_info { | ||
1462 | uint64_t u64; | ||
1463 | struct cvmx_gmxx_rx_prt_info_s { | ||
1464 | uint64_t reserved_32_63:32; | ||
1465 | uint64_t drop:16; | ||
1466 | uint64_t commit:16; | ||
1467 | } s; | ||
1468 | struct cvmx_gmxx_rx_prt_info_cn30xx { | ||
1469 | uint64_t reserved_19_63:45; | ||
1470 | uint64_t drop:3; | ||
1471 | uint64_t reserved_3_15:13; | ||
1472 | uint64_t commit:3; | ||
1473 | } cn30xx; | ||
1474 | struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx; | ||
1475 | struct cvmx_gmxx_rx_prt_info_s cn38xx; | ||
1476 | struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx; | ||
1477 | struct cvmx_gmxx_rx_prt_info_cn52xx { | ||
1478 | uint64_t reserved_20_63:44; | ||
1479 | uint64_t drop:4; | ||
1480 | uint64_t reserved_4_15:12; | ||
1481 | uint64_t commit:4; | ||
1482 | } cn52xx; | ||
1483 | struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1; | ||
1484 | struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx; | ||
1485 | struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1; | ||
1486 | struct cvmx_gmxx_rx_prt_info_s cn58xx; | ||
1487 | struct cvmx_gmxx_rx_prt_info_s cn58xxp1; | ||
1488 | }; | ||
1489 | |||
1490 | union cvmx_gmxx_rx_prts { | ||
1491 | uint64_t u64; | ||
1492 | struct cvmx_gmxx_rx_prts_s { | ||
1493 | uint64_t reserved_3_63:61; | ||
1494 | uint64_t prts:3; | ||
1495 | } s; | ||
1496 | struct cvmx_gmxx_rx_prts_s cn30xx; | ||
1497 | struct cvmx_gmxx_rx_prts_s cn31xx; | ||
1498 | struct cvmx_gmxx_rx_prts_s cn38xx; | ||
1499 | struct cvmx_gmxx_rx_prts_s cn38xxp2; | ||
1500 | struct cvmx_gmxx_rx_prts_s cn50xx; | ||
1501 | struct cvmx_gmxx_rx_prts_s cn52xx; | ||
1502 | struct cvmx_gmxx_rx_prts_s cn52xxp1; | ||
1503 | struct cvmx_gmxx_rx_prts_s cn56xx; | ||
1504 | struct cvmx_gmxx_rx_prts_s cn56xxp1; | ||
1505 | struct cvmx_gmxx_rx_prts_s cn58xx; | ||
1506 | struct cvmx_gmxx_rx_prts_s cn58xxp1; | ||
1507 | }; | ||
1508 | |||
1509 | union cvmx_gmxx_rx_tx_status { | ||
1510 | uint64_t u64; | ||
1511 | struct cvmx_gmxx_rx_tx_status_s { | ||
1512 | uint64_t reserved_7_63:57; | ||
1513 | uint64_t tx:3; | ||
1514 | uint64_t reserved_3_3:1; | ||
1515 | uint64_t rx:3; | ||
1516 | } s; | ||
1517 | struct cvmx_gmxx_rx_tx_status_s cn30xx; | ||
1518 | struct cvmx_gmxx_rx_tx_status_s cn31xx; | ||
1519 | struct cvmx_gmxx_rx_tx_status_s cn50xx; | ||
1520 | }; | ||
1521 | |||
1522 | union cvmx_gmxx_rx_xaui_bad_col { | ||
1523 | uint64_t u64; | ||
1524 | struct cvmx_gmxx_rx_xaui_bad_col_s { | ||
1525 | uint64_t reserved_40_63:24; | ||
1526 | uint64_t val:1; | ||
1527 | uint64_t state:3; | ||
1528 | uint64_t lane_rxc:4; | ||
1529 | uint64_t lane_rxd:32; | ||
1530 | } s; | ||
1531 | struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx; | ||
1532 | struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1; | ||
1533 | struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx; | ||
1534 | struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1; | ||
1535 | }; | ||
1536 | |||
1537 | union cvmx_gmxx_rx_xaui_ctl { | ||
1538 | uint64_t u64; | ||
1539 | struct cvmx_gmxx_rx_xaui_ctl_s { | ||
1540 | uint64_t reserved_2_63:62; | ||
1541 | uint64_t status:2; | ||
1542 | } s; | ||
1543 | struct cvmx_gmxx_rx_xaui_ctl_s cn52xx; | ||
1544 | struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1; | ||
1545 | struct cvmx_gmxx_rx_xaui_ctl_s cn56xx; | ||
1546 | struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1; | ||
1547 | }; | ||
1548 | |||
1549 | union cvmx_gmxx_smacx { | ||
1550 | uint64_t u64; | ||
1551 | struct cvmx_gmxx_smacx_s { | ||
1552 | uint64_t reserved_48_63:16; | ||
1553 | uint64_t smac:48; | ||
1554 | } s; | ||
1555 | struct cvmx_gmxx_smacx_s cn30xx; | ||
1556 | struct cvmx_gmxx_smacx_s cn31xx; | ||
1557 | struct cvmx_gmxx_smacx_s cn38xx; | ||
1558 | struct cvmx_gmxx_smacx_s cn38xxp2; | ||
1559 | struct cvmx_gmxx_smacx_s cn50xx; | ||
1560 | struct cvmx_gmxx_smacx_s cn52xx; | ||
1561 | struct cvmx_gmxx_smacx_s cn52xxp1; | ||
1562 | struct cvmx_gmxx_smacx_s cn56xx; | ||
1563 | struct cvmx_gmxx_smacx_s cn56xxp1; | ||
1564 | struct cvmx_gmxx_smacx_s cn58xx; | ||
1565 | struct cvmx_gmxx_smacx_s cn58xxp1; | ||
1566 | }; | ||
1567 | |||
1568 | union cvmx_gmxx_stat_bp { | ||
1569 | uint64_t u64; | ||
1570 | struct cvmx_gmxx_stat_bp_s { | ||
1571 | uint64_t reserved_17_63:47; | ||
1572 | uint64_t bp:1; | ||
1573 | uint64_t cnt:16; | ||
1574 | } s; | ||
1575 | struct cvmx_gmxx_stat_bp_s cn30xx; | ||
1576 | struct cvmx_gmxx_stat_bp_s cn31xx; | ||
1577 | struct cvmx_gmxx_stat_bp_s cn38xx; | ||
1578 | struct cvmx_gmxx_stat_bp_s cn38xxp2; | ||
1579 | struct cvmx_gmxx_stat_bp_s cn50xx; | ||
1580 | struct cvmx_gmxx_stat_bp_s cn52xx; | ||
1581 | struct cvmx_gmxx_stat_bp_s cn52xxp1; | ||
1582 | struct cvmx_gmxx_stat_bp_s cn56xx; | ||
1583 | struct cvmx_gmxx_stat_bp_s cn56xxp1; | ||
1584 | struct cvmx_gmxx_stat_bp_s cn58xx; | ||
1585 | struct cvmx_gmxx_stat_bp_s cn58xxp1; | ||
1586 | }; | ||
1587 | |||
1588 | union cvmx_gmxx_txx_append { | ||
1589 | uint64_t u64; | ||
1590 | struct cvmx_gmxx_txx_append_s { | ||
1591 | uint64_t reserved_4_63:60; | ||
1592 | uint64_t force_fcs:1; | ||
1593 | uint64_t fcs:1; | ||
1594 | uint64_t pad:1; | ||
1595 | uint64_t preamble:1; | ||
1596 | } s; | ||
1597 | struct cvmx_gmxx_txx_append_s cn30xx; | ||
1598 | struct cvmx_gmxx_txx_append_s cn31xx; | ||
1599 | struct cvmx_gmxx_txx_append_s cn38xx; | ||
1600 | struct cvmx_gmxx_txx_append_s cn38xxp2; | ||
1601 | struct cvmx_gmxx_txx_append_s cn50xx; | ||
1602 | struct cvmx_gmxx_txx_append_s cn52xx; | ||
1603 | struct cvmx_gmxx_txx_append_s cn52xxp1; | ||
1604 | struct cvmx_gmxx_txx_append_s cn56xx; | ||
1605 | struct cvmx_gmxx_txx_append_s cn56xxp1; | ||
1606 | struct cvmx_gmxx_txx_append_s cn58xx; | ||
1607 | struct cvmx_gmxx_txx_append_s cn58xxp1; | ||
1608 | }; | ||
1609 | |||
1610 | union cvmx_gmxx_txx_burst { | ||
1611 | uint64_t u64; | ||
1612 | struct cvmx_gmxx_txx_burst_s { | ||
1613 | uint64_t reserved_16_63:48; | ||
1614 | uint64_t burst:16; | ||
1615 | } s; | ||
1616 | struct cvmx_gmxx_txx_burst_s cn30xx; | ||
1617 | struct cvmx_gmxx_txx_burst_s cn31xx; | ||
1618 | struct cvmx_gmxx_txx_burst_s cn38xx; | ||
1619 | struct cvmx_gmxx_txx_burst_s cn38xxp2; | ||
1620 | struct cvmx_gmxx_txx_burst_s cn50xx; | ||
1621 | struct cvmx_gmxx_txx_burst_s cn52xx; | ||
1622 | struct cvmx_gmxx_txx_burst_s cn52xxp1; | ||
1623 | struct cvmx_gmxx_txx_burst_s cn56xx; | ||
1624 | struct cvmx_gmxx_txx_burst_s cn56xxp1; | ||
1625 | struct cvmx_gmxx_txx_burst_s cn58xx; | ||
1626 | struct cvmx_gmxx_txx_burst_s cn58xxp1; | ||
1627 | }; | ||
1628 | |||
1629 | union cvmx_gmxx_txx_cbfc_xoff { | ||
1630 | uint64_t u64; | ||
1631 | struct cvmx_gmxx_txx_cbfc_xoff_s { | ||
1632 | uint64_t reserved_16_63:48; | ||
1633 | uint64_t xoff:16; | ||
1634 | } s; | ||
1635 | struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx; | ||
1636 | struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx; | ||
1637 | }; | ||
1638 | |||
1639 | union cvmx_gmxx_txx_cbfc_xon { | ||
1640 | uint64_t u64; | ||
1641 | struct cvmx_gmxx_txx_cbfc_xon_s { | ||
1642 | uint64_t reserved_16_63:48; | ||
1643 | uint64_t xon:16; | ||
1644 | } s; | ||
1645 | struct cvmx_gmxx_txx_cbfc_xon_s cn52xx; | ||
1646 | struct cvmx_gmxx_txx_cbfc_xon_s cn56xx; | ||
1647 | }; | ||
1648 | |||
1649 | union cvmx_gmxx_txx_clk { | ||
1650 | uint64_t u64; | ||
1651 | struct cvmx_gmxx_txx_clk_s { | ||
1652 | uint64_t reserved_6_63:58; | ||
1653 | uint64_t clk_cnt:6; | ||
1654 | } s; | ||
1655 | struct cvmx_gmxx_txx_clk_s cn30xx; | ||
1656 | struct cvmx_gmxx_txx_clk_s cn31xx; | ||
1657 | struct cvmx_gmxx_txx_clk_s cn38xx; | ||
1658 | struct cvmx_gmxx_txx_clk_s cn38xxp2; | ||
1659 | struct cvmx_gmxx_txx_clk_s cn50xx; | ||
1660 | struct cvmx_gmxx_txx_clk_s cn58xx; | ||
1661 | struct cvmx_gmxx_txx_clk_s cn58xxp1; | ||
1662 | }; | ||
1663 | |||
1664 | union cvmx_gmxx_txx_ctl { | ||
1665 | uint64_t u64; | ||
1666 | struct cvmx_gmxx_txx_ctl_s { | ||
1667 | uint64_t reserved_2_63:62; | ||
1668 | uint64_t xsdef_en:1; | ||
1669 | uint64_t xscol_en:1; | ||
1670 | } s; | ||
1671 | struct cvmx_gmxx_txx_ctl_s cn30xx; | ||
1672 | struct cvmx_gmxx_txx_ctl_s cn31xx; | ||
1673 | struct cvmx_gmxx_txx_ctl_s cn38xx; | ||
1674 | struct cvmx_gmxx_txx_ctl_s cn38xxp2; | ||
1675 | struct cvmx_gmxx_txx_ctl_s cn50xx; | ||
1676 | struct cvmx_gmxx_txx_ctl_s cn52xx; | ||
1677 | struct cvmx_gmxx_txx_ctl_s cn52xxp1; | ||
1678 | struct cvmx_gmxx_txx_ctl_s cn56xx; | ||
1679 | struct cvmx_gmxx_txx_ctl_s cn56xxp1; | ||
1680 | struct cvmx_gmxx_txx_ctl_s cn58xx; | ||
1681 | struct cvmx_gmxx_txx_ctl_s cn58xxp1; | ||
1682 | }; | ||
1683 | |||
1684 | union cvmx_gmxx_txx_min_pkt { | ||
1685 | uint64_t u64; | ||
1686 | struct cvmx_gmxx_txx_min_pkt_s { | ||
1687 | uint64_t reserved_8_63:56; | ||
1688 | uint64_t min_size:8; | ||
1689 | } s; | ||
1690 | struct cvmx_gmxx_txx_min_pkt_s cn30xx; | ||
1691 | struct cvmx_gmxx_txx_min_pkt_s cn31xx; | ||
1692 | struct cvmx_gmxx_txx_min_pkt_s cn38xx; | ||
1693 | struct cvmx_gmxx_txx_min_pkt_s cn38xxp2; | ||
1694 | struct cvmx_gmxx_txx_min_pkt_s cn50xx; | ||
1695 | struct cvmx_gmxx_txx_min_pkt_s cn52xx; | ||
1696 | struct cvmx_gmxx_txx_min_pkt_s cn52xxp1; | ||
1697 | struct cvmx_gmxx_txx_min_pkt_s cn56xx; | ||
1698 | struct cvmx_gmxx_txx_min_pkt_s cn56xxp1; | ||
1699 | struct cvmx_gmxx_txx_min_pkt_s cn58xx; | ||
1700 | struct cvmx_gmxx_txx_min_pkt_s cn58xxp1; | ||
1701 | }; | ||
1702 | |||
1703 | union cvmx_gmxx_txx_pause_pkt_interval { | ||
1704 | uint64_t u64; | ||
1705 | struct cvmx_gmxx_txx_pause_pkt_interval_s { | ||
1706 | uint64_t reserved_16_63:48; | ||
1707 | uint64_t interval:16; | ||
1708 | } s; | ||
1709 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx; | ||
1710 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx; | ||
1711 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx; | ||
1712 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2; | ||
1713 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx; | ||
1714 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx; | ||
1715 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1; | ||
1716 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx; | ||
1717 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1; | ||
1718 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx; | ||
1719 | struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1; | ||
1720 | }; | ||
1721 | |||
1722 | union cvmx_gmxx_txx_pause_pkt_time { | ||
1723 | uint64_t u64; | ||
1724 | struct cvmx_gmxx_txx_pause_pkt_time_s { | ||
1725 | uint64_t reserved_16_63:48; | ||
1726 | uint64_t time:16; | ||
1727 | } s; | ||
1728 | struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx; | ||
1729 | struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx; | ||
1730 | struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx; | ||
1731 | struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2; | ||
1732 | struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx; | ||
1733 | struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx; | ||
1734 | struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1; | ||
1735 | struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx; | ||
1736 | struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1; | ||
1737 | struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx; | ||
1738 | struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1; | ||
1739 | }; | ||
1740 | |||
1741 | union cvmx_gmxx_txx_pause_togo { | ||
1742 | uint64_t u64; | ||
1743 | struct cvmx_gmxx_txx_pause_togo_s { | ||
1744 | uint64_t reserved_32_63:32; | ||
1745 | uint64_t msg_time:16; | ||
1746 | uint64_t time:16; | ||
1747 | } s; | ||
1748 | struct cvmx_gmxx_txx_pause_togo_cn30xx { | ||
1749 | uint64_t reserved_16_63:48; | ||
1750 | uint64_t time:16; | ||
1751 | } cn30xx; | ||
1752 | struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx; | ||
1753 | struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx; | ||
1754 | struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2; | ||
1755 | struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx; | ||
1756 | struct cvmx_gmxx_txx_pause_togo_s cn52xx; | ||
1757 | struct cvmx_gmxx_txx_pause_togo_s cn52xxp1; | ||
1758 | struct cvmx_gmxx_txx_pause_togo_s cn56xx; | ||
1759 | struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1; | ||
1760 | struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx; | ||
1761 | struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1; | ||
1762 | }; | ||
1763 | |||
1764 | union cvmx_gmxx_txx_pause_zero { | ||
1765 | uint64_t u64; | ||
1766 | struct cvmx_gmxx_txx_pause_zero_s { | ||
1767 | uint64_t reserved_1_63:63; | ||
1768 | uint64_t send:1; | ||
1769 | } s; | ||
1770 | struct cvmx_gmxx_txx_pause_zero_s cn30xx; | ||
1771 | struct cvmx_gmxx_txx_pause_zero_s cn31xx; | ||
1772 | struct cvmx_gmxx_txx_pause_zero_s cn38xx; | ||
1773 | struct cvmx_gmxx_txx_pause_zero_s cn38xxp2; | ||
1774 | struct cvmx_gmxx_txx_pause_zero_s cn50xx; | ||
1775 | struct cvmx_gmxx_txx_pause_zero_s cn52xx; | ||
1776 | struct cvmx_gmxx_txx_pause_zero_s cn52xxp1; | ||
1777 | struct cvmx_gmxx_txx_pause_zero_s cn56xx; | ||
1778 | struct cvmx_gmxx_txx_pause_zero_s cn56xxp1; | ||
1779 | struct cvmx_gmxx_txx_pause_zero_s cn58xx; | ||
1780 | struct cvmx_gmxx_txx_pause_zero_s cn58xxp1; | ||
1781 | }; | ||
1782 | |||
1783 | union cvmx_gmxx_txx_sgmii_ctl { | ||
1784 | uint64_t u64; | ||
1785 | struct cvmx_gmxx_txx_sgmii_ctl_s { | ||
1786 | uint64_t reserved_1_63:63; | ||
1787 | uint64_t align:1; | ||
1788 | } s; | ||
1789 | struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx; | ||
1790 | struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1; | ||
1791 | struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx; | ||
1792 | struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1; | ||
1793 | }; | ||
1794 | |||
1795 | union cvmx_gmxx_txx_slot { | ||
1796 | uint64_t u64; | ||
1797 | struct cvmx_gmxx_txx_slot_s { | ||
1798 | uint64_t reserved_10_63:54; | ||
1799 | uint64_t slot:10; | ||
1800 | } s; | ||
1801 | struct cvmx_gmxx_txx_slot_s cn30xx; | ||
1802 | struct cvmx_gmxx_txx_slot_s cn31xx; | ||
1803 | struct cvmx_gmxx_txx_slot_s cn38xx; | ||
1804 | struct cvmx_gmxx_txx_slot_s cn38xxp2; | ||
1805 | struct cvmx_gmxx_txx_slot_s cn50xx; | ||
1806 | struct cvmx_gmxx_txx_slot_s cn52xx; | ||
1807 | struct cvmx_gmxx_txx_slot_s cn52xxp1; | ||
1808 | struct cvmx_gmxx_txx_slot_s cn56xx; | ||
1809 | struct cvmx_gmxx_txx_slot_s cn56xxp1; | ||
1810 | struct cvmx_gmxx_txx_slot_s cn58xx; | ||
1811 | struct cvmx_gmxx_txx_slot_s cn58xxp1; | ||
1812 | }; | ||
1813 | |||
1814 | union cvmx_gmxx_txx_soft_pause { | ||
1815 | uint64_t u64; | ||
1816 | struct cvmx_gmxx_txx_soft_pause_s { | ||
1817 | uint64_t reserved_16_63:48; | ||
1818 | uint64_t time:16; | ||
1819 | } s; | ||
1820 | struct cvmx_gmxx_txx_soft_pause_s cn30xx; | ||
1821 | struct cvmx_gmxx_txx_soft_pause_s cn31xx; | ||
1822 | struct cvmx_gmxx_txx_soft_pause_s cn38xx; | ||
1823 | struct cvmx_gmxx_txx_soft_pause_s cn38xxp2; | ||
1824 | struct cvmx_gmxx_txx_soft_pause_s cn50xx; | ||
1825 | struct cvmx_gmxx_txx_soft_pause_s cn52xx; | ||
1826 | struct cvmx_gmxx_txx_soft_pause_s cn52xxp1; | ||
1827 | struct cvmx_gmxx_txx_soft_pause_s cn56xx; | ||
1828 | struct cvmx_gmxx_txx_soft_pause_s cn56xxp1; | ||
1829 | struct cvmx_gmxx_txx_soft_pause_s cn58xx; | ||
1830 | struct cvmx_gmxx_txx_soft_pause_s cn58xxp1; | ||
1831 | }; | ||
1832 | |||
1833 | union cvmx_gmxx_txx_stat0 { | ||
1834 | uint64_t u64; | ||
1835 | struct cvmx_gmxx_txx_stat0_s { | ||
1836 | uint64_t xsdef:32; | ||
1837 | uint64_t xscol:32; | ||
1838 | } s; | ||
1839 | struct cvmx_gmxx_txx_stat0_s cn30xx; | ||
1840 | struct cvmx_gmxx_txx_stat0_s cn31xx; | ||
1841 | struct cvmx_gmxx_txx_stat0_s cn38xx; | ||
1842 | struct cvmx_gmxx_txx_stat0_s cn38xxp2; | ||
1843 | struct cvmx_gmxx_txx_stat0_s cn50xx; | ||
1844 | struct cvmx_gmxx_txx_stat0_s cn52xx; | ||
1845 | struct cvmx_gmxx_txx_stat0_s cn52xxp1; | ||
1846 | struct cvmx_gmxx_txx_stat0_s cn56xx; | ||
1847 | struct cvmx_gmxx_txx_stat0_s cn56xxp1; | ||
1848 | struct cvmx_gmxx_txx_stat0_s cn58xx; | ||
1849 | struct cvmx_gmxx_txx_stat0_s cn58xxp1; | ||
1850 | }; | ||
1851 | |||
1852 | union cvmx_gmxx_txx_stat1 { | ||
1853 | uint64_t u64; | ||
1854 | struct cvmx_gmxx_txx_stat1_s { | ||
1855 | uint64_t scol:32; | ||
1856 | uint64_t mcol:32; | ||
1857 | } s; | ||
1858 | struct cvmx_gmxx_txx_stat1_s cn30xx; | ||
1859 | struct cvmx_gmxx_txx_stat1_s cn31xx; | ||
1860 | struct cvmx_gmxx_txx_stat1_s cn38xx; | ||
1861 | struct cvmx_gmxx_txx_stat1_s cn38xxp2; | ||
1862 | struct cvmx_gmxx_txx_stat1_s cn50xx; | ||
1863 | struct cvmx_gmxx_txx_stat1_s cn52xx; | ||
1864 | struct cvmx_gmxx_txx_stat1_s cn52xxp1; | ||
1865 | struct cvmx_gmxx_txx_stat1_s cn56xx; | ||
1866 | struct cvmx_gmxx_txx_stat1_s cn56xxp1; | ||
1867 | struct cvmx_gmxx_txx_stat1_s cn58xx; | ||
1868 | struct cvmx_gmxx_txx_stat1_s cn58xxp1; | ||
1869 | }; | ||
1870 | |||
1871 | union cvmx_gmxx_txx_stat2 { | ||
1872 | uint64_t u64; | ||
1873 | struct cvmx_gmxx_txx_stat2_s { | ||
1874 | uint64_t reserved_48_63:16; | ||
1875 | uint64_t octs:48; | ||
1876 | } s; | ||
1877 | struct cvmx_gmxx_txx_stat2_s cn30xx; | ||
1878 | struct cvmx_gmxx_txx_stat2_s cn31xx; | ||
1879 | struct cvmx_gmxx_txx_stat2_s cn38xx; | ||
1880 | struct cvmx_gmxx_txx_stat2_s cn38xxp2; | ||
1881 | struct cvmx_gmxx_txx_stat2_s cn50xx; | ||
1882 | struct cvmx_gmxx_txx_stat2_s cn52xx; | ||
1883 | struct cvmx_gmxx_txx_stat2_s cn52xxp1; | ||
1884 | struct cvmx_gmxx_txx_stat2_s cn56xx; | ||
1885 | struct cvmx_gmxx_txx_stat2_s cn56xxp1; | ||
1886 | struct cvmx_gmxx_txx_stat2_s cn58xx; | ||
1887 | struct cvmx_gmxx_txx_stat2_s cn58xxp1; | ||
1888 | }; | ||
1889 | |||
1890 | union cvmx_gmxx_txx_stat3 { | ||
1891 | uint64_t u64; | ||
1892 | struct cvmx_gmxx_txx_stat3_s { | ||
1893 | uint64_t reserved_32_63:32; | ||
1894 | uint64_t pkts:32; | ||
1895 | } s; | ||
1896 | struct cvmx_gmxx_txx_stat3_s cn30xx; | ||
1897 | struct cvmx_gmxx_txx_stat3_s cn31xx; | ||
1898 | struct cvmx_gmxx_txx_stat3_s cn38xx; | ||
1899 | struct cvmx_gmxx_txx_stat3_s cn38xxp2; | ||
1900 | struct cvmx_gmxx_txx_stat3_s cn50xx; | ||
1901 | struct cvmx_gmxx_txx_stat3_s cn52xx; | ||
1902 | struct cvmx_gmxx_txx_stat3_s cn52xxp1; | ||
1903 | struct cvmx_gmxx_txx_stat3_s cn56xx; | ||
1904 | struct cvmx_gmxx_txx_stat3_s cn56xxp1; | ||
1905 | struct cvmx_gmxx_txx_stat3_s cn58xx; | ||
1906 | struct cvmx_gmxx_txx_stat3_s cn58xxp1; | ||
1907 | }; | ||
1908 | |||
1909 | union cvmx_gmxx_txx_stat4 { | ||
1910 | uint64_t u64; | ||
1911 | struct cvmx_gmxx_txx_stat4_s { | ||
1912 | uint64_t hist1:32; | ||
1913 | uint64_t hist0:32; | ||
1914 | } s; | ||
1915 | struct cvmx_gmxx_txx_stat4_s cn30xx; | ||
1916 | struct cvmx_gmxx_txx_stat4_s cn31xx; | ||
1917 | struct cvmx_gmxx_txx_stat4_s cn38xx; | ||
1918 | struct cvmx_gmxx_txx_stat4_s cn38xxp2; | ||
1919 | struct cvmx_gmxx_txx_stat4_s cn50xx; | ||
1920 | struct cvmx_gmxx_txx_stat4_s cn52xx; | ||
1921 | struct cvmx_gmxx_txx_stat4_s cn52xxp1; | ||
1922 | struct cvmx_gmxx_txx_stat4_s cn56xx; | ||
1923 | struct cvmx_gmxx_txx_stat4_s cn56xxp1; | ||
1924 | struct cvmx_gmxx_txx_stat4_s cn58xx; | ||
1925 | struct cvmx_gmxx_txx_stat4_s cn58xxp1; | ||
1926 | }; | ||
1927 | |||
1928 | union cvmx_gmxx_txx_stat5 { | ||
1929 | uint64_t u64; | ||
1930 | struct cvmx_gmxx_txx_stat5_s { | ||
1931 | uint64_t hist3:32; | ||
1932 | uint64_t hist2:32; | ||
1933 | } s; | ||
1934 | struct cvmx_gmxx_txx_stat5_s cn30xx; | ||
1935 | struct cvmx_gmxx_txx_stat5_s cn31xx; | ||
1936 | struct cvmx_gmxx_txx_stat5_s cn38xx; | ||
1937 | struct cvmx_gmxx_txx_stat5_s cn38xxp2; | ||
1938 | struct cvmx_gmxx_txx_stat5_s cn50xx; | ||
1939 | struct cvmx_gmxx_txx_stat5_s cn52xx; | ||
1940 | struct cvmx_gmxx_txx_stat5_s cn52xxp1; | ||
1941 | struct cvmx_gmxx_txx_stat5_s cn56xx; | ||
1942 | struct cvmx_gmxx_txx_stat5_s cn56xxp1; | ||
1943 | struct cvmx_gmxx_txx_stat5_s cn58xx; | ||
1944 | struct cvmx_gmxx_txx_stat5_s cn58xxp1; | ||
1945 | }; | ||
1946 | |||
1947 | union cvmx_gmxx_txx_stat6 { | ||
1948 | uint64_t u64; | ||
1949 | struct cvmx_gmxx_txx_stat6_s { | ||
1950 | uint64_t hist5:32; | ||
1951 | uint64_t hist4:32; | ||
1952 | } s; | ||
1953 | struct cvmx_gmxx_txx_stat6_s cn30xx; | ||
1954 | struct cvmx_gmxx_txx_stat6_s cn31xx; | ||
1955 | struct cvmx_gmxx_txx_stat6_s cn38xx; | ||
1956 | struct cvmx_gmxx_txx_stat6_s cn38xxp2; | ||
1957 | struct cvmx_gmxx_txx_stat6_s cn50xx; | ||
1958 | struct cvmx_gmxx_txx_stat6_s cn52xx; | ||
1959 | struct cvmx_gmxx_txx_stat6_s cn52xxp1; | ||
1960 | struct cvmx_gmxx_txx_stat6_s cn56xx; | ||
1961 | struct cvmx_gmxx_txx_stat6_s cn56xxp1; | ||
1962 | struct cvmx_gmxx_txx_stat6_s cn58xx; | ||
1963 | struct cvmx_gmxx_txx_stat6_s cn58xxp1; | ||
1964 | }; | ||
1965 | |||
1966 | union cvmx_gmxx_txx_stat7 { | ||
1967 | uint64_t u64; | ||
1968 | struct cvmx_gmxx_txx_stat7_s { | ||
1969 | uint64_t hist7:32; | ||
1970 | uint64_t hist6:32; | ||
1971 | } s; | ||
1972 | struct cvmx_gmxx_txx_stat7_s cn30xx; | ||
1973 | struct cvmx_gmxx_txx_stat7_s cn31xx; | ||
1974 | struct cvmx_gmxx_txx_stat7_s cn38xx; | ||
1975 | struct cvmx_gmxx_txx_stat7_s cn38xxp2; | ||
1976 | struct cvmx_gmxx_txx_stat7_s cn50xx; | ||
1977 | struct cvmx_gmxx_txx_stat7_s cn52xx; | ||
1978 | struct cvmx_gmxx_txx_stat7_s cn52xxp1; | ||
1979 | struct cvmx_gmxx_txx_stat7_s cn56xx; | ||
1980 | struct cvmx_gmxx_txx_stat7_s cn56xxp1; | ||
1981 | struct cvmx_gmxx_txx_stat7_s cn58xx; | ||
1982 | struct cvmx_gmxx_txx_stat7_s cn58xxp1; | ||
1983 | }; | ||
1984 | |||
1985 | union cvmx_gmxx_txx_stat8 { | ||
1986 | uint64_t u64; | ||
1987 | struct cvmx_gmxx_txx_stat8_s { | ||
1988 | uint64_t mcst:32; | ||
1989 | uint64_t bcst:32; | ||
1990 | } s; | ||
1991 | struct cvmx_gmxx_txx_stat8_s cn30xx; | ||
1992 | struct cvmx_gmxx_txx_stat8_s cn31xx; | ||
1993 | struct cvmx_gmxx_txx_stat8_s cn38xx; | ||
1994 | struct cvmx_gmxx_txx_stat8_s cn38xxp2; | ||
1995 | struct cvmx_gmxx_txx_stat8_s cn50xx; | ||
1996 | struct cvmx_gmxx_txx_stat8_s cn52xx; | ||
1997 | struct cvmx_gmxx_txx_stat8_s cn52xxp1; | ||
1998 | struct cvmx_gmxx_txx_stat8_s cn56xx; | ||
1999 | struct cvmx_gmxx_txx_stat8_s cn56xxp1; | ||
2000 | struct cvmx_gmxx_txx_stat8_s cn58xx; | ||
2001 | struct cvmx_gmxx_txx_stat8_s cn58xxp1; | ||
2002 | }; | ||
2003 | |||
2004 | union cvmx_gmxx_txx_stat9 { | ||
2005 | uint64_t u64; | ||
2006 | struct cvmx_gmxx_txx_stat9_s { | ||
2007 | uint64_t undflw:32; | ||
2008 | uint64_t ctl:32; | ||
2009 | } s; | ||
2010 | struct cvmx_gmxx_txx_stat9_s cn30xx; | ||
2011 | struct cvmx_gmxx_txx_stat9_s cn31xx; | ||
2012 | struct cvmx_gmxx_txx_stat9_s cn38xx; | ||
2013 | struct cvmx_gmxx_txx_stat9_s cn38xxp2; | ||
2014 | struct cvmx_gmxx_txx_stat9_s cn50xx; | ||
2015 | struct cvmx_gmxx_txx_stat9_s cn52xx; | ||
2016 | struct cvmx_gmxx_txx_stat9_s cn52xxp1; | ||
2017 | struct cvmx_gmxx_txx_stat9_s cn56xx; | ||
2018 | struct cvmx_gmxx_txx_stat9_s cn56xxp1; | ||
2019 | struct cvmx_gmxx_txx_stat9_s cn58xx; | ||
2020 | struct cvmx_gmxx_txx_stat9_s cn58xxp1; | ||
2021 | }; | ||
2022 | |||
2023 | union cvmx_gmxx_txx_stats_ctl { | ||
2024 | uint64_t u64; | ||
2025 | struct cvmx_gmxx_txx_stats_ctl_s { | ||
2026 | uint64_t reserved_1_63:63; | ||
2027 | uint64_t rd_clr:1; | ||
2028 | } s; | ||
2029 | struct cvmx_gmxx_txx_stats_ctl_s cn30xx; | ||
2030 | struct cvmx_gmxx_txx_stats_ctl_s cn31xx; | ||
2031 | struct cvmx_gmxx_txx_stats_ctl_s cn38xx; | ||
2032 | struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2; | ||
2033 | struct cvmx_gmxx_txx_stats_ctl_s cn50xx; | ||
2034 | struct cvmx_gmxx_txx_stats_ctl_s cn52xx; | ||
2035 | struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1; | ||
2036 | struct cvmx_gmxx_txx_stats_ctl_s cn56xx; | ||
2037 | struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1; | ||
2038 | struct cvmx_gmxx_txx_stats_ctl_s cn58xx; | ||
2039 | struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1; | ||
2040 | }; | ||
2041 | |||
2042 | union cvmx_gmxx_txx_thresh { | ||
2043 | uint64_t u64; | ||
2044 | struct cvmx_gmxx_txx_thresh_s { | ||
2045 | uint64_t reserved_9_63:55; | ||
2046 | uint64_t cnt:9; | ||
2047 | } s; | ||
2048 | struct cvmx_gmxx_txx_thresh_cn30xx { | ||
2049 | uint64_t reserved_7_63:57; | ||
2050 | uint64_t cnt:7; | ||
2051 | } cn30xx; | ||
2052 | struct cvmx_gmxx_txx_thresh_cn30xx cn31xx; | ||
2053 | struct cvmx_gmxx_txx_thresh_s cn38xx; | ||
2054 | struct cvmx_gmxx_txx_thresh_s cn38xxp2; | ||
2055 | struct cvmx_gmxx_txx_thresh_cn30xx cn50xx; | ||
2056 | struct cvmx_gmxx_txx_thresh_s cn52xx; | ||
2057 | struct cvmx_gmxx_txx_thresh_s cn52xxp1; | ||
2058 | struct cvmx_gmxx_txx_thresh_s cn56xx; | ||
2059 | struct cvmx_gmxx_txx_thresh_s cn56xxp1; | ||
2060 | struct cvmx_gmxx_txx_thresh_s cn58xx; | ||
2061 | struct cvmx_gmxx_txx_thresh_s cn58xxp1; | ||
2062 | }; | ||
2063 | |||
2064 | union cvmx_gmxx_tx_bp { | ||
2065 | uint64_t u64; | ||
2066 | struct cvmx_gmxx_tx_bp_s { | ||
2067 | uint64_t reserved_4_63:60; | ||
2068 | uint64_t bp:4; | ||
2069 | } s; | ||
2070 | struct cvmx_gmxx_tx_bp_cn30xx { | ||
2071 | uint64_t reserved_3_63:61; | ||
2072 | uint64_t bp:3; | ||
2073 | } cn30xx; | ||
2074 | struct cvmx_gmxx_tx_bp_cn30xx cn31xx; | ||
2075 | struct cvmx_gmxx_tx_bp_s cn38xx; | ||
2076 | struct cvmx_gmxx_tx_bp_s cn38xxp2; | ||
2077 | struct cvmx_gmxx_tx_bp_cn30xx cn50xx; | ||
2078 | struct cvmx_gmxx_tx_bp_s cn52xx; | ||
2079 | struct cvmx_gmxx_tx_bp_s cn52xxp1; | ||
2080 | struct cvmx_gmxx_tx_bp_s cn56xx; | ||
2081 | struct cvmx_gmxx_tx_bp_s cn56xxp1; | ||
2082 | struct cvmx_gmxx_tx_bp_s cn58xx; | ||
2083 | struct cvmx_gmxx_tx_bp_s cn58xxp1; | ||
2084 | }; | ||
2085 | |||
2086 | union cvmx_gmxx_tx_clk_mskx { | ||
2087 | uint64_t u64; | ||
2088 | struct cvmx_gmxx_tx_clk_mskx_s { | ||
2089 | uint64_t reserved_1_63:63; | ||
2090 | uint64_t msk:1; | ||
2091 | } s; | ||
2092 | struct cvmx_gmxx_tx_clk_mskx_s cn30xx; | ||
2093 | struct cvmx_gmxx_tx_clk_mskx_s cn50xx; | ||
2094 | }; | ||
2095 | |||
2096 | union cvmx_gmxx_tx_col_attempt { | ||
2097 | uint64_t u64; | ||
2098 | struct cvmx_gmxx_tx_col_attempt_s { | ||
2099 | uint64_t reserved_5_63:59; | ||
2100 | uint64_t limit:5; | ||
2101 | } s; | ||
2102 | struct cvmx_gmxx_tx_col_attempt_s cn30xx; | ||
2103 | struct cvmx_gmxx_tx_col_attempt_s cn31xx; | ||
2104 | struct cvmx_gmxx_tx_col_attempt_s cn38xx; | ||
2105 | struct cvmx_gmxx_tx_col_attempt_s cn38xxp2; | ||
2106 | struct cvmx_gmxx_tx_col_attempt_s cn50xx; | ||
2107 | struct cvmx_gmxx_tx_col_attempt_s cn52xx; | ||
2108 | struct cvmx_gmxx_tx_col_attempt_s cn52xxp1; | ||
2109 | struct cvmx_gmxx_tx_col_attempt_s cn56xx; | ||
2110 | struct cvmx_gmxx_tx_col_attempt_s cn56xxp1; | ||
2111 | struct cvmx_gmxx_tx_col_attempt_s cn58xx; | ||
2112 | struct cvmx_gmxx_tx_col_attempt_s cn58xxp1; | ||
2113 | }; | ||
2114 | |||
2115 | union cvmx_gmxx_tx_corrupt { | ||
2116 | uint64_t u64; | ||
2117 | struct cvmx_gmxx_tx_corrupt_s { | ||
2118 | uint64_t reserved_4_63:60; | ||
2119 | uint64_t corrupt:4; | ||
2120 | } s; | ||
2121 | struct cvmx_gmxx_tx_corrupt_cn30xx { | ||
2122 | uint64_t reserved_3_63:61; | ||
2123 | uint64_t corrupt:3; | ||
2124 | } cn30xx; | ||
2125 | struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx; | ||
2126 | struct cvmx_gmxx_tx_corrupt_s cn38xx; | ||
2127 | struct cvmx_gmxx_tx_corrupt_s cn38xxp2; | ||
2128 | struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx; | ||
2129 | struct cvmx_gmxx_tx_corrupt_s cn52xx; | ||
2130 | struct cvmx_gmxx_tx_corrupt_s cn52xxp1; | ||
2131 | struct cvmx_gmxx_tx_corrupt_s cn56xx; | ||
2132 | struct cvmx_gmxx_tx_corrupt_s cn56xxp1; | ||
2133 | struct cvmx_gmxx_tx_corrupt_s cn58xx; | ||
2134 | struct cvmx_gmxx_tx_corrupt_s cn58xxp1; | ||
2135 | }; | ||
2136 | |||
2137 | union cvmx_gmxx_tx_hg2_reg1 { | ||
2138 | uint64_t u64; | ||
2139 | struct cvmx_gmxx_tx_hg2_reg1_s { | ||
2140 | uint64_t reserved_16_63:48; | ||
2141 | uint64_t tx_xof:16; | ||
2142 | } s; | ||
2143 | struct cvmx_gmxx_tx_hg2_reg1_s cn52xx; | ||
2144 | struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1; | ||
2145 | struct cvmx_gmxx_tx_hg2_reg1_s cn56xx; | ||
2146 | }; | ||
2147 | |||
2148 | union cvmx_gmxx_tx_hg2_reg2 { | ||
2149 | uint64_t u64; | ||
2150 | struct cvmx_gmxx_tx_hg2_reg2_s { | ||
2151 | uint64_t reserved_16_63:48; | ||
2152 | uint64_t tx_xon:16; | ||
2153 | } s; | ||
2154 | struct cvmx_gmxx_tx_hg2_reg2_s cn52xx; | ||
2155 | struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1; | ||
2156 | struct cvmx_gmxx_tx_hg2_reg2_s cn56xx; | ||
2157 | }; | ||
2158 | |||
2159 | union cvmx_gmxx_tx_ifg { | ||
2160 | uint64_t u64; | ||
2161 | struct cvmx_gmxx_tx_ifg_s { | ||
2162 | uint64_t reserved_8_63:56; | ||
2163 | uint64_t ifg2:4; | ||
2164 | uint64_t ifg1:4; | ||
2165 | } s; | ||
2166 | struct cvmx_gmxx_tx_ifg_s cn30xx; | ||
2167 | struct cvmx_gmxx_tx_ifg_s cn31xx; | ||
2168 | struct cvmx_gmxx_tx_ifg_s cn38xx; | ||
2169 | struct cvmx_gmxx_tx_ifg_s cn38xxp2; | ||
2170 | struct cvmx_gmxx_tx_ifg_s cn50xx; | ||
2171 | struct cvmx_gmxx_tx_ifg_s cn52xx; | ||
2172 | struct cvmx_gmxx_tx_ifg_s cn52xxp1; | ||
2173 | struct cvmx_gmxx_tx_ifg_s cn56xx; | ||
2174 | struct cvmx_gmxx_tx_ifg_s cn56xxp1; | ||
2175 | struct cvmx_gmxx_tx_ifg_s cn58xx; | ||
2176 | struct cvmx_gmxx_tx_ifg_s cn58xxp1; | ||
2177 | }; | ||
2178 | |||
2179 | union cvmx_gmxx_tx_int_en { | ||
2180 | uint64_t u64; | ||
2181 | struct cvmx_gmxx_tx_int_en_s { | ||
2182 | uint64_t reserved_20_63:44; | ||
2183 | uint64_t late_col:4; | ||
2184 | uint64_t xsdef:4; | ||
2185 | uint64_t xscol:4; | ||
2186 | uint64_t reserved_6_7:2; | ||
2187 | uint64_t undflw:4; | ||
2188 | uint64_t ncb_nxa:1; | ||
2189 | uint64_t pko_nxa:1; | ||
2190 | } s; | ||
2191 | struct cvmx_gmxx_tx_int_en_cn30xx { | ||
2192 | uint64_t reserved_19_63:45; | ||
2193 | uint64_t late_col:3; | ||
2194 | uint64_t reserved_15_15:1; | ||
2195 | uint64_t xsdef:3; | ||
2196 | uint64_t reserved_11_11:1; | ||
2197 | uint64_t xscol:3; | ||
2198 | uint64_t reserved_5_7:3; | ||
2199 | uint64_t undflw:3; | ||
2200 | uint64_t reserved_1_1:1; | ||
2201 | uint64_t pko_nxa:1; | ||
2202 | } cn30xx; | ||
2203 | struct cvmx_gmxx_tx_int_en_cn31xx { | ||
2204 | uint64_t reserved_15_63:49; | ||
2205 | uint64_t xsdef:3; | ||
2206 | uint64_t reserved_11_11:1; | ||
2207 | uint64_t xscol:3; | ||
2208 | uint64_t reserved_5_7:3; | ||
2209 | uint64_t undflw:3; | ||
2210 | uint64_t reserved_1_1:1; | ||
2211 | uint64_t pko_nxa:1; | ||
2212 | } cn31xx; | ||
2213 | struct cvmx_gmxx_tx_int_en_s cn38xx; | ||
2214 | struct cvmx_gmxx_tx_int_en_cn38xxp2 { | ||
2215 | uint64_t reserved_16_63:48; | ||
2216 | uint64_t xsdef:4; | ||
2217 | uint64_t xscol:4; | ||
2218 | uint64_t reserved_6_7:2; | ||
2219 | uint64_t undflw:4; | ||
2220 | uint64_t ncb_nxa:1; | ||
2221 | uint64_t pko_nxa:1; | ||
2222 | } cn38xxp2; | ||
2223 | struct cvmx_gmxx_tx_int_en_cn30xx cn50xx; | ||
2224 | struct cvmx_gmxx_tx_int_en_cn52xx { | ||
2225 | uint64_t reserved_20_63:44; | ||
2226 | uint64_t late_col:4; | ||
2227 | uint64_t xsdef:4; | ||
2228 | uint64_t xscol:4; | ||
2229 | uint64_t reserved_6_7:2; | ||
2230 | uint64_t undflw:4; | ||
2231 | uint64_t reserved_1_1:1; | ||
2232 | uint64_t pko_nxa:1; | ||
2233 | } cn52xx; | ||
2234 | struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1; | ||
2235 | struct cvmx_gmxx_tx_int_en_cn52xx cn56xx; | ||
2236 | struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1; | ||
2237 | struct cvmx_gmxx_tx_int_en_s cn58xx; | ||
2238 | struct cvmx_gmxx_tx_int_en_s cn58xxp1; | ||
2239 | }; | ||
2240 | |||
2241 | union cvmx_gmxx_tx_int_reg { | ||
2242 | uint64_t u64; | ||
2243 | struct cvmx_gmxx_tx_int_reg_s { | ||
2244 | uint64_t reserved_20_63:44; | ||
2245 | uint64_t late_col:4; | ||
2246 | uint64_t xsdef:4; | ||
2247 | uint64_t xscol:4; | ||
2248 | uint64_t reserved_6_7:2; | ||
2249 | uint64_t undflw:4; | ||
2250 | uint64_t ncb_nxa:1; | ||
2251 | uint64_t pko_nxa:1; | ||
2252 | } s; | ||
2253 | struct cvmx_gmxx_tx_int_reg_cn30xx { | ||
2254 | uint64_t reserved_19_63:45; | ||
2255 | uint64_t late_col:3; | ||
2256 | uint64_t reserved_15_15:1; | ||
2257 | uint64_t xsdef:3; | ||
2258 | uint64_t reserved_11_11:1; | ||
2259 | uint64_t xscol:3; | ||
2260 | uint64_t reserved_5_7:3; | ||
2261 | uint64_t undflw:3; | ||
2262 | uint64_t reserved_1_1:1; | ||
2263 | uint64_t pko_nxa:1; | ||
2264 | } cn30xx; | ||
2265 | struct cvmx_gmxx_tx_int_reg_cn31xx { | ||
2266 | uint64_t reserved_15_63:49; | ||
2267 | uint64_t xsdef:3; | ||
2268 | uint64_t reserved_11_11:1; | ||
2269 | uint64_t xscol:3; | ||
2270 | uint64_t reserved_5_7:3; | ||
2271 | uint64_t undflw:3; | ||
2272 | uint64_t reserved_1_1:1; | ||
2273 | uint64_t pko_nxa:1; | ||
2274 | } cn31xx; | ||
2275 | struct cvmx_gmxx_tx_int_reg_s cn38xx; | ||
2276 | struct cvmx_gmxx_tx_int_reg_cn38xxp2 { | ||
2277 | uint64_t reserved_16_63:48; | ||
2278 | uint64_t xsdef:4; | ||
2279 | uint64_t xscol:4; | ||
2280 | uint64_t reserved_6_7:2; | ||
2281 | uint64_t undflw:4; | ||
2282 | uint64_t ncb_nxa:1; | ||
2283 | uint64_t pko_nxa:1; | ||
2284 | } cn38xxp2; | ||
2285 | struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx; | ||
2286 | struct cvmx_gmxx_tx_int_reg_cn52xx { | ||
2287 | uint64_t reserved_20_63:44; | ||
2288 | uint64_t late_col:4; | ||
2289 | uint64_t xsdef:4; | ||
2290 | uint64_t xscol:4; | ||
2291 | uint64_t reserved_6_7:2; | ||
2292 | uint64_t undflw:4; | ||
2293 | uint64_t reserved_1_1:1; | ||
2294 | uint64_t pko_nxa:1; | ||
2295 | } cn52xx; | ||
2296 | struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1; | ||
2297 | struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx; | ||
2298 | struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1; | ||
2299 | struct cvmx_gmxx_tx_int_reg_s cn58xx; | ||
2300 | struct cvmx_gmxx_tx_int_reg_s cn58xxp1; | ||
2301 | }; | ||
2302 | |||
2303 | union cvmx_gmxx_tx_jam { | ||
2304 | uint64_t u64; | ||
2305 | struct cvmx_gmxx_tx_jam_s { | ||
2306 | uint64_t reserved_8_63:56; | ||
2307 | uint64_t jam:8; | ||
2308 | } s; | ||
2309 | struct cvmx_gmxx_tx_jam_s cn30xx; | ||
2310 | struct cvmx_gmxx_tx_jam_s cn31xx; | ||
2311 | struct cvmx_gmxx_tx_jam_s cn38xx; | ||
2312 | struct cvmx_gmxx_tx_jam_s cn38xxp2; | ||
2313 | struct cvmx_gmxx_tx_jam_s cn50xx; | ||
2314 | struct cvmx_gmxx_tx_jam_s cn52xx; | ||
2315 | struct cvmx_gmxx_tx_jam_s cn52xxp1; | ||
2316 | struct cvmx_gmxx_tx_jam_s cn56xx; | ||
2317 | struct cvmx_gmxx_tx_jam_s cn56xxp1; | ||
2318 | struct cvmx_gmxx_tx_jam_s cn58xx; | ||
2319 | struct cvmx_gmxx_tx_jam_s cn58xxp1; | ||
2320 | }; | ||
2321 | |||
2322 | union cvmx_gmxx_tx_lfsr { | ||
2323 | uint64_t u64; | ||
2324 | struct cvmx_gmxx_tx_lfsr_s { | ||
2325 | uint64_t reserved_16_63:48; | ||
2326 | uint64_t lfsr:16; | ||
2327 | } s; | ||
2328 | struct cvmx_gmxx_tx_lfsr_s cn30xx; | ||
2329 | struct cvmx_gmxx_tx_lfsr_s cn31xx; | ||
2330 | struct cvmx_gmxx_tx_lfsr_s cn38xx; | ||
2331 | struct cvmx_gmxx_tx_lfsr_s cn38xxp2; | ||
2332 | struct cvmx_gmxx_tx_lfsr_s cn50xx; | ||
2333 | struct cvmx_gmxx_tx_lfsr_s cn52xx; | ||
2334 | struct cvmx_gmxx_tx_lfsr_s cn52xxp1; | ||
2335 | struct cvmx_gmxx_tx_lfsr_s cn56xx; | ||
2336 | struct cvmx_gmxx_tx_lfsr_s cn56xxp1; | ||
2337 | struct cvmx_gmxx_tx_lfsr_s cn58xx; | ||
2338 | struct cvmx_gmxx_tx_lfsr_s cn58xxp1; | ||
2339 | }; | ||
2340 | |||
2341 | union cvmx_gmxx_tx_ovr_bp { | ||
2342 | uint64_t u64; | ||
2343 | struct cvmx_gmxx_tx_ovr_bp_s { | ||
2344 | uint64_t reserved_48_63:16; | ||
2345 | uint64_t tx_prt_bp:16; | ||
2346 | uint64_t reserved_12_31:20; | ||
2347 | uint64_t en:4; | ||
2348 | uint64_t bp:4; | ||
2349 | uint64_t ign_full:4; | ||
2350 | } s; | ||
2351 | struct cvmx_gmxx_tx_ovr_bp_cn30xx { | ||
2352 | uint64_t reserved_11_63:53; | ||
2353 | uint64_t en:3; | ||
2354 | uint64_t reserved_7_7:1; | ||
2355 | uint64_t bp:3; | ||
2356 | uint64_t reserved_3_3:1; | ||
2357 | uint64_t ign_full:3; | ||
2358 | } cn30xx; | ||
2359 | struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx; | ||
2360 | struct cvmx_gmxx_tx_ovr_bp_cn38xx { | ||
2361 | uint64_t reserved_12_63:52; | ||
2362 | uint64_t en:4; | ||
2363 | uint64_t bp:4; | ||
2364 | uint64_t ign_full:4; | ||
2365 | } cn38xx; | ||
2366 | struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2; | ||
2367 | struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx; | ||
2368 | struct cvmx_gmxx_tx_ovr_bp_s cn52xx; | ||
2369 | struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1; | ||
2370 | struct cvmx_gmxx_tx_ovr_bp_s cn56xx; | ||
2371 | struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1; | ||
2372 | struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx; | ||
2373 | struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1; | ||
2374 | }; | ||
2375 | |||
2376 | union cvmx_gmxx_tx_pause_pkt_dmac { | ||
2377 | uint64_t u64; | ||
2378 | struct cvmx_gmxx_tx_pause_pkt_dmac_s { | ||
2379 | uint64_t reserved_48_63:16; | ||
2380 | uint64_t dmac:48; | ||
2381 | } s; | ||
2382 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx; | ||
2383 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx; | ||
2384 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx; | ||
2385 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2; | ||
2386 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx; | ||
2387 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx; | ||
2388 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1; | ||
2389 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx; | ||
2390 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1; | ||
2391 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx; | ||
2392 | struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1; | ||
2393 | }; | ||
2394 | |||
2395 | union cvmx_gmxx_tx_pause_pkt_type { | ||
2396 | uint64_t u64; | ||
2397 | struct cvmx_gmxx_tx_pause_pkt_type_s { | ||
2398 | uint64_t reserved_16_63:48; | ||
2399 | uint64_t type:16; | ||
2400 | } s; | ||
2401 | struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx; | ||
2402 | struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx; | ||
2403 | struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx; | ||
2404 | struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2; | ||
2405 | struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx; | ||
2406 | struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx; | ||
2407 | struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1; | ||
2408 | struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx; | ||
2409 | struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1; | ||
2410 | struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx; | ||
2411 | struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1; | ||
2412 | }; | ||
2413 | |||
2414 | union cvmx_gmxx_tx_prts { | ||
2415 | uint64_t u64; | ||
2416 | struct cvmx_gmxx_tx_prts_s { | ||
2417 | uint64_t reserved_5_63:59; | ||
2418 | uint64_t prts:5; | ||
2419 | } s; | ||
2420 | struct cvmx_gmxx_tx_prts_s cn30xx; | ||
2421 | struct cvmx_gmxx_tx_prts_s cn31xx; | ||
2422 | struct cvmx_gmxx_tx_prts_s cn38xx; | ||
2423 | struct cvmx_gmxx_tx_prts_s cn38xxp2; | ||
2424 | struct cvmx_gmxx_tx_prts_s cn50xx; | ||
2425 | struct cvmx_gmxx_tx_prts_s cn52xx; | ||
2426 | struct cvmx_gmxx_tx_prts_s cn52xxp1; | ||
2427 | struct cvmx_gmxx_tx_prts_s cn56xx; | ||
2428 | struct cvmx_gmxx_tx_prts_s cn56xxp1; | ||
2429 | struct cvmx_gmxx_tx_prts_s cn58xx; | ||
2430 | struct cvmx_gmxx_tx_prts_s cn58xxp1; | ||
2431 | }; | ||
2432 | |||
2433 | union cvmx_gmxx_tx_spi_ctl { | ||
2434 | uint64_t u64; | ||
2435 | struct cvmx_gmxx_tx_spi_ctl_s { | ||
2436 | uint64_t reserved_2_63:62; | ||
2437 | uint64_t tpa_clr:1; | ||
2438 | uint64_t cont_pkt:1; | ||
2439 | } s; | ||
2440 | struct cvmx_gmxx_tx_spi_ctl_s cn38xx; | ||
2441 | struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2; | ||
2442 | struct cvmx_gmxx_tx_spi_ctl_s cn58xx; | ||
2443 | struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1; | ||
2444 | }; | ||
2445 | |||
2446 | union cvmx_gmxx_tx_spi_drain { | ||
2447 | uint64_t u64; | ||
2448 | struct cvmx_gmxx_tx_spi_drain_s { | ||
2449 | uint64_t reserved_16_63:48; | ||
2450 | uint64_t drain:16; | ||
2451 | } s; | ||
2452 | struct cvmx_gmxx_tx_spi_drain_s cn38xx; | ||
2453 | struct cvmx_gmxx_tx_spi_drain_s cn58xx; | ||
2454 | struct cvmx_gmxx_tx_spi_drain_s cn58xxp1; | ||
2455 | }; | ||
2456 | |||
2457 | union cvmx_gmxx_tx_spi_max { | ||
2458 | uint64_t u64; | ||
2459 | struct cvmx_gmxx_tx_spi_max_s { | ||
2460 | uint64_t reserved_23_63:41; | ||
2461 | uint64_t slice:7; | ||
2462 | uint64_t max2:8; | ||
2463 | uint64_t max1:8; | ||
2464 | } s; | ||
2465 | struct cvmx_gmxx_tx_spi_max_cn38xx { | ||
2466 | uint64_t reserved_16_63:48; | ||
2467 | uint64_t max2:8; | ||
2468 | uint64_t max1:8; | ||
2469 | } cn38xx; | ||
2470 | struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2; | ||
2471 | struct cvmx_gmxx_tx_spi_max_s cn58xx; | ||
2472 | struct cvmx_gmxx_tx_spi_max_s cn58xxp1; | ||
2473 | }; | ||
2474 | |||
2475 | union cvmx_gmxx_tx_spi_roundx { | ||
2476 | uint64_t u64; | ||
2477 | struct cvmx_gmxx_tx_spi_roundx_s { | ||
2478 | uint64_t reserved_16_63:48; | ||
2479 | uint64_t round:16; | ||
2480 | } s; | ||
2481 | struct cvmx_gmxx_tx_spi_roundx_s cn58xx; | ||
2482 | struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1; | ||
2483 | }; | ||
2484 | |||
2485 | union cvmx_gmxx_tx_spi_thresh { | ||
2486 | uint64_t u64; | ||
2487 | struct cvmx_gmxx_tx_spi_thresh_s { | ||
2488 | uint64_t reserved_6_63:58; | ||
2489 | uint64_t thresh:6; | ||
2490 | } s; | ||
2491 | struct cvmx_gmxx_tx_spi_thresh_s cn38xx; | ||
2492 | struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2; | ||
2493 | struct cvmx_gmxx_tx_spi_thresh_s cn58xx; | ||
2494 | struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1; | ||
2495 | }; | ||
2496 | |||
2497 | union cvmx_gmxx_tx_xaui_ctl { | ||
2498 | uint64_t u64; | ||
2499 | struct cvmx_gmxx_tx_xaui_ctl_s { | ||
2500 | uint64_t reserved_11_63:53; | ||
2501 | uint64_t hg_pause_hgi:2; | ||
2502 | uint64_t hg_en:1; | ||
2503 | uint64_t reserved_7_7:1; | ||
2504 | uint64_t ls_byp:1; | ||
2505 | uint64_t ls:2; | ||
2506 | uint64_t reserved_2_3:2; | ||
2507 | uint64_t uni_en:1; | ||
2508 | uint64_t dic_en:1; | ||
2509 | } s; | ||
2510 | struct cvmx_gmxx_tx_xaui_ctl_s cn52xx; | ||
2511 | struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1; | ||
2512 | struct cvmx_gmxx_tx_xaui_ctl_s cn56xx; | ||
2513 | struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1; | ||
2514 | }; | ||
2515 | |||
2516 | union cvmx_gmxx_xaui_ext_loopback { | ||
2517 | uint64_t u64; | ||
2518 | struct cvmx_gmxx_xaui_ext_loopback_s { | ||
2519 | uint64_t reserved_5_63:59; | ||
2520 | uint64_t en:1; | ||
2521 | uint64_t thresh:4; | ||
2522 | } s; | ||
2523 | struct cvmx_gmxx_xaui_ext_loopback_s cn52xx; | ||
2524 | struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1; | ||
2525 | struct cvmx_gmxx_xaui_ext_loopback_s cn56xx; | ||
2526 | struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1; | ||
2527 | }; | ||
2528 | |||
2529 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/drivers/staging/octeon/cvmx-helper-board.c new file mode 100644 index 000000000000..3085e38a6f99 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-board.c | |||
@@ -0,0 +1,706 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * | ||
30 | * Helper functions to abstract board specific data about | ||
31 | * network ports from the rest of the cvmx-helper files. | ||
32 | */ | ||
33 | |||
34 | #include <asm/octeon/octeon.h> | ||
35 | #include <asm/octeon/cvmx-bootinfo.h> | ||
36 | |||
37 | #include "cvmx-config.h" | ||
38 | |||
39 | #include "cvmx-mdio.h" | ||
40 | |||
41 | #include "cvmx-helper.h" | ||
42 | #include "cvmx-helper-util.h" | ||
43 | #include "cvmx-helper-board.h" | ||
44 | |||
45 | #include "cvmx-gmxx-defs.h" | ||
46 | #include "cvmx-asxx-defs.h" | ||
47 | |||
48 | /** | ||
49 | * cvmx_override_board_link_get(int ipd_port) is a function | ||
50 | * pointer. It is meant to allow customization of the process of | ||
51 | * talking to a PHY to determine link speed. It is called every | ||
52 | * time a PHY must be polled for link status. Users should set | ||
53 | * this pointer to a function before calling any cvmx-helper | ||
54 | * operations. | ||
55 | */ | ||
56 | cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) = | ||
57 | NULL; | ||
58 | |||
59 | /** | ||
60 | * Return the MII PHY address associated with the given IPD | ||
61 | * port. A result of -1 means there isn't a MII capable PHY | ||
62 | * connected to this port. On chips supporting multiple MII | ||
63 | * busses the bus number is encoded in bits <15:8>. | ||
64 | * | ||
65 | * This function must be modified for every new Octeon board. | ||
66 | * Internally it uses switch statements based on the cvmx_sysinfo | ||
67 | * data to determine board types and revisions. It replies on the | ||
68 | * fact that every Octeon board receives a unique board type | ||
69 | * enumeration from the bootloader. | ||
70 | * | ||
71 | * @ipd_port: Octeon IPD port to get the MII address for. | ||
72 | * | ||
73 | * Returns MII PHY address and bus number or -1. | ||
74 | */ | ||
75 | int cvmx_helper_board_get_mii_address(int ipd_port) | ||
76 | { | ||
77 | switch (cvmx_sysinfo_get()->board_type) { | ||
78 | case CVMX_BOARD_TYPE_SIM: | ||
79 | /* Simulator doesn't have MII */ | ||
80 | return -1; | ||
81 | case CVMX_BOARD_TYPE_EBT3000: | ||
82 | case CVMX_BOARD_TYPE_EBT5800: | ||
83 | case CVMX_BOARD_TYPE_THUNDER: | ||
84 | case CVMX_BOARD_TYPE_NICPRO2: | ||
85 | /* Interface 0 is SPI4, interface 1 is RGMII */ | ||
86 | if ((ipd_port >= 16) && (ipd_port < 20)) | ||
87 | return ipd_port - 16; | ||
88 | else | ||
89 | return -1; | ||
90 | case CVMX_BOARD_TYPE_KODAMA: | ||
91 | case CVMX_BOARD_TYPE_EBH3100: | ||
92 | case CVMX_BOARD_TYPE_HIKARI: | ||
93 | case CVMX_BOARD_TYPE_CN3010_EVB_HS5: | ||
94 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: | ||
95 | case CVMX_BOARD_TYPE_CN3020_EVB_HS5: | ||
96 | /* | ||
97 | * Port 0 is WAN connected to a PHY, Port 1 is GMII | ||
98 | * connected to a switch | ||
99 | */ | ||
100 | if (ipd_port == 0) | ||
101 | return 4; | ||
102 | else if (ipd_port == 1) | ||
103 | return 9; | ||
104 | else | ||
105 | return -1; | ||
106 | case CVMX_BOARD_TYPE_NAC38: | ||
107 | /* Board has 8 RGMII ports PHYs are 0-7 */ | ||
108 | if ((ipd_port >= 0) && (ipd_port < 4)) | ||
109 | return ipd_port; | ||
110 | else if ((ipd_port >= 16) && (ipd_port < 20)) | ||
111 | return ipd_port - 16 + 4; | ||
112 | else | ||
113 | return -1; | ||
114 | case CVMX_BOARD_TYPE_EBH3000: | ||
115 | /* Board has dual SPI4 and no PHYs */ | ||
116 | return -1; | ||
117 | case CVMX_BOARD_TYPE_EBH5200: | ||
118 | case CVMX_BOARD_TYPE_EBH5201: | ||
119 | case CVMX_BOARD_TYPE_EBT5200: | ||
120 | /* | ||
121 | * Board has 4 SGMII ports. The PHYs start right after the MII | ||
122 | * ports MII0 = 0, MII1 = 1, SGMII = 2-5. | ||
123 | */ | ||
124 | if ((ipd_port >= 0) && (ipd_port < 4)) | ||
125 | return ipd_port + 2; | ||
126 | else | ||
127 | return -1; | ||
128 | case CVMX_BOARD_TYPE_EBH5600: | ||
129 | case CVMX_BOARD_TYPE_EBH5601: | ||
130 | case CVMX_BOARD_TYPE_EBH5610: | ||
131 | /* | ||
132 | * Board has 8 SGMII ports. 4 connect out, two connect | ||
133 | * to a switch, and 2 loop to each other | ||
134 | */ | ||
135 | if ((ipd_port >= 0) && (ipd_port < 4)) | ||
136 | return ipd_port + 1; | ||
137 | else | ||
138 | return -1; | ||
139 | case CVMX_BOARD_TYPE_CUST_NB5: | ||
140 | if (ipd_port == 2) | ||
141 | return 4; | ||
142 | else | ||
143 | return -1; | ||
144 | case CVMX_BOARD_TYPE_NIC_XLE_4G: | ||
145 | /* Board has 4 SGMII ports. connected QLM3(interface 1) */ | ||
146 | if ((ipd_port >= 16) && (ipd_port < 20)) | ||
147 | return ipd_port - 16 + 1; | ||
148 | else | ||
149 | return -1; | ||
150 | case CVMX_BOARD_TYPE_BBGW_REF: | ||
151 | /* | ||
152 | * No PHYs are connected to Octeon, everything is | ||
153 | * through switch. | ||
154 | */ | ||
155 | return -1; | ||
156 | } | ||
157 | |||
158 | /* Some unknown board. Somebody forgot to update this function... */ | ||
159 | cvmx_dprintf | ||
160 | ("cvmx_helper_board_get_mii_address: Unknown board type %d\n", | ||
161 | cvmx_sysinfo_get()->board_type); | ||
162 | return -1; | ||
163 | } | ||
164 | |||
165 | /** | ||
166 | * This function is the board specific method of determining an | ||
167 | * ethernet ports link speed. Most Octeon boards have Marvell PHYs | ||
168 | * and are handled by the fall through case. This function must be | ||
169 | * updated for boards that don't have the normal Marvell PHYs. | ||
170 | * | ||
171 | * This function must be modified for every new Octeon board. | ||
172 | * Internally it uses switch statements based on the cvmx_sysinfo | ||
173 | * data to determine board types and revisions. It relies on the | ||
174 | * fact that every Octeon board receives a unique board type | ||
175 | * enumeration from the bootloader. | ||
176 | * | ||
177 | * @ipd_port: IPD input port associated with the port we want to get link | ||
178 | * status for. | ||
179 | * | ||
180 | * Returns The ports link status. If the link isn't fully resolved, this must | ||
181 | * return zero. | ||
182 | */ | ||
183 | cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) | ||
184 | { | ||
185 | cvmx_helper_link_info_t result; | ||
186 | int phy_addr; | ||
187 | int is_broadcom_phy = 0; | ||
188 | |||
189 | /* Give the user a chance to override the processing of this function */ | ||
190 | if (cvmx_override_board_link_get) | ||
191 | return cvmx_override_board_link_get(ipd_port); | ||
192 | |||
193 | /* Unless we fix it later, all links are defaulted to down */ | ||
194 | result.u64 = 0; | ||
195 | |||
196 | /* | ||
197 | * This switch statement should handle all ports that either don't use | ||
198 | * Marvell PHYS, or don't support in-band status. | ||
199 | */ | ||
200 | switch (cvmx_sysinfo_get()->board_type) { | ||
201 | case CVMX_BOARD_TYPE_SIM: | ||
202 | /* The simulator gives you a simulated 1Gbps full duplex link */ | ||
203 | result.s.link_up = 1; | ||
204 | result.s.full_duplex = 1; | ||
205 | result.s.speed = 1000; | ||
206 | return result; | ||
207 | case CVMX_BOARD_TYPE_EBH3100: | ||
208 | case CVMX_BOARD_TYPE_CN3010_EVB_HS5: | ||
209 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: | ||
210 | case CVMX_BOARD_TYPE_CN3020_EVB_HS5: | ||
211 | /* Port 1 on these boards is always Gigabit */ | ||
212 | if (ipd_port == 1) { | ||
213 | result.s.link_up = 1; | ||
214 | result.s.full_duplex = 1; | ||
215 | result.s.speed = 1000; | ||
216 | return result; | ||
217 | } | ||
218 | /* Fall through to the generic code below */ | ||
219 | break; | ||
220 | case CVMX_BOARD_TYPE_CUST_NB5: | ||
221 | /* Port 1 on these boards is always Gigabit */ | ||
222 | if (ipd_port == 1) { | ||
223 | result.s.link_up = 1; | ||
224 | result.s.full_duplex = 1; | ||
225 | result.s.speed = 1000; | ||
226 | return result; | ||
227 | } else /* The other port uses a broadcom PHY */ | ||
228 | is_broadcom_phy = 1; | ||
229 | break; | ||
230 | case CVMX_BOARD_TYPE_BBGW_REF: | ||
231 | /* Port 1 on these boards is always Gigabit */ | ||
232 | if (ipd_port == 2) { | ||
233 | /* Port 2 is not hooked up */ | ||
234 | result.u64 = 0; | ||
235 | return result; | ||
236 | } else { | ||
237 | /* Ports 0 and 1 connect to the switch */ | ||
238 | result.s.link_up = 1; | ||
239 | result.s.full_duplex = 1; | ||
240 | result.s.speed = 1000; | ||
241 | return result; | ||
242 | } | ||
243 | break; | ||
244 | } | ||
245 | |||
246 | phy_addr = cvmx_helper_board_get_mii_address(ipd_port); | ||
247 | if (phy_addr != -1) { | ||
248 | if (is_broadcom_phy) { | ||
249 | /* | ||
250 | * Below we are going to read SMI/MDIO | ||
251 | * register 0x19 which works on Broadcom | ||
252 | * parts | ||
253 | */ | ||
254 | int phy_status = | ||
255 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
256 | 0x19); | ||
257 | switch ((phy_status >> 8) & 0x7) { | ||
258 | case 0: | ||
259 | result.u64 = 0; | ||
260 | break; | ||
261 | case 1: | ||
262 | result.s.link_up = 1; | ||
263 | result.s.full_duplex = 0; | ||
264 | result.s.speed = 10; | ||
265 | break; | ||
266 | case 2: | ||
267 | result.s.link_up = 1; | ||
268 | result.s.full_duplex = 1; | ||
269 | result.s.speed = 10; | ||
270 | break; | ||
271 | case 3: | ||
272 | result.s.link_up = 1; | ||
273 | result.s.full_duplex = 0; | ||
274 | result.s.speed = 100; | ||
275 | break; | ||
276 | case 4: | ||
277 | result.s.link_up = 1; | ||
278 | result.s.full_duplex = 1; | ||
279 | result.s.speed = 100; | ||
280 | break; | ||
281 | case 5: | ||
282 | result.s.link_up = 1; | ||
283 | result.s.full_duplex = 1; | ||
284 | result.s.speed = 100; | ||
285 | break; | ||
286 | case 6: | ||
287 | result.s.link_up = 1; | ||
288 | result.s.full_duplex = 0; | ||
289 | result.s.speed = 1000; | ||
290 | break; | ||
291 | case 7: | ||
292 | result.s.link_up = 1; | ||
293 | result.s.full_duplex = 1; | ||
294 | result.s.speed = 1000; | ||
295 | break; | ||
296 | } | ||
297 | } else { | ||
298 | /* | ||
299 | * This code assumes we are using a Marvell | ||
300 | * Gigabit PHY. All the speed information can | ||
301 | * be read from register 17 in one | ||
302 | * go. Somebody using a different PHY will | ||
303 | * need to handle it above in the board | ||
304 | * specific area. | ||
305 | */ | ||
306 | int phy_status = | ||
307 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17); | ||
308 | |||
309 | /* | ||
310 | * If the resolve bit 11 isn't set, see if | ||
311 | * autoneg is turned off (bit 12, reg 0). The | ||
312 | * resolve bit doesn't get set properly when | ||
313 | * autoneg is off, so force it. | ||
314 | */ | ||
315 | if ((phy_status & (1 << 11)) == 0) { | ||
316 | int auto_status = | ||
317 | cvmx_mdio_read(phy_addr >> 8, | ||
318 | phy_addr & 0xff, 0); | ||
319 | if ((auto_status & (1 << 12)) == 0) | ||
320 | phy_status |= 1 << 11; | ||
321 | } | ||
322 | |||
323 | /* | ||
324 | * Only return a link if the PHY has finished | ||
325 | * auto negotiation and set the resolved bit | ||
326 | * (bit 11) | ||
327 | */ | ||
328 | if (phy_status & (1 << 11)) { | ||
329 | result.s.link_up = 1; | ||
330 | result.s.full_duplex = ((phy_status >> 13) & 1); | ||
331 | switch ((phy_status >> 14) & 3) { | ||
332 | case 0: /* 10 Mbps */ | ||
333 | result.s.speed = 10; | ||
334 | break; | ||
335 | case 1: /* 100 Mbps */ | ||
336 | result.s.speed = 100; | ||
337 | break; | ||
338 | case 2: /* 1 Gbps */ | ||
339 | result.s.speed = 1000; | ||
340 | break; | ||
341 | case 3: /* Illegal */ | ||
342 | result.u64 = 0; | ||
343 | break; | ||
344 | } | ||
345 | } | ||
346 | } | ||
347 | } else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) | ||
348 | || OCTEON_IS_MODEL(OCTEON_CN58XX) | ||
349 | || OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
350 | /* | ||
351 | * We don't have a PHY address, so attempt to use | ||
352 | * in-band status. It is really important that boards | ||
353 | * not supporting in-band status never get | ||
354 | * here. Reading broken in-band status tends to do bad | ||
355 | * things | ||
356 | */ | ||
357 | union cvmx_gmxx_rxx_rx_inbnd inband_status; | ||
358 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
359 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
360 | inband_status.u64 = | ||
361 | cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); | ||
362 | |||
363 | result.s.link_up = inband_status.s.status; | ||
364 | result.s.full_duplex = inband_status.s.duplex; | ||
365 | switch (inband_status.s.speed) { | ||
366 | case 0: /* 10 Mbps */ | ||
367 | result.s.speed = 10; | ||
368 | break; | ||
369 | case 1: /* 100 Mbps */ | ||
370 | result.s.speed = 100; | ||
371 | break; | ||
372 | case 2: /* 1 Gbps */ | ||
373 | result.s.speed = 1000; | ||
374 | break; | ||
375 | case 3: /* Illegal */ | ||
376 | result.u64 = 0; | ||
377 | break; | ||
378 | } | ||
379 | } else { | ||
380 | /* | ||
381 | * We don't have a PHY address and we don't have | ||
382 | * in-band status. There is no way to determine the | ||
383 | * link speed. Return down assuming this port isn't | ||
384 | * wired | ||
385 | */ | ||
386 | result.u64 = 0; | ||
387 | } | ||
388 | |||
389 | /* If link is down, return all fields as zero. */ | ||
390 | if (!result.s.link_up) | ||
391 | result.u64 = 0; | ||
392 | |||
393 | return result; | ||
394 | } | ||
395 | |||
396 | /** | ||
397 | * This function as a board specific method of changing the PHY | ||
398 | * speed, duplex, and auto-negotiation. This programs the PHY and | ||
399 | * not Octeon. This can be used to force Octeon's links to | ||
400 | * specific settings. | ||
401 | * | ||
402 | * @phy_addr: The address of the PHY to program | ||
403 | * @enable_autoneg: | ||
404 | * Non zero if you want to enable auto-negotiation. | ||
405 | * @link_info: Link speed to program. If the speed is zero and auto-negotiation | ||
406 | * is enabled, all possible negotiation speeds are advertised. | ||
407 | * | ||
408 | * Returns Zero on success, negative on failure | ||
409 | */ | ||
410 | int cvmx_helper_board_link_set_phy(int phy_addr, | ||
411 | cvmx_helper_board_set_phy_link_flags_types_t | ||
412 | link_flags, | ||
413 | cvmx_helper_link_info_t link_info) | ||
414 | { | ||
415 | |||
416 | /* Set the flow control settings based on link_flags */ | ||
417 | if ((link_flags & set_phy_link_flags_flow_control_mask) != | ||
418 | set_phy_link_flags_flow_control_dont_touch) { | ||
419 | cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; | ||
420 | reg_autoneg_adver.u16 = | ||
421 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
422 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER); | ||
423 | reg_autoneg_adver.s.asymmetric_pause = | ||
424 | (link_flags & set_phy_link_flags_flow_control_mask) == | ||
425 | set_phy_link_flags_flow_control_enable; | ||
426 | reg_autoneg_adver.s.pause = | ||
427 | (link_flags & set_phy_link_flags_flow_control_mask) == | ||
428 | set_phy_link_flags_flow_control_enable; | ||
429 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | ||
430 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER, | ||
431 | reg_autoneg_adver.u16); | ||
432 | } | ||
433 | |||
434 | /* If speed isn't set and autoneg is on advertise all supported modes */ | ||
435 | if ((link_flags & set_phy_link_flags_autoneg) | ||
436 | && (link_info.s.speed == 0)) { | ||
437 | cvmx_mdio_phy_reg_control_t reg_control; | ||
438 | cvmx_mdio_phy_reg_status_t reg_status; | ||
439 | cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; | ||
440 | cvmx_mdio_phy_reg_extended_status_t reg_extended_status; | ||
441 | cvmx_mdio_phy_reg_control_1000_t reg_control_1000; | ||
442 | |||
443 | reg_status.u16 = | ||
444 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
445 | CVMX_MDIO_PHY_REG_STATUS); | ||
446 | reg_autoneg_adver.u16 = | ||
447 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
448 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER); | ||
449 | reg_autoneg_adver.s.advert_100base_t4 = | ||
450 | reg_status.s.capable_100base_t4; | ||
451 | reg_autoneg_adver.s.advert_10base_tx_full = | ||
452 | reg_status.s.capable_10_full; | ||
453 | reg_autoneg_adver.s.advert_10base_tx_half = | ||
454 | reg_status.s.capable_10_half; | ||
455 | reg_autoneg_adver.s.advert_100base_tx_full = | ||
456 | reg_status.s.capable_100base_x_full; | ||
457 | reg_autoneg_adver.s.advert_100base_tx_half = | ||
458 | reg_status.s.capable_100base_x_half; | ||
459 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | ||
460 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER, | ||
461 | reg_autoneg_adver.u16); | ||
462 | if (reg_status.s.capable_extended_status) { | ||
463 | reg_extended_status.u16 = | ||
464 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
465 | CVMX_MDIO_PHY_REG_EXTENDED_STATUS); | ||
466 | reg_control_1000.u16 = | ||
467 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
468 | CVMX_MDIO_PHY_REG_CONTROL_1000); | ||
469 | reg_control_1000.s.advert_1000base_t_full = | ||
470 | reg_extended_status.s.capable_1000base_t_full; | ||
471 | reg_control_1000.s.advert_1000base_t_half = | ||
472 | reg_extended_status.s.capable_1000base_t_half; | ||
473 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | ||
474 | CVMX_MDIO_PHY_REG_CONTROL_1000, | ||
475 | reg_control_1000.u16); | ||
476 | } | ||
477 | reg_control.u16 = | ||
478 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
479 | CVMX_MDIO_PHY_REG_CONTROL); | ||
480 | reg_control.s.autoneg_enable = 1; | ||
481 | reg_control.s.restart_autoneg = 1; | ||
482 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | ||
483 | CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); | ||
484 | } else if ((link_flags & set_phy_link_flags_autoneg)) { | ||
485 | cvmx_mdio_phy_reg_control_t reg_control; | ||
486 | cvmx_mdio_phy_reg_status_t reg_status; | ||
487 | cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; | ||
488 | cvmx_mdio_phy_reg_extended_status_t reg_extended_status; | ||
489 | cvmx_mdio_phy_reg_control_1000_t reg_control_1000; | ||
490 | |||
491 | reg_status.u16 = | ||
492 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
493 | CVMX_MDIO_PHY_REG_STATUS); | ||
494 | reg_autoneg_adver.u16 = | ||
495 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
496 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER); | ||
497 | reg_autoneg_adver.s.advert_100base_t4 = 0; | ||
498 | reg_autoneg_adver.s.advert_10base_tx_full = 0; | ||
499 | reg_autoneg_adver.s.advert_10base_tx_half = 0; | ||
500 | reg_autoneg_adver.s.advert_100base_tx_full = 0; | ||
501 | reg_autoneg_adver.s.advert_100base_tx_half = 0; | ||
502 | if (reg_status.s.capable_extended_status) { | ||
503 | reg_extended_status.u16 = | ||
504 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
505 | CVMX_MDIO_PHY_REG_EXTENDED_STATUS); | ||
506 | reg_control_1000.u16 = | ||
507 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
508 | CVMX_MDIO_PHY_REG_CONTROL_1000); | ||
509 | reg_control_1000.s.advert_1000base_t_full = 0; | ||
510 | reg_control_1000.s.advert_1000base_t_half = 0; | ||
511 | } | ||
512 | switch (link_info.s.speed) { | ||
513 | case 10: | ||
514 | reg_autoneg_adver.s.advert_10base_tx_full = | ||
515 | link_info.s.full_duplex; | ||
516 | reg_autoneg_adver.s.advert_10base_tx_half = | ||
517 | !link_info.s.full_duplex; | ||
518 | break; | ||
519 | case 100: | ||
520 | reg_autoneg_adver.s.advert_100base_tx_full = | ||
521 | link_info.s.full_duplex; | ||
522 | reg_autoneg_adver.s.advert_100base_tx_half = | ||
523 | !link_info.s.full_duplex; | ||
524 | break; | ||
525 | case 1000: | ||
526 | reg_control_1000.s.advert_1000base_t_full = | ||
527 | link_info.s.full_duplex; | ||
528 | reg_control_1000.s.advert_1000base_t_half = | ||
529 | !link_info.s.full_duplex; | ||
530 | break; | ||
531 | } | ||
532 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | ||
533 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER, | ||
534 | reg_autoneg_adver.u16); | ||
535 | if (reg_status.s.capable_extended_status) | ||
536 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | ||
537 | CVMX_MDIO_PHY_REG_CONTROL_1000, | ||
538 | reg_control_1000.u16); | ||
539 | reg_control.u16 = | ||
540 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
541 | CVMX_MDIO_PHY_REG_CONTROL); | ||
542 | reg_control.s.autoneg_enable = 1; | ||
543 | reg_control.s.restart_autoneg = 1; | ||
544 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | ||
545 | CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); | ||
546 | } else { | ||
547 | cvmx_mdio_phy_reg_control_t reg_control; | ||
548 | reg_control.u16 = | ||
549 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | ||
550 | CVMX_MDIO_PHY_REG_CONTROL); | ||
551 | reg_control.s.autoneg_enable = 0; | ||
552 | reg_control.s.restart_autoneg = 1; | ||
553 | reg_control.s.duplex = link_info.s.full_duplex; | ||
554 | if (link_info.s.speed == 1000) { | ||
555 | reg_control.s.speed_msb = 1; | ||
556 | reg_control.s.speed_lsb = 0; | ||
557 | } else if (link_info.s.speed == 100) { | ||
558 | reg_control.s.speed_msb = 0; | ||
559 | reg_control.s.speed_lsb = 1; | ||
560 | } else if (link_info.s.speed == 10) { | ||
561 | reg_control.s.speed_msb = 0; | ||
562 | reg_control.s.speed_lsb = 0; | ||
563 | } | ||
564 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | ||
565 | CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); | ||
566 | } | ||
567 | return 0; | ||
568 | } | ||
569 | |||
570 | /** | ||
571 | * This function is called by cvmx_helper_interface_probe() after it | ||
572 | * determines the number of ports Octeon can support on a specific | ||
573 | * interface. This function is the per board location to override | ||
574 | * this value. It is called with the number of ports Octeon might | ||
575 | * support and should return the number of actual ports on the | ||
576 | * board. | ||
577 | * | ||
578 | * This function must be modifed for every new Octeon board. | ||
579 | * Internally it uses switch statements based on the cvmx_sysinfo | ||
580 | * data to determine board types and revisions. It relys on the | ||
581 | * fact that every Octeon board receives a unique board type | ||
582 | * enumeration from the bootloader. | ||
583 | * | ||
584 | * @interface: Interface to probe | ||
585 | * @supported_ports: | ||
586 | * Number of ports Octeon supports. | ||
587 | * | ||
588 | * Returns Number of ports the actual board supports. Many times this will | ||
589 | * simple be "support_ports". | ||
590 | */ | ||
591 | int __cvmx_helper_board_interface_probe(int interface, int supported_ports) | ||
592 | { | ||
593 | switch (cvmx_sysinfo_get()->board_type) { | ||
594 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: | ||
595 | if (interface == 0) | ||
596 | return 2; | ||
597 | break; | ||
598 | case CVMX_BOARD_TYPE_BBGW_REF: | ||
599 | if (interface == 0) | ||
600 | return 2; | ||
601 | break; | ||
602 | case CVMX_BOARD_TYPE_NIC_XLE_4G: | ||
603 | if (interface == 0) | ||
604 | return 0; | ||
605 | break; | ||
606 | /* The 2nd interface on the EBH5600 is connected to the Marvel switch, | ||
607 | which we don't support. Disable ports connected to it */ | ||
608 | case CVMX_BOARD_TYPE_EBH5600: | ||
609 | if (interface == 1) | ||
610 | return 0; | ||
611 | break; | ||
612 | } | ||
613 | return supported_ports; | ||
614 | } | ||
615 | |||
616 | /** | ||
617 | * Enable packet input/output from the hardware. This function is | ||
618 | * called after by cvmx_helper_packet_hardware_enable() to | ||
619 | * perform board specific initialization. For most boards | ||
620 | * nothing is needed. | ||
621 | * | ||
622 | * @interface: Interface to enable | ||
623 | * | ||
624 | * Returns Zero on success, negative on failure | ||
625 | */ | ||
626 | int __cvmx_helper_board_hardware_enable(int interface) | ||
627 | { | ||
628 | if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) { | ||
629 | if (interface == 0) { | ||
630 | /* Different config for switch port */ | ||
631 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); | ||
632 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); | ||
633 | /* | ||
634 | * Boards with gigabit WAN ports need a | ||
635 | * different setting that is compatible with | ||
636 | * 100 Mbit settings | ||
637 | */ | ||
638 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), | ||
639 | 0xc); | ||
640 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), | ||
641 | 0xc); | ||
642 | } | ||
643 | } else if (cvmx_sysinfo_get()->board_type == | ||
644 | CVMX_BOARD_TYPE_CN3010_EVB_HS5) { | ||
645 | /* | ||
646 | * Broadcom PHYs require differnet ASX | ||
647 | * clocks. Unfortunately many boards don't define a | ||
648 | * new board Id and simply mangle the | ||
649 | * CN3010_EVB_HS5 | ||
650 | */ | ||
651 | if (interface == 0) { | ||
652 | /* | ||
653 | * Some boards use a hacked up bootloader that | ||
654 | * identifies them as CN3010_EVB_HS5 | ||
655 | * evaluation boards. This leads to all kinds | ||
656 | * of configuration problems. Detect one | ||
657 | * case, and print warning, while trying to do | ||
658 | * the right thing. | ||
659 | */ | ||
660 | int phy_addr = cvmx_helper_board_get_mii_address(0); | ||
661 | if (phy_addr != -1) { | ||
662 | int phy_identifier = | ||
663 | cvmx_mdio_read(phy_addr >> 8, | ||
664 | phy_addr & 0xff, 0x2); | ||
665 | /* Is it a Broadcom PHY? */ | ||
666 | if (phy_identifier == 0x0143) { | ||
667 | cvmx_dprintf("\n"); | ||
668 | cvmx_dprintf("ERROR:\n"); | ||
669 | cvmx_dprintf | ||
670 | ("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n"); | ||
671 | cvmx_dprintf | ||
672 | ("ERROR: The board type is mis-configured, and software malfunctions are likely.\n"); | ||
673 | cvmx_dprintf | ||
674 | ("ERROR: All boards require a unique board type to identify them.\n"); | ||
675 | cvmx_dprintf("ERROR:\n"); | ||
676 | cvmx_dprintf("\n"); | ||
677 | cvmx_wait(1000000000); | ||
678 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX | ||
679 | (0, interface), 5); | ||
680 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX | ||
681 | (0, interface), 5); | ||
682 | } | ||
683 | } | ||
684 | } | ||
685 | } | ||
686 | return 0; | ||
687 | } | ||
688 | |||
689 | cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void) | ||
690 | { | ||
691 | switch (cvmx_sysinfo_get()->board_type) { | ||
692 | case CVMX_BOARD_TYPE_BBGW_REF: | ||
693 | return USB_CLOCK_TYPE_CRYSTAL_12; | ||
694 | } | ||
695 | return USB_CLOCK_TYPE_REF_48; | ||
696 | } | ||
697 | |||
698 | int __cvmx_helper_board_usb_get_num_ports(int supported_ports) | ||
699 | { | ||
700 | switch (cvmx_sysinfo_get()->board_type) { | ||
701 | case CVMX_BOARD_TYPE_NIC_XLE_4G: | ||
702 | return 0; | ||
703 | } | ||
704 | |||
705 | return supported_ports; | ||
706 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/drivers/staging/octeon/cvmx-helper-board.h new file mode 100644 index 000000000000..dc20b01247c4 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-board.h | |||
@@ -0,0 +1,180 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * | ||
30 | * Helper functions to abstract board specific data about | ||
31 | * network ports from the rest of the cvmx-helper files. | ||
32 | * | ||
33 | */ | ||
34 | #ifndef __CVMX_HELPER_BOARD_H__ | ||
35 | #define __CVMX_HELPER_BOARD_H__ | ||
36 | |||
37 | #include "cvmx-helper.h" | ||
38 | |||
39 | typedef enum { | ||
40 | USB_CLOCK_TYPE_REF_12, | ||
41 | USB_CLOCK_TYPE_REF_24, | ||
42 | USB_CLOCK_TYPE_REF_48, | ||
43 | USB_CLOCK_TYPE_CRYSTAL_12, | ||
44 | } cvmx_helper_board_usb_clock_types_t; | ||
45 | |||
46 | typedef enum { | ||
47 | set_phy_link_flags_autoneg = 0x1, | ||
48 | set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, | ||
49 | set_phy_link_flags_flow_control_enable = 0x1 << 1, | ||
50 | set_phy_link_flags_flow_control_disable = 0x2 << 1, | ||
51 | set_phy_link_flags_flow_control_mask = 0x3 << 1, /* Mask for 2 bit wide flow control field */ | ||
52 | } cvmx_helper_board_set_phy_link_flags_types_t; | ||
53 | |||
54 | /** | ||
55 | * cvmx_override_board_link_get(int ipd_port) is a function | ||
56 | * pointer. It is meant to allow customization of the process of | ||
57 | * talking to a PHY to determine link speed. It is called every | ||
58 | * time a PHY must be polled for link status. Users should set | ||
59 | * this pointer to a function before calling any cvmx-helper | ||
60 | * operations. | ||
61 | */ | ||
62 | extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port); | ||
63 | |||
64 | /** | ||
65 | * Return the MII PHY address associated with the given IPD | ||
66 | * port. A result of -1 means there isn't a MII capable PHY | ||
67 | * connected to this port. On chips supporting multiple MII | ||
68 | * busses the bus number is encoded in bits <15:8>. | ||
69 | * | ||
70 | * This function must be modifed for every new Octeon board. | ||
71 | * Internally it uses switch statements based on the cvmx_sysinfo | ||
72 | * data to determine board types and revisions. It relys on the | ||
73 | * fact that every Octeon board receives a unique board type | ||
74 | * enumeration from the bootloader. | ||
75 | * | ||
76 | * @ipd_port: Octeon IPD port to get the MII address for. | ||
77 | * | ||
78 | * Returns MII PHY address and bus number or -1. | ||
79 | */ | ||
80 | extern int cvmx_helper_board_get_mii_address(int ipd_port); | ||
81 | |||
82 | /** | ||
83 | * This function as a board specific method of changing the PHY | ||
84 | * speed, duplex, and autonegotiation. This programs the PHY and | ||
85 | * not Octeon. This can be used to force Octeon's links to | ||
86 | * specific settings. | ||
87 | * | ||
88 | * @phy_addr: The address of the PHY to program | ||
89 | * @link_flags: | ||
90 | * Flags to control autonegotiation. Bit 0 is autonegotiation | ||
91 | * enable/disable to maintain backware compatability. | ||
92 | * @link_info: Link speed to program. If the speed is zero and autonegotiation | ||
93 | * is enabled, all possible negotiation speeds are advertised. | ||
94 | * | ||
95 | * Returns Zero on success, negative on failure | ||
96 | */ | ||
97 | int cvmx_helper_board_link_set_phy(int phy_addr, | ||
98 | cvmx_helper_board_set_phy_link_flags_types_t | ||
99 | link_flags, | ||
100 | cvmx_helper_link_info_t link_info); | ||
101 | |||
102 | /** | ||
103 | * This function is the board specific method of determining an | ||
104 | * ethernet ports link speed. Most Octeon boards have Marvell PHYs | ||
105 | * and are handled by the fall through case. This function must be | ||
106 | * updated for boards that don't have the normal Marvell PHYs. | ||
107 | * | ||
108 | * This function must be modifed for every new Octeon board. | ||
109 | * Internally it uses switch statements based on the cvmx_sysinfo | ||
110 | * data to determine board types and revisions. It relys on the | ||
111 | * fact that every Octeon board receives a unique board type | ||
112 | * enumeration from the bootloader. | ||
113 | * | ||
114 | * @ipd_port: IPD input port associated with the port we want to get link | ||
115 | * status for. | ||
116 | * | ||
117 | * Returns The ports link status. If the link isn't fully resolved, this must | ||
118 | * return zero. | ||
119 | */ | ||
120 | extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port); | ||
121 | |||
122 | /** | ||
123 | * This function is called by cvmx_helper_interface_probe() after it | ||
124 | * determines the number of ports Octeon can support on a specific | ||
125 | * interface. This function is the per board location to override | ||
126 | * this value. It is called with the number of ports Octeon might | ||
127 | * support and should return the number of actual ports on the | ||
128 | * board. | ||
129 | * | ||
130 | * This function must be modifed for every new Octeon board. | ||
131 | * Internally it uses switch statements based on the cvmx_sysinfo | ||
132 | * data to determine board types and revisions. It relys on the | ||
133 | * fact that every Octeon board receives a unique board type | ||
134 | * enumeration from the bootloader. | ||
135 | * | ||
136 | * @interface: Interface to probe | ||
137 | * @supported_ports: | ||
138 | * Number of ports Octeon supports. | ||
139 | * | ||
140 | * Returns Number of ports the actual board supports. Many times this will | ||
141 | * simple be "support_ports". | ||
142 | */ | ||
143 | extern int __cvmx_helper_board_interface_probe(int interface, | ||
144 | int supported_ports); | ||
145 | |||
146 | /** | ||
147 | * Enable packet input/output from the hardware. This function is | ||
148 | * called after by cvmx_helper_packet_hardware_enable() to | ||
149 | * perform board specific initialization. For most boards | ||
150 | * nothing is needed. | ||
151 | * | ||
152 | * @interface: Interface to enable | ||
153 | * | ||
154 | * Returns Zero on success, negative on failure | ||
155 | */ | ||
156 | extern int __cvmx_helper_board_hardware_enable(int interface); | ||
157 | |||
158 | /** | ||
159 | * Gets the clock type used for the USB block based on board type. | ||
160 | * Used by the USB code for auto configuration of clock type. | ||
161 | * | ||
162 | * Returns USB clock type enumeration | ||
163 | */ | ||
164 | cvmx_helper_board_usb_clock_types_t | ||
165 | __cvmx_helper_board_usb_get_clock_type(void); | ||
166 | |||
167 | /** | ||
168 | * Adjusts the number of available USB ports on Octeon based on board | ||
169 | * specifics. | ||
170 | * | ||
171 | * @supported_ports: expected number of ports based on chip type; | ||
172 | * | ||
173 | * | ||
174 | * Returns number of available usb ports, based on board specifics. | ||
175 | * Return value is supported_ports if function does not | ||
176 | * override. | ||
177 | */ | ||
178 | int __cvmx_helper_board_usb_get_num_ports(int supported_ports); | ||
179 | |||
180 | #endif /* __CVMX_HELPER_BOARD_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-helper-fpa.c b/drivers/staging/octeon/cvmx-helper-fpa.c new file mode 100644 index 000000000000..c239e5f4ab9a --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-fpa.c | |||
@@ -0,0 +1,243 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * | ||
31 | * Helper functions for FPA setup. | ||
32 | * | ||
33 | */ | ||
34 | #include "executive-config.h" | ||
35 | #include "cvmx-config.h" | ||
36 | #include "cvmx.h" | ||
37 | #include "cvmx-bootmem.h" | ||
38 | #include "cvmx-fpa.h" | ||
39 | #include "cvmx-helper-fpa.h" | ||
40 | |||
41 | /** | ||
42 | * Allocate memory for and initialize a single FPA pool. | ||
43 | * | ||
44 | * @pool: Pool to initialize | ||
45 | * @buffer_size: Size of buffers to allocate in bytes | ||
46 | * @buffers: Number of buffers to put in the pool. Zero is allowed | ||
47 | * @name: String name of the pool for debugging purposes | ||
48 | * Returns Zero on success, non-zero on failure | ||
49 | */ | ||
50 | static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size, | ||
51 | uint64_t buffers, const char *name) | ||
52 | { | ||
53 | uint64_t current_num; | ||
54 | void *memory; | ||
55 | uint64_t align = CVMX_CACHE_LINE_SIZE; | ||
56 | |||
57 | /* | ||
58 | * Align the allocation so that power of 2 size buffers are | ||
59 | * naturally aligned. | ||
60 | */ | ||
61 | while (align < buffer_size) | ||
62 | align = align << 1; | ||
63 | |||
64 | if (buffers == 0) | ||
65 | return 0; | ||
66 | |||
67 | current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool)); | ||
68 | if (current_num) { | ||
69 | cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. " | ||
70 | "Skipping setup.\n", | ||
71 | pool, name, (unsigned long long)current_num); | ||
72 | return 0; | ||
73 | } | ||
74 | |||
75 | memory = cvmx_bootmem_alloc(buffer_size * buffers, align); | ||
76 | if (memory == NULL) { | ||
77 | cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n", | ||
78 | pool, name); | ||
79 | return -1; | ||
80 | } | ||
81 | cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers); | ||
82 | return 0; | ||
83 | } | ||
84 | |||
85 | /** | ||
86 | * Allocate memory and initialize the FPA pools using memory | ||
87 | * from cvmx-bootmem. Specifying zero for the number of | ||
88 | * buffers will cause that FPA pool to not be setup. This is | ||
89 | * useful if you aren't using some of the hardware and want | ||
90 | * to save memory. Use cvmx_helper_initialize_fpa instead of | ||
91 | * this function directly. | ||
92 | * | ||
93 | * @pip_pool: Should always be CVMX_FPA_PACKET_POOL | ||
94 | * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE | ||
95 | * @pip_buffers: | ||
96 | * Number of packet buffers. | ||
97 | * @wqe_pool: Should always be CVMX_FPA_WQE_POOL | ||
98 | * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE | ||
99 | * @wqe_entries: | ||
100 | * Number of work queue entries | ||
101 | * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL | ||
102 | * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE | ||
103 | * @pko_buffers: | ||
104 | * PKO Command buffers. You should at minimum have two per | ||
105 | * each PKO queue. | ||
106 | * @tim_pool: Should always be CVMX_FPA_TIMER_POOL | ||
107 | * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE | ||
108 | * @tim_buffers: | ||
109 | * TIM ring buffer command queues. At least two per timer bucket | ||
110 | * is recommened. | ||
111 | * @dfa_pool: Should always be CVMX_FPA_DFA_POOL | ||
112 | * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE | ||
113 | * @dfa_buffers: | ||
114 | * DFA command buffer. A relatively small (32 for example) | ||
115 | * number should work. | ||
116 | * Returns Zero on success, non-zero if out of memory | ||
117 | */ | ||
118 | static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size, | ||
119 | int pip_buffers, int wqe_pool, | ||
120 | int wqe_size, int wqe_entries, | ||
121 | int pko_pool, int pko_size, | ||
122 | int pko_buffers, int tim_pool, | ||
123 | int tim_size, int tim_buffers, | ||
124 | int dfa_pool, int dfa_size, | ||
125 | int dfa_buffers) | ||
126 | { | ||
127 | int status; | ||
128 | |||
129 | cvmx_fpa_enable(); | ||
130 | |||
131 | if ((pip_buffers > 0) && (pip_buffers <= 64)) | ||
132 | cvmx_dprintf | ||
133 | ("Warning: %d packet buffers may not be enough for hardware" | ||
134 | " prefetch. 65 or more is recommended.\n", pip_buffers); | ||
135 | |||
136 | if (pip_pool >= 0) { | ||
137 | status = | ||
138 | __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size, | ||
139 | pip_buffers, | ||
140 | "Packet Buffers"); | ||
141 | if (status) | ||
142 | return status; | ||
143 | } | ||
144 | |||
145 | if (wqe_pool >= 0) { | ||
146 | status = | ||
147 | __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size, | ||
148 | wqe_entries, | ||
149 | "Work Queue Entries"); | ||
150 | if (status) | ||
151 | return status; | ||
152 | } | ||
153 | |||
154 | if (pko_pool >= 0) { | ||
155 | status = | ||
156 | __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size, | ||
157 | pko_buffers, | ||
158 | "PKO Command Buffers"); | ||
159 | if (status) | ||
160 | return status; | ||
161 | } | ||
162 | |||
163 | if (tim_pool >= 0) { | ||
164 | status = | ||
165 | __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size, | ||
166 | tim_buffers, | ||
167 | "TIM Command Buffers"); | ||
168 | if (status) | ||
169 | return status; | ||
170 | } | ||
171 | |||
172 | if (dfa_pool >= 0) { | ||
173 | status = | ||
174 | __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size, | ||
175 | dfa_buffers, | ||
176 | "DFA Command Buffers"); | ||
177 | if (status) | ||
178 | return status; | ||
179 | } | ||
180 | |||
181 | return 0; | ||
182 | } | ||
183 | |||
184 | /** | ||
185 | * Allocate memory and initialize the FPA pools using memory | ||
186 | * from cvmx-bootmem. Sizes of each element in the pools is | ||
187 | * controlled by the cvmx-config.h header file. Specifying | ||
188 | * zero for any parameter will cause that FPA pool to not be | ||
189 | * setup. This is useful if you aren't using some of the | ||
190 | * hardware and want to save memory. | ||
191 | * | ||
192 | * @packet_buffers: | ||
193 | * Number of packet buffers to allocate | ||
194 | * @work_queue_entries: | ||
195 | * Number of work queue entries | ||
196 | * @pko_buffers: | ||
197 | * PKO Command buffers. You should at minimum have two per | ||
198 | * each PKO queue. | ||
199 | * @tim_buffers: | ||
200 | * TIM ring buffer command queues. At least two per timer bucket | ||
201 | * is recommened. | ||
202 | * @dfa_buffers: | ||
203 | * DFA command buffer. A relatively small (32 for example) | ||
204 | * number should work. | ||
205 | * Returns Zero on success, non-zero if out of memory | ||
206 | */ | ||
207 | int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries, | ||
208 | int pko_buffers, int tim_buffers, | ||
209 | int dfa_buffers) | ||
210 | { | ||
211 | #ifndef CVMX_FPA_PACKET_POOL | ||
212 | #define CVMX_FPA_PACKET_POOL -1 | ||
213 | #define CVMX_FPA_PACKET_POOL_SIZE 0 | ||
214 | #endif | ||
215 | #ifndef CVMX_FPA_WQE_POOL | ||
216 | #define CVMX_FPA_WQE_POOL -1 | ||
217 | #define CVMX_FPA_WQE_POOL_SIZE 0 | ||
218 | #endif | ||
219 | #ifndef CVMX_FPA_OUTPUT_BUFFER_POOL | ||
220 | #define CVMX_FPA_OUTPUT_BUFFER_POOL -1 | ||
221 | #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0 | ||
222 | #endif | ||
223 | #ifndef CVMX_FPA_TIMER_POOL | ||
224 | #define CVMX_FPA_TIMER_POOL -1 | ||
225 | #define CVMX_FPA_TIMER_POOL_SIZE 0 | ||
226 | #endif | ||
227 | #ifndef CVMX_FPA_DFA_POOL | ||
228 | #define CVMX_FPA_DFA_POOL -1 | ||
229 | #define CVMX_FPA_DFA_POOL_SIZE 0 | ||
230 | #endif | ||
231 | return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL, | ||
232 | CVMX_FPA_PACKET_POOL_SIZE, | ||
233 | packet_buffers, CVMX_FPA_WQE_POOL, | ||
234 | CVMX_FPA_WQE_POOL_SIZE, | ||
235 | work_queue_entries, | ||
236 | CVMX_FPA_OUTPUT_BUFFER_POOL, | ||
237 | CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, | ||
238 | pko_buffers, CVMX_FPA_TIMER_POOL, | ||
239 | CVMX_FPA_TIMER_POOL_SIZE, | ||
240 | tim_buffers, CVMX_FPA_DFA_POOL, | ||
241 | CVMX_FPA_DFA_POOL_SIZE, | ||
242 | dfa_buffers); | ||
243 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper-fpa.h b/drivers/staging/octeon/cvmx-helper-fpa.h new file mode 100644 index 000000000000..5ff8c93198de --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-fpa.h | |||
@@ -0,0 +1,64 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * | ||
31 | * Helper functions for FPA setup. | ||
32 | * | ||
33 | */ | ||
34 | #ifndef __CVMX_HELPER_H_FPA__ | ||
35 | #define __CVMX_HELPER_H_FPA__ | ||
36 | |||
37 | /** | ||
38 | * Allocate memory and initialize the FPA pools using memory | ||
39 | * from cvmx-bootmem. Sizes of each element in the pools is | ||
40 | * controlled by the cvmx-config.h header file. Specifying | ||
41 | * zero for any parameter will cause that FPA pool to not be | ||
42 | * setup. This is useful if you aren't using some of the | ||
43 | * hardware and want to save memory. | ||
44 | * | ||
45 | * @packet_buffers: | ||
46 | * Number of packet buffers to allocate | ||
47 | * @work_queue_entries: | ||
48 | * Number of work queue entries | ||
49 | * @pko_buffers: | ||
50 | * PKO Command buffers. You should at minimum have two per | ||
51 | * each PKO queue. | ||
52 | * @tim_buffers: | ||
53 | * TIM ring buffer command queues. At least two per timer bucket | ||
54 | * is recommened. | ||
55 | * @dfa_buffers: | ||
56 | * DFA command buffer. A relatively small (32 for example) | ||
57 | * number should work. | ||
58 | * Returns Zero on success, non-zero if out of memory | ||
59 | */ | ||
60 | extern int cvmx_helper_initialize_fpa(int packet_buffers, | ||
61 | int work_queue_entries, int pko_buffers, | ||
62 | int tim_buffers, int dfa_buffers); | ||
63 | |||
64 | #endif /* __CVMX_HELPER_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/drivers/staging/octeon/cvmx-helper-loop.c new file mode 100644 index 000000000000..55a571a69529 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-loop.c | |||
@@ -0,0 +1,85 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Functions for LOOP initialization, configuration, | ||
30 | * and monitoring. | ||
31 | */ | ||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "cvmx-config.h" | ||
35 | |||
36 | #include "cvmx-helper.h" | ||
37 | #include "cvmx-pip-defs.h" | ||
38 | |||
39 | /** | ||
40 | * Probe a LOOP interface and determine the number of ports | ||
41 | * connected to it. The LOOP interface should still be down | ||
42 | * after this call. | ||
43 | * | ||
44 | * @interface: Interface to probe | ||
45 | * | ||
46 | * Returns Number of ports on the interface. Zero to disable. | ||
47 | */ | ||
48 | int __cvmx_helper_loop_probe(int interface) | ||
49 | { | ||
50 | union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs; | ||
51 | int num_ports = 4; | ||
52 | int port; | ||
53 | |||
54 | /* We need to disable length checking so packet < 64 bytes and jumbo | ||
55 | frames don't get errors */ | ||
56 | for (port = 0; port < num_ports; port++) { | ||
57 | union cvmx_pip_prt_cfgx port_cfg; | ||
58 | int ipd_port = cvmx_helper_get_ipd_port(interface, port); | ||
59 | port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); | ||
60 | port_cfg.s.maxerr_en = 0; | ||
61 | port_cfg.s.minerr_en = 0; | ||
62 | cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); | ||
63 | } | ||
64 | |||
65 | /* Disable FCS stripping for loopback ports */ | ||
66 | ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); | ||
67 | ipd_sub_port_fcs.s.port_bit2 = 0; | ||
68 | cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); | ||
69 | return num_ports; | ||
70 | } | ||
71 | |||
72 | /** | ||
73 | * Bringup and enable a LOOP interface. After this call packet | ||
74 | * I/O should be fully functional. This is called with IPD | ||
75 | * enabled but PKO disabled. | ||
76 | * | ||
77 | * @interface: Interface to bring up | ||
78 | * | ||
79 | * Returns Zero on success, negative on failure | ||
80 | */ | ||
81 | int __cvmx_helper_loop_enable(int interface) | ||
82 | { | ||
83 | /* Do nothing. */ | ||
84 | return 0; | ||
85 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/drivers/staging/octeon/cvmx-helper-loop.h new file mode 100644 index 000000000000..e646a6ccce75 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-loop.h | |||
@@ -0,0 +1,59 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as published by | ||
11 | * the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, | ||
14 | * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. | ||
16 | * See the GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this file; if not, write to the Free Software | ||
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
21 | * or visit http://www.gnu.org/licenses/. | ||
22 | * | ||
23 | * This file may also be available under a different license from Cavium. | ||
24 | * Contact Cavium Networks for more information | ||
25 | ***********************license end**************************************/ | ||
26 | |||
27 | /** | ||
28 | * @file | ||
29 | * | ||
30 | * Functions for LOOP initialization, configuration, | ||
31 | * and monitoring. | ||
32 | * | ||
33 | */ | ||
34 | #ifndef __CVMX_HELPER_LOOP_H__ | ||
35 | #define __CVMX_HELPER_LOOP_H__ | ||
36 | |||
37 | /** | ||
38 | * Probe a LOOP interface and determine the number of ports | ||
39 | * connected to it. The LOOP interface should still be down after | ||
40 | * this call. | ||
41 | * | ||
42 | * @interface: Interface to probe | ||
43 | * | ||
44 | * Returns Number of ports on the interface. Zero to disable. | ||
45 | */ | ||
46 | extern int __cvmx_helper_loop_probe(int interface); | ||
47 | |||
48 | /** | ||
49 | * Bringup and enable a LOOP interface. After this call packet | ||
50 | * I/O should be fully functional. This is called with IPD | ||
51 | * enabled but PKO disabled. | ||
52 | * | ||
53 | * @interface: Interface to bring up | ||
54 | * | ||
55 | * Returns Zero on success, negative on failure | ||
56 | */ | ||
57 | extern int __cvmx_helper_loop_enable(int interface); | ||
58 | |||
59 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/drivers/staging/octeon/cvmx-helper-npi.c new file mode 100644 index 000000000000..7388a1e72b38 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-npi.c | |||
@@ -0,0 +1,113 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Functions for NPI initialization, configuration, | ||
30 | * and monitoring. | ||
31 | */ | ||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "cvmx-config.h" | ||
35 | |||
36 | #include "cvmx-helper.h" | ||
37 | |||
38 | #include "cvmx-pip-defs.h" | ||
39 | |||
40 | /** | ||
41 | * Probe a NPI interface and determine the number of ports | ||
42 | * connected to it. The NPI interface should still be down | ||
43 | * after this call. | ||
44 | * | ||
45 | * @interface: Interface to probe | ||
46 | * | ||
47 | * Returns Number of ports on the interface. Zero to disable. | ||
48 | */ | ||
49 | int __cvmx_helper_npi_probe(int interface) | ||
50 | { | ||
51 | #if CVMX_PKO_QUEUES_PER_PORT_PCI > 0 | ||
52 | if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) | ||
53 | return 4; | ||
54 | else if (OCTEON_IS_MODEL(OCTEON_CN56XX) | ||
55 | && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) | ||
56 | /* The packet engines didn't exist before pass 2 */ | ||
57 | return 4; | ||
58 | else if (OCTEON_IS_MODEL(OCTEON_CN52XX) | ||
59 | && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) | ||
60 | /* The packet engines didn't exist before pass 2 */ | ||
61 | return 4; | ||
62 | #if 0 | ||
63 | /* | ||
64 | * Technically CN30XX, CN31XX, and CN50XX contain packet | ||
65 | * engines, but nobody ever uses them. Since this is the case, | ||
66 | * we disable them here. | ||
67 | */ | ||
68 | else if (OCTEON_IS_MODEL(OCTEON_CN31XX) | ||
69 | || OCTEON_IS_MODEL(OCTEON_CN50XX)) | ||
70 | return 2; | ||
71 | else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) | ||
72 | return 1; | ||
73 | #endif | ||
74 | #endif | ||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | /** | ||
79 | * Bringup and enable a NPI interface. After this call packet | ||
80 | * I/O should be fully functional. This is called with IPD | ||
81 | * enabled but PKO disabled. | ||
82 | * | ||
83 | * @interface: Interface to bring up | ||
84 | * | ||
85 | * Returns Zero on success, negative on failure | ||
86 | */ | ||
87 | int __cvmx_helper_npi_enable(int interface) | ||
88 | { | ||
89 | /* | ||
90 | * On CN50XX, CN52XX, and CN56XX we need to disable length | ||
91 | * checking so packet < 64 bytes and jumbo frames don't get | ||
92 | * errors. | ||
93 | */ | ||
94 | if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && | ||
95 | !OCTEON_IS_MODEL(OCTEON_CN58XX)) { | ||
96 | int num_ports = cvmx_helper_ports_on_interface(interface); | ||
97 | int port; | ||
98 | for (port = 0; port < num_ports; port++) { | ||
99 | union cvmx_pip_prt_cfgx port_cfg; | ||
100 | int ipd_port = | ||
101 | cvmx_helper_get_ipd_port(interface, port); | ||
102 | port_cfg.u64 = | ||
103 | cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); | ||
104 | port_cfg.s.maxerr_en = 0; | ||
105 | port_cfg.s.minerr_en = 0; | ||
106 | cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), | ||
107 | port_cfg.u64); | ||
108 | } | ||
109 | } | ||
110 | |||
111 | /* Enables are controlled by the remote host, so nothing to do here */ | ||
112 | return 0; | ||
113 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/drivers/staging/octeon/cvmx-helper-npi.h new file mode 100644 index 000000000000..908e7b08c214 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-npi.h | |||
@@ -0,0 +1,60 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * | ||
31 | * Functions for NPI initialization, configuration, | ||
32 | * and monitoring. | ||
33 | * | ||
34 | */ | ||
35 | #ifndef __CVMX_HELPER_NPI_H__ | ||
36 | #define __CVMX_HELPER_NPI_H__ | ||
37 | |||
38 | /** | ||
39 | * Probe a NPI interface and determine the number of ports | ||
40 | * connected to it. The NPI interface should still be down after | ||
41 | * this call. | ||
42 | * | ||
43 | * @interface: Interface to probe | ||
44 | * | ||
45 | * Returns Number of ports on the interface. Zero to disable. | ||
46 | */ | ||
47 | extern int __cvmx_helper_npi_probe(int interface); | ||
48 | |||
49 | /** | ||
50 | * Bringup and enable a NPI interface. After this call packet | ||
51 | * I/O should be fully functional. This is called with IPD | ||
52 | * enabled but PKO disabled. | ||
53 | * | ||
54 | * @interface: Interface to bring up | ||
55 | * | ||
56 | * Returns Zero on success, negative on failure | ||
57 | */ | ||
58 | extern int __cvmx_helper_npi_enable(int interface); | ||
59 | |||
60 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.c b/drivers/staging/octeon/cvmx-helper-rgmii.c new file mode 100644 index 000000000000..aa2d5d7fee2b --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-rgmii.c | |||
@@ -0,0 +1,525 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Functions for RGMII/GMII/MII initialization, configuration, | ||
30 | * and monitoring. | ||
31 | */ | ||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "cvmx-config.h" | ||
35 | |||
36 | |||
37 | #include "cvmx-mdio.h" | ||
38 | #include "cvmx-pko.h" | ||
39 | #include "cvmx-helper.h" | ||
40 | #include "cvmx-helper-board.h" | ||
41 | |||
42 | #include <asm/octeon/cvmx-npi-defs.h> | ||
43 | #include "cvmx-gmxx-defs.h" | ||
44 | #include "cvmx-asxx-defs.h" | ||
45 | #include "cvmx-dbg-defs.h" | ||
46 | |||
47 | void __cvmx_interrupt_gmxx_enable(int interface); | ||
48 | void __cvmx_interrupt_asxx_enable(int block); | ||
49 | |||
50 | /** | ||
51 | * Probe RGMII ports and determine the number present | ||
52 | * | ||
53 | * @interface: Interface to probe | ||
54 | * | ||
55 | * Returns Number of RGMII/GMII/MII ports (0-4). | ||
56 | */ | ||
57 | int __cvmx_helper_rgmii_probe(int interface) | ||
58 | { | ||
59 | int num_ports = 0; | ||
60 | union cvmx_gmxx_inf_mode mode; | ||
61 | mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); | ||
62 | |||
63 | if (mode.s.type) { | ||
64 | if (OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
65 | || OCTEON_IS_MODEL(OCTEON_CN58XX)) { | ||
66 | cvmx_dprintf("ERROR: RGMII initialize called in " | ||
67 | "SPI interface\n"); | ||
68 | } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) | ||
69 | || OCTEON_IS_MODEL(OCTEON_CN30XX) | ||
70 | || OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
71 | /* | ||
72 | * On these chips "type" says we're in | ||
73 | * GMII/MII mode. This limits us to 2 ports | ||
74 | */ | ||
75 | num_ports = 2; | ||
76 | } else { | ||
77 | cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", | ||
78 | __func__); | ||
79 | } | ||
80 | } else { | ||
81 | if (OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
82 | || OCTEON_IS_MODEL(OCTEON_CN58XX)) { | ||
83 | num_ports = 4; | ||
84 | } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) | ||
85 | || OCTEON_IS_MODEL(OCTEON_CN30XX) | ||
86 | || OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
87 | num_ports = 3; | ||
88 | } else { | ||
89 | cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", | ||
90 | __func__); | ||
91 | } | ||
92 | } | ||
93 | return num_ports; | ||
94 | } | ||
95 | |||
96 | /** | ||
97 | * Put an RGMII interface in loopback mode. Internal packets sent | ||
98 | * out will be received back again on the same port. Externally | ||
99 | * received packets will echo back out. | ||
100 | * | ||
101 | * @port: IPD port number to loop. | ||
102 | */ | ||
103 | void cvmx_helper_rgmii_internal_loopback(int port) | ||
104 | { | ||
105 | int interface = (port >> 4) & 1; | ||
106 | int index = port & 0xf; | ||
107 | uint64_t tmp; | ||
108 | |||
109 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
110 | gmx_cfg.u64 = 0; | ||
111 | gmx_cfg.s.duplex = 1; | ||
112 | gmx_cfg.s.slottime = 1; | ||
113 | gmx_cfg.s.speed = 1; | ||
114 | cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); | ||
115 | cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); | ||
116 | cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); | ||
117 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
118 | tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); | ||
119 | cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); | ||
120 | tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); | ||
121 | cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); | ||
122 | tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); | ||
123 | cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); | ||
124 | gmx_cfg.s.en = 1; | ||
125 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
126 | } | ||
127 | |||
128 | /** | ||
129 | * Workaround ASX setup errata with CN38XX pass1 | ||
130 | * | ||
131 | * @interface: Interface to setup | ||
132 | * @port: Port to setup (0..3) | ||
133 | * @cpu_clock_hz: | ||
134 | * Chip frequency in Hertz | ||
135 | * | ||
136 | * Returns Zero on success, negative on failure | ||
137 | */ | ||
138 | static int __cvmx_helper_errata_asx_pass1(int interface, int port, | ||
139 | int cpu_clock_hz) | ||
140 | { | ||
141 | /* Set hi water mark as per errata GMX-4 */ | ||
142 | if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000) | ||
143 | cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12); | ||
144 | else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000) | ||
145 | cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11); | ||
146 | else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000) | ||
147 | cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10); | ||
148 | else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000) | ||
149 | cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9); | ||
150 | else | ||
151 | cvmx_dprintf("Illegal clock frequency (%d). " | ||
152 | "CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz); | ||
153 | return 0; | ||
154 | } | ||
155 | |||
156 | /** | ||
157 | * Configure all of the ASX, GMX, and PKO regsiters required | ||
158 | * to get RGMII to function on the supplied interface. | ||
159 | * | ||
160 | * @interface: PKO Interface to configure (0 or 1) | ||
161 | * | ||
162 | * Returns Zero on success | ||
163 | */ | ||
164 | int __cvmx_helper_rgmii_enable(int interface) | ||
165 | { | ||
166 | int num_ports = cvmx_helper_ports_on_interface(interface); | ||
167 | int port; | ||
168 | struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get(); | ||
169 | union cvmx_gmxx_inf_mode mode; | ||
170 | union cvmx_asxx_tx_prt_en asx_tx; | ||
171 | union cvmx_asxx_rx_prt_en asx_rx; | ||
172 | |||
173 | mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); | ||
174 | |||
175 | if (mode.s.en == 0) | ||
176 | return -1; | ||
177 | if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || | ||
178 | OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1) | ||
179 | /* Ignore SPI interfaces */ | ||
180 | return -1; | ||
181 | |||
182 | /* Configure the ASX registers needed to use the RGMII ports */ | ||
183 | asx_tx.u64 = 0; | ||
184 | asx_tx.s.prt_en = cvmx_build_mask(num_ports); | ||
185 | cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64); | ||
186 | |||
187 | asx_rx.u64 = 0; | ||
188 | asx_rx.s.prt_en = cvmx_build_mask(num_ports); | ||
189 | cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64); | ||
190 | |||
191 | /* Configure the GMX registers needed to use the RGMII ports */ | ||
192 | for (port = 0; port < num_ports; port++) { | ||
193 | /* Setting of CVMX_GMXX_TXX_THRESH has been moved to | ||
194 | __cvmx_helper_setup_gmx() */ | ||
195 | |||
196 | if (cvmx_octeon_is_pass1()) | ||
197 | __cvmx_helper_errata_asx_pass1(interface, port, | ||
198 | sys_info_ptr-> | ||
199 | cpu_clock_hz); | ||
200 | else { | ||
201 | /* | ||
202 | * Configure more flexible RGMII preamble | ||
203 | * checking. Pass 1 doesn't support this | ||
204 | * feature. | ||
205 | */ | ||
206 | union cvmx_gmxx_rxx_frm_ctl frm_ctl; | ||
207 | frm_ctl.u64 = | ||
208 | cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL | ||
209 | (port, interface)); | ||
210 | /* New field, so must be compile time */ | ||
211 | frm_ctl.s.pre_free = 1; | ||
212 | cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), | ||
213 | frm_ctl.u64); | ||
214 | } | ||
215 | |||
216 | /* | ||
217 | * Each pause frame transmitted will ask for about 10M | ||
218 | * bit times before resume. If buffer space comes | ||
219 | * available before that time has expired, an XON | ||
220 | * pause frame (0 time) will be transmitted to restart | ||
221 | * the flow. | ||
222 | */ | ||
223 | cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), | ||
224 | 20000); | ||
225 | cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL | ||
226 | (port, interface), 19000); | ||
227 | |||
228 | if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
229 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), | ||
230 | 16); | ||
231 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), | ||
232 | 16); | ||
233 | } else { | ||
234 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), | ||
235 | 24); | ||
236 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), | ||
237 | 24); | ||
238 | } | ||
239 | } | ||
240 | |||
241 | __cvmx_helper_setup_gmx(interface, num_ports); | ||
242 | |||
243 | /* enable the ports now */ | ||
244 | for (port = 0; port < num_ports; port++) { | ||
245 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
246 | cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port | ||
247 | (interface, port)); | ||
248 | gmx_cfg.u64 = | ||
249 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface)); | ||
250 | gmx_cfg.s.en = 1; | ||
251 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), | ||
252 | gmx_cfg.u64); | ||
253 | } | ||
254 | __cvmx_interrupt_asxx_enable(interface); | ||
255 | __cvmx_interrupt_gmxx_enable(interface); | ||
256 | |||
257 | return 0; | ||
258 | } | ||
259 | |||
260 | /** | ||
261 | * Return the link state of an IPD/PKO port as returned by | ||
262 | * auto negotiation. The result of this function may not match | ||
263 | * Octeon's link config if auto negotiation has changed since | ||
264 | * the last call to cvmx_helper_link_set(). | ||
265 | * | ||
266 | * @ipd_port: IPD/PKO port to query | ||
267 | * | ||
268 | * Returns Link state | ||
269 | */ | ||
270 | cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port) | ||
271 | { | ||
272 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
273 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
274 | union cvmx_asxx_prt_loop asxx_prt_loop; | ||
275 | |||
276 | asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); | ||
277 | if (asxx_prt_loop.s.int_loop & (1 << index)) { | ||
278 | /* Force 1Gbps full duplex on internal loopback */ | ||
279 | cvmx_helper_link_info_t result; | ||
280 | result.u64 = 0; | ||
281 | result.s.full_duplex = 1; | ||
282 | result.s.link_up = 1; | ||
283 | result.s.speed = 1000; | ||
284 | return result; | ||
285 | } else | ||
286 | return __cvmx_helper_board_link_get(ipd_port); | ||
287 | } | ||
288 | |||
289 | /** | ||
290 | * Configure an IPD/PKO port for the specified link state. This | ||
291 | * function does not influence auto negotiation at the PHY level. | ||
292 | * The passed link state must always match the link state returned | ||
293 | * by cvmx_helper_link_get(). It is normally best to use | ||
294 | * cvmx_helper_link_autoconf() instead. | ||
295 | * | ||
296 | * @ipd_port: IPD/PKO port to configure | ||
297 | * @link_info: The new link state | ||
298 | * | ||
299 | * Returns Zero on success, negative on failure | ||
300 | */ | ||
301 | int __cvmx_helper_rgmii_link_set(int ipd_port, | ||
302 | cvmx_helper_link_info_t link_info) | ||
303 | { | ||
304 | int result = 0; | ||
305 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
306 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
307 | union cvmx_gmxx_prtx_cfg original_gmx_cfg; | ||
308 | union cvmx_gmxx_prtx_cfg new_gmx_cfg; | ||
309 | union cvmx_pko_mem_queue_qos pko_mem_queue_qos; | ||
310 | union cvmx_pko_mem_queue_qos pko_mem_queue_qos_save[16]; | ||
311 | union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp; | ||
312 | union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp_save; | ||
313 | int i; | ||
314 | |||
315 | /* Ignore speed sets in the simulator */ | ||
316 | if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) | ||
317 | return 0; | ||
318 | |||
319 | /* Read the current settings so we know the current enable state */ | ||
320 | original_gmx_cfg.u64 = | ||
321 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
322 | new_gmx_cfg = original_gmx_cfg; | ||
323 | |||
324 | /* Disable the lowest level RX */ | ||
325 | cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), | ||
326 | cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & | ||
327 | ~(1 << index)); | ||
328 | |||
329 | /* Disable all queues so that TX should become idle */ | ||
330 | for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { | ||
331 | int queue = cvmx_pko_get_base_queue(ipd_port) + i; | ||
332 | cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); | ||
333 | pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS); | ||
334 | pko_mem_queue_qos.s.pid = ipd_port; | ||
335 | pko_mem_queue_qos.s.qid = queue; | ||
336 | pko_mem_queue_qos_save[i] = pko_mem_queue_qos; | ||
337 | pko_mem_queue_qos.s.qos_mask = 0; | ||
338 | cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64); | ||
339 | } | ||
340 | |||
341 | /* Disable backpressure */ | ||
342 | gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); | ||
343 | gmx_tx_ovr_bp_save = gmx_tx_ovr_bp; | ||
344 | gmx_tx_ovr_bp.s.bp &= ~(1 << index); | ||
345 | gmx_tx_ovr_bp.s.en |= 1 << index; | ||
346 | cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); | ||
347 | cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); | ||
348 | |||
349 | /* | ||
350 | * Poll the GMX state machine waiting for it to become | ||
351 | * idle. Preferably we should only change speed when it is | ||
352 | * idle. If it doesn't become idle we will still do the speed | ||
353 | * change, but there is a slight chance that GMX will | ||
354 | * lockup. | ||
355 | */ | ||
356 | cvmx_write_csr(CVMX_NPI_DBG_SELECT, | ||
357 | interface * 0x800 + index * 0x100 + 0x880); | ||
358 | CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7, | ||
359 | ==, 0, 10000); | ||
360 | CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf, | ||
361 | ==, 0, 10000); | ||
362 | |||
363 | /* Disable the port before we make any changes */ | ||
364 | new_gmx_cfg.s.en = 0; | ||
365 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); | ||
366 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
367 | |||
368 | /* Set full/half duplex */ | ||
369 | if (cvmx_octeon_is_pass1()) | ||
370 | /* Half duplex is broken for 38XX Pass 1 */ | ||
371 | new_gmx_cfg.s.duplex = 1; | ||
372 | else if (!link_info.s.link_up) | ||
373 | /* Force full duplex on down links */ | ||
374 | new_gmx_cfg.s.duplex = 1; | ||
375 | else | ||
376 | new_gmx_cfg.s.duplex = link_info.s.full_duplex; | ||
377 | |||
378 | /* Set the link speed. Anything unknown is set to 1Gbps */ | ||
379 | if (link_info.s.speed == 10) { | ||
380 | new_gmx_cfg.s.slottime = 0; | ||
381 | new_gmx_cfg.s.speed = 0; | ||
382 | } else if (link_info.s.speed == 100) { | ||
383 | new_gmx_cfg.s.slottime = 0; | ||
384 | new_gmx_cfg.s.speed = 0; | ||
385 | } else { | ||
386 | new_gmx_cfg.s.slottime = 1; | ||
387 | new_gmx_cfg.s.speed = 1; | ||
388 | } | ||
389 | |||
390 | /* Adjust the clocks */ | ||
391 | if (link_info.s.speed == 10) { | ||
392 | cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50); | ||
393 | cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); | ||
394 | cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); | ||
395 | } else if (link_info.s.speed == 100) { | ||
396 | cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5); | ||
397 | cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); | ||
398 | cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); | ||
399 | } else { | ||
400 | cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); | ||
401 | cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); | ||
402 | cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); | ||
403 | } | ||
404 | |||
405 | if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
406 | if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) { | ||
407 | union cvmx_gmxx_inf_mode mode; | ||
408 | mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); | ||
409 | |||
410 | /* | ||
411 | * Port .en .type .p0mii Configuration | ||
412 | * ---- --- ----- ------ ----------------------------------------- | ||
413 | * X 0 X X All links are disabled. | ||
414 | * 0 1 X 0 Port 0 is RGMII | ||
415 | * 0 1 X 1 Port 0 is MII | ||
416 | * 1 1 0 X Ports 1 and 2 are configured as RGMII ports. | ||
417 | * 1 1 1 X Port 1: GMII/MII; Port 2: disabled. GMII or | ||
418 | * MII port is selected by GMX_PRT1_CFG[SPEED]. | ||
419 | */ | ||
420 | |||
421 | /* In MII mode, CLK_CNT = 1. */ | ||
422 | if (((index == 0) && (mode.s.p0mii == 1)) | ||
423 | || ((index != 0) && (mode.s.type == 1))) { | ||
424 | cvmx_write_csr(CVMX_GMXX_TXX_CLK | ||
425 | (index, interface), 1); | ||
426 | } | ||
427 | } | ||
428 | } | ||
429 | |||
430 | /* Do a read to make sure all setup stuff is complete */ | ||
431 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
432 | |||
433 | /* Save the new GMX setting without enabling the port */ | ||
434 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); | ||
435 | |||
436 | /* Enable the lowest level RX */ | ||
437 | cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), | ||
438 | cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 << | ||
439 | index)); | ||
440 | |||
441 | /* Re-enable the TX path */ | ||
442 | for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { | ||
443 | int queue = cvmx_pko_get_base_queue(ipd_port) + i; | ||
444 | cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); | ||
445 | cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, | ||
446 | pko_mem_queue_qos_save[i].u64); | ||
447 | } | ||
448 | |||
449 | /* Restore backpressure */ | ||
450 | cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64); | ||
451 | |||
452 | /* Restore the GMX enable state. Port config is complete */ | ||
453 | new_gmx_cfg.s.en = original_gmx_cfg.s.en; | ||
454 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); | ||
455 | |||
456 | return result; | ||
457 | } | ||
458 | |||
459 | /** | ||
460 | * Configure a port for internal and/or external loopback. Internal loopback | ||
461 | * causes packets sent by the port to be received by Octeon. External loopback | ||
462 | * causes packets received from the wire to sent out again. | ||
463 | * | ||
464 | * @ipd_port: IPD/PKO port to loopback. | ||
465 | * @enable_internal: | ||
466 | * Non zero if you want internal loopback | ||
467 | * @enable_external: | ||
468 | * Non zero if you want external loopback | ||
469 | * | ||
470 | * Returns Zero on success, negative on failure. | ||
471 | */ | ||
472 | int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal, | ||
473 | int enable_external) | ||
474 | { | ||
475 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
476 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
477 | int original_enable; | ||
478 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
479 | union cvmx_asxx_prt_loop asxx_prt_loop; | ||
480 | |||
481 | /* Read the current enable state and save it */ | ||
482 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
483 | original_enable = gmx_cfg.s.en; | ||
484 | /* Force port to be disabled */ | ||
485 | gmx_cfg.s.en = 0; | ||
486 | if (enable_internal) { | ||
487 | /* Force speed if we're doing internal loopback */ | ||
488 | gmx_cfg.s.duplex = 1; | ||
489 | gmx_cfg.s.slottime = 1; | ||
490 | gmx_cfg.s.speed = 1; | ||
491 | cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); | ||
492 | cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); | ||
493 | cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); | ||
494 | } | ||
495 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
496 | |||
497 | /* Set the loopback bits */ | ||
498 | asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); | ||
499 | if (enable_internal) | ||
500 | asxx_prt_loop.s.int_loop |= 1 << index; | ||
501 | else | ||
502 | asxx_prt_loop.s.int_loop &= ~(1 << index); | ||
503 | if (enable_external) | ||
504 | asxx_prt_loop.s.ext_loop |= 1 << index; | ||
505 | else | ||
506 | asxx_prt_loop.s.ext_loop &= ~(1 << index); | ||
507 | cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64); | ||
508 | |||
509 | /* Force enables in internal loopback */ | ||
510 | if (enable_internal) { | ||
511 | uint64_t tmp; | ||
512 | tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); | ||
513 | cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), | ||
514 | (1 << index) | tmp); | ||
515 | tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); | ||
516 | cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), | ||
517 | (1 << index) | tmp); | ||
518 | original_enable = 1; | ||
519 | } | ||
520 | |||
521 | /* Restore the enable state */ | ||
522 | gmx_cfg.s.en = original_enable; | ||
523 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
524 | return 0; | ||
525 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/drivers/staging/octeon/cvmx-helper-rgmii.h new file mode 100644 index 000000000000..ea2652604a57 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-rgmii.h | |||
@@ -0,0 +1,110 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * | ||
31 | * Functions for RGMII/GMII/MII initialization, configuration, | ||
32 | * and monitoring. | ||
33 | * | ||
34 | */ | ||
35 | #ifndef __CVMX_HELPER_RGMII_H__ | ||
36 | #define __CVMX_HELPER_RGMII_H__ | ||
37 | |||
38 | /** | ||
39 | * Probe RGMII ports and determine the number present | ||
40 | * | ||
41 | * @interface: Interface to probe | ||
42 | * | ||
43 | * Returns Number of RGMII/GMII/MII ports (0-4). | ||
44 | */ | ||
45 | extern int __cvmx_helper_rgmii_probe(int interface); | ||
46 | |||
47 | /** | ||
48 | * Put an RGMII interface in loopback mode. Internal packets sent | ||
49 | * out will be received back again on the same port. Externally | ||
50 | * received packets will echo back out. | ||
51 | * | ||
52 | * @port: IPD port number to loop. | ||
53 | */ | ||
54 | extern void cvmx_helper_rgmii_internal_loopback(int port); | ||
55 | |||
56 | /** | ||
57 | * Configure all of the ASX, GMX, and PKO regsiters required | ||
58 | * to get RGMII to function on the supplied interface. | ||
59 | * | ||
60 | * @interface: PKO Interface to configure (0 or 1) | ||
61 | * | ||
62 | * Returns Zero on success | ||
63 | */ | ||
64 | extern int __cvmx_helper_rgmii_enable(int interface); | ||
65 | |||
66 | /** | ||
67 | * Return the link state of an IPD/PKO port as returned by | ||
68 | * auto negotiation. The result of this function may not match | ||
69 | * Octeon's link config if auto negotiation has changed since | ||
70 | * the last call to cvmx_helper_link_set(). | ||
71 | * | ||
72 | * @ipd_port: IPD/PKO port to query | ||
73 | * | ||
74 | * Returns Link state | ||
75 | */ | ||
76 | extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port); | ||
77 | |||
78 | /** | ||
79 | * Configure an IPD/PKO port for the specified link state. This | ||
80 | * function does not influence auto negotiation at the PHY level. | ||
81 | * The passed link state must always match the link state returned | ||
82 | * by cvmx_helper_link_get(). It is normally best to use | ||
83 | * cvmx_helper_link_autoconf() instead. | ||
84 | * | ||
85 | * @ipd_port: IPD/PKO port to configure | ||
86 | * @link_info: The new link state | ||
87 | * | ||
88 | * Returns Zero on success, negative on failure | ||
89 | */ | ||
90 | extern int __cvmx_helper_rgmii_link_set(int ipd_port, | ||
91 | cvmx_helper_link_info_t link_info); | ||
92 | |||
93 | /** | ||
94 | * Configure a port for internal and/or external loopback. Internal loopback | ||
95 | * causes packets sent by the port to be received by Octeon. External loopback | ||
96 | * causes packets received from the wire to sent out again. | ||
97 | * | ||
98 | * @ipd_port: IPD/PKO port to loopback. | ||
99 | * @enable_internal: | ||
100 | * Non zero if you want internal loopback | ||
101 | * @enable_external: | ||
102 | * Non zero if you want external loopback | ||
103 | * | ||
104 | * Returns Zero on success, negative on failure. | ||
105 | */ | ||
106 | extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port, | ||
107 | int enable_internal, | ||
108 | int enable_external); | ||
109 | |||
110 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.c b/drivers/staging/octeon/cvmx-helper-sgmii.c new file mode 100644 index 000000000000..6214e3b6d975 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-sgmii.c | |||
@@ -0,0 +1,550 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Functions for SGMII initialization, configuration, | ||
30 | * and monitoring. | ||
31 | */ | ||
32 | |||
33 | #include <asm/octeon/octeon.h> | ||
34 | |||
35 | #include "cvmx-config.h" | ||
36 | |||
37 | #include "cvmx-mdio.h" | ||
38 | #include "cvmx-helper.h" | ||
39 | #include "cvmx-helper-board.h" | ||
40 | |||
41 | #include "cvmx-gmxx-defs.h" | ||
42 | #include "cvmx-pcsx-defs.h" | ||
43 | |||
44 | void __cvmx_interrupt_gmxx_enable(int interface); | ||
45 | void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); | ||
46 | void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); | ||
47 | |||
48 | /** | ||
49 | * Perform initialization required only once for an SGMII port. | ||
50 | * | ||
51 | * @interface: Interface to init | ||
52 | * @index: Index of prot on the interface | ||
53 | * | ||
54 | * Returns Zero on success, negative on failure | ||
55 | */ | ||
56 | static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) | ||
57 | { | ||
58 | const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; | ||
59 | union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg; | ||
60 | union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg; | ||
61 | union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; | ||
62 | |||
63 | /* Disable GMX */ | ||
64 | gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
65 | gmxx_prtx_cfg.s.en = 0; | ||
66 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); | ||
67 | |||
68 | /* | ||
69 | * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the | ||
70 | * appropriate value. 1000BASE-X specifies a 10ms | ||
71 | * interval. SGMII specifies a 1.6ms interval. | ||
72 | */ | ||
73 | pcs_misc_ctl_reg.u64 = | ||
74 | cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); | ||
75 | pcsx_linkx_timer_count_reg.u64 = | ||
76 | cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); | ||
77 | if (pcs_misc_ctl_reg.s.mode) { | ||
78 | /* 1000BASE-X */ | ||
79 | pcsx_linkx_timer_count_reg.s.count = | ||
80 | (10000ull * clock_mhz) >> 10; | ||
81 | } else { | ||
82 | /* SGMII */ | ||
83 | pcsx_linkx_timer_count_reg.s.count = | ||
84 | (1600ull * clock_mhz) >> 10; | ||
85 | } | ||
86 | cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), | ||
87 | pcsx_linkx_timer_count_reg.u64); | ||
88 | |||
89 | /* | ||
90 | * Write the advertisement register to be used as the | ||
91 | * tx_Config_Reg<D15:D0> of the autonegotiation. In | ||
92 | * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG. | ||
93 | * In SGMII PHY mode, tx_Config_Reg<D15:D0> is | ||
94 | * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, | ||
95 | * tx_Config_Reg<D15:D0> is the fixed value 0x4001, so this | ||
96 | * step can be skipped. | ||
97 | */ | ||
98 | if (pcs_misc_ctl_reg.s.mode) { | ||
99 | /* 1000BASE-X */ | ||
100 | union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg; | ||
101 | pcsx_anx_adv_reg.u64 = | ||
102 | cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); | ||
103 | pcsx_anx_adv_reg.s.rem_flt = 0; | ||
104 | pcsx_anx_adv_reg.s.pause = 3; | ||
105 | pcsx_anx_adv_reg.s.hfd = 1; | ||
106 | pcsx_anx_adv_reg.s.fd = 1; | ||
107 | cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), | ||
108 | pcsx_anx_adv_reg.u64); | ||
109 | } else { | ||
110 | union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; | ||
111 | pcsx_miscx_ctl_reg.u64 = | ||
112 | cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); | ||
113 | if (pcsx_miscx_ctl_reg.s.mac_phy) { | ||
114 | /* PHY Mode */ | ||
115 | union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg; | ||
116 | pcsx_sgmx_an_adv_reg.u64 = | ||
117 | cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG | ||
118 | (index, interface)); | ||
119 | pcsx_sgmx_an_adv_reg.s.link = 1; | ||
120 | pcsx_sgmx_an_adv_reg.s.dup = 1; | ||
121 | pcsx_sgmx_an_adv_reg.s.speed = 2; | ||
122 | cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG | ||
123 | (index, interface), | ||
124 | pcsx_sgmx_an_adv_reg.u64); | ||
125 | } else { | ||
126 | /* MAC Mode - Nothing to do */ | ||
127 | } | ||
128 | } | ||
129 | return 0; | ||
130 | } | ||
131 | |||
132 | /** | ||
133 | * Initialize the SERTES link for the first time or after a loss | ||
134 | * of link. | ||
135 | * | ||
136 | * @interface: Interface to init | ||
137 | * @index: Index of prot on the interface | ||
138 | * | ||
139 | * Returns Zero on success, negative on failure | ||
140 | */ | ||
141 | static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index) | ||
142 | { | ||
143 | union cvmx_pcsx_mrx_control_reg control_reg; | ||
144 | |||
145 | /* | ||
146 | * Take PCS through a reset sequence. | ||
147 | * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero. | ||
148 | * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the | ||
149 | * value of the other PCS*_MR*_CONTROL_REG bits). Read | ||
150 | * PCS*_MR*_CONTROL_REG[RESET] until it changes value to | ||
151 | * zero. | ||
152 | */ | ||
153 | control_reg.u64 = | ||
154 | cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); | ||
155 | if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { | ||
156 | control_reg.s.reset = 1; | ||
157 | cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), | ||
158 | control_reg.u64); | ||
159 | if (CVMX_WAIT_FOR_FIELD64 | ||
160 | (CVMX_PCSX_MRX_CONTROL_REG(index, interface), | ||
161 | union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) { | ||
162 | cvmx_dprintf("SGMII%d: Timeout waiting for port %d " | ||
163 | "to finish reset\n", | ||
164 | interface, index); | ||
165 | return -1; | ||
166 | } | ||
167 | } | ||
168 | |||
169 | /* | ||
170 | * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh | ||
171 | * sgmii negotiation starts. | ||
172 | */ | ||
173 | control_reg.s.rst_an = 1; | ||
174 | control_reg.s.an_en = 1; | ||
175 | control_reg.s.pwr_dn = 0; | ||
176 | cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), | ||
177 | control_reg.u64); | ||
178 | |||
179 | /* | ||
180 | * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating | ||
181 | * that sgmii autonegotiation is complete. In MAC mode this | ||
182 | * isn't an ethernet link, but a link between Octeon and the | ||
183 | * PHY. | ||
184 | */ | ||
185 | if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && | ||
186 | CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface), | ||
187 | union cvmx_pcsx_mrx_status_reg, an_cpt, ==, 1, | ||
188 | 10000)) { | ||
189 | /* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */ | ||
190 | return -1; | ||
191 | } | ||
192 | return 0; | ||
193 | } | ||
194 | |||
195 | /** | ||
196 | * Configure an SGMII link to the specified speed after the SERTES | ||
197 | * link is up. | ||
198 | * | ||
199 | * @interface: Interface to init | ||
200 | * @index: Index of prot on the interface | ||
201 | * @link_info: Link state to configure | ||
202 | * | ||
203 | * Returns Zero on success, negative on failure | ||
204 | */ | ||
205 | static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, | ||
206 | int index, | ||
207 | cvmx_helper_link_info_t | ||
208 | link_info) | ||
209 | { | ||
210 | int is_enabled; | ||
211 | union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; | ||
212 | union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; | ||
213 | |||
214 | /* Disable GMX before we make any changes. Remember the enable state */ | ||
215 | gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
216 | is_enabled = gmxx_prtx_cfg.s.en; | ||
217 | gmxx_prtx_cfg.s.en = 0; | ||
218 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); | ||
219 | |||
220 | /* Wait for GMX to be idle */ | ||
221 | if (CVMX_WAIT_FOR_FIELD64 | ||
222 | (CVMX_GMXX_PRTX_CFG(index, interface), union cvmx_gmxx_prtx_cfg, | ||
223 | rx_idle, ==, 1, 10000) | ||
224 | || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), | ||
225 | union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1, | ||
226 | 10000)) { | ||
227 | cvmx_dprintf | ||
228 | ("SGMII%d: Timeout waiting for port %d to be idle\n", | ||
229 | interface, index); | ||
230 | return -1; | ||
231 | } | ||
232 | |||
233 | /* Read GMX CFG again to make sure the disable completed */ | ||
234 | gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
235 | |||
236 | /* | ||
237 | * Get the misc control for PCS. We will need to set the | ||
238 | * duplication amount. | ||
239 | */ | ||
240 | pcsx_miscx_ctl_reg.u64 = | ||
241 | cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); | ||
242 | |||
243 | /* | ||
244 | * Use GMXENO to force the link down if the status we get says | ||
245 | * it should be down. | ||
246 | */ | ||
247 | pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up; | ||
248 | |||
249 | /* Only change the duplex setting if the link is up */ | ||
250 | if (link_info.s.link_up) | ||
251 | gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex; | ||
252 | |||
253 | /* Do speed based setting for GMX */ | ||
254 | switch (link_info.s.speed) { | ||
255 | case 10: | ||
256 | gmxx_prtx_cfg.s.speed = 0; | ||
257 | gmxx_prtx_cfg.s.speed_msb = 1; | ||
258 | gmxx_prtx_cfg.s.slottime = 0; | ||
259 | /* Setting from GMX-603 */ | ||
260 | pcsx_miscx_ctl_reg.s.samp_pt = 25; | ||
261 | cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); | ||
262 | cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); | ||
263 | break; | ||
264 | case 100: | ||
265 | gmxx_prtx_cfg.s.speed = 0; | ||
266 | gmxx_prtx_cfg.s.speed_msb = 0; | ||
267 | gmxx_prtx_cfg.s.slottime = 0; | ||
268 | pcsx_miscx_ctl_reg.s.samp_pt = 0x5; | ||
269 | cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); | ||
270 | cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); | ||
271 | break; | ||
272 | case 1000: | ||
273 | gmxx_prtx_cfg.s.speed = 1; | ||
274 | gmxx_prtx_cfg.s.speed_msb = 0; | ||
275 | gmxx_prtx_cfg.s.slottime = 1; | ||
276 | pcsx_miscx_ctl_reg.s.samp_pt = 1; | ||
277 | cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512); | ||
278 | cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192); | ||
279 | break; | ||
280 | default: | ||
281 | break; | ||
282 | } | ||
283 | |||
284 | /* Write the new misc control for PCS */ | ||
285 | cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), | ||
286 | pcsx_miscx_ctl_reg.u64); | ||
287 | |||
288 | /* Write the new GMX settings with the port still disabled */ | ||
289 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); | ||
290 | |||
291 | /* Read GMX CFG again to make sure the config completed */ | ||
292 | gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
293 | |||
294 | /* Restore the enabled / disabled state */ | ||
295 | gmxx_prtx_cfg.s.en = is_enabled; | ||
296 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); | ||
297 | |||
298 | return 0; | ||
299 | } | ||
300 | |||
301 | /** | ||
302 | * Bring up the SGMII interface to be ready for packet I/O but | ||
303 | * leave I/O disabled using the GMX override. This function | ||
304 | * follows the bringup documented in 10.6.3 of the manual. | ||
305 | * | ||
306 | * @interface: Interface to bringup | ||
307 | * @num_ports: Number of ports on the interface | ||
308 | * | ||
309 | * Returns Zero on success, negative on failure | ||
310 | */ | ||
311 | static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) | ||
312 | { | ||
313 | int index; | ||
314 | |||
315 | __cvmx_helper_setup_gmx(interface, num_ports); | ||
316 | |||
317 | for (index = 0; index < num_ports; index++) { | ||
318 | int ipd_port = cvmx_helper_get_ipd_port(interface, index); | ||
319 | __cvmx_helper_sgmii_hardware_init_one_time(interface, index); | ||
320 | __cvmx_helper_sgmii_link_set(ipd_port, | ||
321 | __cvmx_helper_sgmii_link_get | ||
322 | (ipd_port)); | ||
323 | |||
324 | } | ||
325 | |||
326 | return 0; | ||
327 | } | ||
328 | |||
329 | /** | ||
330 | * Probe a SGMII interface and determine the number of ports | ||
331 | * connected to it. The SGMII interface should still be down after | ||
332 | * this call. | ||
333 | * | ||
334 | * @interface: Interface to probe | ||
335 | * | ||
336 | * Returns Number of ports on the interface. Zero to disable. | ||
337 | */ | ||
338 | int __cvmx_helper_sgmii_probe(int interface) | ||
339 | { | ||
340 | union cvmx_gmxx_inf_mode mode; | ||
341 | |||
342 | /* | ||
343 | * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the | ||
344 | * interface needs to be enabled before IPD otherwise per port | ||
345 | * backpressure may not work properly | ||
346 | */ | ||
347 | mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); | ||
348 | mode.s.en = 1; | ||
349 | cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); | ||
350 | return 4; | ||
351 | } | ||
352 | |||
353 | /** | ||
354 | * Bringup and enable a SGMII interface. After this call packet | ||
355 | * I/O should be fully functional. This is called with IPD | ||
356 | * enabled but PKO disabled. | ||
357 | * | ||
358 | * @interface: Interface to bring up | ||
359 | * | ||
360 | * Returns Zero on success, negative on failure | ||
361 | */ | ||
362 | int __cvmx_helper_sgmii_enable(int interface) | ||
363 | { | ||
364 | int num_ports = cvmx_helper_ports_on_interface(interface); | ||
365 | int index; | ||
366 | |||
367 | __cvmx_helper_sgmii_hardware_init(interface, num_ports); | ||
368 | |||
369 | for (index = 0; index < num_ports; index++) { | ||
370 | union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; | ||
371 | gmxx_prtx_cfg.u64 = | ||
372 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
373 | gmxx_prtx_cfg.s.en = 1; | ||
374 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), | ||
375 | gmxx_prtx_cfg.u64); | ||
376 | __cvmx_interrupt_pcsx_intx_en_reg_enable(index, interface); | ||
377 | } | ||
378 | __cvmx_interrupt_pcsxx_int_en_reg_enable(interface); | ||
379 | __cvmx_interrupt_gmxx_enable(interface); | ||
380 | return 0; | ||
381 | } | ||
382 | |||
383 | /** | ||
384 | * Return the link state of an IPD/PKO port as returned by | ||
385 | * auto negotiation. The result of this function may not match | ||
386 | * Octeon's link config if auto negotiation has changed since | ||
387 | * the last call to cvmx_helper_link_set(). | ||
388 | * | ||
389 | * @ipd_port: IPD/PKO port to query | ||
390 | * | ||
391 | * Returns Link state | ||
392 | */ | ||
393 | cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port) | ||
394 | { | ||
395 | cvmx_helper_link_info_t result; | ||
396 | union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg; | ||
397 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
398 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
399 | union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg; | ||
400 | |||
401 | result.u64 = 0; | ||
402 | |||
403 | if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { | ||
404 | /* The simulator gives you a simulated 1Gbps full duplex link */ | ||
405 | result.s.link_up = 1; | ||
406 | result.s.full_duplex = 1; | ||
407 | result.s.speed = 1000; | ||
408 | return result; | ||
409 | } | ||
410 | |||
411 | pcsx_mrx_control_reg.u64 = | ||
412 | cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); | ||
413 | if (pcsx_mrx_control_reg.s.loopbck1) { | ||
414 | /* Force 1Gbps full duplex link for internal loopback */ | ||
415 | result.s.link_up = 1; | ||
416 | result.s.full_duplex = 1; | ||
417 | result.s.speed = 1000; | ||
418 | return result; | ||
419 | } | ||
420 | |||
421 | pcs_misc_ctl_reg.u64 = | ||
422 | cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); | ||
423 | if (pcs_misc_ctl_reg.s.mode) { | ||
424 | /* 1000BASE-X */ | ||
425 | /* FIXME */ | ||
426 | } else { | ||
427 | union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; | ||
428 | pcsx_miscx_ctl_reg.u64 = | ||
429 | cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); | ||
430 | if (pcsx_miscx_ctl_reg.s.mac_phy) { | ||
431 | /* PHY Mode */ | ||
432 | union cvmx_pcsx_mrx_status_reg pcsx_mrx_status_reg; | ||
433 | union cvmx_pcsx_anx_results_reg pcsx_anx_results_reg; | ||
434 | |||
435 | /* | ||
436 | * Don't bother continuing if the SERTES low | ||
437 | * level link is down | ||
438 | */ | ||
439 | pcsx_mrx_status_reg.u64 = | ||
440 | cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG | ||
441 | (index, interface)); | ||
442 | if (pcsx_mrx_status_reg.s.lnk_st == 0) { | ||
443 | if (__cvmx_helper_sgmii_hardware_init_link | ||
444 | (interface, index) != 0) | ||
445 | return result; | ||
446 | } | ||
447 | |||
448 | /* Read the autoneg results */ | ||
449 | pcsx_anx_results_reg.u64 = | ||
450 | cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG | ||
451 | (index, interface)); | ||
452 | if (pcsx_anx_results_reg.s.an_cpt) { | ||
453 | /* | ||
454 | * Auto negotiation is complete. Set | ||
455 | * status accordingly. | ||
456 | */ | ||
457 | result.s.full_duplex = | ||
458 | pcsx_anx_results_reg.s.dup; | ||
459 | result.s.link_up = | ||
460 | pcsx_anx_results_reg.s.link_ok; | ||
461 | switch (pcsx_anx_results_reg.s.spd) { | ||
462 | case 0: | ||
463 | result.s.speed = 10; | ||
464 | break; | ||
465 | case 1: | ||
466 | result.s.speed = 100; | ||
467 | break; | ||
468 | case 2: | ||
469 | result.s.speed = 1000; | ||
470 | break; | ||
471 | default: | ||
472 | result.s.speed = 0; | ||
473 | result.s.link_up = 0; | ||
474 | break; | ||
475 | } | ||
476 | } else { | ||
477 | /* | ||
478 | * Auto negotiation isn't | ||
479 | * complete. Return link down. | ||
480 | */ | ||
481 | result.s.speed = 0; | ||
482 | result.s.link_up = 0; | ||
483 | } | ||
484 | } else { /* MAC Mode */ | ||
485 | |||
486 | result = __cvmx_helper_board_link_get(ipd_port); | ||
487 | } | ||
488 | } | ||
489 | return result; | ||
490 | } | ||
491 | |||
492 | /** | ||
493 | * Configure an IPD/PKO port for the specified link state. This | ||
494 | * function does not influence auto negotiation at the PHY level. | ||
495 | * The passed link state must always match the link state returned | ||
496 | * by cvmx_helper_link_get(). It is normally best to use | ||
497 | * cvmx_helper_link_autoconf() instead. | ||
498 | * | ||
499 | * @ipd_port: IPD/PKO port to configure | ||
500 | * @link_info: The new link state | ||
501 | * | ||
502 | * Returns Zero on success, negative on failure | ||
503 | */ | ||
504 | int __cvmx_helper_sgmii_link_set(int ipd_port, | ||
505 | cvmx_helper_link_info_t link_info) | ||
506 | { | ||
507 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
508 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
509 | __cvmx_helper_sgmii_hardware_init_link(interface, index); | ||
510 | return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, | ||
511 | link_info); | ||
512 | } | ||
513 | |||
514 | /** | ||
515 | * Configure a port for internal and/or external loopback. Internal | ||
516 | * loopback causes packets sent by the port to be received by | ||
517 | * Octeon. External loopback causes packets received from the wire to | ||
518 | * sent out again. | ||
519 | * | ||
520 | * @ipd_port: IPD/PKO port to loopback. | ||
521 | * @enable_internal: | ||
522 | * Non zero if you want internal loopback | ||
523 | * @enable_external: | ||
524 | * Non zero if you want external loopback | ||
525 | * | ||
526 | * Returns Zero on success, negative on failure. | ||
527 | */ | ||
528 | int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal, | ||
529 | int enable_external) | ||
530 | { | ||
531 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
532 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
533 | union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg; | ||
534 | union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; | ||
535 | |||
536 | pcsx_mrx_control_reg.u64 = | ||
537 | cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); | ||
538 | pcsx_mrx_control_reg.s.loopbck1 = enable_internal; | ||
539 | cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), | ||
540 | pcsx_mrx_control_reg.u64); | ||
541 | |||
542 | pcsx_miscx_ctl_reg.u64 = | ||
543 | cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); | ||
544 | pcsx_miscx_ctl_reg.s.loopbck2 = enable_external; | ||
545 | cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), | ||
546 | pcsx_miscx_ctl_reg.u64); | ||
547 | |||
548 | __cvmx_helper_sgmii_hardware_init_link(interface, index); | ||
549 | return 0; | ||
550 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/drivers/staging/octeon/cvmx-helper-sgmii.h new file mode 100644 index 000000000000..19b48d60857f --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-sgmii.h | |||
@@ -0,0 +1,104 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * | ||
31 | * Functions for SGMII initialization, configuration, | ||
32 | * and monitoring. | ||
33 | * | ||
34 | */ | ||
35 | #ifndef __CVMX_HELPER_SGMII_H__ | ||
36 | #define __CVMX_HELPER_SGMII_H__ | ||
37 | |||
38 | /** | ||
39 | * Probe a SGMII interface and determine the number of ports | ||
40 | * connected to it. The SGMII interface should still be down after | ||
41 | * this call. | ||
42 | * | ||
43 | * @interface: Interface to probe | ||
44 | * | ||
45 | * Returns Number of ports on the interface. Zero to disable. | ||
46 | */ | ||
47 | extern int __cvmx_helper_sgmii_probe(int interface); | ||
48 | |||
49 | /** | ||
50 | * Bringup and enable a SGMII interface. After this call packet | ||
51 | * I/O should be fully functional. This is called with IPD | ||
52 | * enabled but PKO disabled. | ||
53 | * | ||
54 | * @interface: Interface to bring up | ||
55 | * | ||
56 | * Returns Zero on success, negative on failure | ||
57 | */ | ||
58 | extern int __cvmx_helper_sgmii_enable(int interface); | ||
59 | |||
60 | /** | ||
61 | * Return the link state of an IPD/PKO port as returned by | ||
62 | * auto negotiation. The result of this function may not match | ||
63 | * Octeon's link config if auto negotiation has changed since | ||
64 | * the last call to cvmx_helper_link_set(). | ||
65 | * | ||
66 | * @ipd_port: IPD/PKO port to query | ||
67 | * | ||
68 | * Returns Link state | ||
69 | */ | ||
70 | extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port); | ||
71 | |||
72 | /** | ||
73 | * Configure an IPD/PKO port for the specified link state. This | ||
74 | * function does not influence auto negotiation at the PHY level. | ||
75 | * The passed link state must always match the link state returned | ||
76 | * by cvmx_helper_link_get(). It is normally best to use | ||
77 | * cvmx_helper_link_autoconf() instead. | ||
78 | * | ||
79 | * @ipd_port: IPD/PKO port to configure | ||
80 | * @link_info: The new link state | ||
81 | * | ||
82 | * Returns Zero on success, negative on failure | ||
83 | */ | ||
84 | extern int __cvmx_helper_sgmii_link_set(int ipd_port, | ||
85 | cvmx_helper_link_info_t link_info); | ||
86 | |||
87 | /** | ||
88 | * Configure a port for internal and/or external loopback. Internal loopback | ||
89 | * causes packets sent by the port to be received by Octeon. External loopback | ||
90 | * causes packets received from the wire to sent out again. | ||
91 | * | ||
92 | * @ipd_port: IPD/PKO port to loopback. | ||
93 | * @enable_internal: | ||
94 | * Non zero if you want internal loopback | ||
95 | * @enable_external: | ||
96 | * Non zero if you want external loopback | ||
97 | * | ||
98 | * Returns Zero on success, negative on failure. | ||
99 | */ | ||
100 | extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port, | ||
101 | int enable_internal, | ||
102 | int enable_external); | ||
103 | |||
104 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-helper-spi.c b/drivers/staging/octeon/cvmx-helper-spi.c new file mode 100644 index 000000000000..8ba6c832471e --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-spi.c | |||
@@ -0,0 +1,195 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | void __cvmx_interrupt_gmxx_enable(int interface); | ||
29 | void __cvmx_interrupt_spxx_int_msk_enable(int index); | ||
30 | void __cvmx_interrupt_stxx_int_msk_enable(int index); | ||
31 | |||
32 | /* | ||
33 | * Functions for SPI initialization, configuration, | ||
34 | * and monitoring. | ||
35 | */ | ||
36 | #include <asm/octeon/octeon.h> | ||
37 | |||
38 | #include "cvmx-config.h" | ||
39 | #include "cvmx-spi.h" | ||
40 | #include "cvmx-helper.h" | ||
41 | |||
42 | #include "cvmx-pip-defs.h" | ||
43 | #include "cvmx-pko-defs.h" | ||
44 | |||
45 | /* | ||
46 | * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI | ||
47 | * initialization routines wait for SPI training. You can override the | ||
48 | * value using executive-config.h if necessary. | ||
49 | */ | ||
50 | #ifndef CVMX_HELPER_SPI_TIMEOUT | ||
51 | #define CVMX_HELPER_SPI_TIMEOUT 10 | ||
52 | #endif | ||
53 | |||
54 | /** | ||
55 | * Probe a SPI interface and determine the number of ports | ||
56 | * connected to it. The SPI interface should still be down after | ||
57 | * this call. | ||
58 | * | ||
59 | * @interface: Interface to probe | ||
60 | * | ||
61 | * Returns Number of ports on the interface. Zero to disable. | ||
62 | */ | ||
63 | int __cvmx_helper_spi_probe(int interface) | ||
64 | { | ||
65 | int num_ports = 0; | ||
66 | |||
67 | if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && | ||
68 | cvmx_spi4000_is_present(interface)) { | ||
69 | num_ports = 10; | ||
70 | } else { | ||
71 | union cvmx_pko_reg_crc_enable enable; | ||
72 | num_ports = 16; | ||
73 | /* | ||
74 | * Unlike the SPI4000, most SPI devices don't | ||
75 | * automatically put on the L2 CRC. For everything | ||
76 | * except for the SPI4000 have PKO append the L2 CRC | ||
77 | * to the packet. | ||
78 | */ | ||
79 | enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE); | ||
80 | enable.s.enable |= 0xffff << (interface * 16); | ||
81 | cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64); | ||
82 | } | ||
83 | __cvmx_helper_setup_gmx(interface, num_ports); | ||
84 | return num_ports; | ||
85 | } | ||
86 | |||
87 | /** | ||
88 | * Bringup and enable a SPI interface. After this call packet I/O | ||
89 | * should be fully functional. This is called with IPD enabled but | ||
90 | * PKO disabled. | ||
91 | * | ||
92 | * @interface: Interface to bring up | ||
93 | * | ||
94 | * Returns Zero on success, negative on failure | ||
95 | */ | ||
96 | int __cvmx_helper_spi_enable(int interface) | ||
97 | { | ||
98 | /* | ||
99 | * Normally the ethernet L2 CRC is checked and stripped in the | ||
100 | * GMX block. When you are using SPI, this isn' the case and | ||
101 | * IPD needs to check the L2 CRC. | ||
102 | */ | ||
103 | int num_ports = cvmx_helper_ports_on_interface(interface); | ||
104 | int ipd_port; | ||
105 | for (ipd_port = interface * 16; ipd_port < interface * 16 + num_ports; | ||
106 | ipd_port++) { | ||
107 | union cvmx_pip_prt_cfgx port_config; | ||
108 | port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); | ||
109 | port_config.s.crc_en = 1; | ||
110 | cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); | ||
111 | } | ||
112 | |||
113 | if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { | ||
114 | cvmx_spi_start_interface(interface, CVMX_SPI_MODE_DUPLEX, | ||
115 | CVMX_HELPER_SPI_TIMEOUT, num_ports); | ||
116 | if (cvmx_spi4000_is_present(interface)) | ||
117 | cvmx_spi4000_initialize(interface); | ||
118 | } | ||
119 | __cvmx_interrupt_spxx_int_msk_enable(interface); | ||
120 | __cvmx_interrupt_stxx_int_msk_enable(interface); | ||
121 | __cvmx_interrupt_gmxx_enable(interface); | ||
122 | return 0; | ||
123 | } | ||
124 | |||
125 | /** | ||
126 | * Return the link state of an IPD/PKO port as returned by | ||
127 | * auto negotiation. The result of this function may not match | ||
128 | * Octeon's link config if auto negotiation has changed since | ||
129 | * the last call to cvmx_helper_link_set(). | ||
130 | * | ||
131 | * @ipd_port: IPD/PKO port to query | ||
132 | * | ||
133 | * Returns Link state | ||
134 | */ | ||
135 | cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port) | ||
136 | { | ||
137 | cvmx_helper_link_info_t result; | ||
138 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
139 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
140 | result.u64 = 0; | ||
141 | |||
142 | if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { | ||
143 | /* The simulator gives you a simulated full duplex link */ | ||
144 | result.s.link_up = 1; | ||
145 | result.s.full_duplex = 1; | ||
146 | result.s.speed = 10000; | ||
147 | } else if (cvmx_spi4000_is_present(interface)) { | ||
148 | union cvmx_gmxx_rxx_rx_inbnd inband = | ||
149 | cvmx_spi4000_check_speed(interface, index); | ||
150 | result.s.link_up = inband.s.status; | ||
151 | result.s.full_duplex = inband.s.duplex; | ||
152 | switch (inband.s.speed) { | ||
153 | case 0: /* 10 Mbps */ | ||
154 | result.s.speed = 10; | ||
155 | break; | ||
156 | case 1: /* 100 Mbps */ | ||
157 | result.s.speed = 100; | ||
158 | break; | ||
159 | case 2: /* 1 Gbps */ | ||
160 | result.s.speed = 1000; | ||
161 | break; | ||
162 | case 3: /* Illegal */ | ||
163 | result.s.speed = 0; | ||
164 | result.s.link_up = 0; | ||
165 | break; | ||
166 | } | ||
167 | } else { | ||
168 | /* For generic SPI we can't determine the link, just return some | ||
169 | sane results */ | ||
170 | result.s.link_up = 1; | ||
171 | result.s.full_duplex = 1; | ||
172 | result.s.speed = 10000; | ||
173 | } | ||
174 | return result; | ||
175 | } | ||
176 | |||
177 | /** | ||
178 | * Configure an IPD/PKO port for the specified link state. This | ||
179 | * function does not influence auto negotiation at the PHY level. | ||
180 | * The passed link state must always match the link state returned | ||
181 | * by cvmx_helper_link_get(). It is normally best to use | ||
182 | * cvmx_helper_link_autoconf() instead. | ||
183 | * | ||
184 | * @ipd_port: IPD/PKO port to configure | ||
185 | * @link_info: The new link state | ||
186 | * | ||
187 | * Returns Zero on success, negative on failure | ||
188 | */ | ||
189 | int __cvmx_helper_spi_link_set(int ipd_port, cvmx_helper_link_info_t link_info) | ||
190 | { | ||
191 | /* Nothing to do. If we have a SPI4000 then the setup was already performed | ||
192 | by cvmx_spi4000_check_speed(). If not then there isn't any link | ||
193 | info */ | ||
194 | return 0; | ||
195 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/drivers/staging/octeon/cvmx-helper-spi.h new file mode 100644 index 000000000000..69bac036d10e --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-spi.h | |||
@@ -0,0 +1,84 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Functions for SPI initialization, configuration, | ||
30 | * and monitoring. | ||
31 | */ | ||
32 | #ifndef __CVMX_HELPER_SPI_H__ | ||
33 | #define __CVMX_HELPER_SPI_H__ | ||
34 | |||
35 | /** | ||
36 | * Probe a SPI interface and determine the number of ports | ||
37 | * connected to it. The SPI interface should still be down after | ||
38 | * this call. | ||
39 | * | ||
40 | * @interface: Interface to probe | ||
41 | * | ||
42 | * Returns Number of ports on the interface. Zero to disable. | ||
43 | */ | ||
44 | extern int __cvmx_helper_spi_probe(int interface); | ||
45 | |||
46 | /** | ||
47 | * Bringup and enable a SPI interface. After this call packet I/O | ||
48 | * should be fully functional. This is called with IPD enabled but | ||
49 | * PKO disabled. | ||
50 | * | ||
51 | * @interface: Interface to bring up | ||
52 | * | ||
53 | * Returns Zero on success, negative on failure | ||
54 | */ | ||
55 | extern int __cvmx_helper_spi_enable(int interface); | ||
56 | |||
57 | /** | ||
58 | * Return the link state of an IPD/PKO port as returned by | ||
59 | * auto negotiation. The result of this function may not match | ||
60 | * Octeon's link config if auto negotiation has changed since | ||
61 | * the last call to cvmx_helper_link_set(). | ||
62 | * | ||
63 | * @ipd_port: IPD/PKO port to query | ||
64 | * | ||
65 | * Returns Link state | ||
66 | */ | ||
67 | extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port); | ||
68 | |||
69 | /** | ||
70 | * Configure an IPD/PKO port for the specified link state. This | ||
71 | * function does not influence auto negotiation at the PHY level. | ||
72 | * The passed link state must always match the link state returned | ||
73 | * by cvmx_helper_link_get(). It is normally best to use | ||
74 | * cvmx_helper_link_autoconf() instead. | ||
75 | * | ||
76 | * @ipd_port: IPD/PKO port to configure | ||
77 | * @link_info: The new link state | ||
78 | * | ||
79 | * Returns Zero on success, negative on failure | ||
80 | */ | ||
81 | extern int __cvmx_helper_spi_link_set(int ipd_port, | ||
82 | cvmx_helper_link_info_t link_info); | ||
83 | |||
84 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/drivers/staging/octeon/cvmx-helper-util.c new file mode 100644 index 000000000000..41ef8a40bb03 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-util.c | |||
@@ -0,0 +1,433 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Small helper utilities. | ||
30 | */ | ||
31 | #include <linux/kernel.h> | ||
32 | |||
33 | #include <asm/octeon/octeon.h> | ||
34 | |||
35 | #include "cvmx-config.h" | ||
36 | |||
37 | #include "cvmx-fpa.h" | ||
38 | #include "cvmx-pip.h" | ||
39 | #include "cvmx-pko.h" | ||
40 | #include "cvmx-ipd.h" | ||
41 | #include "cvmx-spi.h" | ||
42 | |||
43 | #include "cvmx-helper.h" | ||
44 | #include "cvmx-helper-util.h" | ||
45 | |||
46 | #include <asm/octeon/cvmx-ipd-defs.h> | ||
47 | |||
48 | /** | ||
49 | * Convert a interface mode into a human readable string | ||
50 | * | ||
51 | * @mode: Mode to convert | ||
52 | * | ||
53 | * Returns String | ||
54 | */ | ||
55 | const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t | ||
56 | mode) | ||
57 | { | ||
58 | switch (mode) { | ||
59 | case CVMX_HELPER_INTERFACE_MODE_DISABLED: | ||
60 | return "DISABLED"; | ||
61 | case CVMX_HELPER_INTERFACE_MODE_RGMII: | ||
62 | return "RGMII"; | ||
63 | case CVMX_HELPER_INTERFACE_MODE_GMII: | ||
64 | return "GMII"; | ||
65 | case CVMX_HELPER_INTERFACE_MODE_SPI: | ||
66 | return "SPI"; | ||
67 | case CVMX_HELPER_INTERFACE_MODE_PCIE: | ||
68 | return "PCIE"; | ||
69 | case CVMX_HELPER_INTERFACE_MODE_XAUI: | ||
70 | return "XAUI"; | ||
71 | case CVMX_HELPER_INTERFACE_MODE_SGMII: | ||
72 | return "SGMII"; | ||
73 | case CVMX_HELPER_INTERFACE_MODE_PICMG: | ||
74 | return "PICMG"; | ||
75 | case CVMX_HELPER_INTERFACE_MODE_NPI: | ||
76 | return "NPI"; | ||
77 | case CVMX_HELPER_INTERFACE_MODE_LOOP: | ||
78 | return "LOOP"; | ||
79 | } | ||
80 | return "UNKNOWN"; | ||
81 | } | ||
82 | |||
83 | /** | ||
84 | * Debug routine to dump the packet structure to the console | ||
85 | * | ||
86 | * @work: Work queue entry containing the packet to dump | ||
87 | * Returns | ||
88 | */ | ||
89 | int cvmx_helper_dump_packet(cvmx_wqe_t *work) | ||
90 | { | ||
91 | uint64_t count; | ||
92 | uint64_t remaining_bytes; | ||
93 | union cvmx_buf_ptr buffer_ptr; | ||
94 | uint64_t start_of_buffer; | ||
95 | uint8_t *data_address; | ||
96 | uint8_t *end_of_data; | ||
97 | |||
98 | cvmx_dprintf("Packet Length: %u\n", work->len); | ||
99 | cvmx_dprintf(" Input Port: %u\n", work->ipprt); | ||
100 | cvmx_dprintf(" QoS: %u\n", work->qos); | ||
101 | cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs); | ||
102 | |||
103 | if (work->word2.s.bufs == 0) { | ||
104 | union cvmx_ipd_wqe_fpa_queue wqe_pool; | ||
105 | wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE); | ||
106 | buffer_ptr.u64 = 0; | ||
107 | buffer_ptr.s.pool = wqe_pool.s.wqe_pool; | ||
108 | buffer_ptr.s.size = 128; | ||
109 | buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data); | ||
110 | if (likely(!work->word2.s.not_IP)) { | ||
111 | union cvmx_pip_ip_offset pip_ip_offset; | ||
112 | pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET); | ||
113 | buffer_ptr.s.addr += | ||
114 | (pip_ip_offset.s.offset << 3) - | ||
115 | work->word2.s.ip_offset; | ||
116 | buffer_ptr.s.addr += (work->word2.s.is_v6 ^ 1) << 2; | ||
117 | } else { | ||
118 | /* | ||
119 | * WARNING: This code assumes that the packet | ||
120 | * is not RAW. If it was, we would use | ||
121 | * PIP_GBL_CFG[RAW_SHF] instead of | ||
122 | * PIP_GBL_CFG[NIP_SHF]. | ||
123 | */ | ||
124 | union cvmx_pip_gbl_cfg pip_gbl_cfg; | ||
125 | pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG); | ||
126 | buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf; | ||
127 | } | ||
128 | } else | ||
129 | buffer_ptr = work->packet_ptr; | ||
130 | remaining_bytes = work->len; | ||
131 | |||
132 | while (remaining_bytes) { | ||
133 | start_of_buffer = | ||
134 | ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; | ||
135 | cvmx_dprintf(" Buffer Start:%llx\n", | ||
136 | (unsigned long long)start_of_buffer); | ||
137 | cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i); | ||
138 | cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back); | ||
139 | cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool); | ||
140 | cvmx_dprintf(" Buffer Data: %llx\n", | ||
141 | (unsigned long long)buffer_ptr.s.addr); | ||
142 | cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size); | ||
143 | |||
144 | cvmx_dprintf("\t\t"); | ||
145 | data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr); | ||
146 | end_of_data = data_address + buffer_ptr.s.size; | ||
147 | count = 0; | ||
148 | while (data_address < end_of_data) { | ||
149 | if (remaining_bytes == 0) | ||
150 | break; | ||
151 | else | ||
152 | remaining_bytes--; | ||
153 | cvmx_dprintf("%02x", (unsigned int)*data_address); | ||
154 | data_address++; | ||
155 | if (remaining_bytes && (count == 7)) { | ||
156 | cvmx_dprintf("\n\t\t"); | ||
157 | count = 0; | ||
158 | } else | ||
159 | count++; | ||
160 | } | ||
161 | cvmx_dprintf("\n"); | ||
162 | |||
163 | if (remaining_bytes) | ||
164 | buffer_ptr = *(union cvmx_buf_ptr *) | ||
165 | cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); | ||
166 | } | ||
167 | return 0; | ||
168 | } | ||
169 | |||
170 | /** | ||
171 | * Setup Random Early Drop on a specific input queue | ||
172 | * | ||
173 | * @queue: Input queue to setup RED on (0-7) | ||
174 | * @pass_thresh: | ||
175 | * Packets will begin slowly dropping when there are less than | ||
176 | * this many packet buffers free in FPA 0. | ||
177 | * @drop_thresh: | ||
178 | * All incomming packets will be dropped when there are less | ||
179 | * than this many free packet buffers in FPA 0. | ||
180 | * Returns Zero on success. Negative on failure | ||
181 | */ | ||
182 | int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh) | ||
183 | { | ||
184 | union cvmx_ipd_qosx_red_marks red_marks; | ||
185 | union cvmx_ipd_red_quex_param red_param; | ||
186 | |||
187 | /* Set RED to begin dropping packets when there are pass_thresh buffers | ||
188 | left. It will linearly drop more packets until reaching drop_thresh | ||
189 | buffers */ | ||
190 | red_marks.u64 = 0; | ||
191 | red_marks.s.drop = drop_thresh; | ||
192 | red_marks.s.pass = pass_thresh; | ||
193 | cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); | ||
194 | |||
195 | /* Use the actual queue 0 counter, not the average */ | ||
196 | red_param.u64 = 0; | ||
197 | red_param.s.prb_con = | ||
198 | (255ul << 24) / (red_marks.s.pass - red_marks.s.drop); | ||
199 | red_param.s.avg_con = 1; | ||
200 | red_param.s.new_con = 255; | ||
201 | red_param.s.use_pcnt = 1; | ||
202 | cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); | ||
203 | return 0; | ||
204 | } | ||
205 | |||
206 | /** | ||
207 | * Setup Random Early Drop to automatically begin dropping packets. | ||
208 | * | ||
209 | * @pass_thresh: | ||
210 | * Packets will begin slowly dropping when there are less than | ||
211 | * this many packet buffers free in FPA 0. | ||
212 | * @drop_thresh: | ||
213 | * All incomming packets will be dropped when there are less | ||
214 | * than this many free packet buffers in FPA 0. | ||
215 | * Returns Zero on success. Negative on failure | ||
216 | */ | ||
217 | int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) | ||
218 | { | ||
219 | union cvmx_ipd_portx_bp_page_cnt page_cnt; | ||
220 | union cvmx_ipd_bp_prt_red_end ipd_bp_prt_red_end; | ||
221 | union cvmx_ipd_red_port_enable red_port_enable; | ||
222 | int queue; | ||
223 | int interface; | ||
224 | int port; | ||
225 | |||
226 | /* Disable backpressure based on queued buffers. It needs SW support */ | ||
227 | page_cnt.u64 = 0; | ||
228 | page_cnt.s.bp_enb = 0; | ||
229 | page_cnt.s.page_cnt = 100; | ||
230 | for (interface = 0; interface < 2; interface++) { | ||
231 | for (port = cvmx_helper_get_first_ipd_port(interface); | ||
232 | port < cvmx_helper_get_last_ipd_port(interface); port++) | ||
233 | cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), | ||
234 | page_cnt.u64); | ||
235 | } | ||
236 | |||
237 | for (queue = 0; queue < 8; queue++) | ||
238 | cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh); | ||
239 | |||
240 | /* Shutoff the dropping based on the per port page count. SW isn't | ||
241 | decrementing it right now */ | ||
242 | ipd_bp_prt_red_end.u64 = 0; | ||
243 | ipd_bp_prt_red_end.s.prt_enb = 0; | ||
244 | cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); | ||
245 | |||
246 | red_port_enable.u64 = 0; | ||
247 | red_port_enable.s.prt_enb = 0xfffffffffull; | ||
248 | red_port_enable.s.avg_dly = 10000; | ||
249 | red_port_enable.s.prb_dly = 10000; | ||
250 | cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); | ||
251 | |||
252 | return 0; | ||
253 | } | ||
254 | |||
255 | /** | ||
256 | * Setup the common GMX settings that determine the number of | ||
257 | * ports. These setting apply to almost all configurations of all | ||
258 | * chips. | ||
259 | * | ||
260 | * @interface: Interface to configure | ||
261 | * @num_ports: Number of ports on the interface | ||
262 | * | ||
263 | * Returns Zero on success, negative on failure | ||
264 | */ | ||
265 | int __cvmx_helper_setup_gmx(int interface, int num_ports) | ||
266 | { | ||
267 | union cvmx_gmxx_tx_prts gmx_tx_prts; | ||
268 | union cvmx_gmxx_rx_prts gmx_rx_prts; | ||
269 | union cvmx_pko_reg_gmx_port_mode pko_mode; | ||
270 | union cvmx_gmxx_txx_thresh gmx_tx_thresh; | ||
271 | int index; | ||
272 | |||
273 | /* Tell GMX the number of TX ports on this interface */ | ||
274 | gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface)); | ||
275 | gmx_tx_prts.s.prts = num_ports; | ||
276 | cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); | ||
277 | |||
278 | /* Tell GMX the number of RX ports on this interface. This only | ||
279 | ** applies to *GMII and XAUI ports */ | ||
280 | if (cvmx_helper_interface_get_mode(interface) == | ||
281 | CVMX_HELPER_INTERFACE_MODE_RGMII | ||
282 | || cvmx_helper_interface_get_mode(interface) == | ||
283 | CVMX_HELPER_INTERFACE_MODE_SGMII | ||
284 | || cvmx_helper_interface_get_mode(interface) == | ||
285 | CVMX_HELPER_INTERFACE_MODE_GMII | ||
286 | || cvmx_helper_interface_get_mode(interface) == | ||
287 | CVMX_HELPER_INTERFACE_MODE_XAUI) { | ||
288 | if (num_ports > 4) { | ||
289 | cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal " | ||
290 | "num_ports\n"); | ||
291 | return -1; | ||
292 | } | ||
293 | |||
294 | gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface)); | ||
295 | gmx_rx_prts.s.prts = num_ports; | ||
296 | cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); | ||
297 | } | ||
298 | |||
299 | /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */ | ||
300 | if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) | ||
301 | && !OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
302 | /* Tell PKO the number of ports on this interface */ | ||
303 | pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); | ||
304 | if (interface == 0) { | ||
305 | if (num_ports == 1) | ||
306 | pko_mode.s.mode0 = 4; | ||
307 | else if (num_ports == 2) | ||
308 | pko_mode.s.mode0 = 3; | ||
309 | else if (num_ports <= 4) | ||
310 | pko_mode.s.mode0 = 2; | ||
311 | else if (num_ports <= 8) | ||
312 | pko_mode.s.mode0 = 1; | ||
313 | else | ||
314 | pko_mode.s.mode0 = 0; | ||
315 | } else { | ||
316 | if (num_ports == 1) | ||
317 | pko_mode.s.mode1 = 4; | ||
318 | else if (num_ports == 2) | ||
319 | pko_mode.s.mode1 = 3; | ||
320 | else if (num_ports <= 4) | ||
321 | pko_mode.s.mode1 = 2; | ||
322 | else if (num_ports <= 8) | ||
323 | pko_mode.s.mode1 = 1; | ||
324 | else | ||
325 | pko_mode.s.mode1 = 0; | ||
326 | } | ||
327 | cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); | ||
328 | } | ||
329 | |||
330 | /* | ||
331 | * Set GMX to buffer as much data as possible before starting | ||
332 | * transmit. This reduces the chances that we have a TX under | ||
333 | * run due to memory contention. Any packet that fits entirely | ||
334 | * in the GMX FIFO can never have an under run regardless of | ||
335 | * memory load. | ||
336 | */ | ||
337 | gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); | ||
338 | if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) | ||
339 | || OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
340 | /* These chips have a fixed max threshold of 0x40 */ | ||
341 | gmx_tx_thresh.s.cnt = 0x40; | ||
342 | } else { | ||
343 | /* Choose the max value for the number of ports */ | ||
344 | if (num_ports <= 1) | ||
345 | gmx_tx_thresh.s.cnt = 0x100 / 1; | ||
346 | else if (num_ports == 2) | ||
347 | gmx_tx_thresh.s.cnt = 0x100 / 2; | ||
348 | else | ||
349 | gmx_tx_thresh.s.cnt = 0x100 / 4; | ||
350 | } | ||
351 | /* | ||
352 | * SPI and XAUI can have lots of ports but the GMX hardware | ||
353 | * only ever has a max of 4. | ||
354 | */ | ||
355 | if (num_ports > 4) | ||
356 | num_ports = 4; | ||
357 | for (index = 0; index < num_ports; index++) | ||
358 | cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), | ||
359 | gmx_tx_thresh.u64); | ||
360 | |||
361 | return 0; | ||
362 | } | ||
363 | |||
364 | /** | ||
365 | * Returns the IPD/PKO port number for a port on teh given | ||
366 | * interface. | ||
367 | * | ||
368 | * @interface: Interface to use | ||
369 | * @port: Port on the interface | ||
370 | * | ||
371 | * Returns IPD/PKO port number | ||
372 | */ | ||
373 | int cvmx_helper_get_ipd_port(int interface, int port) | ||
374 | { | ||
375 | switch (interface) { | ||
376 | case 0: | ||
377 | return port; | ||
378 | case 1: | ||
379 | return port + 16; | ||
380 | case 2: | ||
381 | return port + 32; | ||
382 | case 3: | ||
383 | return port + 36; | ||
384 | } | ||
385 | return -1; | ||
386 | } | ||
387 | |||
388 | /** | ||
389 | * Returns the interface number for an IPD/PKO port number. | ||
390 | * | ||
391 | * @ipd_port: IPD/PKO port number | ||
392 | * | ||
393 | * Returns Interface number | ||
394 | */ | ||
395 | int cvmx_helper_get_interface_num(int ipd_port) | ||
396 | { | ||
397 | if (ipd_port < 16) | ||
398 | return 0; | ||
399 | else if (ipd_port < 32) | ||
400 | return 1; | ||
401 | else if (ipd_port < 36) | ||
402 | return 2; | ||
403 | else if (ipd_port < 40) | ||
404 | return 3; | ||
405 | else | ||
406 | cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD " | ||
407 | "port number\n"); | ||
408 | |||
409 | return -1; | ||
410 | } | ||
411 | |||
412 | /** | ||
413 | * Returns the interface index number for an IPD/PKO port | ||
414 | * number. | ||
415 | * | ||
416 | * @ipd_port: IPD/PKO port number | ||
417 | * | ||
418 | * Returns Interface index number | ||
419 | */ | ||
420 | int cvmx_helper_get_interface_index_num(int ipd_port) | ||
421 | { | ||
422 | if (ipd_port < 32) | ||
423 | return ipd_port & 15; | ||
424 | else if (ipd_port < 36) | ||
425 | return ipd_port & 3; | ||
426 | else if (ipd_port < 40) | ||
427 | return ipd_port & 3; | ||
428 | else | ||
429 | cvmx_dprintf("cvmx_helper_get_interface_index_num: " | ||
430 | "Illegal IPD port number\n"); | ||
431 | |||
432 | return -1; | ||
433 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/drivers/staging/octeon/cvmx-helper-util.h new file mode 100644 index 000000000000..6a6e52fc22c1 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-util.h | |||
@@ -0,0 +1,215 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * | ||
30 | * Small helper utilities. | ||
31 | * | ||
32 | */ | ||
33 | |||
34 | #ifndef __CVMX_HELPER_UTIL_H__ | ||
35 | #define __CVMX_HELPER_UTIL_H__ | ||
36 | |||
37 | /** | ||
38 | * Convert a interface mode into a human readable string | ||
39 | * | ||
40 | * @mode: Mode to convert | ||
41 | * | ||
42 | * Returns String | ||
43 | */ | ||
44 | extern const char | ||
45 | *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode); | ||
46 | |||
47 | /** | ||
48 | * Debug routine to dump the packet structure to the console | ||
49 | * | ||
50 | * @work: Work queue entry containing the packet to dump | ||
51 | * Returns | ||
52 | */ | ||
53 | extern int cvmx_helper_dump_packet(cvmx_wqe_t *work); | ||
54 | |||
55 | /** | ||
56 | * Setup Random Early Drop on a specific input queue | ||
57 | * | ||
58 | * @queue: Input queue to setup RED on (0-7) | ||
59 | * @pass_thresh: | ||
60 | * Packets will begin slowly dropping when there are less than | ||
61 | * this many packet buffers free in FPA 0. | ||
62 | * @drop_thresh: | ||
63 | * All incomming packets will be dropped when there are less | ||
64 | * than this many free packet buffers in FPA 0. | ||
65 | * Returns Zero on success. Negative on failure | ||
66 | */ | ||
67 | extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh, | ||
68 | int drop_thresh); | ||
69 | |||
70 | /** | ||
71 | * Setup Random Early Drop to automatically begin dropping packets. | ||
72 | * | ||
73 | * @pass_thresh: | ||
74 | * Packets will begin slowly dropping when there are less than | ||
75 | * this many packet buffers free in FPA 0. | ||
76 | * @drop_thresh: | ||
77 | * All incomming packets will be dropped when there are less | ||
78 | * than this many free packet buffers in FPA 0. | ||
79 | * Returns Zero on success. Negative on failure | ||
80 | */ | ||
81 | extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh); | ||
82 | |||
83 | /** | ||
84 | * Get the version of the CVMX libraries. | ||
85 | * | ||
86 | * Returns Version string. Note this buffer is allocated statically | ||
87 | * and will be shared by all callers. | ||
88 | */ | ||
89 | extern const char *cvmx_helper_get_version(void); | ||
90 | |||
91 | /** | ||
92 | * Setup the common GMX settings that determine the number of | ||
93 | * ports. These setting apply to almost all configurations of all | ||
94 | * chips. | ||
95 | * | ||
96 | * @interface: Interface to configure | ||
97 | * @num_ports: Number of ports on the interface | ||
98 | * | ||
99 | * Returns Zero on success, negative on failure | ||
100 | */ | ||
101 | extern int __cvmx_helper_setup_gmx(int interface, int num_ports); | ||
102 | |||
103 | /** | ||
104 | * Returns the IPD/PKO port number for a port on the given | ||
105 | * interface. | ||
106 | * | ||
107 | * @interface: Interface to use | ||
108 | * @port: Port on the interface | ||
109 | * | ||
110 | * Returns IPD/PKO port number | ||
111 | */ | ||
112 | extern int cvmx_helper_get_ipd_port(int interface, int port); | ||
113 | |||
114 | /** | ||
115 | * Returns the IPD/PKO port number for the first port on the given | ||
116 | * interface. | ||
117 | * | ||
118 | * @interface: Interface to use | ||
119 | * | ||
120 | * Returns IPD/PKO port number | ||
121 | */ | ||
122 | static inline int cvmx_helper_get_first_ipd_port(int interface) | ||
123 | { | ||
124 | return cvmx_helper_get_ipd_port(interface, 0); | ||
125 | } | ||
126 | |||
127 | /** | ||
128 | * Returns the IPD/PKO port number for the last port on the given | ||
129 | * interface. | ||
130 | * | ||
131 | * @interface: Interface to use | ||
132 | * | ||
133 | * Returns IPD/PKO port number | ||
134 | */ | ||
135 | static inline int cvmx_helper_get_last_ipd_port(int interface) | ||
136 | { | ||
137 | extern int cvmx_helper_ports_on_interface(int interface); | ||
138 | |||
139 | return cvmx_helper_get_first_ipd_port(interface) + | ||
140 | cvmx_helper_ports_on_interface(interface) - 1; | ||
141 | } | ||
142 | |||
143 | /** | ||
144 | * Free the packet buffers contained in a work queue entry. | ||
145 | * The work queue entry is not freed. | ||
146 | * | ||
147 | * @work: Work queue entry with packet to free | ||
148 | */ | ||
149 | static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work) | ||
150 | { | ||
151 | uint64_t number_buffers; | ||
152 | union cvmx_buf_ptr buffer_ptr; | ||
153 | union cvmx_buf_ptr next_buffer_ptr; | ||
154 | uint64_t start_of_buffer; | ||
155 | |||
156 | number_buffers = work->word2.s.bufs; | ||
157 | if (number_buffers == 0) | ||
158 | return; | ||
159 | buffer_ptr = work->packet_ptr; | ||
160 | |||
161 | /* | ||
162 | * Since the number of buffers is not zero, we know this is | ||
163 | * not a dynamic short packet. We need to check if it is a | ||
164 | * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is | ||
165 | * true, we need to free all buffers except for the first | ||
166 | * one. The caller doesn't expect their WQE pointer to be | ||
167 | * freed | ||
168 | */ | ||
169 | start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; | ||
170 | if (cvmx_ptr_to_phys(work) == start_of_buffer) { | ||
171 | next_buffer_ptr = | ||
172 | *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); | ||
173 | buffer_ptr = next_buffer_ptr; | ||
174 | number_buffers--; | ||
175 | } | ||
176 | |||
177 | while (number_buffers--) { | ||
178 | /* | ||
179 | * Remember the back pointer is in cache lines, not | ||
180 | * 64bit words | ||
181 | */ | ||
182 | start_of_buffer = | ||
183 | ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; | ||
184 | /* | ||
185 | * Read pointer to next buffer before we free the | ||
186 | * current buffer. | ||
187 | */ | ||
188 | next_buffer_ptr = | ||
189 | *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); | ||
190 | cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer), | ||
191 | buffer_ptr.s.pool, 0); | ||
192 | buffer_ptr = next_buffer_ptr; | ||
193 | } | ||
194 | } | ||
195 | |||
196 | /** | ||
197 | * Returns the interface number for an IPD/PKO port number. | ||
198 | * | ||
199 | * @ipd_port: IPD/PKO port number | ||
200 | * | ||
201 | * Returns Interface number | ||
202 | */ | ||
203 | extern int cvmx_helper_get_interface_num(int ipd_port); | ||
204 | |||
205 | /** | ||
206 | * Returns the interface index number for an IPD/PKO port | ||
207 | * number. | ||
208 | * | ||
209 | * @ipd_port: IPD/PKO port number | ||
210 | * | ||
211 | * Returns Interface index number | ||
212 | */ | ||
213 | extern int cvmx_helper_get_interface_index_num(int ipd_port); | ||
214 | |||
215 | #endif /* __CVMX_HELPER_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/drivers/staging/octeon/cvmx-helper-xaui.c new file mode 100644 index 000000000000..a11e6769e234 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-xaui.c | |||
@@ -0,0 +1,348 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Functions for XAUI initialization, configuration, | ||
30 | * and monitoring. | ||
31 | * | ||
32 | */ | ||
33 | |||
34 | #include <asm/octeon/octeon.h> | ||
35 | |||
36 | #include "cvmx-config.h" | ||
37 | |||
38 | #include "cvmx-helper.h" | ||
39 | |||
40 | #include "cvmx-pko-defs.h" | ||
41 | #include "cvmx-gmxx-defs.h" | ||
42 | #include "cvmx-pcsxx-defs.h" | ||
43 | |||
44 | void __cvmx_interrupt_gmxx_enable(int interface); | ||
45 | void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); | ||
46 | void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); | ||
47 | /** | ||
48 | * Probe a XAUI interface and determine the number of ports | ||
49 | * connected to it. The XAUI interface should still be down | ||
50 | * after this call. | ||
51 | * | ||
52 | * @interface: Interface to probe | ||
53 | * | ||
54 | * Returns Number of ports on the interface. Zero to disable. | ||
55 | */ | ||
56 | int __cvmx_helper_xaui_probe(int interface) | ||
57 | { | ||
58 | int i; | ||
59 | union cvmx_gmxx_hg2_control gmx_hg2_control; | ||
60 | union cvmx_gmxx_inf_mode mode; | ||
61 | |||
62 | /* | ||
63 | * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the | ||
64 | * interface needs to be enabled before IPD otherwise per port | ||
65 | * backpressure may not work properly. | ||
66 | */ | ||
67 | mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); | ||
68 | mode.s.en = 1; | ||
69 | cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); | ||
70 | |||
71 | __cvmx_helper_setup_gmx(interface, 1); | ||
72 | |||
73 | /* | ||
74 | * Setup PKO to support 16 ports for HiGig2 virtual | ||
75 | * ports. We're pointing all of the PKO packet ports for this | ||
76 | * interface to the XAUI. This allows us to use HiGig2 | ||
77 | * backpressure per port. | ||
78 | */ | ||
79 | for (i = 0; i < 16; i++) { | ||
80 | union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs; | ||
81 | pko_mem_port_ptrs.u64 = 0; | ||
82 | /* | ||
83 | * We set each PKO port to have equal priority in a | ||
84 | * round robin fashion. | ||
85 | */ | ||
86 | pko_mem_port_ptrs.s.static_p = 0; | ||
87 | pko_mem_port_ptrs.s.qos_mask = 0xff; | ||
88 | /* All PKO ports map to the same XAUI hardware port */ | ||
89 | pko_mem_port_ptrs.s.eid = interface * 4; | ||
90 | pko_mem_port_ptrs.s.pid = interface * 16 + i; | ||
91 | cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); | ||
92 | } | ||
93 | |||
94 | /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ | ||
95 | gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); | ||
96 | if (gmx_hg2_control.s.hg2tx_en) | ||
97 | return 16; | ||
98 | else | ||
99 | return 1; | ||
100 | } | ||
101 | |||
102 | /** | ||
103 | * Bringup and enable a XAUI interface. After this call packet | ||
104 | * I/O should be fully functional. This is called with IPD | ||
105 | * enabled but PKO disabled. | ||
106 | * | ||
107 | * @interface: Interface to bring up | ||
108 | * | ||
109 | * Returns Zero on success, negative on failure | ||
110 | */ | ||
111 | int __cvmx_helper_xaui_enable(int interface) | ||
112 | { | ||
113 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
114 | union cvmx_pcsxx_control1_reg xauiCtl; | ||
115 | union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl; | ||
116 | union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl; | ||
117 | union cvmx_gmxx_rxx_int_en gmx_rx_int_en; | ||
118 | union cvmx_gmxx_tx_int_en gmx_tx_int_en; | ||
119 | union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; | ||
120 | |||
121 | /* (1) Interface has already been enabled. */ | ||
122 | |||
123 | /* (2) Disable GMX. */ | ||
124 | xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface)); | ||
125 | xauiMiscCtl.s.gmxeno = 1; | ||
126 | cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); | ||
127 | |||
128 | /* (3) Disable GMX and PCSX interrupts. */ | ||
129 | gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface)); | ||
130 | cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); | ||
131 | gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface)); | ||
132 | cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); | ||
133 | pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface)); | ||
134 | cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); | ||
135 | |||
136 | /* (4) Bring up the PCSX and GMX reconciliation layer. */ | ||
137 | /* (4)a Set polarity and lane swapping. */ | ||
138 | /* (4)b */ | ||
139 | gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); | ||
140 | /* Enable better IFG packing and improves performance */ | ||
141 | gmxXauiTxCtl.s.dic_en = 1; | ||
142 | gmxXauiTxCtl.s.uni_en = 0; | ||
143 | cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64); | ||
144 | |||
145 | /* (4)c Aply reset sequence */ | ||
146 | xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); | ||
147 | xauiCtl.s.lo_pwr = 0; | ||
148 | xauiCtl.s.reset = 1; | ||
149 | cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64); | ||
150 | |||
151 | /* Wait for PCS to come out of reset */ | ||
152 | if (CVMX_WAIT_FOR_FIELD64 | ||
153 | (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg, | ||
154 | reset, ==, 0, 10000)) | ||
155 | return -1; | ||
156 | /* Wait for PCS to be aligned */ | ||
157 | if (CVMX_WAIT_FOR_FIELD64 | ||
158 | (CVMX_PCSXX_10GBX_STATUS_REG(interface), | ||
159 | union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000)) | ||
160 | return -1; | ||
161 | /* Wait for RX to be ready */ | ||
162 | if (CVMX_WAIT_FOR_FIELD64 | ||
163 | (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl, | ||
164 | status, ==, 0, 10000)) | ||
165 | return -1; | ||
166 | |||
167 | /* (6) Configure GMX */ | ||
168 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); | ||
169 | gmx_cfg.s.en = 0; | ||
170 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); | ||
171 | |||
172 | /* Wait for GMX RX to be idle */ | ||
173 | if (CVMX_WAIT_FOR_FIELD64 | ||
174 | (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, | ||
175 | rx_idle, ==, 1, 10000)) | ||
176 | return -1; | ||
177 | /* Wait for GMX TX to be idle */ | ||
178 | if (CVMX_WAIT_FOR_FIELD64 | ||
179 | (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, | ||
180 | tx_idle, ==, 1, 10000)) | ||
181 | return -1; | ||
182 | |||
183 | /* GMX configure */ | ||
184 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); | ||
185 | gmx_cfg.s.speed = 1; | ||
186 | gmx_cfg.s.speed_msb = 0; | ||
187 | gmx_cfg.s.slottime = 1; | ||
188 | cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1); | ||
189 | cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512); | ||
190 | cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192); | ||
191 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); | ||
192 | |||
193 | /* (7) Clear out any error state */ | ||
194 | cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface), | ||
195 | cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface))); | ||
196 | cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), | ||
197 | cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface))); | ||
198 | cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), | ||
199 | cvmx_read_csr(CVMX_PCSXX_INT_REG(interface))); | ||
200 | |||
201 | /* Wait for receive link */ | ||
202 | if (CVMX_WAIT_FOR_FIELD64 | ||
203 | (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg, | ||
204 | rcv_lnk, ==, 1, 10000)) | ||
205 | return -1; | ||
206 | if (CVMX_WAIT_FOR_FIELD64 | ||
207 | (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, | ||
208 | xmtflt, ==, 0, 10000)) | ||
209 | return -1; | ||
210 | if (CVMX_WAIT_FOR_FIELD64 | ||
211 | (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, | ||
212 | rcvflt, ==, 0, 10000)) | ||
213 | return -1; | ||
214 | |||
215 | cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64); | ||
216 | cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); | ||
217 | cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64); | ||
218 | |||
219 | cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0)); | ||
220 | |||
221 | /* (8) Enable packet reception */ | ||
222 | xauiMiscCtl.s.gmxeno = 0; | ||
223 | cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); | ||
224 | |||
225 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); | ||
226 | gmx_cfg.s.en = 1; | ||
227 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); | ||
228 | |||
229 | __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface); | ||
230 | __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface); | ||
231 | __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface); | ||
232 | __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface); | ||
233 | __cvmx_interrupt_pcsxx_int_en_reg_enable(interface); | ||
234 | __cvmx_interrupt_gmxx_enable(interface); | ||
235 | |||
236 | return 0; | ||
237 | } | ||
238 | |||
239 | /** | ||
240 | * Return the link state of an IPD/PKO port as returned by | ||
241 | * auto negotiation. The result of this function may not match | ||
242 | * Octeon's link config if auto negotiation has changed since | ||
243 | * the last call to cvmx_helper_link_set(). | ||
244 | * | ||
245 | * @ipd_port: IPD/PKO port to query | ||
246 | * | ||
247 | * Returns Link state | ||
248 | */ | ||
249 | cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port) | ||
250 | { | ||
251 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
252 | union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; | ||
253 | union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; | ||
254 | union cvmx_pcsxx_status1_reg pcsxx_status1_reg; | ||
255 | cvmx_helper_link_info_t result; | ||
256 | |||
257 | gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); | ||
258 | gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); | ||
259 | pcsxx_status1_reg.u64 = | ||
260 | cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface)); | ||
261 | result.u64 = 0; | ||
262 | |||
263 | /* Only return a link if both RX and TX are happy */ | ||
264 | if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) && | ||
265 | (pcsxx_status1_reg.s.rcv_lnk == 1)) { | ||
266 | result.s.link_up = 1; | ||
267 | result.s.full_duplex = 1; | ||
268 | result.s.speed = 10000; | ||
269 | } else { | ||
270 | /* Disable GMX and PCSX interrupts. */ | ||
271 | cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); | ||
272 | cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); | ||
273 | cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); | ||
274 | } | ||
275 | return result; | ||
276 | } | ||
277 | |||
278 | /** | ||
279 | * Configure an IPD/PKO port for the specified link state. This | ||
280 | * function does not influence auto negotiation at the PHY level. | ||
281 | * The passed link state must always match the link state returned | ||
282 | * by cvmx_helper_link_get(). It is normally best to use | ||
283 | * cvmx_helper_link_autoconf() instead. | ||
284 | * | ||
285 | * @ipd_port: IPD/PKO port to configure | ||
286 | * @link_info: The new link state | ||
287 | * | ||
288 | * Returns Zero on success, negative on failure | ||
289 | */ | ||
290 | int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info) | ||
291 | { | ||
292 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
293 | union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; | ||
294 | union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; | ||
295 | |||
296 | gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); | ||
297 | gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); | ||
298 | |||
299 | /* If the link shouldn't be up, then just return */ | ||
300 | if (!link_info.s.link_up) | ||
301 | return 0; | ||
302 | |||
303 | /* Do nothing if both RX and TX are happy */ | ||
304 | if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0)) | ||
305 | return 0; | ||
306 | |||
307 | /* Bring the link up */ | ||
308 | return __cvmx_helper_xaui_enable(interface); | ||
309 | } | ||
310 | |||
311 | /** | ||
312 | * Configure a port for internal and/or external loopback. Internal loopback | ||
313 | * causes packets sent by the port to be received by Octeon. External loopback | ||
314 | * causes packets received from the wire to sent out again. | ||
315 | * | ||
316 | * @ipd_port: IPD/PKO port to loopback. | ||
317 | * @enable_internal: | ||
318 | * Non zero if you want internal loopback | ||
319 | * @enable_external: | ||
320 | * Non zero if you want external loopback | ||
321 | * | ||
322 | * Returns Zero on success, negative on failure. | ||
323 | */ | ||
324 | extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, | ||
325 | int enable_internal, | ||
326 | int enable_external) | ||
327 | { | ||
328 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
329 | union cvmx_pcsxx_control1_reg pcsxx_control1_reg; | ||
330 | union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback; | ||
331 | |||
332 | /* Set the internal loop */ | ||
333 | pcsxx_control1_reg.u64 = | ||
334 | cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); | ||
335 | pcsxx_control1_reg.s.loopbck1 = enable_internal; | ||
336 | cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), | ||
337 | pcsxx_control1_reg.u64); | ||
338 | |||
339 | /* Set the external loop */ | ||
340 | gmxx_xaui_ext_loopback.u64 = | ||
341 | cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface)); | ||
342 | gmxx_xaui_ext_loopback.s.en = enable_external; | ||
343 | cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface), | ||
344 | gmxx_xaui_ext_loopback.u64); | ||
345 | |||
346 | /* Take the link through a reset */ | ||
347 | return __cvmx_helper_xaui_enable(interface); | ||
348 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/drivers/staging/octeon/cvmx-helper-xaui.h new file mode 100644 index 000000000000..4b4db2f93cd4 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-xaui.h | |||
@@ -0,0 +1,103 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * | ||
31 | * Functions for XAUI initialization, configuration, | ||
32 | * and monitoring. | ||
33 | * | ||
34 | */ | ||
35 | #ifndef __CVMX_HELPER_XAUI_H__ | ||
36 | #define __CVMX_HELPER_XAUI_H__ | ||
37 | |||
38 | /** | ||
39 | * Probe a XAUI interface and determine the number of ports | ||
40 | * connected to it. The XAUI interface should still be down | ||
41 | * after this call. | ||
42 | * | ||
43 | * @interface: Interface to probe | ||
44 | * | ||
45 | * Returns Number of ports on the interface. Zero to disable. | ||
46 | */ | ||
47 | extern int __cvmx_helper_xaui_probe(int interface); | ||
48 | |||
49 | /** | ||
50 | * Bringup and enable a XAUI interface. After this call packet | ||
51 | * I/O should be fully functional. This is called with IPD | ||
52 | * enabled but PKO disabled. | ||
53 | * | ||
54 | * @interface: Interface to bring up | ||
55 | * | ||
56 | * Returns Zero on success, negative on failure | ||
57 | */ | ||
58 | extern int __cvmx_helper_xaui_enable(int interface); | ||
59 | |||
60 | /** | ||
61 | * Return the link state of an IPD/PKO port as returned by | ||
62 | * auto negotiation. The result of this function may not match | ||
63 | * Octeon's link config if auto negotiation has changed since | ||
64 | * the last call to cvmx_helper_link_set(). | ||
65 | * | ||
66 | * @ipd_port: IPD/PKO port to query | ||
67 | * | ||
68 | * Returns Link state | ||
69 | */ | ||
70 | extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port); | ||
71 | |||
72 | /** | ||
73 | * Configure an IPD/PKO port for the specified link state. This | ||
74 | * function does not influence auto negotiation at the PHY level. | ||
75 | * The passed link state must always match the link state returned | ||
76 | * by cvmx_helper_link_get(). It is normally best to use | ||
77 | * cvmx_helper_link_autoconf() instead. | ||
78 | * | ||
79 | * @ipd_port: IPD/PKO port to configure | ||
80 | * @link_info: The new link state | ||
81 | * | ||
82 | * Returns Zero on success, negative on failure | ||
83 | */ | ||
84 | extern int __cvmx_helper_xaui_link_set(int ipd_port, | ||
85 | cvmx_helper_link_info_t link_info); | ||
86 | |||
87 | /** | ||
88 | * Configure a port for internal and/or external loopback. Internal loopback | ||
89 | * causes packets sent by the port to be received by Octeon. External loopback | ||
90 | * causes packets received from the wire to sent out again. | ||
91 | * | ||
92 | * @ipd_port: IPD/PKO port to loopback. | ||
93 | * @enable_internal: | ||
94 | * Non zero if you want internal loopback | ||
95 | * @enable_external: | ||
96 | * Non zero if you want external loopback | ||
97 | * | ||
98 | * Returns Zero on success, negative on failure. | ||
99 | */ | ||
100 | extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, | ||
101 | int enable_internal, | ||
102 | int enable_external); | ||
103 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-helper.c b/drivers/staging/octeon/cvmx-helper.c new file mode 100644 index 000000000000..591506643d02 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper.c | |||
@@ -0,0 +1,1058 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * | ||
30 | * Helper functions for common, but complicated tasks. | ||
31 | * | ||
32 | */ | ||
33 | #include <asm/octeon/octeon.h> | ||
34 | |||
35 | #include "cvmx-config.h" | ||
36 | |||
37 | #include "cvmx-fpa.h" | ||
38 | #include "cvmx-pip.h" | ||
39 | #include "cvmx-pko.h" | ||
40 | #include "cvmx-ipd.h" | ||
41 | #include "cvmx-spi.h" | ||
42 | #include "cvmx-helper.h" | ||
43 | #include "cvmx-helper-board.h" | ||
44 | |||
45 | #include "cvmx-pip-defs.h" | ||
46 | #include "cvmx-smix-defs.h" | ||
47 | #include "cvmx-asxx-defs.h" | ||
48 | |||
49 | /** | ||
50 | * cvmx_override_pko_queue_priority(int ipd_port, uint64_t | ||
51 | * priorities[16]) is a function pointer. It is meant to allow | ||
52 | * customization of the PKO queue priorities based on the port | ||
53 | * number. Users should set this pointer to a function before | ||
54 | * calling any cvmx-helper operations. | ||
55 | */ | ||
56 | void (*cvmx_override_pko_queue_priority) (int pko_port, | ||
57 | uint64_t priorities[16]); | ||
58 | |||
59 | /** | ||
60 | * cvmx_override_ipd_port_setup(int ipd_port) is a function | ||
61 | * pointer. It is meant to allow customization of the IPD port | ||
62 | * setup before packet input/output comes online. It is called | ||
63 | * after cvmx-helper does the default IPD configuration, but | ||
64 | * before IPD is enabled. Users should set this pointer to a | ||
65 | * function before calling any cvmx-helper operations. | ||
66 | */ | ||
67 | void (*cvmx_override_ipd_port_setup) (int ipd_port); | ||
68 | |||
69 | /* Port count per interface */ | ||
70 | static int interface_port_count[4] = { 0, 0, 0, 0 }; | ||
71 | |||
72 | /* Port last configured link info index by IPD/PKO port */ | ||
73 | static cvmx_helper_link_info_t | ||
74 | port_link_info[CVMX_PIP_NUM_INPUT_PORTS]; | ||
75 | |||
76 | /** | ||
77 | * Return the number of interfaces the chip has. Each interface | ||
78 | * may have multiple ports. Most chips support two interfaces, | ||
79 | * but the CNX0XX and CNX1XX are exceptions. These only support | ||
80 | * one interface. | ||
81 | * | ||
82 | * Returns Number of interfaces on chip | ||
83 | */ | ||
84 | int cvmx_helper_get_number_of_interfaces(void) | ||
85 | { | ||
86 | if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) | ||
87 | return 4; | ||
88 | else | ||
89 | return 3; | ||
90 | } | ||
91 | |||
92 | /** | ||
93 | * Return the number of ports on an interface. Depending on the | ||
94 | * chip and configuration, this can be 1-16. A value of 0 | ||
95 | * specifies that the interface doesn't exist or isn't usable. | ||
96 | * | ||
97 | * @interface: Interface to get the port count for | ||
98 | * | ||
99 | * Returns Number of ports on interface. Can be Zero. | ||
100 | */ | ||
101 | int cvmx_helper_ports_on_interface(int interface) | ||
102 | { | ||
103 | return interface_port_count[interface]; | ||
104 | } | ||
105 | |||
106 | /** | ||
107 | * Get the operating mode of an interface. Depending on the Octeon | ||
108 | * chip and configuration, this function returns an enumeration | ||
109 | * of the type of packet I/O supported by an interface. | ||
110 | * | ||
111 | * @interface: Interface to probe | ||
112 | * | ||
113 | * Returns Mode of the interface. Unknown or unsupported interfaces return | ||
114 | * DISABLED. | ||
115 | */ | ||
116 | cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) | ||
117 | { | ||
118 | union cvmx_gmxx_inf_mode mode; | ||
119 | if (interface == 2) | ||
120 | return CVMX_HELPER_INTERFACE_MODE_NPI; | ||
121 | |||
122 | if (interface == 3) { | ||
123 | if (OCTEON_IS_MODEL(OCTEON_CN56XX) | ||
124 | || OCTEON_IS_MODEL(OCTEON_CN52XX)) | ||
125 | return CVMX_HELPER_INTERFACE_MODE_LOOP; | ||
126 | else | ||
127 | return CVMX_HELPER_INTERFACE_MODE_DISABLED; | ||
128 | } | ||
129 | |||
130 | if (interface == 0 | ||
131 | && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5 | ||
132 | && cvmx_sysinfo_get()->board_rev_major == 1) { | ||
133 | /* | ||
134 | * Lie about interface type of CN3005 board. This | ||
135 | * board has a switch on port 1 like the other | ||
136 | * evaluation boards, but it is connected over RGMII | ||
137 | * instead of GMII. Report GMII mode so that the | ||
138 | * speed is forced to 1 Gbit full duplex. Other than | ||
139 | * some initial configuration (which does not use the | ||
140 | * output of this function) there is no difference in | ||
141 | * setup between GMII and RGMII modes. | ||
142 | */ | ||
143 | return CVMX_HELPER_INTERFACE_MODE_GMII; | ||
144 | } | ||
145 | |||
146 | /* Interface 1 is always disabled on CN31XX and CN30XX */ | ||
147 | if ((interface == 1) | ||
148 | && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) | ||
149 | || OCTEON_IS_MODEL(OCTEON_CN50XX) | ||
150 | || OCTEON_IS_MODEL(OCTEON_CN52XX))) | ||
151 | return CVMX_HELPER_INTERFACE_MODE_DISABLED; | ||
152 | |||
153 | mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); | ||
154 | |||
155 | if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { | ||
156 | switch (mode.cn56xx.mode) { | ||
157 | case 0: | ||
158 | return CVMX_HELPER_INTERFACE_MODE_DISABLED; | ||
159 | case 1: | ||
160 | return CVMX_HELPER_INTERFACE_MODE_XAUI; | ||
161 | case 2: | ||
162 | return CVMX_HELPER_INTERFACE_MODE_SGMII; | ||
163 | case 3: | ||
164 | return CVMX_HELPER_INTERFACE_MODE_PICMG; | ||
165 | default: | ||
166 | return CVMX_HELPER_INTERFACE_MODE_DISABLED; | ||
167 | } | ||
168 | } else { | ||
169 | if (!mode.s.en) | ||
170 | return CVMX_HELPER_INTERFACE_MODE_DISABLED; | ||
171 | |||
172 | if (mode.s.type) { | ||
173 | if (OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
174 | || OCTEON_IS_MODEL(OCTEON_CN58XX)) | ||
175 | return CVMX_HELPER_INTERFACE_MODE_SPI; | ||
176 | else | ||
177 | return CVMX_HELPER_INTERFACE_MODE_GMII; | ||
178 | } else | ||
179 | return CVMX_HELPER_INTERFACE_MODE_RGMII; | ||
180 | } | ||
181 | } | ||
182 | |||
183 | /** | ||
184 | * Configure the IPD/PIP tagging and QoS options for a specific | ||
185 | * port. This function determines the POW work queue entry | ||
186 | * contents for a port. The setup performed here is controlled by | ||
187 | * the defines in executive-config.h. | ||
188 | * | ||
189 | * @ipd_port: Port to configure. This follows the IPD numbering, not the | ||
190 | * per interface numbering | ||
191 | * | ||
192 | * Returns Zero on success, negative on failure | ||
193 | */ | ||
194 | static int __cvmx_helper_port_setup_ipd(int ipd_port) | ||
195 | { | ||
196 | union cvmx_pip_prt_cfgx port_config; | ||
197 | union cvmx_pip_prt_tagx tag_config; | ||
198 | |||
199 | port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); | ||
200 | tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port)); | ||
201 | |||
202 | /* Have each port go to a different POW queue */ | ||
203 | port_config.s.qos = ipd_port & 0x7; | ||
204 | |||
205 | /* Process the headers and place the IP header in the work queue */ | ||
206 | port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE; | ||
207 | |||
208 | tag_config.s.ip6_src_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP; | ||
209 | tag_config.s.ip6_dst_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_IP; | ||
210 | tag_config.s.ip6_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT; | ||
211 | tag_config.s.ip6_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT; | ||
212 | tag_config.s.ip6_nxth_flag = CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER; | ||
213 | tag_config.s.ip4_src_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP; | ||
214 | tag_config.s.ip4_dst_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_IP; | ||
215 | tag_config.s.ip4_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT; | ||
216 | tag_config.s.ip4_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT; | ||
217 | tag_config.s.ip4_pctl_flag = CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL; | ||
218 | tag_config.s.inc_prt_flag = CVMX_HELPER_INPUT_TAG_INPUT_PORT; | ||
219 | tag_config.s.tcp6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; | ||
220 | tag_config.s.tcp4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; | ||
221 | tag_config.s.ip6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; | ||
222 | tag_config.s.ip4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; | ||
223 | tag_config.s.non_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; | ||
224 | /* Put all packets in group 0. Other groups can be used by the app */ | ||
225 | tag_config.s.grp = 0; | ||
226 | |||
227 | cvmx_pip_config_port(ipd_port, port_config, tag_config); | ||
228 | |||
229 | /* Give the user a chance to override our setting for each port */ | ||
230 | if (cvmx_override_ipd_port_setup) | ||
231 | cvmx_override_ipd_port_setup(ipd_port); | ||
232 | |||
233 | return 0; | ||
234 | } | ||
235 | |||
236 | /** | ||
237 | * This function probes an interface to determine the actual | ||
238 | * number of hardware ports connected to it. It doesn't setup the | ||
239 | * ports or enable them. The main goal here is to set the global | ||
240 | * interface_port_count[interface] correctly. Hardware setup of the | ||
241 | * ports will be performed later. | ||
242 | * | ||
243 | * @interface: Interface to probe | ||
244 | * | ||
245 | * Returns Zero on success, negative on failure | ||
246 | */ | ||
247 | int cvmx_helper_interface_probe(int interface) | ||
248 | { | ||
249 | /* At this stage in the game we don't want packets to be moving yet. | ||
250 | The following probe calls should perform hardware setup | ||
251 | needed to determine port counts. Receive must still be disabled */ | ||
252 | switch (cvmx_helper_interface_get_mode(interface)) { | ||
253 | /* These types don't support ports to IPD/PKO */ | ||
254 | case CVMX_HELPER_INTERFACE_MODE_DISABLED: | ||
255 | case CVMX_HELPER_INTERFACE_MODE_PCIE: | ||
256 | interface_port_count[interface] = 0; | ||
257 | break; | ||
258 | /* XAUI is a single high speed port */ | ||
259 | case CVMX_HELPER_INTERFACE_MODE_XAUI: | ||
260 | interface_port_count[interface] = | ||
261 | __cvmx_helper_xaui_probe(interface); | ||
262 | break; | ||
263 | /* | ||
264 | * RGMII/GMII/MII are all treated about the same. Most | ||
265 | * functions refer to these ports as RGMII. | ||
266 | */ | ||
267 | case CVMX_HELPER_INTERFACE_MODE_RGMII: | ||
268 | case CVMX_HELPER_INTERFACE_MODE_GMII: | ||
269 | interface_port_count[interface] = | ||
270 | __cvmx_helper_rgmii_probe(interface); | ||
271 | break; | ||
272 | /* | ||
273 | * SPI4 can have 1-16 ports depending on the device at | ||
274 | * the other end. | ||
275 | */ | ||
276 | case CVMX_HELPER_INTERFACE_MODE_SPI: | ||
277 | interface_port_count[interface] = | ||
278 | __cvmx_helper_spi_probe(interface); | ||
279 | break; | ||
280 | /* | ||
281 | * SGMII can have 1-4 ports depending on how many are | ||
282 | * hooked up. | ||
283 | */ | ||
284 | case CVMX_HELPER_INTERFACE_MODE_SGMII: | ||
285 | case CVMX_HELPER_INTERFACE_MODE_PICMG: | ||
286 | interface_port_count[interface] = | ||
287 | __cvmx_helper_sgmii_probe(interface); | ||
288 | break; | ||
289 | /* PCI target Network Packet Interface */ | ||
290 | case CVMX_HELPER_INTERFACE_MODE_NPI: | ||
291 | interface_port_count[interface] = | ||
292 | __cvmx_helper_npi_probe(interface); | ||
293 | break; | ||
294 | /* | ||
295 | * Special loopback only ports. These are not the same | ||
296 | * as other ports in loopback mode. | ||
297 | */ | ||
298 | case CVMX_HELPER_INTERFACE_MODE_LOOP: | ||
299 | interface_port_count[interface] = | ||
300 | __cvmx_helper_loop_probe(interface); | ||
301 | break; | ||
302 | } | ||
303 | |||
304 | interface_port_count[interface] = | ||
305 | __cvmx_helper_board_interface_probe(interface, | ||
306 | interface_port_count | ||
307 | [interface]); | ||
308 | |||
309 | /* Make sure all global variables propagate to other cores */ | ||
310 | CVMX_SYNCWS; | ||
311 | |||
312 | return 0; | ||
313 | } | ||
314 | |||
315 | /** | ||
316 | * Setup the IPD/PIP for the ports on an interface. Packet | ||
317 | * classification and tagging are set for every port on the | ||
318 | * interface. The number of ports on the interface must already | ||
319 | * have been probed. | ||
320 | * | ||
321 | * @interface: Interface to setup IPD/PIP for | ||
322 | * | ||
323 | * Returns Zero on success, negative on failure | ||
324 | */ | ||
325 | static int __cvmx_helper_interface_setup_ipd(int interface) | ||
326 | { | ||
327 | int ipd_port = cvmx_helper_get_ipd_port(interface, 0); | ||
328 | int num_ports = interface_port_count[interface]; | ||
329 | |||
330 | while (num_ports--) { | ||
331 | __cvmx_helper_port_setup_ipd(ipd_port); | ||
332 | ipd_port++; | ||
333 | } | ||
334 | return 0; | ||
335 | } | ||
336 | |||
337 | /** | ||
338 | * Setup global setting for IPD/PIP not related to a specific | ||
339 | * interface or port. This must be called before IPD is enabled. | ||
340 | * | ||
341 | * Returns Zero on success, negative on failure. | ||
342 | */ | ||
343 | static int __cvmx_helper_global_setup_ipd(void) | ||
344 | { | ||
345 | /* Setup the global packet input options */ | ||
346 | cvmx_ipd_config(CVMX_FPA_PACKET_POOL_SIZE / 8, | ||
347 | CVMX_HELPER_FIRST_MBUFF_SKIP / 8, | ||
348 | CVMX_HELPER_NOT_FIRST_MBUFF_SKIP / 8, | ||
349 | /* The +8 is to account for the next ptr */ | ||
350 | (CVMX_HELPER_FIRST_MBUFF_SKIP + 8) / 128, | ||
351 | /* The +8 is to account for the next ptr */ | ||
352 | (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP + 8) / 128, | ||
353 | CVMX_FPA_WQE_POOL, | ||
354 | CVMX_IPD_OPC_MODE_STT, | ||
355 | CVMX_HELPER_ENABLE_BACK_PRESSURE); | ||
356 | return 0; | ||
357 | } | ||
358 | |||
359 | /** | ||
360 | * Setup the PKO for the ports on an interface. The number of | ||
361 | * queues per port and the priority of each PKO output queue | ||
362 | * is set here. PKO must be disabled when this function is called. | ||
363 | * | ||
364 | * @interface: Interface to setup PKO for | ||
365 | * | ||
366 | * Returns Zero on success, negative on failure | ||
367 | */ | ||
368 | static int __cvmx_helper_interface_setup_pko(int interface) | ||
369 | { | ||
370 | /* | ||
371 | * Each packet output queue has an associated priority. The | ||
372 | * higher the priority, the more often it can send a packet. A | ||
373 | * priority of 8 means it can send in all 8 rounds of | ||
374 | * contention. We're going to make each queue one less than | ||
375 | * the last. The vector of priorities has been extended to | ||
376 | * support CN5xxx CPUs, where up to 16 queues can be | ||
377 | * associated to a port. To keep backward compatibility we | ||
378 | * don't change the initial 8 priorities and replicate them in | ||
379 | * the second half. With per-core PKO queues (PKO lockless | ||
380 | * operation) all queues have the same priority. | ||
381 | */ | ||
382 | uint64_t priorities[16] = | ||
383 | { 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1 }; | ||
384 | |||
385 | /* | ||
386 | * Setup the IPD/PIP and PKO for the ports discovered | ||
387 | * above. Here packet classification, tagging and output | ||
388 | * priorities are set. | ||
389 | */ | ||
390 | int ipd_port = cvmx_helper_get_ipd_port(interface, 0); | ||
391 | int num_ports = interface_port_count[interface]; | ||
392 | while (num_ports--) { | ||
393 | /* | ||
394 | * Give the user a chance to override the per queue | ||
395 | * priorities. | ||
396 | */ | ||
397 | if (cvmx_override_pko_queue_priority) | ||
398 | cvmx_override_pko_queue_priority(ipd_port, priorities); | ||
399 | |||
400 | cvmx_pko_config_port(ipd_port, | ||
401 | cvmx_pko_get_base_queue_per_core(ipd_port, | ||
402 | 0), | ||
403 | cvmx_pko_get_num_queues(ipd_port), | ||
404 | priorities); | ||
405 | ipd_port++; | ||
406 | } | ||
407 | return 0; | ||
408 | } | ||
409 | |||
410 | /** | ||
411 | * Setup global setting for PKO not related to a specific | ||
412 | * interface or port. This must be called before PKO is enabled. | ||
413 | * | ||
414 | * Returns Zero on success, negative on failure. | ||
415 | */ | ||
416 | static int __cvmx_helper_global_setup_pko(void) | ||
417 | { | ||
418 | /* | ||
419 | * Disable tagwait FAU timeout. This needs to be done before | ||
420 | * anyone might start packet output using tags. | ||
421 | */ | ||
422 | union cvmx_iob_fau_timeout fau_to; | ||
423 | fau_to.u64 = 0; | ||
424 | fau_to.s.tout_val = 0xfff; | ||
425 | fau_to.s.tout_enb = 0; | ||
426 | cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); | ||
427 | return 0; | ||
428 | } | ||
429 | |||
430 | /** | ||
431 | * Setup global backpressure setting. | ||
432 | * | ||
433 | * Returns Zero on success, negative on failure | ||
434 | */ | ||
435 | static int __cvmx_helper_global_setup_backpressure(void) | ||
436 | { | ||
437 | #if CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE | ||
438 | /* Disable backpressure if configured to do so */ | ||
439 | /* Disable backpressure (pause frame) generation */ | ||
440 | int num_interfaces = cvmx_helper_get_number_of_interfaces(); | ||
441 | int interface; | ||
442 | for (interface = 0; interface < num_interfaces; interface++) { | ||
443 | switch (cvmx_helper_interface_get_mode(interface)) { | ||
444 | case CVMX_HELPER_INTERFACE_MODE_DISABLED: | ||
445 | case CVMX_HELPER_INTERFACE_MODE_PCIE: | ||
446 | case CVMX_HELPER_INTERFACE_MODE_NPI: | ||
447 | case CVMX_HELPER_INTERFACE_MODE_LOOP: | ||
448 | case CVMX_HELPER_INTERFACE_MODE_XAUI: | ||
449 | break; | ||
450 | case CVMX_HELPER_INTERFACE_MODE_RGMII: | ||
451 | case CVMX_HELPER_INTERFACE_MODE_GMII: | ||
452 | case CVMX_HELPER_INTERFACE_MODE_SPI: | ||
453 | case CVMX_HELPER_INTERFACE_MODE_SGMII: | ||
454 | case CVMX_HELPER_INTERFACE_MODE_PICMG: | ||
455 | cvmx_gmx_set_backpressure_override(interface, 0xf); | ||
456 | break; | ||
457 | } | ||
458 | } | ||
459 | #endif | ||
460 | |||
461 | return 0; | ||
462 | } | ||
463 | |||
464 | /** | ||
465 | * Enable packet input/output from the hardware. This function is | ||
466 | * called after all internal setup is complete and IPD is enabled. | ||
467 | * After this function completes, packets will be accepted from the | ||
468 | * hardware ports. PKO should still be disabled to make sure packets | ||
469 | * aren't sent out partially setup hardware. | ||
470 | * | ||
471 | * @interface: Interface to enable | ||
472 | * | ||
473 | * Returns Zero on success, negative on failure | ||
474 | */ | ||
475 | static int __cvmx_helper_packet_hardware_enable(int interface) | ||
476 | { | ||
477 | int result = 0; | ||
478 | switch (cvmx_helper_interface_get_mode(interface)) { | ||
479 | /* These types don't support ports to IPD/PKO */ | ||
480 | case CVMX_HELPER_INTERFACE_MODE_DISABLED: | ||
481 | case CVMX_HELPER_INTERFACE_MODE_PCIE: | ||
482 | /* Nothing to do */ | ||
483 | break; | ||
484 | /* XAUI is a single high speed port */ | ||
485 | case CVMX_HELPER_INTERFACE_MODE_XAUI: | ||
486 | result = __cvmx_helper_xaui_enable(interface); | ||
487 | break; | ||
488 | /* | ||
489 | * RGMII/GMII/MII are all treated about the same. Most | ||
490 | * functions refer to these ports as RGMII | ||
491 | */ | ||
492 | case CVMX_HELPER_INTERFACE_MODE_RGMII: | ||
493 | case CVMX_HELPER_INTERFACE_MODE_GMII: | ||
494 | result = __cvmx_helper_rgmii_enable(interface); | ||
495 | break; | ||
496 | /* | ||
497 | * SPI4 can have 1-16 ports depending on the device at | ||
498 | * the other end | ||
499 | */ | ||
500 | case CVMX_HELPER_INTERFACE_MODE_SPI: | ||
501 | result = __cvmx_helper_spi_enable(interface); | ||
502 | break; | ||
503 | /* | ||
504 | * SGMII can have 1-4 ports depending on how many are | ||
505 | * hooked up | ||
506 | */ | ||
507 | case CVMX_HELPER_INTERFACE_MODE_SGMII: | ||
508 | case CVMX_HELPER_INTERFACE_MODE_PICMG: | ||
509 | result = __cvmx_helper_sgmii_enable(interface); | ||
510 | break; | ||
511 | /* PCI target Network Packet Interface */ | ||
512 | case CVMX_HELPER_INTERFACE_MODE_NPI: | ||
513 | result = __cvmx_helper_npi_enable(interface); | ||
514 | break; | ||
515 | /* | ||
516 | * Special loopback only ports. These are not the same | ||
517 | * as other ports in loopback mode | ||
518 | */ | ||
519 | case CVMX_HELPER_INTERFACE_MODE_LOOP: | ||
520 | result = __cvmx_helper_loop_enable(interface); | ||
521 | break; | ||
522 | } | ||
523 | result |= __cvmx_helper_board_hardware_enable(interface); | ||
524 | return result; | ||
525 | } | ||
526 | |||
527 | /** | ||
528 | * Function to adjust internal IPD pointer alignments | ||
529 | * | ||
530 | * Returns 0 on success | ||
531 | * !0 on failure | ||
532 | */ | ||
533 | int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) | ||
534 | { | ||
535 | #define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \ | ||
536 | (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP) | ||
537 | #define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \ | ||
538 | (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP) | ||
539 | #define FIX_IPD_OUTPORT 0 | ||
540 | /* Ports 0-15 are interface 0, 16-31 are interface 1 */ | ||
541 | #define INTERFACE(port) (port >> 4) | ||
542 | #define INDEX(port) (port & 0xf) | ||
543 | uint64_t *p64; | ||
544 | cvmx_pko_command_word0_t pko_command; | ||
545 | union cvmx_buf_ptr g_buffer, pkt_buffer; | ||
546 | cvmx_wqe_t *work; | ||
547 | int size, num_segs = 0, wqe_pcnt, pkt_pcnt; | ||
548 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
549 | int retry_cnt; | ||
550 | int retry_loop_cnt; | ||
551 | int mtu; | ||
552 | int i; | ||
553 | cvmx_helper_link_info_t link_info; | ||
554 | |||
555 | /* Save values for restore at end */ | ||
556 | uint64_t prtx_cfg = | ||
557 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG | ||
558 | (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); | ||
559 | uint64_t tx_ptr_en = | ||
560 | cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); | ||
561 | uint64_t rx_ptr_en = | ||
562 | cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); | ||
563 | uint64_t rxx_jabber = | ||
564 | cvmx_read_csr(CVMX_GMXX_RXX_JABBER | ||
565 | (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); | ||
566 | uint64_t frame_max = | ||
567 | cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX | ||
568 | (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); | ||
569 | |||
570 | /* Configure port to gig FDX as required for loopback mode */ | ||
571 | cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT); | ||
572 | |||
573 | /* | ||
574 | * Disable reception on all ports so if traffic is present it | ||
575 | * will not interfere. | ||
576 | */ | ||
577 | cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0); | ||
578 | |||
579 | cvmx_wait(100000000ull); | ||
580 | |||
581 | for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) { | ||
582 | retry_cnt = 100000; | ||
583 | wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT); | ||
584 | pkt_pcnt = (wqe_pcnt >> 7) & 0x7f; | ||
585 | wqe_pcnt &= 0x7f; | ||
586 | |||
587 | num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3; | ||
588 | |||
589 | if (num_segs == 0) | ||
590 | goto fix_ipd_exit; | ||
591 | |||
592 | num_segs += 1; | ||
593 | |||
594 | size = | ||
595 | FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES + | ||
596 | ((num_segs - 1) * FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) - | ||
597 | (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2); | ||
598 | |||
599 | cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), | ||
600 | 1 << INDEX(FIX_IPD_OUTPORT)); | ||
601 | CVMX_SYNC; | ||
602 | |||
603 | g_buffer.u64 = 0; | ||
604 | g_buffer.s.addr = | ||
605 | cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL)); | ||
606 | if (g_buffer.s.addr == 0) { | ||
607 | cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " | ||
608 | "buffer allocation failure.\n"); | ||
609 | goto fix_ipd_exit; | ||
610 | } | ||
611 | |||
612 | g_buffer.s.pool = CVMX_FPA_WQE_POOL; | ||
613 | g_buffer.s.size = num_segs; | ||
614 | |||
615 | pkt_buffer.u64 = 0; | ||
616 | pkt_buffer.s.addr = | ||
617 | cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL)); | ||
618 | if (pkt_buffer.s.addr == 0) { | ||
619 | cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " | ||
620 | "buffer allocation failure.\n"); | ||
621 | goto fix_ipd_exit; | ||
622 | } | ||
623 | pkt_buffer.s.i = 1; | ||
624 | pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL; | ||
625 | pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES; | ||
626 | |||
627 | p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr); | ||
628 | p64[0] = 0xffffffffffff0000ull; | ||
629 | p64[1] = 0x08004510ull; | ||
630 | p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull; | ||
631 | p64[3] = 0x3a5fc0a81073c0a8ull; | ||
632 | |||
633 | for (i = 0; i < num_segs; i++) { | ||
634 | if (i > 0) | ||
635 | pkt_buffer.s.size = | ||
636 | FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES; | ||
637 | |||
638 | if (i == (num_segs - 1)) | ||
639 | pkt_buffer.s.i = 0; | ||
640 | |||
641 | *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr + | ||
642 | 8 * i) = pkt_buffer.u64; | ||
643 | } | ||
644 | |||
645 | /* Build the PKO command */ | ||
646 | pko_command.u64 = 0; | ||
647 | pko_command.s.segs = num_segs; | ||
648 | pko_command.s.total_bytes = size; | ||
649 | pko_command.s.dontfree = 0; | ||
650 | pko_command.s.gather = 1; | ||
651 | |||
652 | gmx_cfg.u64 = | ||
653 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG | ||
654 | (INDEX(FIX_IPD_OUTPORT), | ||
655 | INTERFACE(FIX_IPD_OUTPORT))); | ||
656 | gmx_cfg.s.en = 1; | ||
657 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG | ||
658 | (INDEX(FIX_IPD_OUTPORT), | ||
659 | INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64); | ||
660 | cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), | ||
661 | 1 << INDEX(FIX_IPD_OUTPORT)); | ||
662 | cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), | ||
663 | 1 << INDEX(FIX_IPD_OUTPORT)); | ||
664 | |||
665 | mtu = | ||
666 | cvmx_read_csr(CVMX_GMXX_RXX_JABBER | ||
667 | (INDEX(FIX_IPD_OUTPORT), | ||
668 | INTERFACE(FIX_IPD_OUTPORT))); | ||
669 | cvmx_write_csr(CVMX_GMXX_RXX_JABBER | ||
670 | (INDEX(FIX_IPD_OUTPORT), | ||
671 | INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); | ||
672 | cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX | ||
673 | (INDEX(FIX_IPD_OUTPORT), | ||
674 | INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); | ||
675 | |||
676 | cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT, | ||
677 | cvmx_pko_get_base_queue | ||
678 | (FIX_IPD_OUTPORT), | ||
679 | CVMX_PKO_LOCK_CMD_QUEUE); | ||
680 | cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT, | ||
681 | cvmx_pko_get_base_queue | ||
682 | (FIX_IPD_OUTPORT), pko_command, | ||
683 | g_buffer, CVMX_PKO_LOCK_CMD_QUEUE); | ||
684 | |||
685 | CVMX_SYNC; | ||
686 | |||
687 | do { | ||
688 | work = cvmx_pow_work_request_sync(CVMX_POW_WAIT); | ||
689 | retry_cnt--; | ||
690 | } while ((work == NULL) && (retry_cnt > 0)); | ||
691 | |||
692 | if (!retry_cnt) | ||
693 | cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " | ||
694 | "get_work() timeout occured.\n"); | ||
695 | |||
696 | /* Free packet */ | ||
697 | if (work) | ||
698 | cvmx_helper_free_packet_data(work); | ||
699 | } | ||
700 | |||
701 | fix_ipd_exit: | ||
702 | |||
703 | /* Return CSR configs to saved values */ | ||
704 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG | ||
705 | (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), | ||
706 | prtx_cfg); | ||
707 | cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), | ||
708 | tx_ptr_en); | ||
709 | cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), | ||
710 | rx_ptr_en); | ||
711 | cvmx_write_csr(CVMX_GMXX_RXX_JABBER | ||
712 | (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), | ||
713 | rxx_jabber); | ||
714 | cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX | ||
715 | (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), | ||
716 | frame_max); | ||
717 | cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0); | ||
718 | /* Set link to down so autonegotiation will set it up again */ | ||
719 | link_info.u64 = 0; | ||
720 | cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info); | ||
721 | |||
722 | /* | ||
723 | * Bring the link back up as autonegotiation is not done in | ||
724 | * user applications. | ||
725 | */ | ||
726 | cvmx_helper_link_autoconf(FIX_IPD_OUTPORT); | ||
727 | |||
728 | CVMX_SYNC; | ||
729 | if (num_segs) | ||
730 | cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n"); | ||
731 | |||
732 | return !!num_segs; | ||
733 | |||
734 | } | ||
735 | |||
736 | /** | ||
737 | * Called after all internal packet IO paths are setup. This | ||
738 | * function enables IPD/PIP and begins packet input and output. | ||
739 | * | ||
740 | * Returns Zero on success, negative on failure | ||
741 | */ | ||
742 | int cvmx_helper_ipd_and_packet_input_enable(void) | ||
743 | { | ||
744 | int num_interfaces; | ||
745 | int interface; | ||
746 | |||
747 | /* Enable IPD */ | ||
748 | cvmx_ipd_enable(); | ||
749 | |||
750 | /* | ||
751 | * Time to enable hardware ports packet input and output. Note | ||
752 | * that at this point IPD/PIP must be fully functional and PKO | ||
753 | * must be disabled | ||
754 | */ | ||
755 | num_interfaces = cvmx_helper_get_number_of_interfaces(); | ||
756 | for (interface = 0; interface < num_interfaces; interface++) { | ||
757 | if (cvmx_helper_ports_on_interface(interface) > 0) | ||
758 | __cvmx_helper_packet_hardware_enable(interface); | ||
759 | } | ||
760 | |||
761 | /* Finally enable PKO now that the entire path is up and running */ | ||
762 | cvmx_pko_enable(); | ||
763 | |||
764 | if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1) | ||
765 | || OCTEON_IS_MODEL(OCTEON_CN30XX_PASS1)) | ||
766 | && (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)) | ||
767 | __cvmx_helper_errata_fix_ipd_ptr_alignment(); | ||
768 | return 0; | ||
769 | } | ||
770 | |||
771 | /** | ||
772 | * Initialize the PIP, IPD, and PKO hardware to support | ||
773 | * simple priority based queues for the ethernet ports. Each | ||
774 | * port is configured with a number of priority queues based | ||
775 | * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower | ||
776 | * priority than the previous. | ||
777 | * | ||
778 | * Returns Zero on success, non-zero on failure | ||
779 | */ | ||
780 | int cvmx_helper_initialize_packet_io_global(void) | ||
781 | { | ||
782 | int result = 0; | ||
783 | int interface; | ||
784 | union cvmx_l2c_cfg l2c_cfg; | ||
785 | union cvmx_smix_en smix_en; | ||
786 | const int num_interfaces = cvmx_helper_get_number_of_interfaces(); | ||
787 | |||
788 | /* | ||
789 | * CN52XX pass 1: Due to a bug in 2nd order CDR, it needs to | ||
790 | * be disabled. | ||
791 | */ | ||
792 | if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0)) | ||
793 | __cvmx_helper_errata_qlm_disable_2nd_order_cdr(1); | ||
794 | |||
795 | /* | ||
796 | * Tell L2 to give the IOB statically higher priority compared | ||
797 | * to the cores. This avoids conditions where IO blocks might | ||
798 | * be starved under very high L2 loads. | ||
799 | */ | ||
800 | l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); | ||
801 | l2c_cfg.s.lrf_arb_mode = 0; | ||
802 | l2c_cfg.s.rfb_arb_mode = 0; | ||
803 | cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64); | ||
804 | |||
805 | /* Make sure SMI/MDIO is enabled so we can query PHYs */ | ||
806 | smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0)); | ||
807 | if (!smix_en.s.en) { | ||
808 | smix_en.s.en = 1; | ||
809 | cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64); | ||
810 | } | ||
811 | |||
812 | /* Newer chips actually have two SMI/MDIO interfaces */ | ||
813 | if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && | ||
814 | !OCTEON_IS_MODEL(OCTEON_CN58XX) && | ||
815 | !OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
816 | smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1)); | ||
817 | if (!smix_en.s.en) { | ||
818 | smix_en.s.en = 1; | ||
819 | cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64); | ||
820 | } | ||
821 | } | ||
822 | |||
823 | cvmx_pko_initialize_global(); | ||
824 | for (interface = 0; interface < num_interfaces; interface++) { | ||
825 | result |= cvmx_helper_interface_probe(interface); | ||
826 | if (cvmx_helper_ports_on_interface(interface) > 0) | ||
827 | cvmx_dprintf("Interface %d has %d ports (%s)\n", | ||
828 | interface, | ||
829 | cvmx_helper_ports_on_interface(interface), | ||
830 | cvmx_helper_interface_mode_to_string | ||
831 | (cvmx_helper_interface_get_mode | ||
832 | (interface))); | ||
833 | result |= __cvmx_helper_interface_setup_ipd(interface); | ||
834 | result |= __cvmx_helper_interface_setup_pko(interface); | ||
835 | } | ||
836 | |||
837 | result |= __cvmx_helper_global_setup_ipd(); | ||
838 | result |= __cvmx_helper_global_setup_pko(); | ||
839 | |||
840 | /* Enable any flow control and backpressure */ | ||
841 | result |= __cvmx_helper_global_setup_backpressure(); | ||
842 | |||
843 | #if CVMX_HELPER_ENABLE_IPD | ||
844 | result |= cvmx_helper_ipd_and_packet_input_enable(); | ||
845 | #endif | ||
846 | return result; | ||
847 | } | ||
848 | |||
849 | /** | ||
850 | * Does core local initialization for packet io | ||
851 | * | ||
852 | * Returns Zero on success, non-zero on failure | ||
853 | */ | ||
854 | int cvmx_helper_initialize_packet_io_local(void) | ||
855 | { | ||
856 | return cvmx_pko_initialize_local(); | ||
857 | } | ||
858 | |||
859 | /** | ||
860 | * Auto configure an IPD/PKO port link state and speed. This | ||
861 | * function basically does the equivalent of: | ||
862 | * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port)); | ||
863 | * | ||
864 | * @ipd_port: IPD/PKO port to auto configure | ||
865 | * | ||
866 | * Returns Link state after configure | ||
867 | */ | ||
868 | cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port) | ||
869 | { | ||
870 | cvmx_helper_link_info_t link_info; | ||
871 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
872 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
873 | |||
874 | if (index >= cvmx_helper_ports_on_interface(interface)) { | ||
875 | link_info.u64 = 0; | ||
876 | return link_info; | ||
877 | } | ||
878 | |||
879 | link_info = cvmx_helper_link_get(ipd_port); | ||
880 | if (link_info.u64 == port_link_info[ipd_port].u64) | ||
881 | return link_info; | ||
882 | |||
883 | /* If we fail to set the link speed, port_link_info will not change */ | ||
884 | cvmx_helper_link_set(ipd_port, link_info); | ||
885 | |||
886 | /* | ||
887 | * port_link_info should be the current value, which will be | ||
888 | * different than expect if cvmx_helper_link_set() failed. | ||
889 | */ | ||
890 | return port_link_info[ipd_port]; | ||
891 | } | ||
892 | |||
893 | /** | ||
894 | * Return the link state of an IPD/PKO port as returned by | ||
895 | * auto negotiation. The result of this function may not match | ||
896 | * Octeon's link config if auto negotiation has changed since | ||
897 | * the last call to cvmx_helper_link_set(). | ||
898 | * | ||
899 | * @ipd_port: IPD/PKO port to query | ||
900 | * | ||
901 | * Returns Link state | ||
902 | */ | ||
903 | cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port) | ||
904 | { | ||
905 | cvmx_helper_link_info_t result; | ||
906 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
907 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
908 | |||
909 | /* The default result will be a down link unless the code below | ||
910 | changes it */ | ||
911 | result.u64 = 0; | ||
912 | |||
913 | if (index >= cvmx_helper_ports_on_interface(interface)) | ||
914 | return result; | ||
915 | |||
916 | switch (cvmx_helper_interface_get_mode(interface)) { | ||
917 | case CVMX_HELPER_INTERFACE_MODE_DISABLED: | ||
918 | case CVMX_HELPER_INTERFACE_MODE_PCIE: | ||
919 | /* Network links are not supported */ | ||
920 | break; | ||
921 | case CVMX_HELPER_INTERFACE_MODE_XAUI: | ||
922 | result = __cvmx_helper_xaui_link_get(ipd_port); | ||
923 | break; | ||
924 | case CVMX_HELPER_INTERFACE_MODE_GMII: | ||
925 | if (index == 0) | ||
926 | result = __cvmx_helper_rgmii_link_get(ipd_port); | ||
927 | else { | ||
928 | result.s.full_duplex = 1; | ||
929 | result.s.link_up = 1; | ||
930 | result.s.speed = 1000; | ||
931 | } | ||
932 | break; | ||
933 | case CVMX_HELPER_INTERFACE_MODE_RGMII: | ||
934 | result = __cvmx_helper_rgmii_link_get(ipd_port); | ||
935 | break; | ||
936 | case CVMX_HELPER_INTERFACE_MODE_SPI: | ||
937 | result = __cvmx_helper_spi_link_get(ipd_port); | ||
938 | break; | ||
939 | case CVMX_HELPER_INTERFACE_MODE_SGMII: | ||
940 | case CVMX_HELPER_INTERFACE_MODE_PICMG: | ||
941 | result = __cvmx_helper_sgmii_link_get(ipd_port); | ||
942 | break; | ||
943 | case CVMX_HELPER_INTERFACE_MODE_NPI: | ||
944 | case CVMX_HELPER_INTERFACE_MODE_LOOP: | ||
945 | /* Network links are not supported */ | ||
946 | break; | ||
947 | } | ||
948 | return result; | ||
949 | } | ||
950 | |||
951 | /** | ||
952 | * Configure an IPD/PKO port for the specified link state. This | ||
953 | * function does not influence auto negotiation at the PHY level. | ||
954 | * The passed link state must always match the link state returned | ||
955 | * by cvmx_helper_link_get(). It is normally best to use | ||
956 | * cvmx_helper_link_autoconf() instead. | ||
957 | * | ||
958 | * @ipd_port: IPD/PKO port to configure | ||
959 | * @link_info: The new link state | ||
960 | * | ||
961 | * Returns Zero on success, negative on failure | ||
962 | */ | ||
963 | int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info) | ||
964 | { | ||
965 | int result = -1; | ||
966 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
967 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
968 | |||
969 | if (index >= cvmx_helper_ports_on_interface(interface)) | ||
970 | return -1; | ||
971 | |||
972 | switch (cvmx_helper_interface_get_mode(interface)) { | ||
973 | case CVMX_HELPER_INTERFACE_MODE_DISABLED: | ||
974 | case CVMX_HELPER_INTERFACE_MODE_PCIE: | ||
975 | break; | ||
976 | case CVMX_HELPER_INTERFACE_MODE_XAUI: | ||
977 | result = __cvmx_helper_xaui_link_set(ipd_port, link_info); | ||
978 | break; | ||
979 | /* | ||
980 | * RGMII/GMII/MII are all treated about the same. Most | ||
981 | * functions refer to these ports as RGMII. | ||
982 | */ | ||
983 | case CVMX_HELPER_INTERFACE_MODE_RGMII: | ||
984 | case CVMX_HELPER_INTERFACE_MODE_GMII: | ||
985 | result = __cvmx_helper_rgmii_link_set(ipd_port, link_info); | ||
986 | break; | ||
987 | case CVMX_HELPER_INTERFACE_MODE_SPI: | ||
988 | result = __cvmx_helper_spi_link_set(ipd_port, link_info); | ||
989 | break; | ||
990 | case CVMX_HELPER_INTERFACE_MODE_SGMII: | ||
991 | case CVMX_HELPER_INTERFACE_MODE_PICMG: | ||
992 | result = __cvmx_helper_sgmii_link_set(ipd_port, link_info); | ||
993 | break; | ||
994 | case CVMX_HELPER_INTERFACE_MODE_NPI: | ||
995 | case CVMX_HELPER_INTERFACE_MODE_LOOP: | ||
996 | break; | ||
997 | } | ||
998 | /* Set the port_link_info here so that the link status is updated | ||
999 | no matter how cvmx_helper_link_set is called. We don't change | ||
1000 | the value if link_set failed */ | ||
1001 | if (result == 0) | ||
1002 | port_link_info[ipd_port].u64 = link_info.u64; | ||
1003 | return result; | ||
1004 | } | ||
1005 | |||
1006 | /** | ||
1007 | * Configure a port for internal and/or external loopback. Internal loopback | ||
1008 | * causes packets sent by the port to be received by Octeon. External loopback | ||
1009 | * causes packets received from the wire to sent out again. | ||
1010 | * | ||
1011 | * @ipd_port: IPD/PKO port to loopback. | ||
1012 | * @enable_internal: | ||
1013 | * Non zero if you want internal loopback | ||
1014 | * @enable_external: | ||
1015 | * Non zero if you want external loopback | ||
1016 | * | ||
1017 | * Returns Zero on success, negative on failure. | ||
1018 | */ | ||
1019 | int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, | ||
1020 | int enable_external) | ||
1021 | { | ||
1022 | int result = -1; | ||
1023 | int interface = cvmx_helper_get_interface_num(ipd_port); | ||
1024 | int index = cvmx_helper_get_interface_index_num(ipd_port); | ||
1025 | |||
1026 | if (index >= cvmx_helper_ports_on_interface(interface)) | ||
1027 | return -1; | ||
1028 | |||
1029 | switch (cvmx_helper_interface_get_mode(interface)) { | ||
1030 | case CVMX_HELPER_INTERFACE_MODE_DISABLED: | ||
1031 | case CVMX_HELPER_INTERFACE_MODE_PCIE: | ||
1032 | case CVMX_HELPER_INTERFACE_MODE_SPI: | ||
1033 | case CVMX_HELPER_INTERFACE_MODE_NPI: | ||
1034 | case CVMX_HELPER_INTERFACE_MODE_LOOP: | ||
1035 | break; | ||
1036 | case CVMX_HELPER_INTERFACE_MODE_XAUI: | ||
1037 | result = | ||
1038 | __cvmx_helper_xaui_configure_loopback(ipd_port, | ||
1039 | enable_internal, | ||
1040 | enable_external); | ||
1041 | break; | ||
1042 | case CVMX_HELPER_INTERFACE_MODE_RGMII: | ||
1043 | case CVMX_HELPER_INTERFACE_MODE_GMII: | ||
1044 | result = | ||
1045 | __cvmx_helper_rgmii_configure_loopback(ipd_port, | ||
1046 | enable_internal, | ||
1047 | enable_external); | ||
1048 | break; | ||
1049 | case CVMX_HELPER_INTERFACE_MODE_SGMII: | ||
1050 | case CVMX_HELPER_INTERFACE_MODE_PICMG: | ||
1051 | result = | ||
1052 | __cvmx_helper_sgmii_configure_loopback(ipd_port, | ||
1053 | enable_internal, | ||
1054 | enable_external); | ||
1055 | break; | ||
1056 | } | ||
1057 | return result; | ||
1058 | } | ||
diff --git a/drivers/staging/octeon/cvmx-helper.h b/drivers/staging/octeon/cvmx-helper.h new file mode 100644 index 000000000000..51916f3cc40c --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper.h | |||
@@ -0,0 +1,227 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * | ||
30 | * Helper functions for common, but complicated tasks. | ||
31 | * | ||
32 | */ | ||
33 | |||
34 | #ifndef __CVMX_HELPER_H__ | ||
35 | #define __CVMX_HELPER_H__ | ||
36 | |||
37 | #include "cvmx-config.h" | ||
38 | #include "cvmx-fpa.h" | ||
39 | #include "cvmx-wqe.h" | ||
40 | |||
41 | typedef enum { | ||
42 | CVMX_HELPER_INTERFACE_MODE_DISABLED, | ||
43 | CVMX_HELPER_INTERFACE_MODE_RGMII, | ||
44 | CVMX_HELPER_INTERFACE_MODE_GMII, | ||
45 | CVMX_HELPER_INTERFACE_MODE_SPI, | ||
46 | CVMX_HELPER_INTERFACE_MODE_PCIE, | ||
47 | CVMX_HELPER_INTERFACE_MODE_XAUI, | ||
48 | CVMX_HELPER_INTERFACE_MODE_SGMII, | ||
49 | CVMX_HELPER_INTERFACE_MODE_PICMG, | ||
50 | CVMX_HELPER_INTERFACE_MODE_NPI, | ||
51 | CVMX_HELPER_INTERFACE_MODE_LOOP, | ||
52 | } cvmx_helper_interface_mode_t; | ||
53 | |||
54 | typedef union { | ||
55 | uint64_t u64; | ||
56 | struct { | ||
57 | uint64_t reserved_20_63:44; | ||
58 | uint64_t link_up:1; /**< Is the physical link up? */ | ||
59 | uint64_t full_duplex:1; /**< 1 if the link is full duplex */ | ||
60 | uint64_t speed:18; /**< Speed of the link in Mbps */ | ||
61 | } s; | ||
62 | } cvmx_helper_link_info_t; | ||
63 | |||
64 | #include "cvmx-helper-fpa.h" | ||
65 | |||
66 | #include <asm/octeon/cvmx-helper-errata.h> | ||
67 | #include "cvmx-helper-loop.h" | ||
68 | #include "cvmx-helper-npi.h" | ||
69 | #include "cvmx-helper-rgmii.h" | ||
70 | #include "cvmx-helper-sgmii.h" | ||
71 | #include "cvmx-helper-spi.h" | ||
72 | #include "cvmx-helper-util.h" | ||
73 | #include "cvmx-helper-xaui.h" | ||
74 | |||
75 | /** | ||
76 | * cvmx_override_pko_queue_priority(int ipd_port, uint64_t | ||
77 | * priorities[16]) is a function pointer. It is meant to allow | ||
78 | * customization of the PKO queue priorities based on the port | ||
79 | * number. Users should set this pointer to a function before | ||
80 | * calling any cvmx-helper operations. | ||
81 | */ | ||
82 | extern void (*cvmx_override_pko_queue_priority) (int pko_port, | ||
83 | uint64_t priorities[16]); | ||
84 | |||
85 | /** | ||
86 | * cvmx_override_ipd_port_setup(int ipd_port) is a function | ||
87 | * pointer. It is meant to allow customization of the IPD port | ||
88 | * setup before packet input/output comes online. It is called | ||
89 | * after cvmx-helper does the default IPD configuration, but | ||
90 | * before IPD is enabled. Users should set this pointer to a | ||
91 | * function before calling any cvmx-helper operations. | ||
92 | */ | ||
93 | extern void (*cvmx_override_ipd_port_setup) (int ipd_port); | ||
94 | |||
95 | /** | ||
96 | * This function enables the IPD and also enables the packet interfaces. | ||
97 | * The packet interfaces (RGMII and SPI) must be enabled after the | ||
98 | * IPD. This should be called by the user program after any additional | ||
99 | * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD | ||
100 | * is not set in the executive-config.h file. | ||
101 | * | ||
102 | * Returns 0 on success | ||
103 | * -1 on failure | ||
104 | */ | ||
105 | extern int cvmx_helper_ipd_and_packet_input_enable(void); | ||
106 | |||
107 | /** | ||
108 | * Initialize the PIP, IPD, and PKO hardware to support | ||
109 | * simple priority based queues for the ethernet ports. Each | ||
110 | * port is configured with a number of priority queues based | ||
111 | * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower | ||
112 | * priority than the previous. | ||
113 | * | ||
114 | * Returns Zero on success, non-zero on failure | ||
115 | */ | ||
116 | extern int cvmx_helper_initialize_packet_io_global(void); | ||
117 | |||
118 | /** | ||
119 | * Does core local initialization for packet io | ||
120 | * | ||
121 | * Returns Zero on success, non-zero on failure | ||
122 | */ | ||
123 | extern int cvmx_helper_initialize_packet_io_local(void); | ||
124 | |||
125 | /** | ||
126 | * Returns the number of ports on the given interface. | ||
127 | * The interface must be initialized before the port count | ||
128 | * can be returned. | ||
129 | * | ||
130 | * @interface: Which interface to return port count for. | ||
131 | * | ||
132 | * Returns Port count for interface | ||
133 | * -1 for uninitialized interface | ||
134 | */ | ||
135 | extern int cvmx_helper_ports_on_interface(int interface); | ||
136 | |||
137 | /** | ||
138 | * Return the number of interfaces the chip has. Each interface | ||
139 | * may have multiple ports. Most chips support two interfaces, | ||
140 | * but the CNX0XX and CNX1XX are exceptions. These only support | ||
141 | * one interface. | ||
142 | * | ||
143 | * Returns Number of interfaces on chip | ||
144 | */ | ||
145 | extern int cvmx_helper_get_number_of_interfaces(void); | ||
146 | |||
147 | /** | ||
148 | * Get the operating mode of an interface. Depending on the Octeon | ||
149 | * chip and configuration, this function returns an enumeration | ||
150 | * of the type of packet I/O supported by an interface. | ||
151 | * | ||
152 | * @interface: Interface to probe | ||
153 | * | ||
154 | * Returns Mode of the interface. Unknown or unsupported interfaces return | ||
155 | * DISABLED. | ||
156 | */ | ||
157 | extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int | ||
158 | interface); | ||
159 | |||
160 | /** | ||
161 | * Auto configure an IPD/PKO port link state and speed. This | ||
162 | * function basically does the equivalent of: | ||
163 | * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port)); | ||
164 | * | ||
165 | * @ipd_port: IPD/PKO port to auto configure | ||
166 | * | ||
167 | * Returns Link state after configure | ||
168 | */ | ||
169 | extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port); | ||
170 | |||
171 | /** | ||
172 | * Return the link state of an IPD/PKO port as returned by | ||
173 | * auto negotiation. The result of this function may not match | ||
174 | * Octeon's link config if auto negotiation has changed since | ||
175 | * the last call to cvmx_helper_link_set(). | ||
176 | * | ||
177 | * @ipd_port: IPD/PKO port to query | ||
178 | * | ||
179 | * Returns Link state | ||
180 | */ | ||
181 | extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port); | ||
182 | |||
183 | /** | ||
184 | * Configure an IPD/PKO port for the specified link state. This | ||
185 | * function does not influence auto negotiation at the PHY level. | ||
186 | * The passed link state must always match the link state returned | ||
187 | * by cvmx_helper_link_get(). It is normally best to use | ||
188 | * cvmx_helper_link_autoconf() instead. | ||
189 | * | ||
190 | * @ipd_port: IPD/PKO port to configure | ||
191 | * @link_info: The new link state | ||
192 | * | ||
193 | * Returns Zero on success, negative on failure | ||
194 | */ | ||
195 | extern int cvmx_helper_link_set(int ipd_port, | ||
196 | cvmx_helper_link_info_t link_info); | ||
197 | |||
198 | /** | ||
199 | * This function probes an interface to determine the actual | ||
200 | * number of hardware ports connected to it. It doesn't setup the | ||
201 | * ports or enable them. The main goal here is to set the global | ||
202 | * interface_port_count[interface] correctly. Hardware setup of the | ||
203 | * ports will be performed later. | ||
204 | * | ||
205 | * @interface: Interface to probe | ||
206 | * | ||
207 | * Returns Zero on success, negative on failure | ||
208 | */ | ||
209 | extern int cvmx_helper_interface_probe(int interface); | ||
210 | |||
211 | /** | ||
212 | * Configure a port for internal and/or external loopback. Internal loopback | ||
213 | * causes packets sent by the port to be received by Octeon. External loopback | ||
214 | * causes packets received from the wire to sent out again. | ||
215 | * | ||
216 | * @ipd_port: IPD/PKO port to loopback. | ||
217 | * @enable_internal: | ||
218 | * Non zero if you want internal loopback | ||
219 | * @enable_external: | ||
220 | * Non zero if you want external loopback | ||
221 | * | ||
222 | * Returns Zero on success, negative on failure. | ||
223 | */ | ||
224 | extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, | ||
225 | int enable_external); | ||
226 | |||
227 | #endif /* __CVMX_HELPER_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-interrupt-decodes.c b/drivers/staging/octeon/cvmx-interrupt-decodes.c new file mode 100644 index 000000000000..a3337e382ee9 --- /dev/null +++ b/drivers/staging/octeon/cvmx-interrupt-decodes.c | |||
@@ -0,0 +1,371 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2009 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * | ||
30 | * Automatically generated functions useful for enabling | ||
31 | * and decoding RSL_INT_BLOCKS interrupts. | ||
32 | * | ||
33 | */ | ||
34 | |||
35 | #include <asm/octeon/octeon.h> | ||
36 | |||
37 | #include "cvmx-gmxx-defs.h" | ||
38 | #include "cvmx-pcsx-defs.h" | ||
39 | #include "cvmx-pcsxx-defs.h" | ||
40 | #include "cvmx-spxx-defs.h" | ||
41 | #include "cvmx-stxx-defs.h" | ||
42 | |||
43 | #ifndef PRINT_ERROR | ||
44 | #define PRINT_ERROR(format, ...) | ||
45 | #endif | ||
46 | |||
47 | |||
48 | /** | ||
49 | * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t | ||
50 | */ | ||
51 | void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) | ||
52 | { | ||
53 | union cvmx_gmxx_rxx_int_en gmx_rx_int_en; | ||
54 | cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), | ||
55 | cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block))); | ||
56 | gmx_rx_int_en.u64 = 0; | ||
57 | if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { | ||
58 | /* Skipping gmx_rx_int_en.s.reserved_29_63 */ | ||
59 | gmx_rx_int_en.s.hg2cc = 1; | ||
60 | gmx_rx_int_en.s.hg2fld = 1; | ||
61 | gmx_rx_int_en.s.undat = 1; | ||
62 | gmx_rx_int_en.s.uneop = 1; | ||
63 | gmx_rx_int_en.s.unsop = 1; | ||
64 | gmx_rx_int_en.s.bad_term = 1; | ||
65 | gmx_rx_int_en.s.bad_seq = 1; | ||
66 | gmx_rx_int_en.s.rem_fault = 1; | ||
67 | gmx_rx_int_en.s.loc_fault = 1; | ||
68 | gmx_rx_int_en.s.pause_drp = 1; | ||
69 | /* Skipping gmx_rx_int_en.s.reserved_16_18 */ | ||
70 | /*gmx_rx_int_en.s.ifgerr = 1; */ | ||
71 | /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ | ||
72 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ | ||
73 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | ||
74 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | ||
75 | gmx_rx_int_en.s.ovrerr = 1; | ||
76 | /* Skipping gmx_rx_int_en.s.reserved_9_9 */ | ||
77 | gmx_rx_int_en.s.skperr = 1; | ||
78 | gmx_rx_int_en.s.rcverr = 1; | ||
79 | /* Skipping gmx_rx_int_en.s.reserved_5_6 */ | ||
80 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | ||
81 | gmx_rx_int_en.s.jabber = 1; | ||
82 | /* Skipping gmx_rx_int_en.s.reserved_2_2 */ | ||
83 | gmx_rx_int_en.s.carext = 1; | ||
84 | /* Skipping gmx_rx_int_en.s.reserved_0_0 */ | ||
85 | } | ||
86 | if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { | ||
87 | /* Skipping gmx_rx_int_en.s.reserved_19_63 */ | ||
88 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | ||
89 | /*gmx_rx_int_en.s.phy_spd = 1; */ | ||
90 | /*gmx_rx_int_en.s.phy_link = 1; */ | ||
91 | /*gmx_rx_int_en.s.ifgerr = 1; */ | ||
92 | /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ | ||
93 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ | ||
94 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | ||
95 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | ||
96 | gmx_rx_int_en.s.ovrerr = 1; | ||
97 | gmx_rx_int_en.s.niberr = 1; | ||
98 | gmx_rx_int_en.s.skperr = 1; | ||
99 | gmx_rx_int_en.s.rcverr = 1; | ||
100 | /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ | ||
101 | gmx_rx_int_en.s.alnerr = 1; | ||
102 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | ||
103 | gmx_rx_int_en.s.jabber = 1; | ||
104 | gmx_rx_int_en.s.maxerr = 1; | ||
105 | gmx_rx_int_en.s.carext = 1; | ||
106 | gmx_rx_int_en.s.minerr = 1; | ||
107 | } | ||
108 | if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
109 | /* Skipping gmx_rx_int_en.s.reserved_20_63 */ | ||
110 | gmx_rx_int_en.s.pause_drp = 1; | ||
111 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | ||
112 | /*gmx_rx_int_en.s.phy_spd = 1; */ | ||
113 | /*gmx_rx_int_en.s.phy_link = 1; */ | ||
114 | /*gmx_rx_int_en.s.ifgerr = 1; */ | ||
115 | /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ | ||
116 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ | ||
117 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | ||
118 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | ||
119 | gmx_rx_int_en.s.ovrerr = 1; | ||
120 | gmx_rx_int_en.s.niberr = 1; | ||
121 | gmx_rx_int_en.s.skperr = 1; | ||
122 | gmx_rx_int_en.s.rcverr = 1; | ||
123 | /* Skipping gmx_rx_int_en.s.reserved_6_6 */ | ||
124 | gmx_rx_int_en.s.alnerr = 1; | ||
125 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | ||
126 | gmx_rx_int_en.s.jabber = 1; | ||
127 | /* Skipping gmx_rx_int_en.s.reserved_2_2 */ | ||
128 | gmx_rx_int_en.s.carext = 1; | ||
129 | /* Skipping gmx_rx_int_en.s.reserved_0_0 */ | ||
130 | } | ||
131 | if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { | ||
132 | /* Skipping gmx_rx_int_en.s.reserved_19_63 */ | ||
133 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | ||
134 | /*gmx_rx_int_en.s.phy_spd = 1; */ | ||
135 | /*gmx_rx_int_en.s.phy_link = 1; */ | ||
136 | /*gmx_rx_int_en.s.ifgerr = 1; */ | ||
137 | /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ | ||
138 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ | ||
139 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | ||
140 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | ||
141 | gmx_rx_int_en.s.ovrerr = 1; | ||
142 | gmx_rx_int_en.s.niberr = 1; | ||
143 | gmx_rx_int_en.s.skperr = 1; | ||
144 | gmx_rx_int_en.s.rcverr = 1; | ||
145 | /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ | ||
146 | gmx_rx_int_en.s.alnerr = 1; | ||
147 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | ||
148 | gmx_rx_int_en.s.jabber = 1; | ||
149 | gmx_rx_int_en.s.maxerr = 1; | ||
150 | gmx_rx_int_en.s.carext = 1; | ||
151 | gmx_rx_int_en.s.minerr = 1; | ||
152 | } | ||
153 | if (OCTEON_IS_MODEL(OCTEON_CN31XX)) { | ||
154 | /* Skipping gmx_rx_int_en.s.reserved_19_63 */ | ||
155 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | ||
156 | /*gmx_rx_int_en.s.phy_spd = 1; */ | ||
157 | /*gmx_rx_int_en.s.phy_link = 1; */ | ||
158 | /*gmx_rx_int_en.s.ifgerr = 1; */ | ||
159 | /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ | ||
160 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ | ||
161 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | ||
162 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | ||
163 | gmx_rx_int_en.s.ovrerr = 1; | ||
164 | gmx_rx_int_en.s.niberr = 1; | ||
165 | gmx_rx_int_en.s.skperr = 1; | ||
166 | gmx_rx_int_en.s.rcverr = 1; | ||
167 | /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ | ||
168 | gmx_rx_int_en.s.alnerr = 1; | ||
169 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | ||
170 | gmx_rx_int_en.s.jabber = 1; | ||
171 | gmx_rx_int_en.s.maxerr = 1; | ||
172 | gmx_rx_int_en.s.carext = 1; | ||
173 | gmx_rx_int_en.s.minerr = 1; | ||
174 | } | ||
175 | if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { | ||
176 | /* Skipping gmx_rx_int_en.s.reserved_20_63 */ | ||
177 | gmx_rx_int_en.s.pause_drp = 1; | ||
178 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | ||
179 | /*gmx_rx_int_en.s.phy_spd = 1; */ | ||
180 | /*gmx_rx_int_en.s.phy_link = 1; */ | ||
181 | /*gmx_rx_int_en.s.ifgerr = 1; */ | ||
182 | /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ | ||
183 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ | ||
184 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | ||
185 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | ||
186 | gmx_rx_int_en.s.ovrerr = 1; | ||
187 | gmx_rx_int_en.s.niberr = 1; | ||
188 | gmx_rx_int_en.s.skperr = 1; | ||
189 | gmx_rx_int_en.s.rcverr = 1; | ||
190 | /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ | ||
191 | gmx_rx_int_en.s.alnerr = 1; | ||
192 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | ||
193 | gmx_rx_int_en.s.jabber = 1; | ||
194 | gmx_rx_int_en.s.maxerr = 1; | ||
195 | gmx_rx_int_en.s.carext = 1; | ||
196 | gmx_rx_int_en.s.minerr = 1; | ||
197 | } | ||
198 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { | ||
199 | /* Skipping gmx_rx_int_en.s.reserved_29_63 */ | ||
200 | gmx_rx_int_en.s.hg2cc = 1; | ||
201 | gmx_rx_int_en.s.hg2fld = 1; | ||
202 | gmx_rx_int_en.s.undat = 1; | ||
203 | gmx_rx_int_en.s.uneop = 1; | ||
204 | gmx_rx_int_en.s.unsop = 1; | ||
205 | gmx_rx_int_en.s.bad_term = 1; | ||
206 | gmx_rx_int_en.s.bad_seq = 0; | ||
207 | gmx_rx_int_en.s.rem_fault = 1; | ||
208 | gmx_rx_int_en.s.loc_fault = 0; | ||
209 | gmx_rx_int_en.s.pause_drp = 1; | ||
210 | /* Skipping gmx_rx_int_en.s.reserved_16_18 */ | ||
211 | /*gmx_rx_int_en.s.ifgerr = 1; */ | ||
212 | /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ | ||
213 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ | ||
214 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | ||
215 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | ||
216 | gmx_rx_int_en.s.ovrerr = 1; | ||
217 | /* Skipping gmx_rx_int_en.s.reserved_9_9 */ | ||
218 | gmx_rx_int_en.s.skperr = 1; | ||
219 | gmx_rx_int_en.s.rcverr = 1; | ||
220 | /* Skipping gmx_rx_int_en.s.reserved_5_6 */ | ||
221 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | ||
222 | gmx_rx_int_en.s.jabber = 1; | ||
223 | /* Skipping gmx_rx_int_en.s.reserved_2_2 */ | ||
224 | gmx_rx_int_en.s.carext = 1; | ||
225 | /* Skipping gmx_rx_int_en.s.reserved_0_0 */ | ||
226 | } | ||
227 | cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); | ||
228 | } | ||
229 | /** | ||
230 | * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t | ||
231 | */ | ||
232 | void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block) | ||
233 | { | ||
234 | union cvmx_pcsx_intx_en_reg pcs_int_en_reg; | ||
235 | cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), | ||
236 | cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block))); | ||
237 | pcs_int_en_reg.u64 = 0; | ||
238 | if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { | ||
239 | /* Skipping pcs_int_en_reg.s.reserved_12_63 */ | ||
240 | /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ | ||
241 | pcs_int_en_reg.s.sync_bad_en = 1; | ||
242 | pcs_int_en_reg.s.an_bad_en = 1; | ||
243 | pcs_int_en_reg.s.rxlock_en = 1; | ||
244 | pcs_int_en_reg.s.rxbad_en = 1; | ||
245 | /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ | ||
246 | pcs_int_en_reg.s.txbad_en = 1; | ||
247 | pcs_int_en_reg.s.txfifo_en = 1; | ||
248 | pcs_int_en_reg.s.txfifu_en = 1; | ||
249 | pcs_int_en_reg.s.an_err_en = 1; | ||
250 | /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ | ||
251 | /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ | ||
252 | } | ||
253 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { | ||
254 | /* Skipping pcs_int_en_reg.s.reserved_12_63 */ | ||
255 | /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ | ||
256 | pcs_int_en_reg.s.sync_bad_en = 1; | ||
257 | pcs_int_en_reg.s.an_bad_en = 1; | ||
258 | pcs_int_en_reg.s.rxlock_en = 1; | ||
259 | pcs_int_en_reg.s.rxbad_en = 1; | ||
260 | /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ | ||
261 | pcs_int_en_reg.s.txbad_en = 1; | ||
262 | pcs_int_en_reg.s.txfifo_en = 1; | ||
263 | pcs_int_en_reg.s.txfifu_en = 1; | ||
264 | pcs_int_en_reg.s.an_err_en = 1; | ||
265 | /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ | ||
266 | /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ | ||
267 | } | ||
268 | cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); | ||
269 | } | ||
270 | /** | ||
271 | * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t | ||
272 | */ | ||
273 | void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index) | ||
274 | { | ||
275 | union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; | ||
276 | cvmx_write_csr(CVMX_PCSXX_INT_REG(index), | ||
277 | cvmx_read_csr(CVMX_PCSXX_INT_REG(index))); | ||
278 | pcsx_int_en_reg.u64 = 0; | ||
279 | if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { | ||
280 | /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ | ||
281 | pcsx_int_en_reg.s.algnlos_en = 1; | ||
282 | pcsx_int_en_reg.s.synlos_en = 1; | ||
283 | pcsx_int_en_reg.s.bitlckls_en = 1; | ||
284 | pcsx_int_en_reg.s.rxsynbad_en = 1; | ||
285 | pcsx_int_en_reg.s.rxbad_en = 1; | ||
286 | pcsx_int_en_reg.s.txflt_en = 1; | ||
287 | } | ||
288 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { | ||
289 | /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ | ||
290 | pcsx_int_en_reg.s.algnlos_en = 1; | ||
291 | pcsx_int_en_reg.s.synlos_en = 1; | ||
292 | pcsx_int_en_reg.s.bitlckls_en = 0; /* Happens if XAUI module is not installed */ | ||
293 | pcsx_int_en_reg.s.rxsynbad_en = 1; | ||
294 | pcsx_int_en_reg.s.rxbad_en = 1; | ||
295 | pcsx_int_en_reg.s.txflt_en = 1; | ||
296 | } | ||
297 | cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); | ||
298 | } | ||
299 | |||
300 | /** | ||
301 | * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t | ||
302 | */ | ||
303 | void __cvmx_interrupt_spxx_int_msk_enable(int index) | ||
304 | { | ||
305 | union cvmx_spxx_int_msk spx_int_msk; | ||
306 | cvmx_write_csr(CVMX_SPXX_INT_REG(index), | ||
307 | cvmx_read_csr(CVMX_SPXX_INT_REG(index))); | ||
308 | spx_int_msk.u64 = 0; | ||
309 | if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { | ||
310 | /* Skipping spx_int_msk.s.reserved_12_63 */ | ||
311 | spx_int_msk.s.calerr = 1; | ||
312 | spx_int_msk.s.syncerr = 1; | ||
313 | spx_int_msk.s.diperr = 1; | ||
314 | spx_int_msk.s.tpaovr = 1; | ||
315 | spx_int_msk.s.rsverr = 1; | ||
316 | spx_int_msk.s.drwnng = 1; | ||
317 | spx_int_msk.s.clserr = 1; | ||
318 | spx_int_msk.s.spiovr = 1; | ||
319 | /* Skipping spx_int_msk.s.reserved_2_3 */ | ||
320 | spx_int_msk.s.abnorm = 1; | ||
321 | spx_int_msk.s.prtnxa = 1; | ||
322 | } | ||
323 | if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { | ||
324 | /* Skipping spx_int_msk.s.reserved_12_63 */ | ||
325 | spx_int_msk.s.calerr = 1; | ||
326 | spx_int_msk.s.syncerr = 1; | ||
327 | spx_int_msk.s.diperr = 1; | ||
328 | spx_int_msk.s.tpaovr = 1; | ||
329 | spx_int_msk.s.rsverr = 1; | ||
330 | spx_int_msk.s.drwnng = 1; | ||
331 | spx_int_msk.s.clserr = 1; | ||
332 | spx_int_msk.s.spiovr = 1; | ||
333 | /* Skipping spx_int_msk.s.reserved_2_3 */ | ||
334 | spx_int_msk.s.abnorm = 1; | ||
335 | spx_int_msk.s.prtnxa = 1; | ||
336 | } | ||
337 | cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); | ||
338 | } | ||
339 | /** | ||
340 | * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t | ||
341 | */ | ||
342 | void __cvmx_interrupt_stxx_int_msk_enable(int index) | ||
343 | { | ||
344 | union cvmx_stxx_int_msk stx_int_msk; | ||
345 | cvmx_write_csr(CVMX_STXX_INT_REG(index), | ||
346 | cvmx_read_csr(CVMX_STXX_INT_REG(index))); | ||
347 | stx_int_msk.u64 = 0; | ||
348 | if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { | ||
349 | /* Skipping stx_int_msk.s.reserved_8_63 */ | ||
350 | stx_int_msk.s.frmerr = 1; | ||
351 | stx_int_msk.s.unxfrm = 1; | ||
352 | stx_int_msk.s.nosync = 1; | ||
353 | stx_int_msk.s.diperr = 1; | ||
354 | stx_int_msk.s.datovr = 1; | ||
355 | stx_int_msk.s.ovrbst = 1; | ||
356 | stx_int_msk.s.calpar1 = 1; | ||
357 | stx_int_msk.s.calpar0 = 1; | ||
358 | } | ||
359 | if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { | ||
360 | /* Skipping stx_int_msk.s.reserved_8_63 */ | ||
361 | stx_int_msk.s.frmerr = 1; | ||
362 | stx_int_msk.s.unxfrm = 1; | ||
363 | stx_int_msk.s.nosync = 1; | ||
364 | stx_int_msk.s.diperr = 1; | ||
365 | stx_int_msk.s.datovr = 1; | ||
366 | stx_int_msk.s.ovrbst = 1; | ||
367 | stx_int_msk.s.calpar1 = 1; | ||
368 | stx_int_msk.s.calpar0 = 1; | ||
369 | } | ||
370 | cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); | ||
371 | } | ||
diff --git a/drivers/staging/octeon/cvmx-interrupt-rsl.c b/drivers/staging/octeon/cvmx-interrupt-rsl.c new file mode 100644 index 000000000000..df50048cfbc0 --- /dev/null +++ b/drivers/staging/octeon/cvmx-interrupt-rsl.c | |||
@@ -0,0 +1,140 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Utility functions to decode Octeon's RSL_INT_BLOCKS | ||
30 | * interrupts into error messages. | ||
31 | */ | ||
32 | |||
33 | #include <asm/octeon/octeon.h> | ||
34 | |||
35 | #include "cvmx-asxx-defs.h" | ||
36 | #include "cvmx-gmxx-defs.h" | ||
37 | |||
38 | #ifndef PRINT_ERROR | ||
39 | #define PRINT_ERROR(format, ...) | ||
40 | #endif | ||
41 | |||
42 | void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block); | ||
43 | |||
44 | /** | ||
45 | * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and | ||
46 | * CN58XX. | ||
47 | * | ||
48 | * @block: Interface to enable 0-1 | ||
49 | */ | ||
50 | void __cvmx_interrupt_asxx_enable(int block) | ||
51 | { | ||
52 | int mask; | ||
53 | union cvmx_asxx_int_en csr; | ||
54 | /* | ||
55 | * CN38XX and CN58XX have two interfaces with 4 ports per | ||
56 | * interface. All other chips have a max of 3 ports on | ||
57 | * interface 0 | ||
58 | */ | ||
59 | if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) | ||
60 | mask = 0xf; /* Set enables for 4 ports */ | ||
61 | else | ||
62 | mask = 0x7; /* Set enables for 3 ports */ | ||
63 | |||
64 | /* Enable interface interrupts */ | ||
65 | csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); | ||
66 | csr.s.txpsh = mask; | ||
67 | csr.s.txpop = mask; | ||
68 | csr.s.ovrflw = mask; | ||
69 | cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); | ||
70 | } | ||
71 | /** | ||
72 | * Enable GMX error reporting for the supplied interface | ||
73 | * | ||
74 | * @interface: Interface to enable | ||
75 | */ | ||
76 | void __cvmx_interrupt_gmxx_enable(int interface) | ||
77 | { | ||
78 | union cvmx_gmxx_inf_mode mode; | ||
79 | union cvmx_gmxx_tx_int_en gmx_tx_int_en; | ||
80 | int num_ports; | ||
81 | int index; | ||
82 | |||
83 | mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); | ||
84 | |||
85 | if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { | ||
86 | if (mode.s.en) { | ||
87 | switch (mode.cn56xx.mode) { | ||
88 | case 1: /* XAUI */ | ||
89 | num_ports = 1; | ||
90 | break; | ||
91 | case 2: /* SGMII */ | ||
92 | case 3: /* PICMG */ | ||
93 | num_ports = 4; | ||
94 | break; | ||
95 | default: /* Disabled */ | ||
96 | num_ports = 0; | ||
97 | break; | ||
98 | } | ||
99 | } else | ||
100 | num_ports = 0; | ||
101 | } else { | ||
102 | if (mode.s.en) { | ||
103 | if (OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
104 | || OCTEON_IS_MODEL(OCTEON_CN58XX)) { | ||
105 | /* | ||
106 | * SPI on CN38XX and CN58XX report all | ||
107 | * errors through port 0. RGMII needs | ||
108 | * to check all 4 ports | ||
109 | */ | ||
110 | if (mode.s.type) | ||
111 | num_ports = 1; | ||
112 | else | ||
113 | num_ports = 4; | ||
114 | } else { | ||
115 | /* | ||
116 | * CN30XX, CN31XX, and CN50XX have two | ||
117 | * or three ports. GMII and MII has 2, | ||
118 | * RGMII has three | ||
119 | */ | ||
120 | if (mode.s.type) | ||
121 | num_ports = 2; | ||
122 | else | ||
123 | num_ports = 3; | ||
124 | } | ||
125 | } else | ||
126 | num_ports = 0; | ||
127 | } | ||
128 | |||
129 | gmx_tx_int_en.u64 = 0; | ||
130 | if (num_ports) { | ||
131 | if (OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
132 | || OCTEON_IS_MODEL(OCTEON_CN58XX)) | ||
133 | gmx_tx_int_en.s.ncb_nxa = 1; | ||
134 | gmx_tx_int_en.s.pko_nxa = 1; | ||
135 | } | ||
136 | gmx_tx_int_en.s.undflw = (1 << num_ports) - 1; | ||
137 | cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); | ||
138 | for (index = 0; index < num_ports; index++) | ||
139 | __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface); | ||
140 | } | ||
diff --git a/drivers/staging/octeon/cvmx-ipd.h b/drivers/staging/octeon/cvmx-ipd.h new file mode 100644 index 000000000000..115a552c5c7f --- /dev/null +++ b/drivers/staging/octeon/cvmx-ipd.h | |||
@@ -0,0 +1,338 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * | ||
30 | * Interface to the hardware Input Packet Data unit. | ||
31 | */ | ||
32 | |||
33 | #ifndef __CVMX_IPD_H__ | ||
34 | #define __CVMX_IPD_H__ | ||
35 | |||
36 | #include <asm/octeon/octeon-feature.h> | ||
37 | |||
38 | #include <asm/octeon/cvmx-ipd-defs.h> | ||
39 | |||
40 | enum cvmx_ipd_mode { | ||
41 | CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ | ||
42 | CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ | ||
43 | CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ | ||
44 | CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ | ||
45 | }; | ||
46 | |||
47 | #ifndef CVMX_ENABLE_LEN_M8_FIX | ||
48 | #define CVMX_ENABLE_LEN_M8_FIX 0 | ||
49 | #endif | ||
50 | |||
51 | /* CSR typedefs have been moved to cvmx-csr-*.h */ | ||
52 | typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t; | ||
53 | typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t; | ||
54 | |||
55 | typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t; | ||
56 | typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t; | ||
57 | |||
58 | /** | ||
59 | * Configure IPD | ||
60 | * | ||
61 | * @mbuff_size: Packets buffer size in 8 byte words | ||
62 | * @first_mbuff_skip: | ||
63 | * Number of 8 byte words to skip in the first buffer | ||
64 | * @not_first_mbuff_skip: | ||
65 | * Number of 8 byte words to skip in each following buffer | ||
66 | * @first_back: Must be same as first_mbuff_skip / 128 | ||
67 | * @second_back: | ||
68 | * Must be same as not_first_mbuff_skip / 128 | ||
69 | * @wqe_fpa_pool: | ||
70 | * FPA pool to get work entries from | ||
71 | * @cache_mode: | ||
72 | * @back_pres_enable_flag: | ||
73 | * Enable or disable port back pressure | ||
74 | */ | ||
75 | static inline void cvmx_ipd_config(uint64_t mbuff_size, | ||
76 | uint64_t first_mbuff_skip, | ||
77 | uint64_t not_first_mbuff_skip, | ||
78 | uint64_t first_back, | ||
79 | uint64_t second_back, | ||
80 | uint64_t wqe_fpa_pool, | ||
81 | enum cvmx_ipd_mode cache_mode, | ||
82 | uint64_t back_pres_enable_flag) | ||
83 | { | ||
84 | cvmx_ipd_mbuff_first_skip_t first_skip; | ||
85 | cvmx_ipd_mbuff_not_first_skip_t not_first_skip; | ||
86 | union cvmx_ipd_packet_mbuff_size size; | ||
87 | cvmx_ipd_first_next_ptr_back_t first_back_struct; | ||
88 | cvmx_ipd_second_next_ptr_back_t second_back_struct; | ||
89 | union cvmx_ipd_wqe_fpa_queue wqe_pool; | ||
90 | union cvmx_ipd_ctl_status ipd_ctl_reg; | ||
91 | |||
92 | first_skip.u64 = 0; | ||
93 | first_skip.s.skip_sz = first_mbuff_skip; | ||
94 | cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); | ||
95 | |||
96 | not_first_skip.u64 = 0; | ||
97 | not_first_skip.s.skip_sz = not_first_mbuff_skip; | ||
98 | cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); | ||
99 | |||
100 | size.u64 = 0; | ||
101 | size.s.mb_size = mbuff_size; | ||
102 | cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); | ||
103 | |||
104 | first_back_struct.u64 = 0; | ||
105 | first_back_struct.s.back = first_back; | ||
106 | cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); | ||
107 | |||
108 | second_back_struct.u64 = 0; | ||
109 | second_back_struct.s.back = second_back; | ||
110 | cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64); | ||
111 | |||
112 | wqe_pool.u64 = 0; | ||
113 | wqe_pool.s.wqe_pool = wqe_fpa_pool; | ||
114 | cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); | ||
115 | |||
116 | ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); | ||
117 | ipd_ctl_reg.s.opc_mode = cache_mode; | ||
118 | ipd_ctl_reg.s.pbp_en = back_pres_enable_flag; | ||
119 | cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); | ||
120 | |||
121 | /* Note: the example RED code that used to be here has been moved to | ||
122 | cvmx_helper_setup_red */ | ||
123 | } | ||
124 | |||
125 | /** | ||
126 | * Enable IPD | ||
127 | */ | ||
128 | static inline void cvmx_ipd_enable(void) | ||
129 | { | ||
130 | union cvmx_ipd_ctl_status ipd_reg; | ||
131 | ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); | ||
132 | if (ipd_reg.s.ipd_en) { | ||
133 | cvmx_dprintf | ||
134 | ("Warning: Enabling IPD when IPD already enabled.\n"); | ||
135 | } | ||
136 | ipd_reg.s.ipd_en = 1; | ||
137 | #if CVMX_ENABLE_LEN_M8_FIX | ||
138 | if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) | ||
139 | ipd_reg.s.len_m8 = TRUE; | ||
140 | #endif | ||
141 | cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); | ||
142 | } | ||
143 | |||
144 | /** | ||
145 | * Disable IPD | ||
146 | */ | ||
147 | static inline void cvmx_ipd_disable(void) | ||
148 | { | ||
149 | union cvmx_ipd_ctl_status ipd_reg; | ||
150 | ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); | ||
151 | ipd_reg.s.ipd_en = 0; | ||
152 | cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); | ||
153 | } | ||
154 | |||
155 | /** | ||
156 | * Supportive function for cvmx_fpa_shutdown_pool. | ||
157 | */ | ||
158 | static inline void cvmx_ipd_free_ptr(void) | ||
159 | { | ||
160 | /* Only CN38XXp{1,2} cannot read pointer out of the IPD */ | ||
161 | if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1) | ||
162 | && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) { | ||
163 | int no_wptr = 0; | ||
164 | union cvmx_ipd_ptr_count ipd_ptr_count; | ||
165 | ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); | ||
166 | |||
167 | /* Handle Work Queue Entry in cn56xx and cn52xx */ | ||
168 | if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) { | ||
169 | union cvmx_ipd_ctl_status ipd_ctl_status; | ||
170 | ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); | ||
171 | if (ipd_ctl_status.s.no_wptr) | ||
172 | no_wptr = 1; | ||
173 | } | ||
174 | |||
175 | /* Free the prefetched WQE */ | ||
176 | if (ipd_ptr_count.s.wqev_cnt) { | ||
177 | union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid; | ||
178 | ipd_wqe_ptr_valid.u64 = | ||
179 | cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID); | ||
180 | if (no_wptr) | ||
181 | cvmx_fpa_free(cvmx_phys_to_ptr | ||
182 | ((uint64_t) ipd_wqe_ptr_valid.s. | ||
183 | ptr << 7), CVMX_FPA_PACKET_POOL, | ||
184 | 0); | ||
185 | else | ||
186 | cvmx_fpa_free(cvmx_phys_to_ptr | ||
187 | ((uint64_t) ipd_wqe_ptr_valid.s. | ||
188 | ptr << 7), CVMX_FPA_WQE_POOL, 0); | ||
189 | } | ||
190 | |||
191 | /* Free all WQE in the fifo */ | ||
192 | if (ipd_ptr_count.s.wqe_pcnt) { | ||
193 | int i; | ||
194 | union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; | ||
195 | ipd_pwp_ptr_fifo_ctl.u64 = | ||
196 | cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); | ||
197 | for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) { | ||
198 | ipd_pwp_ptr_fifo_ctl.s.cena = 0; | ||
199 | ipd_pwp_ptr_fifo_ctl.s.raddr = | ||
200 | ipd_pwp_ptr_fifo_ctl.s.max_cnts + | ||
201 | (ipd_pwp_ptr_fifo_ctl.s.wraddr + | ||
202 | i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; | ||
203 | cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, | ||
204 | ipd_pwp_ptr_fifo_ctl.u64); | ||
205 | ipd_pwp_ptr_fifo_ctl.u64 = | ||
206 | cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); | ||
207 | if (no_wptr) | ||
208 | cvmx_fpa_free(cvmx_phys_to_ptr | ||
209 | ((uint64_t) | ||
210 | ipd_pwp_ptr_fifo_ctl.s. | ||
211 | ptr << 7), | ||
212 | CVMX_FPA_PACKET_POOL, 0); | ||
213 | else | ||
214 | cvmx_fpa_free(cvmx_phys_to_ptr | ||
215 | ((uint64_t) | ||
216 | ipd_pwp_ptr_fifo_ctl.s. | ||
217 | ptr << 7), | ||
218 | CVMX_FPA_WQE_POOL, 0); | ||
219 | } | ||
220 | ipd_pwp_ptr_fifo_ctl.s.cena = 1; | ||
221 | cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, | ||
222 | ipd_pwp_ptr_fifo_ctl.u64); | ||
223 | } | ||
224 | |||
225 | /* Free the prefetched packet */ | ||
226 | if (ipd_ptr_count.s.pktv_cnt) { | ||
227 | union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid; | ||
228 | ipd_pkt_ptr_valid.u64 = | ||
229 | cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID); | ||
230 | cvmx_fpa_free(cvmx_phys_to_ptr | ||
231 | (ipd_pkt_ptr_valid.s.ptr << 7), | ||
232 | CVMX_FPA_PACKET_POOL, 0); | ||
233 | } | ||
234 | |||
235 | /* Free the per port prefetched packets */ | ||
236 | if (1) { | ||
237 | int i; | ||
238 | union cvmx_ipd_prc_port_ptr_fifo_ctl | ||
239 | ipd_prc_port_ptr_fifo_ctl; | ||
240 | ipd_prc_port_ptr_fifo_ctl.u64 = | ||
241 | cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); | ||
242 | |||
243 | for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; | ||
244 | i++) { | ||
245 | ipd_prc_port_ptr_fifo_ctl.s.cena = 0; | ||
246 | ipd_prc_port_ptr_fifo_ctl.s.raddr = | ||
247 | i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt; | ||
248 | cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, | ||
249 | ipd_prc_port_ptr_fifo_ctl.u64); | ||
250 | ipd_prc_port_ptr_fifo_ctl.u64 = | ||
251 | cvmx_read_csr | ||
252 | (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); | ||
253 | cvmx_fpa_free(cvmx_phys_to_ptr | ||
254 | ((uint64_t) | ||
255 | ipd_prc_port_ptr_fifo_ctl.s. | ||
256 | ptr << 7), CVMX_FPA_PACKET_POOL, | ||
257 | 0); | ||
258 | } | ||
259 | ipd_prc_port_ptr_fifo_ctl.s.cena = 1; | ||
260 | cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, | ||
261 | ipd_prc_port_ptr_fifo_ctl.u64); | ||
262 | } | ||
263 | |||
264 | /* Free all packets in the holding fifo */ | ||
265 | if (ipd_ptr_count.s.pfif_cnt) { | ||
266 | int i; | ||
267 | union cvmx_ipd_prc_hold_ptr_fifo_ctl | ||
268 | ipd_prc_hold_ptr_fifo_ctl; | ||
269 | |||
270 | ipd_prc_hold_ptr_fifo_ctl.u64 = | ||
271 | cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); | ||
272 | |||
273 | for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) { | ||
274 | ipd_prc_hold_ptr_fifo_ctl.s.cena = 0; | ||
275 | ipd_prc_hold_ptr_fifo_ctl.s.raddr = | ||
276 | (ipd_prc_hold_ptr_fifo_ctl.s.praddr + | ||
277 | i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt; | ||
278 | cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, | ||
279 | ipd_prc_hold_ptr_fifo_ctl.u64); | ||
280 | ipd_prc_hold_ptr_fifo_ctl.u64 = | ||
281 | cvmx_read_csr | ||
282 | (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); | ||
283 | cvmx_fpa_free(cvmx_phys_to_ptr | ||
284 | ((uint64_t) | ||
285 | ipd_prc_hold_ptr_fifo_ctl.s. | ||
286 | ptr << 7), CVMX_FPA_PACKET_POOL, | ||
287 | 0); | ||
288 | } | ||
289 | ipd_prc_hold_ptr_fifo_ctl.s.cena = 1; | ||
290 | cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, | ||
291 | ipd_prc_hold_ptr_fifo_ctl.u64); | ||
292 | } | ||
293 | |||
294 | /* Free all packets in the fifo */ | ||
295 | if (ipd_ptr_count.s.pkt_pcnt) { | ||
296 | int i; | ||
297 | union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; | ||
298 | ipd_pwp_ptr_fifo_ctl.u64 = | ||
299 | cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); | ||
300 | |||
301 | for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) { | ||
302 | ipd_pwp_ptr_fifo_ctl.s.cena = 0; | ||
303 | ipd_pwp_ptr_fifo_ctl.s.raddr = | ||
304 | (ipd_pwp_ptr_fifo_ctl.s.praddr + | ||
305 | i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; | ||
306 | cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, | ||
307 | ipd_pwp_ptr_fifo_ctl.u64); | ||
308 | ipd_pwp_ptr_fifo_ctl.u64 = | ||
309 | cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); | ||
310 | cvmx_fpa_free(cvmx_phys_to_ptr | ||
311 | ((uint64_t) ipd_pwp_ptr_fifo_ctl. | ||
312 | s.ptr << 7), | ||
313 | CVMX_FPA_PACKET_POOL, 0); | ||
314 | } | ||
315 | ipd_pwp_ptr_fifo_ctl.s.cena = 1; | ||
316 | cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, | ||
317 | ipd_pwp_ptr_fifo_ctl.u64); | ||
318 | } | ||
319 | |||
320 | /* Reset the IPD to get all buffers out of it */ | ||
321 | { | ||
322 | union cvmx_ipd_ctl_status ipd_ctl_status; | ||
323 | ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); | ||
324 | ipd_ctl_status.s.reset = 1; | ||
325 | cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64); | ||
326 | } | ||
327 | |||
328 | /* Reset the PIP */ | ||
329 | { | ||
330 | union cvmx_pip_sft_rst pip_sft_rst; | ||
331 | pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST); | ||
332 | pip_sft_rst.s.rst = 1; | ||
333 | cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64); | ||
334 | } | ||
335 | } | ||
336 | } | ||
337 | |||
338 | #endif /* __CVMX_IPD_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-mdio.h b/drivers/staging/octeon/cvmx-mdio.h new file mode 100644 index 000000000000..c987a75a20cf --- /dev/null +++ b/drivers/staging/octeon/cvmx-mdio.h | |||
@@ -0,0 +1,506 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * | ||
30 | * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3 | ||
31 | * clause 22 and clause 45 operations. | ||
32 | * | ||
33 | */ | ||
34 | |||
35 | #ifndef __CVMX_MIO_H__ | ||
36 | #define __CVMX_MIO_H__ | ||
37 | |||
38 | #include "cvmx-smix-defs.h" | ||
39 | |||
40 | /** | ||
41 | * PHY register 0 from the 802.3 spec | ||
42 | */ | ||
43 | #define CVMX_MDIO_PHY_REG_CONTROL 0 | ||
44 | typedef union { | ||
45 | uint16_t u16; | ||
46 | struct { | ||
47 | uint16_t reset:1; | ||
48 | uint16_t loopback:1; | ||
49 | uint16_t speed_lsb:1; | ||
50 | uint16_t autoneg_enable:1; | ||
51 | uint16_t power_down:1; | ||
52 | uint16_t isolate:1; | ||
53 | uint16_t restart_autoneg:1; | ||
54 | uint16_t duplex:1; | ||
55 | uint16_t collision_test:1; | ||
56 | uint16_t speed_msb:1; | ||
57 | uint16_t unidirectional_enable:1; | ||
58 | uint16_t reserved_0_4:5; | ||
59 | } s; | ||
60 | } cvmx_mdio_phy_reg_control_t; | ||
61 | |||
62 | /** | ||
63 | * PHY register 1 from the 802.3 spec | ||
64 | */ | ||
65 | #define CVMX_MDIO_PHY_REG_STATUS 1 | ||
66 | typedef union { | ||
67 | uint16_t u16; | ||
68 | struct { | ||
69 | uint16_t capable_100base_t4:1; | ||
70 | uint16_t capable_100base_x_full:1; | ||
71 | uint16_t capable_100base_x_half:1; | ||
72 | uint16_t capable_10_full:1; | ||
73 | uint16_t capable_10_half:1; | ||
74 | uint16_t capable_100base_t2_full:1; | ||
75 | uint16_t capable_100base_t2_half:1; | ||
76 | uint16_t capable_extended_status:1; | ||
77 | uint16_t capable_unidirectional:1; | ||
78 | uint16_t capable_mf_preamble_suppression:1; | ||
79 | uint16_t autoneg_complete:1; | ||
80 | uint16_t remote_fault:1; | ||
81 | uint16_t capable_autoneg:1; | ||
82 | uint16_t link_status:1; | ||
83 | uint16_t jabber_detect:1; | ||
84 | uint16_t capable_extended_registers:1; | ||
85 | |||
86 | } s; | ||
87 | } cvmx_mdio_phy_reg_status_t; | ||
88 | |||
89 | /** | ||
90 | * PHY register 2 from the 802.3 spec | ||
91 | */ | ||
92 | #define CVMX_MDIO_PHY_REG_ID1 2 | ||
93 | typedef union { | ||
94 | uint16_t u16; | ||
95 | struct { | ||
96 | uint16_t oui_bits_3_18; | ||
97 | } s; | ||
98 | } cvmx_mdio_phy_reg_id1_t; | ||
99 | |||
100 | /** | ||
101 | * PHY register 3 from the 802.3 spec | ||
102 | */ | ||
103 | #define CVMX_MDIO_PHY_REG_ID2 3 | ||
104 | typedef union { | ||
105 | uint16_t u16; | ||
106 | struct { | ||
107 | uint16_t oui_bits_19_24:6; | ||
108 | uint16_t model:6; | ||
109 | uint16_t revision:4; | ||
110 | } s; | ||
111 | } cvmx_mdio_phy_reg_id2_t; | ||
112 | |||
113 | /** | ||
114 | * PHY register 4 from the 802.3 spec | ||
115 | */ | ||
116 | #define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4 | ||
117 | typedef union { | ||
118 | uint16_t u16; | ||
119 | struct { | ||
120 | uint16_t next_page:1; | ||
121 | uint16_t reserved_14:1; | ||
122 | uint16_t remote_fault:1; | ||
123 | uint16_t reserved_12:1; | ||
124 | uint16_t asymmetric_pause:1; | ||
125 | uint16_t pause:1; | ||
126 | uint16_t advert_100base_t4:1; | ||
127 | uint16_t advert_100base_tx_full:1; | ||
128 | uint16_t advert_100base_tx_half:1; | ||
129 | uint16_t advert_10base_tx_full:1; | ||
130 | uint16_t advert_10base_tx_half:1; | ||
131 | uint16_t selector:5; | ||
132 | } s; | ||
133 | } cvmx_mdio_phy_reg_autoneg_adver_t; | ||
134 | |||
135 | /** | ||
136 | * PHY register 5 from the 802.3 spec | ||
137 | */ | ||
138 | #define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5 | ||
139 | typedef union { | ||
140 | uint16_t u16; | ||
141 | struct { | ||
142 | uint16_t next_page:1; | ||
143 | uint16_t ack:1; | ||
144 | uint16_t remote_fault:1; | ||
145 | uint16_t reserved_12:1; | ||
146 | uint16_t asymmetric_pause:1; | ||
147 | uint16_t pause:1; | ||
148 | uint16_t advert_100base_t4:1; | ||
149 | uint16_t advert_100base_tx_full:1; | ||
150 | uint16_t advert_100base_tx_half:1; | ||
151 | uint16_t advert_10base_tx_full:1; | ||
152 | uint16_t advert_10base_tx_half:1; | ||
153 | uint16_t selector:5; | ||
154 | } s; | ||
155 | } cvmx_mdio_phy_reg_link_partner_ability_t; | ||
156 | |||
157 | /** | ||
158 | * PHY register 6 from the 802.3 spec | ||
159 | */ | ||
160 | #define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6 | ||
161 | typedef union { | ||
162 | uint16_t u16; | ||
163 | struct { | ||
164 | uint16_t reserved_5_15:11; | ||
165 | uint16_t parallel_detection_fault:1; | ||
166 | uint16_t link_partner_next_page_capable:1; | ||
167 | uint16_t local_next_page_capable:1; | ||
168 | uint16_t page_received:1; | ||
169 | uint16_t link_partner_autoneg_capable:1; | ||
170 | |||
171 | } s; | ||
172 | } cvmx_mdio_phy_reg_autoneg_expansion_t; | ||
173 | |||
174 | /** | ||
175 | * PHY register 9 from the 802.3 spec | ||
176 | */ | ||
177 | #define CVMX_MDIO_PHY_REG_CONTROL_1000 9 | ||
178 | typedef union { | ||
179 | uint16_t u16; | ||
180 | struct { | ||
181 | uint16_t test_mode:3; | ||
182 | uint16_t manual_master_slave:1; | ||
183 | uint16_t master:1; | ||
184 | uint16_t port_type:1; | ||
185 | uint16_t advert_1000base_t_full:1; | ||
186 | uint16_t advert_1000base_t_half:1; | ||
187 | uint16_t reserved_0_7:8; | ||
188 | } s; | ||
189 | } cvmx_mdio_phy_reg_control_1000_t; | ||
190 | |||
191 | /** | ||
192 | * PHY register 10 from the 802.3 spec | ||
193 | */ | ||
194 | #define CVMX_MDIO_PHY_REG_STATUS_1000 10 | ||
195 | typedef union { | ||
196 | uint16_t u16; | ||
197 | struct { | ||
198 | uint16_t master_slave_fault:1; | ||
199 | uint16_t is_master:1; | ||
200 | uint16_t local_receiver_ok:1; | ||
201 | uint16_t remote_receiver_ok:1; | ||
202 | uint16_t remote_capable_1000base_t_full:1; | ||
203 | uint16_t remote_capable_1000base_t_half:1; | ||
204 | uint16_t reserved_8_9:2; | ||
205 | uint16_t idle_error_count:8; | ||
206 | } s; | ||
207 | } cvmx_mdio_phy_reg_status_1000_t; | ||
208 | |||
209 | /** | ||
210 | * PHY register 15 from the 802.3 spec | ||
211 | */ | ||
212 | #define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15 | ||
213 | typedef union { | ||
214 | uint16_t u16; | ||
215 | struct { | ||
216 | uint16_t capable_1000base_x_full:1; | ||
217 | uint16_t capable_1000base_x_half:1; | ||
218 | uint16_t capable_1000base_t_full:1; | ||
219 | uint16_t capable_1000base_t_half:1; | ||
220 | uint16_t reserved_0_11:12; | ||
221 | } s; | ||
222 | } cvmx_mdio_phy_reg_extended_status_t; | ||
223 | |||
224 | /** | ||
225 | * PHY register 13 from the 802.3 spec | ||
226 | */ | ||
227 | #define CVMX_MDIO_PHY_REG_MMD_CONTROL 13 | ||
228 | typedef union { | ||
229 | uint16_t u16; | ||
230 | struct { | ||
231 | uint16_t function:2; | ||
232 | uint16_t reserved_5_13:9; | ||
233 | uint16_t devad:5; | ||
234 | } s; | ||
235 | } cvmx_mdio_phy_reg_mmd_control_t; | ||
236 | |||
237 | /** | ||
238 | * PHY register 14 from the 802.3 spec | ||
239 | */ | ||
240 | #define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14 | ||
241 | typedef union { | ||
242 | uint16_t u16; | ||
243 | struct { | ||
244 | uint16_t address_data:16; | ||
245 | } s; | ||
246 | } cvmx_mdio_phy_reg_mmd_address_data_t; | ||
247 | |||
248 | /* Operating request encodings. */ | ||
249 | #define MDIO_CLAUSE_22_WRITE 0 | ||
250 | #define MDIO_CLAUSE_22_READ 1 | ||
251 | |||
252 | #define MDIO_CLAUSE_45_ADDRESS 0 | ||
253 | #define MDIO_CLAUSE_45_WRITE 1 | ||
254 | #define MDIO_CLAUSE_45_READ_INC 2 | ||
255 | #define MDIO_CLAUSE_45_READ 3 | ||
256 | |||
257 | /* MMD identifiers, mostly for accessing devices withing XENPAK modules. */ | ||
258 | #define CVMX_MMD_DEVICE_PMA_PMD 1 | ||
259 | #define CVMX_MMD_DEVICE_WIS 2 | ||
260 | #define CVMX_MMD_DEVICE_PCS 3 | ||
261 | #define CVMX_MMD_DEVICE_PHY_XS 4 | ||
262 | #define CVMX_MMD_DEVICE_DTS_XS 5 | ||
263 | #define CVMX_MMD_DEVICE_TC 6 | ||
264 | #define CVMX_MMD_DEVICE_CL22_EXT 29 | ||
265 | #define CVMX_MMD_DEVICE_VENDOR_1 30 | ||
266 | #define CVMX_MMD_DEVICE_VENDOR_2 31 | ||
267 | |||
268 | /* Helper function to put MDIO interface into clause 45 mode */ | ||
269 | static inline void __cvmx_mdio_set_clause45_mode(int bus_id) | ||
270 | { | ||
271 | union cvmx_smix_clk smi_clk; | ||
272 | /* Put bus into clause 45 mode */ | ||
273 | smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); | ||
274 | smi_clk.s.mode = 1; | ||
275 | smi_clk.s.preamble = 1; | ||
276 | cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); | ||
277 | } | ||
278 | |||
279 | /* Helper function to put MDIO interface into clause 22 mode */ | ||
280 | static inline void __cvmx_mdio_set_clause22_mode(int bus_id) | ||
281 | { | ||
282 | union cvmx_smix_clk smi_clk; | ||
283 | /* Put bus into clause 22 mode */ | ||
284 | smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); | ||
285 | smi_clk.s.mode = 0; | ||
286 | cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); | ||
287 | } | ||
288 | |||
289 | /** | ||
290 | * Perform an MII read. This function is used to read PHY | ||
291 | * registers controlling auto negotiation. | ||
292 | * | ||
293 | * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) | ||
294 | * support multiple busses. | ||
295 | * @phy_id: The MII phy id | ||
296 | * @location: Register location to read | ||
297 | * | ||
298 | * Returns Result from the read or -1 on failure | ||
299 | */ | ||
300 | static inline int cvmx_mdio_read(int bus_id, int phy_id, int location) | ||
301 | { | ||
302 | union cvmx_smix_cmd smi_cmd; | ||
303 | union cvmx_smix_rd_dat smi_rd; | ||
304 | int timeout = 1000; | ||
305 | |||
306 | if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) | ||
307 | __cvmx_mdio_set_clause22_mode(bus_id); | ||
308 | |||
309 | smi_cmd.u64 = 0; | ||
310 | smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ; | ||
311 | smi_cmd.s.phy_adr = phy_id; | ||
312 | smi_cmd.s.reg_adr = location; | ||
313 | cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); | ||
314 | |||
315 | do { | ||
316 | cvmx_wait(1000); | ||
317 | smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); | ||
318 | } while (smi_rd.s.pending && timeout--); | ||
319 | |||
320 | if (smi_rd.s.val) | ||
321 | return smi_rd.s.dat; | ||
322 | else | ||
323 | return -1; | ||
324 | } | ||
325 | |||
326 | /** | ||
327 | * Perform an MII write. This function is used to write PHY | ||
328 | * registers controlling auto negotiation. | ||
329 | * | ||
330 | * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) | ||
331 | * support multiple busses. | ||
332 | * @phy_id: The MII phy id | ||
333 | * @location: Register location to write | ||
334 | * @val: Value to write | ||
335 | * | ||
336 | * Returns -1 on error | ||
337 | * 0 on success | ||
338 | */ | ||
339 | static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val) | ||
340 | { | ||
341 | union cvmx_smix_cmd smi_cmd; | ||
342 | union cvmx_smix_wr_dat smi_wr; | ||
343 | int timeout = 1000; | ||
344 | |||
345 | if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) | ||
346 | __cvmx_mdio_set_clause22_mode(bus_id); | ||
347 | |||
348 | smi_wr.u64 = 0; | ||
349 | smi_wr.s.dat = val; | ||
350 | cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); | ||
351 | |||
352 | smi_cmd.u64 = 0; | ||
353 | smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE; | ||
354 | smi_cmd.s.phy_adr = phy_id; | ||
355 | smi_cmd.s.reg_adr = location; | ||
356 | cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); | ||
357 | |||
358 | do { | ||
359 | cvmx_wait(1000); | ||
360 | smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); | ||
361 | } while (smi_wr.s.pending && --timeout); | ||
362 | if (timeout <= 0) | ||
363 | return -1; | ||
364 | |||
365 | return 0; | ||
366 | } | ||
367 | |||
368 | /** | ||
369 | * Perform an IEEE 802.3 clause 45 MII read. This function is used to | ||
370 | * read PHY registers controlling auto negotiation. | ||
371 | * | ||
372 | * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) | ||
373 | * support multiple busses. | ||
374 | * @phy_id: The MII phy id | ||
375 | * @device: MDIO Managable Device (MMD) id | ||
376 | * @location: Register location to read | ||
377 | * | ||
378 | * Returns Result from the read or -1 on failure | ||
379 | */ | ||
380 | |||
381 | static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, | ||
382 | int location) | ||
383 | { | ||
384 | union cvmx_smix_cmd smi_cmd; | ||
385 | union cvmx_smix_rd_dat smi_rd; | ||
386 | union cvmx_smix_wr_dat smi_wr; | ||
387 | int timeout = 1000; | ||
388 | |||
389 | if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) | ||
390 | return -1; | ||
391 | |||
392 | __cvmx_mdio_set_clause45_mode(bus_id); | ||
393 | |||
394 | smi_wr.u64 = 0; | ||
395 | smi_wr.s.dat = location; | ||
396 | cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); | ||
397 | |||
398 | smi_cmd.u64 = 0; | ||
399 | smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS; | ||
400 | smi_cmd.s.phy_adr = phy_id; | ||
401 | smi_cmd.s.reg_adr = device; | ||
402 | cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); | ||
403 | |||
404 | do { | ||
405 | cvmx_wait(1000); | ||
406 | smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); | ||
407 | } while (smi_wr.s.pending && --timeout); | ||
408 | if (timeout <= 0) { | ||
409 | cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " | ||
410 | "device %2d register %2d TIME OUT(address)\n", | ||
411 | bus_id, phy_id, device, location); | ||
412 | return -1; | ||
413 | } | ||
414 | |||
415 | smi_cmd.u64 = 0; | ||
416 | smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ; | ||
417 | smi_cmd.s.phy_adr = phy_id; | ||
418 | smi_cmd.s.reg_adr = device; | ||
419 | cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); | ||
420 | |||
421 | do { | ||
422 | cvmx_wait(1000); | ||
423 | smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); | ||
424 | } while (smi_rd.s.pending && timeout--); | ||
425 | |||
426 | if (timeout <= 0) { | ||
427 | cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " | ||
428 | "device %2d register %2d TIME OUT(data)\n", | ||
429 | bus_id, phy_id, device, location); | ||
430 | return -1; | ||
431 | } | ||
432 | |||
433 | if (smi_rd.s.val) | ||
434 | return smi_rd.s.dat; | ||
435 | else { | ||
436 | cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " | ||
437 | "device %2d register %2d INVALID READ\n", | ||
438 | bus_id, phy_id, device, location); | ||
439 | return -1; | ||
440 | } | ||
441 | } | ||
442 | |||
443 | /** | ||
444 | * Perform an IEEE 802.3 clause 45 MII write. This function is used to | ||
445 | * write PHY registers controlling auto negotiation. | ||
446 | * | ||
447 | * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) | ||
448 | * support multiple busses. | ||
449 | * @phy_id: The MII phy id | ||
450 | * @device: MDIO Managable Device (MMD) id | ||
451 | * @location: Register location to write | ||
452 | * @val: Value to write | ||
453 | * | ||
454 | * Returns -1 on error | ||
455 | * 0 on success | ||
456 | */ | ||
457 | static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, | ||
458 | int location, int val) | ||
459 | { | ||
460 | union cvmx_smix_cmd smi_cmd; | ||
461 | union cvmx_smix_wr_dat smi_wr; | ||
462 | int timeout = 1000; | ||
463 | |||
464 | if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) | ||
465 | return -1; | ||
466 | |||
467 | __cvmx_mdio_set_clause45_mode(bus_id); | ||
468 | |||
469 | smi_wr.u64 = 0; | ||
470 | smi_wr.s.dat = location; | ||
471 | cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); | ||
472 | |||
473 | smi_cmd.u64 = 0; | ||
474 | smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS; | ||
475 | smi_cmd.s.phy_adr = phy_id; | ||
476 | smi_cmd.s.reg_adr = device; | ||
477 | cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); | ||
478 | |||
479 | do { | ||
480 | cvmx_wait(1000); | ||
481 | smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); | ||
482 | } while (smi_wr.s.pending && --timeout); | ||
483 | if (timeout <= 0) | ||
484 | return -1; | ||
485 | |||
486 | smi_wr.u64 = 0; | ||
487 | smi_wr.s.dat = val; | ||
488 | cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); | ||
489 | |||
490 | smi_cmd.u64 = 0; | ||
491 | smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE; | ||
492 | smi_cmd.s.phy_adr = phy_id; | ||
493 | smi_cmd.s.reg_adr = device; | ||
494 | cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); | ||
495 | |||
496 | do { | ||
497 | cvmx_wait(1000); | ||
498 | smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); | ||
499 | } while (smi_wr.s.pending && --timeout); | ||
500 | if (timeout <= 0) | ||
501 | return -1; | ||
502 | |||
503 | return 0; | ||
504 | } | ||
505 | |||
506 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h new file mode 100644 index 000000000000..62ffe78a8c81 --- /dev/null +++ b/drivers/staging/octeon/cvmx-packet.h | |||
@@ -0,0 +1,65 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * | ||
30 | * Packet buffer defines. | ||
31 | */ | ||
32 | |||
33 | #ifndef __CVMX_PACKET_H__ | ||
34 | #define __CVMX_PACKET_H__ | ||
35 | |||
36 | /** | ||
37 | * This structure defines a buffer pointer on Octeon | ||
38 | */ | ||
39 | union cvmx_buf_ptr { | ||
40 | void *ptr; | ||
41 | uint64_t u64; | ||
42 | struct { | ||
43 | /* | ||
44 | * if set, invert the "free" pick of the overall | ||
45 | * packet. HW always sets this bit to 0 on inbound | ||
46 | * packet | ||
47 | */ | ||
48 | uint64_t i:1; | ||
49 | /* | ||
50 | * Indicates the amount to back up to get to the | ||
51 | * buffer start in cache lines. In most cases this is | ||
52 | * less than one complete cache line, so the value is | ||
53 | * zero. | ||
54 | */ | ||
55 | uint64_t back:4; | ||
56 | /* The pool that the buffer came from / goes to */ | ||
57 | uint64_t pool:3; | ||
58 | /* The size of the segment pointed to by addr (in bytes) */ | ||
59 | uint64_t size:16; | ||
60 | /* Pointer to the first byte of the data, NOT buffer */ | ||
61 | uint64_t addr:40; | ||
62 | } s; | ||
63 | }; | ||
64 | |||
65 | #endif /* __CVMX_PACKET_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/drivers/staging/octeon/cvmx-pcsx-defs.h new file mode 100644 index 000000000000..d45952df5f5b --- /dev/null +++ b/drivers/staging/octeon/cvmx-pcsx-defs.h | |||
@@ -0,0 +1,370 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_PCSX_DEFS_H__ | ||
29 | #define __CVMX_PCSX_DEFS_H__ | ||
30 | |||
31 | #define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \ | ||
32 | CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
33 | #define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \ | ||
34 | CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
35 | #define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \ | ||
36 | CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
37 | #define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \ | ||
38 | CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
39 | #define CVMX_PCSX_INTX_EN_REG(offset, block_id) \ | ||
40 | CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
41 | #define CVMX_PCSX_INTX_REG(offset, block_id) \ | ||
42 | CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
43 | #define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \ | ||
44 | CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
45 | #define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \ | ||
46 | CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
47 | #define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \ | ||
48 | CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
49 | #define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \ | ||
50 | CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
51 | #define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \ | ||
52 | CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
53 | #define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \ | ||
54 | CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
55 | #define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \ | ||
56 | CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
57 | #define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \ | ||
58 | CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
59 | #define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \ | ||
60 | CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
61 | #define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \ | ||
62 | CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
63 | #define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \ | ||
64 | CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) | ||
65 | |||
66 | union cvmx_pcsx_anx_adv_reg { | ||
67 | uint64_t u64; | ||
68 | struct cvmx_pcsx_anx_adv_reg_s { | ||
69 | uint64_t reserved_16_63:48; | ||
70 | uint64_t np:1; | ||
71 | uint64_t reserved_14_14:1; | ||
72 | uint64_t rem_flt:2; | ||
73 | uint64_t reserved_9_11:3; | ||
74 | uint64_t pause:2; | ||
75 | uint64_t hfd:1; | ||
76 | uint64_t fd:1; | ||
77 | uint64_t reserved_0_4:5; | ||
78 | } s; | ||
79 | struct cvmx_pcsx_anx_adv_reg_s cn52xx; | ||
80 | struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; | ||
81 | struct cvmx_pcsx_anx_adv_reg_s cn56xx; | ||
82 | struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; | ||
83 | }; | ||
84 | |||
85 | union cvmx_pcsx_anx_ext_st_reg { | ||
86 | uint64_t u64; | ||
87 | struct cvmx_pcsx_anx_ext_st_reg_s { | ||
88 | uint64_t reserved_16_63:48; | ||
89 | uint64_t thou_xfd:1; | ||
90 | uint64_t thou_xhd:1; | ||
91 | uint64_t thou_tfd:1; | ||
92 | uint64_t thou_thd:1; | ||
93 | uint64_t reserved_0_11:12; | ||
94 | } s; | ||
95 | struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; | ||
96 | struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; | ||
97 | struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; | ||
98 | struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; | ||
99 | }; | ||
100 | |||
101 | union cvmx_pcsx_anx_lp_abil_reg { | ||
102 | uint64_t u64; | ||
103 | struct cvmx_pcsx_anx_lp_abil_reg_s { | ||
104 | uint64_t reserved_16_63:48; | ||
105 | uint64_t np:1; | ||
106 | uint64_t ack:1; | ||
107 | uint64_t rem_flt:2; | ||
108 | uint64_t reserved_9_11:3; | ||
109 | uint64_t pause:2; | ||
110 | uint64_t hfd:1; | ||
111 | uint64_t fd:1; | ||
112 | uint64_t reserved_0_4:5; | ||
113 | } s; | ||
114 | struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; | ||
115 | struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; | ||
116 | struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; | ||
117 | struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; | ||
118 | }; | ||
119 | |||
120 | union cvmx_pcsx_anx_results_reg { | ||
121 | uint64_t u64; | ||
122 | struct cvmx_pcsx_anx_results_reg_s { | ||
123 | uint64_t reserved_7_63:57; | ||
124 | uint64_t pause:2; | ||
125 | uint64_t spd:2; | ||
126 | uint64_t an_cpt:1; | ||
127 | uint64_t dup:1; | ||
128 | uint64_t link_ok:1; | ||
129 | } s; | ||
130 | struct cvmx_pcsx_anx_results_reg_s cn52xx; | ||
131 | struct cvmx_pcsx_anx_results_reg_s cn52xxp1; | ||
132 | struct cvmx_pcsx_anx_results_reg_s cn56xx; | ||
133 | struct cvmx_pcsx_anx_results_reg_s cn56xxp1; | ||
134 | }; | ||
135 | |||
136 | union cvmx_pcsx_intx_en_reg { | ||
137 | uint64_t u64; | ||
138 | struct cvmx_pcsx_intx_en_reg_s { | ||
139 | uint64_t reserved_12_63:52; | ||
140 | uint64_t dup:1; | ||
141 | uint64_t sync_bad_en:1; | ||
142 | uint64_t an_bad_en:1; | ||
143 | uint64_t rxlock_en:1; | ||
144 | uint64_t rxbad_en:1; | ||
145 | uint64_t rxerr_en:1; | ||
146 | uint64_t txbad_en:1; | ||
147 | uint64_t txfifo_en:1; | ||
148 | uint64_t txfifu_en:1; | ||
149 | uint64_t an_err_en:1; | ||
150 | uint64_t xmit_en:1; | ||
151 | uint64_t lnkspd_en:1; | ||
152 | } s; | ||
153 | struct cvmx_pcsx_intx_en_reg_s cn52xx; | ||
154 | struct cvmx_pcsx_intx_en_reg_s cn52xxp1; | ||
155 | struct cvmx_pcsx_intx_en_reg_s cn56xx; | ||
156 | struct cvmx_pcsx_intx_en_reg_s cn56xxp1; | ||
157 | }; | ||
158 | |||
159 | union cvmx_pcsx_intx_reg { | ||
160 | uint64_t u64; | ||
161 | struct cvmx_pcsx_intx_reg_s { | ||
162 | uint64_t reserved_12_63:52; | ||
163 | uint64_t dup:1; | ||
164 | uint64_t sync_bad:1; | ||
165 | uint64_t an_bad:1; | ||
166 | uint64_t rxlock:1; | ||
167 | uint64_t rxbad:1; | ||
168 | uint64_t rxerr:1; | ||
169 | uint64_t txbad:1; | ||
170 | uint64_t txfifo:1; | ||
171 | uint64_t txfifu:1; | ||
172 | uint64_t an_err:1; | ||
173 | uint64_t xmit:1; | ||
174 | uint64_t lnkspd:1; | ||
175 | } s; | ||
176 | struct cvmx_pcsx_intx_reg_s cn52xx; | ||
177 | struct cvmx_pcsx_intx_reg_s cn52xxp1; | ||
178 | struct cvmx_pcsx_intx_reg_s cn56xx; | ||
179 | struct cvmx_pcsx_intx_reg_s cn56xxp1; | ||
180 | }; | ||
181 | |||
182 | union cvmx_pcsx_linkx_timer_count_reg { | ||
183 | uint64_t u64; | ||
184 | struct cvmx_pcsx_linkx_timer_count_reg_s { | ||
185 | uint64_t reserved_16_63:48; | ||
186 | uint64_t count:16; | ||
187 | } s; | ||
188 | struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; | ||
189 | struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; | ||
190 | struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; | ||
191 | struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; | ||
192 | }; | ||
193 | |||
194 | union cvmx_pcsx_log_anlx_reg { | ||
195 | uint64_t u64; | ||
196 | struct cvmx_pcsx_log_anlx_reg_s { | ||
197 | uint64_t reserved_4_63:60; | ||
198 | uint64_t lafifovfl:1; | ||
199 | uint64_t la_en:1; | ||
200 | uint64_t pkt_sz:2; | ||
201 | } s; | ||
202 | struct cvmx_pcsx_log_anlx_reg_s cn52xx; | ||
203 | struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; | ||
204 | struct cvmx_pcsx_log_anlx_reg_s cn56xx; | ||
205 | struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; | ||
206 | }; | ||
207 | |||
208 | union cvmx_pcsx_miscx_ctl_reg { | ||
209 | uint64_t u64; | ||
210 | struct cvmx_pcsx_miscx_ctl_reg_s { | ||
211 | uint64_t reserved_13_63:51; | ||
212 | uint64_t sgmii:1; | ||
213 | uint64_t gmxeno:1; | ||
214 | uint64_t loopbck2:1; | ||
215 | uint64_t mac_phy:1; | ||
216 | uint64_t mode:1; | ||
217 | uint64_t an_ovrd:1; | ||
218 | uint64_t samp_pt:7; | ||
219 | } s; | ||
220 | struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; | ||
221 | struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; | ||
222 | struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; | ||
223 | struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; | ||
224 | }; | ||
225 | |||
226 | union cvmx_pcsx_mrx_control_reg { | ||
227 | uint64_t u64; | ||
228 | struct cvmx_pcsx_mrx_control_reg_s { | ||
229 | uint64_t reserved_16_63:48; | ||
230 | uint64_t reset:1; | ||
231 | uint64_t loopbck1:1; | ||
232 | uint64_t spdlsb:1; | ||
233 | uint64_t an_en:1; | ||
234 | uint64_t pwr_dn:1; | ||
235 | uint64_t reserved_10_10:1; | ||
236 | uint64_t rst_an:1; | ||
237 | uint64_t dup:1; | ||
238 | uint64_t coltst:1; | ||
239 | uint64_t spdmsb:1; | ||
240 | uint64_t uni:1; | ||
241 | uint64_t reserved_0_4:5; | ||
242 | } s; | ||
243 | struct cvmx_pcsx_mrx_control_reg_s cn52xx; | ||
244 | struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; | ||
245 | struct cvmx_pcsx_mrx_control_reg_s cn56xx; | ||
246 | struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; | ||
247 | }; | ||
248 | |||
249 | union cvmx_pcsx_mrx_status_reg { | ||
250 | uint64_t u64; | ||
251 | struct cvmx_pcsx_mrx_status_reg_s { | ||
252 | uint64_t reserved_16_63:48; | ||
253 | uint64_t hun_t4:1; | ||
254 | uint64_t hun_xfd:1; | ||
255 | uint64_t hun_xhd:1; | ||
256 | uint64_t ten_fd:1; | ||
257 | uint64_t ten_hd:1; | ||
258 | uint64_t hun_t2fd:1; | ||
259 | uint64_t hun_t2hd:1; | ||
260 | uint64_t ext_st:1; | ||
261 | uint64_t reserved_7_7:1; | ||
262 | uint64_t prb_sup:1; | ||
263 | uint64_t an_cpt:1; | ||
264 | uint64_t rm_flt:1; | ||
265 | uint64_t an_abil:1; | ||
266 | uint64_t lnk_st:1; | ||
267 | uint64_t reserved_1_1:1; | ||
268 | uint64_t extnd:1; | ||
269 | } s; | ||
270 | struct cvmx_pcsx_mrx_status_reg_s cn52xx; | ||
271 | struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; | ||
272 | struct cvmx_pcsx_mrx_status_reg_s cn56xx; | ||
273 | struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; | ||
274 | }; | ||
275 | |||
276 | union cvmx_pcsx_rxx_states_reg { | ||
277 | uint64_t u64; | ||
278 | struct cvmx_pcsx_rxx_states_reg_s { | ||
279 | uint64_t reserved_16_63:48; | ||
280 | uint64_t rx_bad:1; | ||
281 | uint64_t rx_st:5; | ||
282 | uint64_t sync_bad:1; | ||
283 | uint64_t sync:4; | ||
284 | uint64_t an_bad:1; | ||
285 | uint64_t an_st:4; | ||
286 | } s; | ||
287 | struct cvmx_pcsx_rxx_states_reg_s cn52xx; | ||
288 | struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; | ||
289 | struct cvmx_pcsx_rxx_states_reg_s cn56xx; | ||
290 | struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; | ||
291 | }; | ||
292 | |||
293 | union cvmx_pcsx_rxx_sync_reg { | ||
294 | uint64_t u64; | ||
295 | struct cvmx_pcsx_rxx_sync_reg_s { | ||
296 | uint64_t reserved_2_63:62; | ||
297 | uint64_t sync:1; | ||
298 | uint64_t bit_lock:1; | ||
299 | } s; | ||
300 | struct cvmx_pcsx_rxx_sync_reg_s cn52xx; | ||
301 | struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; | ||
302 | struct cvmx_pcsx_rxx_sync_reg_s cn56xx; | ||
303 | struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; | ||
304 | }; | ||
305 | |||
306 | union cvmx_pcsx_sgmx_an_adv_reg { | ||
307 | uint64_t u64; | ||
308 | struct cvmx_pcsx_sgmx_an_adv_reg_s { | ||
309 | uint64_t reserved_16_63:48; | ||
310 | uint64_t link:1; | ||
311 | uint64_t ack:1; | ||
312 | uint64_t reserved_13_13:1; | ||
313 | uint64_t dup:1; | ||
314 | uint64_t speed:2; | ||
315 | uint64_t reserved_1_9:9; | ||
316 | uint64_t one:1; | ||
317 | } s; | ||
318 | struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; | ||
319 | struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; | ||
320 | struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; | ||
321 | struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; | ||
322 | }; | ||
323 | |||
324 | union cvmx_pcsx_sgmx_lp_adv_reg { | ||
325 | uint64_t u64; | ||
326 | struct cvmx_pcsx_sgmx_lp_adv_reg_s { | ||
327 | uint64_t reserved_16_63:48; | ||
328 | uint64_t link:1; | ||
329 | uint64_t reserved_13_14:2; | ||
330 | uint64_t dup:1; | ||
331 | uint64_t speed:2; | ||
332 | uint64_t reserved_1_9:9; | ||
333 | uint64_t one:1; | ||
334 | } s; | ||
335 | struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; | ||
336 | struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; | ||
337 | struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; | ||
338 | struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; | ||
339 | }; | ||
340 | |||
341 | union cvmx_pcsx_txx_states_reg { | ||
342 | uint64_t u64; | ||
343 | struct cvmx_pcsx_txx_states_reg_s { | ||
344 | uint64_t reserved_7_63:57; | ||
345 | uint64_t xmit:2; | ||
346 | uint64_t tx_bad:1; | ||
347 | uint64_t ord_st:4; | ||
348 | } s; | ||
349 | struct cvmx_pcsx_txx_states_reg_s cn52xx; | ||
350 | struct cvmx_pcsx_txx_states_reg_s cn52xxp1; | ||
351 | struct cvmx_pcsx_txx_states_reg_s cn56xx; | ||
352 | struct cvmx_pcsx_txx_states_reg_s cn56xxp1; | ||
353 | }; | ||
354 | |||
355 | union cvmx_pcsx_tx_rxx_polarity_reg { | ||
356 | uint64_t u64; | ||
357 | struct cvmx_pcsx_tx_rxx_polarity_reg_s { | ||
358 | uint64_t reserved_4_63:60; | ||
359 | uint64_t rxovrd:1; | ||
360 | uint64_t autorxpl:1; | ||
361 | uint64_t rxplrt:1; | ||
362 | uint64_t txplrt:1; | ||
363 | } s; | ||
364 | struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; | ||
365 | struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; | ||
366 | struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; | ||
367 | struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; | ||
368 | }; | ||
369 | |||
370 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/drivers/staging/octeon/cvmx-pcsxx-defs.h new file mode 100644 index 000000000000..55d120fe8aed --- /dev/null +++ b/drivers/staging/octeon/cvmx-pcsxx-defs.h | |||
@@ -0,0 +1,316 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_PCSXX_DEFS_H__ | ||
29 | #define __CVMX_PCSXX_DEFS_H__ | ||
30 | |||
31 | #define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \ | ||
32 | CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull)) | ||
33 | #define CVMX_PCSXX_BIST_STATUS_REG(block_id) \ | ||
34 | CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull)) | ||
35 | #define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \ | ||
36 | CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull)) | ||
37 | #define CVMX_PCSXX_CONTROL1_REG(block_id) \ | ||
38 | CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull)) | ||
39 | #define CVMX_PCSXX_CONTROL2_REG(block_id) \ | ||
40 | CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull)) | ||
41 | #define CVMX_PCSXX_INT_EN_REG(block_id) \ | ||
42 | CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull)) | ||
43 | #define CVMX_PCSXX_INT_REG(block_id) \ | ||
44 | CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull)) | ||
45 | #define CVMX_PCSXX_LOG_ANL_REG(block_id) \ | ||
46 | CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull)) | ||
47 | #define CVMX_PCSXX_MISC_CTL_REG(block_id) \ | ||
48 | CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull)) | ||
49 | #define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \ | ||
50 | CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull)) | ||
51 | #define CVMX_PCSXX_SPD_ABIL_REG(block_id) \ | ||
52 | CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull)) | ||
53 | #define CVMX_PCSXX_STATUS1_REG(block_id) \ | ||
54 | CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull)) | ||
55 | #define CVMX_PCSXX_STATUS2_REG(block_id) \ | ||
56 | CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull)) | ||
57 | #define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \ | ||
58 | CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull)) | ||
59 | #define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \ | ||
60 | CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull)) | ||
61 | |||
62 | union cvmx_pcsxx_10gbx_status_reg { | ||
63 | uint64_t u64; | ||
64 | struct cvmx_pcsxx_10gbx_status_reg_s { | ||
65 | uint64_t reserved_13_63:51; | ||
66 | uint64_t alignd:1; | ||
67 | uint64_t pattst:1; | ||
68 | uint64_t reserved_4_10:7; | ||
69 | uint64_t l3sync:1; | ||
70 | uint64_t l2sync:1; | ||
71 | uint64_t l1sync:1; | ||
72 | uint64_t l0sync:1; | ||
73 | } s; | ||
74 | struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; | ||
75 | struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; | ||
76 | struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; | ||
77 | struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; | ||
78 | }; | ||
79 | |||
80 | union cvmx_pcsxx_bist_status_reg { | ||
81 | uint64_t u64; | ||
82 | struct cvmx_pcsxx_bist_status_reg_s { | ||
83 | uint64_t reserved_1_63:63; | ||
84 | uint64_t bist_status:1; | ||
85 | } s; | ||
86 | struct cvmx_pcsxx_bist_status_reg_s cn52xx; | ||
87 | struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; | ||
88 | struct cvmx_pcsxx_bist_status_reg_s cn56xx; | ||
89 | struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; | ||
90 | }; | ||
91 | |||
92 | union cvmx_pcsxx_bit_lock_status_reg { | ||
93 | uint64_t u64; | ||
94 | struct cvmx_pcsxx_bit_lock_status_reg_s { | ||
95 | uint64_t reserved_4_63:60; | ||
96 | uint64_t bitlck3:1; | ||
97 | uint64_t bitlck2:1; | ||
98 | uint64_t bitlck1:1; | ||
99 | uint64_t bitlck0:1; | ||
100 | } s; | ||
101 | struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; | ||
102 | struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; | ||
103 | struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; | ||
104 | struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; | ||
105 | }; | ||
106 | |||
107 | union cvmx_pcsxx_control1_reg { | ||
108 | uint64_t u64; | ||
109 | struct cvmx_pcsxx_control1_reg_s { | ||
110 | uint64_t reserved_16_63:48; | ||
111 | uint64_t reset:1; | ||
112 | uint64_t loopbck1:1; | ||
113 | uint64_t spdsel1:1; | ||
114 | uint64_t reserved_12_12:1; | ||
115 | uint64_t lo_pwr:1; | ||
116 | uint64_t reserved_7_10:4; | ||
117 | uint64_t spdsel0:1; | ||
118 | uint64_t spd:4; | ||
119 | uint64_t reserved_0_1:2; | ||
120 | } s; | ||
121 | struct cvmx_pcsxx_control1_reg_s cn52xx; | ||
122 | struct cvmx_pcsxx_control1_reg_s cn52xxp1; | ||
123 | struct cvmx_pcsxx_control1_reg_s cn56xx; | ||
124 | struct cvmx_pcsxx_control1_reg_s cn56xxp1; | ||
125 | }; | ||
126 | |||
127 | union cvmx_pcsxx_control2_reg { | ||
128 | uint64_t u64; | ||
129 | struct cvmx_pcsxx_control2_reg_s { | ||
130 | uint64_t reserved_2_63:62; | ||
131 | uint64_t type:2; | ||
132 | } s; | ||
133 | struct cvmx_pcsxx_control2_reg_s cn52xx; | ||
134 | struct cvmx_pcsxx_control2_reg_s cn52xxp1; | ||
135 | struct cvmx_pcsxx_control2_reg_s cn56xx; | ||
136 | struct cvmx_pcsxx_control2_reg_s cn56xxp1; | ||
137 | }; | ||
138 | |||
139 | union cvmx_pcsxx_int_en_reg { | ||
140 | uint64_t u64; | ||
141 | struct cvmx_pcsxx_int_en_reg_s { | ||
142 | uint64_t reserved_6_63:58; | ||
143 | uint64_t algnlos_en:1; | ||
144 | uint64_t synlos_en:1; | ||
145 | uint64_t bitlckls_en:1; | ||
146 | uint64_t rxsynbad_en:1; | ||
147 | uint64_t rxbad_en:1; | ||
148 | uint64_t txflt_en:1; | ||
149 | } s; | ||
150 | struct cvmx_pcsxx_int_en_reg_s cn52xx; | ||
151 | struct cvmx_pcsxx_int_en_reg_s cn52xxp1; | ||
152 | struct cvmx_pcsxx_int_en_reg_s cn56xx; | ||
153 | struct cvmx_pcsxx_int_en_reg_s cn56xxp1; | ||
154 | }; | ||
155 | |||
156 | union cvmx_pcsxx_int_reg { | ||
157 | uint64_t u64; | ||
158 | struct cvmx_pcsxx_int_reg_s { | ||
159 | uint64_t reserved_6_63:58; | ||
160 | uint64_t algnlos:1; | ||
161 | uint64_t synlos:1; | ||
162 | uint64_t bitlckls:1; | ||
163 | uint64_t rxsynbad:1; | ||
164 | uint64_t rxbad:1; | ||
165 | uint64_t txflt:1; | ||
166 | } s; | ||
167 | struct cvmx_pcsxx_int_reg_s cn52xx; | ||
168 | struct cvmx_pcsxx_int_reg_s cn52xxp1; | ||
169 | struct cvmx_pcsxx_int_reg_s cn56xx; | ||
170 | struct cvmx_pcsxx_int_reg_s cn56xxp1; | ||
171 | }; | ||
172 | |||
173 | union cvmx_pcsxx_log_anl_reg { | ||
174 | uint64_t u64; | ||
175 | struct cvmx_pcsxx_log_anl_reg_s { | ||
176 | uint64_t reserved_7_63:57; | ||
177 | uint64_t enc_mode:1; | ||
178 | uint64_t drop_ln:2; | ||
179 | uint64_t lafifovfl:1; | ||
180 | uint64_t la_en:1; | ||
181 | uint64_t pkt_sz:2; | ||
182 | } s; | ||
183 | struct cvmx_pcsxx_log_anl_reg_s cn52xx; | ||
184 | struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; | ||
185 | struct cvmx_pcsxx_log_anl_reg_s cn56xx; | ||
186 | struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; | ||
187 | }; | ||
188 | |||
189 | union cvmx_pcsxx_misc_ctl_reg { | ||
190 | uint64_t u64; | ||
191 | struct cvmx_pcsxx_misc_ctl_reg_s { | ||
192 | uint64_t reserved_4_63:60; | ||
193 | uint64_t tx_swap:1; | ||
194 | uint64_t rx_swap:1; | ||
195 | uint64_t xaui:1; | ||
196 | uint64_t gmxeno:1; | ||
197 | } s; | ||
198 | struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; | ||
199 | struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; | ||
200 | struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; | ||
201 | struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; | ||
202 | }; | ||
203 | |||
204 | union cvmx_pcsxx_rx_sync_states_reg { | ||
205 | uint64_t u64; | ||
206 | struct cvmx_pcsxx_rx_sync_states_reg_s { | ||
207 | uint64_t reserved_16_63:48; | ||
208 | uint64_t sync3st:4; | ||
209 | uint64_t sync2st:4; | ||
210 | uint64_t sync1st:4; | ||
211 | uint64_t sync0st:4; | ||
212 | } s; | ||
213 | struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; | ||
214 | struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; | ||
215 | struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; | ||
216 | struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; | ||
217 | }; | ||
218 | |||
219 | union cvmx_pcsxx_spd_abil_reg { | ||
220 | uint64_t u64; | ||
221 | struct cvmx_pcsxx_spd_abil_reg_s { | ||
222 | uint64_t reserved_2_63:62; | ||
223 | uint64_t tenpasst:1; | ||
224 | uint64_t tengb:1; | ||
225 | } s; | ||
226 | struct cvmx_pcsxx_spd_abil_reg_s cn52xx; | ||
227 | struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; | ||
228 | struct cvmx_pcsxx_spd_abil_reg_s cn56xx; | ||
229 | struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; | ||
230 | }; | ||
231 | |||
232 | union cvmx_pcsxx_status1_reg { | ||
233 | uint64_t u64; | ||
234 | struct cvmx_pcsxx_status1_reg_s { | ||
235 | uint64_t reserved_8_63:56; | ||
236 | uint64_t flt:1; | ||
237 | uint64_t reserved_3_6:4; | ||
238 | uint64_t rcv_lnk:1; | ||
239 | uint64_t lpable:1; | ||
240 | uint64_t reserved_0_0:1; | ||
241 | } s; | ||
242 | struct cvmx_pcsxx_status1_reg_s cn52xx; | ||
243 | struct cvmx_pcsxx_status1_reg_s cn52xxp1; | ||
244 | struct cvmx_pcsxx_status1_reg_s cn56xx; | ||
245 | struct cvmx_pcsxx_status1_reg_s cn56xxp1; | ||
246 | }; | ||
247 | |||
248 | union cvmx_pcsxx_status2_reg { | ||
249 | uint64_t u64; | ||
250 | struct cvmx_pcsxx_status2_reg_s { | ||
251 | uint64_t reserved_16_63:48; | ||
252 | uint64_t dev:2; | ||
253 | uint64_t reserved_12_13:2; | ||
254 | uint64_t xmtflt:1; | ||
255 | uint64_t rcvflt:1; | ||
256 | uint64_t reserved_3_9:7; | ||
257 | uint64_t tengb_w:1; | ||
258 | uint64_t tengb_x:1; | ||
259 | uint64_t tengb_r:1; | ||
260 | } s; | ||
261 | struct cvmx_pcsxx_status2_reg_s cn52xx; | ||
262 | struct cvmx_pcsxx_status2_reg_s cn52xxp1; | ||
263 | struct cvmx_pcsxx_status2_reg_s cn56xx; | ||
264 | struct cvmx_pcsxx_status2_reg_s cn56xxp1; | ||
265 | }; | ||
266 | |||
267 | union cvmx_pcsxx_tx_rx_polarity_reg { | ||
268 | uint64_t u64; | ||
269 | struct cvmx_pcsxx_tx_rx_polarity_reg_s { | ||
270 | uint64_t reserved_10_63:54; | ||
271 | uint64_t xor_rxplrt:4; | ||
272 | uint64_t xor_txplrt:4; | ||
273 | uint64_t rxplrt:1; | ||
274 | uint64_t txplrt:1; | ||
275 | } s; | ||
276 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; | ||
277 | struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { | ||
278 | uint64_t reserved_2_63:62; | ||
279 | uint64_t rxplrt:1; | ||
280 | uint64_t txplrt:1; | ||
281 | } cn52xxp1; | ||
282 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; | ||
283 | struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; | ||
284 | }; | ||
285 | |||
286 | union cvmx_pcsxx_tx_rx_states_reg { | ||
287 | uint64_t u64; | ||
288 | struct cvmx_pcsxx_tx_rx_states_reg_s { | ||
289 | uint64_t reserved_14_63:50; | ||
290 | uint64_t term_err:1; | ||
291 | uint64_t syn3bad:1; | ||
292 | uint64_t syn2bad:1; | ||
293 | uint64_t syn1bad:1; | ||
294 | uint64_t syn0bad:1; | ||
295 | uint64_t rxbad:1; | ||
296 | uint64_t algn_st:3; | ||
297 | uint64_t rx_st:2; | ||
298 | uint64_t tx_st:3; | ||
299 | } s; | ||
300 | struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; | ||
301 | struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { | ||
302 | uint64_t reserved_13_63:51; | ||
303 | uint64_t syn3bad:1; | ||
304 | uint64_t syn2bad:1; | ||
305 | uint64_t syn1bad:1; | ||
306 | uint64_t syn0bad:1; | ||
307 | uint64_t rxbad:1; | ||
308 | uint64_t algn_st:3; | ||
309 | uint64_t rx_st:2; | ||
310 | uint64_t tx_st:3; | ||
311 | } cn52xxp1; | ||
312 | struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; | ||
313 | struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; | ||
314 | }; | ||
315 | |||
316 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/drivers/staging/octeon/cvmx-pip-defs.h new file mode 100644 index 000000000000..5a369100ca68 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pip-defs.h | |||
@@ -0,0 +1,1267 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_PIP_DEFS_H__ | ||
29 | #define __CVMX_PIP_DEFS_H__ | ||
30 | |||
31 | /* | ||
32 | * Enumeration representing the amount of packet processing | ||
33 | * and validation performed by the input hardware. | ||
34 | */ | ||
35 | enum cvmx_pip_port_parse_mode { | ||
36 | /* | ||
37 | * Packet input doesn't perform any processing of the input | ||
38 | * packet. | ||
39 | */ | ||
40 | CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, | ||
41 | /* | ||
42 | * Full packet processing is performed with pointer starting | ||
43 | * at the L2 (ethernet MAC) header. | ||
44 | */ | ||
45 | CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull, | ||
46 | /* | ||
47 | * Input packets are assumed to be IP. Results from non IP | ||
48 | * packets is undefined. Pointers reference the beginning of | ||
49 | * the IP header. | ||
50 | */ | ||
51 | CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull | ||
52 | }; | ||
53 | |||
54 | #define CVMX_PIP_BCK_PRS \ | ||
55 | CVMX_ADD_IO_SEG(0x00011800A0000038ull) | ||
56 | #define CVMX_PIP_BIST_STATUS \ | ||
57 | CVMX_ADD_IO_SEG(0x00011800A0000000ull) | ||
58 | #define CVMX_PIP_CRC_CTLX(offset) \ | ||
59 | CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8)) | ||
60 | #define CVMX_PIP_CRC_IVX(offset) \ | ||
61 | CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8)) | ||
62 | #define CVMX_PIP_DEC_IPSECX(offset) \ | ||
63 | CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8)) | ||
64 | #define CVMX_PIP_DSA_SRC_GRP \ | ||
65 | CVMX_ADD_IO_SEG(0x00011800A0000190ull) | ||
66 | #define CVMX_PIP_DSA_VID_GRP \ | ||
67 | CVMX_ADD_IO_SEG(0x00011800A0000198ull) | ||
68 | #define CVMX_PIP_FRM_LEN_CHKX(offset) \ | ||
69 | CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8)) | ||
70 | #define CVMX_PIP_GBL_CFG \ | ||
71 | CVMX_ADD_IO_SEG(0x00011800A0000028ull) | ||
72 | #define CVMX_PIP_GBL_CTL \ | ||
73 | CVMX_ADD_IO_SEG(0x00011800A0000020ull) | ||
74 | #define CVMX_PIP_HG_PRI_QOS \ | ||
75 | CVMX_ADD_IO_SEG(0x00011800A00001A0ull) | ||
76 | #define CVMX_PIP_INT_EN \ | ||
77 | CVMX_ADD_IO_SEG(0x00011800A0000010ull) | ||
78 | #define CVMX_PIP_INT_REG \ | ||
79 | CVMX_ADD_IO_SEG(0x00011800A0000008ull) | ||
80 | #define CVMX_PIP_IP_OFFSET \ | ||
81 | CVMX_ADD_IO_SEG(0x00011800A0000060ull) | ||
82 | #define CVMX_PIP_PRT_CFGX(offset) \ | ||
83 | CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8)) | ||
84 | #define CVMX_PIP_PRT_TAGX(offset) \ | ||
85 | CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8)) | ||
86 | #define CVMX_PIP_QOS_DIFFX(offset) \ | ||
87 | CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8)) | ||
88 | #define CVMX_PIP_QOS_VLANX(offset) \ | ||
89 | CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8)) | ||
90 | #define CVMX_PIP_QOS_WATCHX(offset) \ | ||
91 | CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8)) | ||
92 | #define CVMX_PIP_RAW_WORD \ | ||
93 | CVMX_ADD_IO_SEG(0x00011800A00000B0ull) | ||
94 | #define CVMX_PIP_SFT_RST \ | ||
95 | CVMX_ADD_IO_SEG(0x00011800A0000030ull) | ||
96 | #define CVMX_PIP_STAT0_PRTX(offset) \ | ||
97 | CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80)) | ||
98 | #define CVMX_PIP_STAT1_PRTX(offset) \ | ||
99 | CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80)) | ||
100 | #define CVMX_PIP_STAT2_PRTX(offset) \ | ||
101 | CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80)) | ||
102 | #define CVMX_PIP_STAT3_PRTX(offset) \ | ||
103 | CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80)) | ||
104 | #define CVMX_PIP_STAT4_PRTX(offset) \ | ||
105 | CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80)) | ||
106 | #define CVMX_PIP_STAT5_PRTX(offset) \ | ||
107 | CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80)) | ||
108 | #define CVMX_PIP_STAT6_PRTX(offset) \ | ||
109 | CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80)) | ||
110 | #define CVMX_PIP_STAT7_PRTX(offset) \ | ||
111 | CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80)) | ||
112 | #define CVMX_PIP_STAT8_PRTX(offset) \ | ||
113 | CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80)) | ||
114 | #define CVMX_PIP_STAT9_PRTX(offset) \ | ||
115 | CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80)) | ||
116 | #define CVMX_PIP_STAT_CTL \ | ||
117 | CVMX_ADD_IO_SEG(0x00011800A0000018ull) | ||
118 | #define CVMX_PIP_STAT_INB_ERRSX(offset) \ | ||
119 | CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32)) | ||
120 | #define CVMX_PIP_STAT_INB_OCTSX(offset) \ | ||
121 | CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32)) | ||
122 | #define CVMX_PIP_STAT_INB_PKTSX(offset) \ | ||
123 | CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32)) | ||
124 | #define CVMX_PIP_TAG_INCX(offset) \ | ||
125 | CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8)) | ||
126 | #define CVMX_PIP_TAG_MASK \ | ||
127 | CVMX_ADD_IO_SEG(0x00011800A0000070ull) | ||
128 | #define CVMX_PIP_TAG_SECRET \ | ||
129 | CVMX_ADD_IO_SEG(0x00011800A0000068ull) | ||
130 | #define CVMX_PIP_TODO_ENTRY \ | ||
131 | CVMX_ADD_IO_SEG(0x00011800A0000078ull) | ||
132 | |||
133 | union cvmx_pip_bck_prs { | ||
134 | uint64_t u64; | ||
135 | struct cvmx_pip_bck_prs_s { | ||
136 | uint64_t bckprs:1; | ||
137 | uint64_t reserved_13_62:50; | ||
138 | uint64_t hiwater:5; | ||
139 | uint64_t reserved_5_7:3; | ||
140 | uint64_t lowater:5; | ||
141 | } s; | ||
142 | struct cvmx_pip_bck_prs_s cn38xx; | ||
143 | struct cvmx_pip_bck_prs_s cn38xxp2; | ||
144 | struct cvmx_pip_bck_prs_s cn56xx; | ||
145 | struct cvmx_pip_bck_prs_s cn56xxp1; | ||
146 | struct cvmx_pip_bck_prs_s cn58xx; | ||
147 | struct cvmx_pip_bck_prs_s cn58xxp1; | ||
148 | }; | ||
149 | |||
150 | union cvmx_pip_bist_status { | ||
151 | uint64_t u64; | ||
152 | struct cvmx_pip_bist_status_s { | ||
153 | uint64_t reserved_18_63:46; | ||
154 | uint64_t bist:18; | ||
155 | } s; | ||
156 | struct cvmx_pip_bist_status_s cn30xx; | ||
157 | struct cvmx_pip_bist_status_s cn31xx; | ||
158 | struct cvmx_pip_bist_status_s cn38xx; | ||
159 | struct cvmx_pip_bist_status_s cn38xxp2; | ||
160 | struct cvmx_pip_bist_status_cn50xx { | ||
161 | uint64_t reserved_17_63:47; | ||
162 | uint64_t bist:17; | ||
163 | } cn50xx; | ||
164 | struct cvmx_pip_bist_status_s cn52xx; | ||
165 | struct cvmx_pip_bist_status_s cn52xxp1; | ||
166 | struct cvmx_pip_bist_status_s cn56xx; | ||
167 | struct cvmx_pip_bist_status_s cn56xxp1; | ||
168 | struct cvmx_pip_bist_status_s cn58xx; | ||
169 | struct cvmx_pip_bist_status_s cn58xxp1; | ||
170 | }; | ||
171 | |||
172 | union cvmx_pip_crc_ctlx { | ||
173 | uint64_t u64; | ||
174 | struct cvmx_pip_crc_ctlx_s { | ||
175 | uint64_t reserved_2_63:62; | ||
176 | uint64_t invres:1; | ||
177 | uint64_t reflect:1; | ||
178 | } s; | ||
179 | struct cvmx_pip_crc_ctlx_s cn38xx; | ||
180 | struct cvmx_pip_crc_ctlx_s cn38xxp2; | ||
181 | struct cvmx_pip_crc_ctlx_s cn58xx; | ||
182 | struct cvmx_pip_crc_ctlx_s cn58xxp1; | ||
183 | }; | ||
184 | |||
185 | union cvmx_pip_crc_ivx { | ||
186 | uint64_t u64; | ||
187 | struct cvmx_pip_crc_ivx_s { | ||
188 | uint64_t reserved_32_63:32; | ||
189 | uint64_t iv:32; | ||
190 | } s; | ||
191 | struct cvmx_pip_crc_ivx_s cn38xx; | ||
192 | struct cvmx_pip_crc_ivx_s cn38xxp2; | ||
193 | struct cvmx_pip_crc_ivx_s cn58xx; | ||
194 | struct cvmx_pip_crc_ivx_s cn58xxp1; | ||
195 | }; | ||
196 | |||
197 | union cvmx_pip_dec_ipsecx { | ||
198 | uint64_t u64; | ||
199 | struct cvmx_pip_dec_ipsecx_s { | ||
200 | uint64_t reserved_18_63:46; | ||
201 | uint64_t tcp:1; | ||
202 | uint64_t udp:1; | ||
203 | uint64_t dprt:16; | ||
204 | } s; | ||
205 | struct cvmx_pip_dec_ipsecx_s cn30xx; | ||
206 | struct cvmx_pip_dec_ipsecx_s cn31xx; | ||
207 | struct cvmx_pip_dec_ipsecx_s cn38xx; | ||
208 | struct cvmx_pip_dec_ipsecx_s cn38xxp2; | ||
209 | struct cvmx_pip_dec_ipsecx_s cn50xx; | ||
210 | struct cvmx_pip_dec_ipsecx_s cn52xx; | ||
211 | struct cvmx_pip_dec_ipsecx_s cn52xxp1; | ||
212 | struct cvmx_pip_dec_ipsecx_s cn56xx; | ||
213 | struct cvmx_pip_dec_ipsecx_s cn56xxp1; | ||
214 | struct cvmx_pip_dec_ipsecx_s cn58xx; | ||
215 | struct cvmx_pip_dec_ipsecx_s cn58xxp1; | ||
216 | }; | ||
217 | |||
218 | union cvmx_pip_dsa_src_grp { | ||
219 | uint64_t u64; | ||
220 | struct cvmx_pip_dsa_src_grp_s { | ||
221 | uint64_t map15:4; | ||
222 | uint64_t map14:4; | ||
223 | uint64_t map13:4; | ||
224 | uint64_t map12:4; | ||
225 | uint64_t map11:4; | ||
226 | uint64_t map10:4; | ||
227 | uint64_t map9:4; | ||
228 | uint64_t map8:4; | ||
229 | uint64_t map7:4; | ||
230 | uint64_t map6:4; | ||
231 | uint64_t map5:4; | ||
232 | uint64_t map4:4; | ||
233 | uint64_t map3:4; | ||
234 | uint64_t map2:4; | ||
235 | uint64_t map1:4; | ||
236 | uint64_t map0:4; | ||
237 | } s; | ||
238 | struct cvmx_pip_dsa_src_grp_s cn52xx; | ||
239 | struct cvmx_pip_dsa_src_grp_s cn52xxp1; | ||
240 | struct cvmx_pip_dsa_src_grp_s cn56xx; | ||
241 | }; | ||
242 | |||
243 | union cvmx_pip_dsa_vid_grp { | ||
244 | uint64_t u64; | ||
245 | struct cvmx_pip_dsa_vid_grp_s { | ||
246 | uint64_t map15:4; | ||
247 | uint64_t map14:4; | ||
248 | uint64_t map13:4; | ||
249 | uint64_t map12:4; | ||
250 | uint64_t map11:4; | ||
251 | uint64_t map10:4; | ||
252 | uint64_t map9:4; | ||
253 | uint64_t map8:4; | ||
254 | uint64_t map7:4; | ||
255 | uint64_t map6:4; | ||
256 | uint64_t map5:4; | ||
257 | uint64_t map4:4; | ||
258 | uint64_t map3:4; | ||
259 | uint64_t map2:4; | ||
260 | uint64_t map1:4; | ||
261 | uint64_t map0:4; | ||
262 | } s; | ||
263 | struct cvmx_pip_dsa_vid_grp_s cn52xx; | ||
264 | struct cvmx_pip_dsa_vid_grp_s cn52xxp1; | ||
265 | struct cvmx_pip_dsa_vid_grp_s cn56xx; | ||
266 | }; | ||
267 | |||
268 | union cvmx_pip_frm_len_chkx { | ||
269 | uint64_t u64; | ||
270 | struct cvmx_pip_frm_len_chkx_s { | ||
271 | uint64_t reserved_32_63:32; | ||
272 | uint64_t maxlen:16; | ||
273 | uint64_t minlen:16; | ||
274 | } s; | ||
275 | struct cvmx_pip_frm_len_chkx_s cn50xx; | ||
276 | struct cvmx_pip_frm_len_chkx_s cn52xx; | ||
277 | struct cvmx_pip_frm_len_chkx_s cn52xxp1; | ||
278 | struct cvmx_pip_frm_len_chkx_s cn56xx; | ||
279 | struct cvmx_pip_frm_len_chkx_s cn56xxp1; | ||
280 | }; | ||
281 | |||
282 | union cvmx_pip_gbl_cfg { | ||
283 | uint64_t u64; | ||
284 | struct cvmx_pip_gbl_cfg_s { | ||
285 | uint64_t reserved_19_63:45; | ||
286 | uint64_t tag_syn:1; | ||
287 | uint64_t ip6_udp:1; | ||
288 | uint64_t max_l2:1; | ||
289 | uint64_t reserved_11_15:5; | ||
290 | uint64_t raw_shf:3; | ||
291 | uint64_t reserved_3_7:5; | ||
292 | uint64_t nip_shf:3; | ||
293 | } s; | ||
294 | struct cvmx_pip_gbl_cfg_s cn30xx; | ||
295 | struct cvmx_pip_gbl_cfg_s cn31xx; | ||
296 | struct cvmx_pip_gbl_cfg_s cn38xx; | ||
297 | struct cvmx_pip_gbl_cfg_s cn38xxp2; | ||
298 | struct cvmx_pip_gbl_cfg_s cn50xx; | ||
299 | struct cvmx_pip_gbl_cfg_s cn52xx; | ||
300 | struct cvmx_pip_gbl_cfg_s cn52xxp1; | ||
301 | struct cvmx_pip_gbl_cfg_s cn56xx; | ||
302 | struct cvmx_pip_gbl_cfg_s cn56xxp1; | ||
303 | struct cvmx_pip_gbl_cfg_s cn58xx; | ||
304 | struct cvmx_pip_gbl_cfg_s cn58xxp1; | ||
305 | }; | ||
306 | |||
307 | union cvmx_pip_gbl_ctl { | ||
308 | uint64_t u64; | ||
309 | struct cvmx_pip_gbl_ctl_s { | ||
310 | uint64_t reserved_27_63:37; | ||
311 | uint64_t dsa_grp_tvid:1; | ||
312 | uint64_t dsa_grp_scmd:1; | ||
313 | uint64_t dsa_grp_sid:1; | ||
314 | uint64_t reserved_21_23:3; | ||
315 | uint64_t ring_en:1; | ||
316 | uint64_t reserved_17_19:3; | ||
317 | uint64_t ignrs:1; | ||
318 | uint64_t vs_wqe:1; | ||
319 | uint64_t vs_qos:1; | ||
320 | uint64_t l2_mal:1; | ||
321 | uint64_t tcp_flag:1; | ||
322 | uint64_t l4_len:1; | ||
323 | uint64_t l4_chk:1; | ||
324 | uint64_t l4_prt:1; | ||
325 | uint64_t l4_mal:1; | ||
326 | uint64_t reserved_6_7:2; | ||
327 | uint64_t ip6_eext:2; | ||
328 | uint64_t ip4_opts:1; | ||
329 | uint64_t ip_hop:1; | ||
330 | uint64_t ip_mal:1; | ||
331 | uint64_t ip_chk:1; | ||
332 | } s; | ||
333 | struct cvmx_pip_gbl_ctl_cn30xx { | ||
334 | uint64_t reserved_17_63:47; | ||
335 | uint64_t ignrs:1; | ||
336 | uint64_t vs_wqe:1; | ||
337 | uint64_t vs_qos:1; | ||
338 | uint64_t l2_mal:1; | ||
339 | uint64_t tcp_flag:1; | ||
340 | uint64_t l4_len:1; | ||
341 | uint64_t l4_chk:1; | ||
342 | uint64_t l4_prt:1; | ||
343 | uint64_t l4_mal:1; | ||
344 | uint64_t reserved_6_7:2; | ||
345 | uint64_t ip6_eext:2; | ||
346 | uint64_t ip4_opts:1; | ||
347 | uint64_t ip_hop:1; | ||
348 | uint64_t ip_mal:1; | ||
349 | uint64_t ip_chk:1; | ||
350 | } cn30xx; | ||
351 | struct cvmx_pip_gbl_ctl_cn30xx cn31xx; | ||
352 | struct cvmx_pip_gbl_ctl_cn30xx cn38xx; | ||
353 | struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2; | ||
354 | struct cvmx_pip_gbl_ctl_cn30xx cn50xx; | ||
355 | struct cvmx_pip_gbl_ctl_s cn52xx; | ||
356 | struct cvmx_pip_gbl_ctl_s cn52xxp1; | ||
357 | struct cvmx_pip_gbl_ctl_s cn56xx; | ||
358 | struct cvmx_pip_gbl_ctl_cn56xxp1 { | ||
359 | uint64_t reserved_21_63:43; | ||
360 | uint64_t ring_en:1; | ||
361 | uint64_t reserved_17_19:3; | ||
362 | uint64_t ignrs:1; | ||
363 | uint64_t vs_wqe:1; | ||
364 | uint64_t vs_qos:1; | ||
365 | uint64_t l2_mal:1; | ||
366 | uint64_t tcp_flag:1; | ||
367 | uint64_t l4_len:1; | ||
368 | uint64_t l4_chk:1; | ||
369 | uint64_t l4_prt:1; | ||
370 | uint64_t l4_mal:1; | ||
371 | uint64_t reserved_6_7:2; | ||
372 | uint64_t ip6_eext:2; | ||
373 | uint64_t ip4_opts:1; | ||
374 | uint64_t ip_hop:1; | ||
375 | uint64_t ip_mal:1; | ||
376 | uint64_t ip_chk:1; | ||
377 | } cn56xxp1; | ||
378 | struct cvmx_pip_gbl_ctl_cn30xx cn58xx; | ||
379 | struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1; | ||
380 | }; | ||
381 | |||
382 | union cvmx_pip_hg_pri_qos { | ||
383 | uint64_t u64; | ||
384 | struct cvmx_pip_hg_pri_qos_s { | ||
385 | uint64_t reserved_11_63:53; | ||
386 | uint64_t qos:3; | ||
387 | uint64_t reserved_6_7:2; | ||
388 | uint64_t pri:6; | ||
389 | } s; | ||
390 | struct cvmx_pip_hg_pri_qos_s cn52xx; | ||
391 | struct cvmx_pip_hg_pri_qos_s cn52xxp1; | ||
392 | struct cvmx_pip_hg_pri_qos_s cn56xx; | ||
393 | }; | ||
394 | |||
395 | union cvmx_pip_int_en { | ||
396 | uint64_t u64; | ||
397 | struct cvmx_pip_int_en_s { | ||
398 | uint64_t reserved_13_63:51; | ||
399 | uint64_t punyerr:1; | ||
400 | uint64_t lenerr:1; | ||
401 | uint64_t maxerr:1; | ||
402 | uint64_t minerr:1; | ||
403 | uint64_t beperr:1; | ||
404 | uint64_t feperr:1; | ||
405 | uint64_t todoovr:1; | ||
406 | uint64_t skprunt:1; | ||
407 | uint64_t badtag:1; | ||
408 | uint64_t prtnxa:1; | ||
409 | uint64_t bckprs:1; | ||
410 | uint64_t crcerr:1; | ||
411 | uint64_t pktdrp:1; | ||
412 | } s; | ||
413 | struct cvmx_pip_int_en_cn30xx { | ||
414 | uint64_t reserved_9_63:55; | ||
415 | uint64_t beperr:1; | ||
416 | uint64_t feperr:1; | ||
417 | uint64_t todoovr:1; | ||
418 | uint64_t skprunt:1; | ||
419 | uint64_t badtag:1; | ||
420 | uint64_t prtnxa:1; | ||
421 | uint64_t bckprs:1; | ||
422 | uint64_t crcerr:1; | ||
423 | uint64_t pktdrp:1; | ||
424 | } cn30xx; | ||
425 | struct cvmx_pip_int_en_cn30xx cn31xx; | ||
426 | struct cvmx_pip_int_en_cn30xx cn38xx; | ||
427 | struct cvmx_pip_int_en_cn30xx cn38xxp2; | ||
428 | struct cvmx_pip_int_en_cn50xx { | ||
429 | uint64_t reserved_12_63:52; | ||
430 | uint64_t lenerr:1; | ||
431 | uint64_t maxerr:1; | ||
432 | uint64_t minerr:1; | ||
433 | uint64_t beperr:1; | ||
434 | uint64_t feperr:1; | ||
435 | uint64_t todoovr:1; | ||
436 | uint64_t skprunt:1; | ||
437 | uint64_t badtag:1; | ||
438 | uint64_t prtnxa:1; | ||
439 | uint64_t bckprs:1; | ||
440 | uint64_t reserved_1_1:1; | ||
441 | uint64_t pktdrp:1; | ||
442 | } cn50xx; | ||
443 | struct cvmx_pip_int_en_cn52xx { | ||
444 | uint64_t reserved_13_63:51; | ||
445 | uint64_t punyerr:1; | ||
446 | uint64_t lenerr:1; | ||
447 | uint64_t maxerr:1; | ||
448 | uint64_t minerr:1; | ||
449 | uint64_t beperr:1; | ||
450 | uint64_t feperr:1; | ||
451 | uint64_t todoovr:1; | ||
452 | uint64_t skprunt:1; | ||
453 | uint64_t badtag:1; | ||
454 | uint64_t prtnxa:1; | ||
455 | uint64_t bckprs:1; | ||
456 | uint64_t reserved_1_1:1; | ||
457 | uint64_t pktdrp:1; | ||
458 | } cn52xx; | ||
459 | struct cvmx_pip_int_en_cn52xx cn52xxp1; | ||
460 | struct cvmx_pip_int_en_s cn56xx; | ||
461 | struct cvmx_pip_int_en_cn56xxp1 { | ||
462 | uint64_t reserved_12_63:52; | ||
463 | uint64_t lenerr:1; | ||
464 | uint64_t maxerr:1; | ||
465 | uint64_t minerr:1; | ||
466 | uint64_t beperr:1; | ||
467 | uint64_t feperr:1; | ||
468 | uint64_t todoovr:1; | ||
469 | uint64_t skprunt:1; | ||
470 | uint64_t badtag:1; | ||
471 | uint64_t prtnxa:1; | ||
472 | uint64_t bckprs:1; | ||
473 | uint64_t crcerr:1; | ||
474 | uint64_t pktdrp:1; | ||
475 | } cn56xxp1; | ||
476 | struct cvmx_pip_int_en_cn58xx { | ||
477 | uint64_t reserved_13_63:51; | ||
478 | uint64_t punyerr:1; | ||
479 | uint64_t reserved_9_11:3; | ||
480 | uint64_t beperr:1; | ||
481 | uint64_t feperr:1; | ||
482 | uint64_t todoovr:1; | ||
483 | uint64_t skprunt:1; | ||
484 | uint64_t badtag:1; | ||
485 | uint64_t prtnxa:1; | ||
486 | uint64_t bckprs:1; | ||
487 | uint64_t crcerr:1; | ||
488 | uint64_t pktdrp:1; | ||
489 | } cn58xx; | ||
490 | struct cvmx_pip_int_en_cn30xx cn58xxp1; | ||
491 | }; | ||
492 | |||
493 | union cvmx_pip_int_reg { | ||
494 | uint64_t u64; | ||
495 | struct cvmx_pip_int_reg_s { | ||
496 | uint64_t reserved_13_63:51; | ||
497 | uint64_t punyerr:1; | ||
498 | uint64_t lenerr:1; | ||
499 | uint64_t maxerr:1; | ||
500 | uint64_t minerr:1; | ||
501 | uint64_t beperr:1; | ||
502 | uint64_t feperr:1; | ||
503 | uint64_t todoovr:1; | ||
504 | uint64_t skprunt:1; | ||
505 | uint64_t badtag:1; | ||
506 | uint64_t prtnxa:1; | ||
507 | uint64_t bckprs:1; | ||
508 | uint64_t crcerr:1; | ||
509 | uint64_t pktdrp:1; | ||
510 | } s; | ||
511 | struct cvmx_pip_int_reg_cn30xx { | ||
512 | uint64_t reserved_9_63:55; | ||
513 | uint64_t beperr:1; | ||
514 | uint64_t feperr:1; | ||
515 | uint64_t todoovr:1; | ||
516 | uint64_t skprunt:1; | ||
517 | uint64_t badtag:1; | ||
518 | uint64_t prtnxa:1; | ||
519 | uint64_t bckprs:1; | ||
520 | uint64_t crcerr:1; | ||
521 | uint64_t pktdrp:1; | ||
522 | } cn30xx; | ||
523 | struct cvmx_pip_int_reg_cn30xx cn31xx; | ||
524 | struct cvmx_pip_int_reg_cn30xx cn38xx; | ||
525 | struct cvmx_pip_int_reg_cn30xx cn38xxp2; | ||
526 | struct cvmx_pip_int_reg_cn50xx { | ||
527 | uint64_t reserved_12_63:52; | ||
528 | uint64_t lenerr:1; | ||
529 | uint64_t maxerr:1; | ||
530 | uint64_t minerr:1; | ||
531 | uint64_t beperr:1; | ||
532 | uint64_t feperr:1; | ||
533 | uint64_t todoovr:1; | ||
534 | uint64_t skprunt:1; | ||
535 | uint64_t badtag:1; | ||
536 | uint64_t prtnxa:1; | ||
537 | uint64_t bckprs:1; | ||
538 | uint64_t reserved_1_1:1; | ||
539 | uint64_t pktdrp:1; | ||
540 | } cn50xx; | ||
541 | struct cvmx_pip_int_reg_cn52xx { | ||
542 | uint64_t reserved_13_63:51; | ||
543 | uint64_t punyerr:1; | ||
544 | uint64_t lenerr:1; | ||
545 | uint64_t maxerr:1; | ||
546 | uint64_t minerr:1; | ||
547 | uint64_t beperr:1; | ||
548 | uint64_t feperr:1; | ||
549 | uint64_t todoovr:1; | ||
550 | uint64_t skprunt:1; | ||
551 | uint64_t badtag:1; | ||
552 | uint64_t prtnxa:1; | ||
553 | uint64_t bckprs:1; | ||
554 | uint64_t reserved_1_1:1; | ||
555 | uint64_t pktdrp:1; | ||
556 | } cn52xx; | ||
557 | struct cvmx_pip_int_reg_cn52xx cn52xxp1; | ||
558 | struct cvmx_pip_int_reg_s cn56xx; | ||
559 | struct cvmx_pip_int_reg_cn56xxp1 { | ||
560 | uint64_t reserved_12_63:52; | ||
561 | uint64_t lenerr:1; | ||
562 | uint64_t maxerr:1; | ||
563 | uint64_t minerr:1; | ||
564 | uint64_t beperr:1; | ||
565 | uint64_t feperr:1; | ||
566 | uint64_t todoovr:1; | ||
567 | uint64_t skprunt:1; | ||
568 | uint64_t badtag:1; | ||
569 | uint64_t prtnxa:1; | ||
570 | uint64_t bckprs:1; | ||
571 | uint64_t crcerr:1; | ||
572 | uint64_t pktdrp:1; | ||
573 | } cn56xxp1; | ||
574 | struct cvmx_pip_int_reg_cn58xx { | ||
575 | uint64_t reserved_13_63:51; | ||
576 | uint64_t punyerr:1; | ||
577 | uint64_t reserved_9_11:3; | ||
578 | uint64_t beperr:1; | ||
579 | uint64_t feperr:1; | ||
580 | uint64_t todoovr:1; | ||
581 | uint64_t skprunt:1; | ||
582 | uint64_t badtag:1; | ||
583 | uint64_t prtnxa:1; | ||
584 | uint64_t bckprs:1; | ||
585 | uint64_t crcerr:1; | ||
586 | uint64_t pktdrp:1; | ||
587 | } cn58xx; | ||
588 | struct cvmx_pip_int_reg_cn30xx cn58xxp1; | ||
589 | }; | ||
590 | |||
591 | union cvmx_pip_ip_offset { | ||
592 | uint64_t u64; | ||
593 | struct cvmx_pip_ip_offset_s { | ||
594 | uint64_t reserved_3_63:61; | ||
595 | uint64_t offset:3; | ||
596 | } s; | ||
597 | struct cvmx_pip_ip_offset_s cn30xx; | ||
598 | struct cvmx_pip_ip_offset_s cn31xx; | ||
599 | struct cvmx_pip_ip_offset_s cn38xx; | ||
600 | struct cvmx_pip_ip_offset_s cn38xxp2; | ||
601 | struct cvmx_pip_ip_offset_s cn50xx; | ||
602 | struct cvmx_pip_ip_offset_s cn52xx; | ||
603 | struct cvmx_pip_ip_offset_s cn52xxp1; | ||
604 | struct cvmx_pip_ip_offset_s cn56xx; | ||
605 | struct cvmx_pip_ip_offset_s cn56xxp1; | ||
606 | struct cvmx_pip_ip_offset_s cn58xx; | ||
607 | struct cvmx_pip_ip_offset_s cn58xxp1; | ||
608 | }; | ||
609 | |||
610 | union cvmx_pip_prt_cfgx { | ||
611 | uint64_t u64; | ||
612 | struct cvmx_pip_prt_cfgx_s { | ||
613 | uint64_t reserved_53_63:11; | ||
614 | uint64_t pad_len:1; | ||
615 | uint64_t vlan_len:1; | ||
616 | uint64_t lenerr_en:1; | ||
617 | uint64_t maxerr_en:1; | ||
618 | uint64_t minerr_en:1; | ||
619 | uint64_t grp_wat_47:4; | ||
620 | uint64_t qos_wat_47:4; | ||
621 | uint64_t reserved_37_39:3; | ||
622 | uint64_t rawdrp:1; | ||
623 | uint64_t tag_inc:2; | ||
624 | uint64_t dyn_rs:1; | ||
625 | uint64_t inst_hdr:1; | ||
626 | uint64_t grp_wat:4; | ||
627 | uint64_t hg_qos:1; | ||
628 | uint64_t qos:3; | ||
629 | uint64_t qos_wat:4; | ||
630 | uint64_t qos_vsel:1; | ||
631 | uint64_t qos_vod:1; | ||
632 | uint64_t qos_diff:1; | ||
633 | uint64_t qos_vlan:1; | ||
634 | uint64_t reserved_13_15:3; | ||
635 | uint64_t crc_en:1; | ||
636 | uint64_t higig_en:1; | ||
637 | uint64_t dsa_en:1; | ||
638 | uint64_t mode:2; | ||
639 | uint64_t reserved_7_7:1; | ||
640 | uint64_t skip:7; | ||
641 | } s; | ||
642 | struct cvmx_pip_prt_cfgx_cn30xx { | ||
643 | uint64_t reserved_37_63:27; | ||
644 | uint64_t rawdrp:1; | ||
645 | uint64_t tag_inc:2; | ||
646 | uint64_t dyn_rs:1; | ||
647 | uint64_t inst_hdr:1; | ||
648 | uint64_t grp_wat:4; | ||
649 | uint64_t reserved_27_27:1; | ||
650 | uint64_t qos:3; | ||
651 | uint64_t qos_wat:4; | ||
652 | uint64_t reserved_18_19:2; | ||
653 | uint64_t qos_diff:1; | ||
654 | uint64_t qos_vlan:1; | ||
655 | uint64_t reserved_10_15:6; | ||
656 | uint64_t mode:2; | ||
657 | uint64_t reserved_7_7:1; | ||
658 | uint64_t skip:7; | ||
659 | } cn30xx; | ||
660 | struct cvmx_pip_prt_cfgx_cn30xx cn31xx; | ||
661 | struct cvmx_pip_prt_cfgx_cn38xx { | ||
662 | uint64_t reserved_37_63:27; | ||
663 | uint64_t rawdrp:1; | ||
664 | uint64_t tag_inc:2; | ||
665 | uint64_t dyn_rs:1; | ||
666 | uint64_t inst_hdr:1; | ||
667 | uint64_t grp_wat:4; | ||
668 | uint64_t reserved_27_27:1; | ||
669 | uint64_t qos:3; | ||
670 | uint64_t qos_wat:4; | ||
671 | uint64_t reserved_18_19:2; | ||
672 | uint64_t qos_diff:1; | ||
673 | uint64_t qos_vlan:1; | ||
674 | uint64_t reserved_13_15:3; | ||
675 | uint64_t crc_en:1; | ||
676 | uint64_t reserved_10_11:2; | ||
677 | uint64_t mode:2; | ||
678 | uint64_t reserved_7_7:1; | ||
679 | uint64_t skip:7; | ||
680 | } cn38xx; | ||
681 | struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2; | ||
682 | struct cvmx_pip_prt_cfgx_cn50xx { | ||
683 | uint64_t reserved_53_63:11; | ||
684 | uint64_t pad_len:1; | ||
685 | uint64_t vlan_len:1; | ||
686 | uint64_t lenerr_en:1; | ||
687 | uint64_t maxerr_en:1; | ||
688 | uint64_t minerr_en:1; | ||
689 | uint64_t grp_wat_47:4; | ||
690 | uint64_t qos_wat_47:4; | ||
691 | uint64_t reserved_37_39:3; | ||
692 | uint64_t rawdrp:1; | ||
693 | uint64_t tag_inc:2; | ||
694 | uint64_t dyn_rs:1; | ||
695 | uint64_t inst_hdr:1; | ||
696 | uint64_t grp_wat:4; | ||
697 | uint64_t reserved_27_27:1; | ||
698 | uint64_t qos:3; | ||
699 | uint64_t qos_wat:4; | ||
700 | uint64_t reserved_19_19:1; | ||
701 | uint64_t qos_vod:1; | ||
702 | uint64_t qos_diff:1; | ||
703 | uint64_t qos_vlan:1; | ||
704 | uint64_t reserved_13_15:3; | ||
705 | uint64_t crc_en:1; | ||
706 | uint64_t reserved_10_11:2; | ||
707 | uint64_t mode:2; | ||
708 | uint64_t reserved_7_7:1; | ||
709 | uint64_t skip:7; | ||
710 | } cn50xx; | ||
711 | struct cvmx_pip_prt_cfgx_s cn52xx; | ||
712 | struct cvmx_pip_prt_cfgx_s cn52xxp1; | ||
713 | struct cvmx_pip_prt_cfgx_s cn56xx; | ||
714 | struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1; | ||
715 | struct cvmx_pip_prt_cfgx_cn58xx { | ||
716 | uint64_t reserved_37_63:27; | ||
717 | uint64_t rawdrp:1; | ||
718 | uint64_t tag_inc:2; | ||
719 | uint64_t dyn_rs:1; | ||
720 | uint64_t inst_hdr:1; | ||
721 | uint64_t grp_wat:4; | ||
722 | uint64_t reserved_27_27:1; | ||
723 | uint64_t qos:3; | ||
724 | uint64_t qos_wat:4; | ||
725 | uint64_t reserved_19_19:1; | ||
726 | uint64_t qos_vod:1; | ||
727 | uint64_t qos_diff:1; | ||
728 | uint64_t qos_vlan:1; | ||
729 | uint64_t reserved_13_15:3; | ||
730 | uint64_t crc_en:1; | ||
731 | uint64_t reserved_10_11:2; | ||
732 | uint64_t mode:2; | ||
733 | uint64_t reserved_7_7:1; | ||
734 | uint64_t skip:7; | ||
735 | } cn58xx; | ||
736 | struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; | ||
737 | }; | ||
738 | |||
739 | union cvmx_pip_prt_tagx { | ||
740 | uint64_t u64; | ||
741 | struct cvmx_pip_prt_tagx_s { | ||
742 | uint64_t reserved_40_63:24; | ||
743 | uint64_t grptagbase:4; | ||
744 | uint64_t grptagmask:4; | ||
745 | uint64_t grptag:1; | ||
746 | uint64_t grptag_mskip:1; | ||
747 | uint64_t tag_mode:2; | ||
748 | uint64_t inc_vs:2; | ||
749 | uint64_t inc_vlan:1; | ||
750 | uint64_t inc_prt_flag:1; | ||
751 | uint64_t ip6_dprt_flag:1; | ||
752 | uint64_t ip4_dprt_flag:1; | ||
753 | uint64_t ip6_sprt_flag:1; | ||
754 | uint64_t ip4_sprt_flag:1; | ||
755 | uint64_t ip6_nxth_flag:1; | ||
756 | uint64_t ip4_pctl_flag:1; | ||
757 | uint64_t ip6_dst_flag:1; | ||
758 | uint64_t ip4_dst_flag:1; | ||
759 | uint64_t ip6_src_flag:1; | ||
760 | uint64_t ip4_src_flag:1; | ||
761 | uint64_t tcp6_tag_type:2; | ||
762 | uint64_t tcp4_tag_type:2; | ||
763 | uint64_t ip6_tag_type:2; | ||
764 | uint64_t ip4_tag_type:2; | ||
765 | uint64_t non_tag_type:2; | ||
766 | uint64_t grp:4; | ||
767 | } s; | ||
768 | struct cvmx_pip_prt_tagx_cn30xx { | ||
769 | uint64_t reserved_40_63:24; | ||
770 | uint64_t grptagbase:4; | ||
771 | uint64_t grptagmask:4; | ||
772 | uint64_t grptag:1; | ||
773 | uint64_t reserved_30_30:1; | ||
774 | uint64_t tag_mode:2; | ||
775 | uint64_t inc_vs:2; | ||
776 | uint64_t inc_vlan:1; | ||
777 | uint64_t inc_prt_flag:1; | ||
778 | uint64_t ip6_dprt_flag:1; | ||
779 | uint64_t ip4_dprt_flag:1; | ||
780 | uint64_t ip6_sprt_flag:1; | ||
781 | uint64_t ip4_sprt_flag:1; | ||
782 | uint64_t ip6_nxth_flag:1; | ||
783 | uint64_t ip4_pctl_flag:1; | ||
784 | uint64_t ip6_dst_flag:1; | ||
785 | uint64_t ip4_dst_flag:1; | ||
786 | uint64_t ip6_src_flag:1; | ||
787 | uint64_t ip4_src_flag:1; | ||
788 | uint64_t tcp6_tag_type:2; | ||
789 | uint64_t tcp4_tag_type:2; | ||
790 | uint64_t ip6_tag_type:2; | ||
791 | uint64_t ip4_tag_type:2; | ||
792 | uint64_t non_tag_type:2; | ||
793 | uint64_t grp:4; | ||
794 | } cn30xx; | ||
795 | struct cvmx_pip_prt_tagx_cn30xx cn31xx; | ||
796 | struct cvmx_pip_prt_tagx_cn30xx cn38xx; | ||
797 | struct cvmx_pip_prt_tagx_cn30xx cn38xxp2; | ||
798 | struct cvmx_pip_prt_tagx_s cn50xx; | ||
799 | struct cvmx_pip_prt_tagx_s cn52xx; | ||
800 | struct cvmx_pip_prt_tagx_s cn52xxp1; | ||
801 | struct cvmx_pip_prt_tagx_s cn56xx; | ||
802 | struct cvmx_pip_prt_tagx_s cn56xxp1; | ||
803 | struct cvmx_pip_prt_tagx_cn30xx cn58xx; | ||
804 | struct cvmx_pip_prt_tagx_cn30xx cn58xxp1; | ||
805 | }; | ||
806 | |||
807 | union cvmx_pip_qos_diffx { | ||
808 | uint64_t u64; | ||
809 | struct cvmx_pip_qos_diffx_s { | ||
810 | uint64_t reserved_3_63:61; | ||
811 | uint64_t qos:3; | ||
812 | } s; | ||
813 | struct cvmx_pip_qos_diffx_s cn30xx; | ||
814 | struct cvmx_pip_qos_diffx_s cn31xx; | ||
815 | struct cvmx_pip_qos_diffx_s cn38xx; | ||
816 | struct cvmx_pip_qos_diffx_s cn38xxp2; | ||
817 | struct cvmx_pip_qos_diffx_s cn50xx; | ||
818 | struct cvmx_pip_qos_diffx_s cn52xx; | ||
819 | struct cvmx_pip_qos_diffx_s cn52xxp1; | ||
820 | struct cvmx_pip_qos_diffx_s cn56xx; | ||
821 | struct cvmx_pip_qos_diffx_s cn56xxp1; | ||
822 | struct cvmx_pip_qos_diffx_s cn58xx; | ||
823 | struct cvmx_pip_qos_diffx_s cn58xxp1; | ||
824 | }; | ||
825 | |||
826 | union cvmx_pip_qos_vlanx { | ||
827 | uint64_t u64; | ||
828 | struct cvmx_pip_qos_vlanx_s { | ||
829 | uint64_t reserved_7_63:57; | ||
830 | uint64_t qos1:3; | ||
831 | uint64_t reserved_3_3:1; | ||
832 | uint64_t qos:3; | ||
833 | } s; | ||
834 | struct cvmx_pip_qos_vlanx_cn30xx { | ||
835 | uint64_t reserved_3_63:61; | ||
836 | uint64_t qos:3; | ||
837 | } cn30xx; | ||
838 | struct cvmx_pip_qos_vlanx_cn30xx cn31xx; | ||
839 | struct cvmx_pip_qos_vlanx_cn30xx cn38xx; | ||
840 | struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2; | ||
841 | struct cvmx_pip_qos_vlanx_cn30xx cn50xx; | ||
842 | struct cvmx_pip_qos_vlanx_s cn52xx; | ||
843 | struct cvmx_pip_qos_vlanx_s cn52xxp1; | ||
844 | struct cvmx_pip_qos_vlanx_s cn56xx; | ||
845 | struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1; | ||
846 | struct cvmx_pip_qos_vlanx_cn30xx cn58xx; | ||
847 | struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1; | ||
848 | }; | ||
849 | |||
850 | union cvmx_pip_qos_watchx { | ||
851 | uint64_t u64; | ||
852 | struct cvmx_pip_qos_watchx_s { | ||
853 | uint64_t reserved_48_63:16; | ||
854 | uint64_t mask:16; | ||
855 | uint64_t reserved_28_31:4; | ||
856 | uint64_t grp:4; | ||
857 | uint64_t reserved_23_23:1; | ||
858 | uint64_t qos:3; | ||
859 | uint64_t reserved_19_19:1; | ||
860 | uint64_t match_type:3; | ||
861 | uint64_t match_value:16; | ||
862 | } s; | ||
863 | struct cvmx_pip_qos_watchx_cn30xx { | ||
864 | uint64_t reserved_48_63:16; | ||
865 | uint64_t mask:16; | ||
866 | uint64_t reserved_28_31:4; | ||
867 | uint64_t grp:4; | ||
868 | uint64_t reserved_23_23:1; | ||
869 | uint64_t qos:3; | ||
870 | uint64_t reserved_18_19:2; | ||
871 | uint64_t match_type:2; | ||
872 | uint64_t match_value:16; | ||
873 | } cn30xx; | ||
874 | struct cvmx_pip_qos_watchx_cn30xx cn31xx; | ||
875 | struct cvmx_pip_qos_watchx_cn30xx cn38xx; | ||
876 | struct cvmx_pip_qos_watchx_cn30xx cn38xxp2; | ||
877 | struct cvmx_pip_qos_watchx_s cn50xx; | ||
878 | struct cvmx_pip_qos_watchx_s cn52xx; | ||
879 | struct cvmx_pip_qos_watchx_s cn52xxp1; | ||
880 | struct cvmx_pip_qos_watchx_s cn56xx; | ||
881 | struct cvmx_pip_qos_watchx_s cn56xxp1; | ||
882 | struct cvmx_pip_qos_watchx_cn30xx cn58xx; | ||
883 | struct cvmx_pip_qos_watchx_cn30xx cn58xxp1; | ||
884 | }; | ||
885 | |||
886 | union cvmx_pip_raw_word { | ||
887 | uint64_t u64; | ||
888 | struct cvmx_pip_raw_word_s { | ||
889 | uint64_t reserved_56_63:8; | ||
890 | uint64_t word:56; | ||
891 | } s; | ||
892 | struct cvmx_pip_raw_word_s cn30xx; | ||
893 | struct cvmx_pip_raw_word_s cn31xx; | ||
894 | struct cvmx_pip_raw_word_s cn38xx; | ||
895 | struct cvmx_pip_raw_word_s cn38xxp2; | ||
896 | struct cvmx_pip_raw_word_s cn50xx; | ||
897 | struct cvmx_pip_raw_word_s cn52xx; | ||
898 | struct cvmx_pip_raw_word_s cn52xxp1; | ||
899 | struct cvmx_pip_raw_word_s cn56xx; | ||
900 | struct cvmx_pip_raw_word_s cn56xxp1; | ||
901 | struct cvmx_pip_raw_word_s cn58xx; | ||
902 | struct cvmx_pip_raw_word_s cn58xxp1; | ||
903 | }; | ||
904 | |||
905 | union cvmx_pip_sft_rst { | ||
906 | uint64_t u64; | ||
907 | struct cvmx_pip_sft_rst_s { | ||
908 | uint64_t reserved_1_63:63; | ||
909 | uint64_t rst:1; | ||
910 | } s; | ||
911 | struct cvmx_pip_sft_rst_s cn30xx; | ||
912 | struct cvmx_pip_sft_rst_s cn31xx; | ||
913 | struct cvmx_pip_sft_rst_s cn38xx; | ||
914 | struct cvmx_pip_sft_rst_s cn50xx; | ||
915 | struct cvmx_pip_sft_rst_s cn52xx; | ||
916 | struct cvmx_pip_sft_rst_s cn52xxp1; | ||
917 | struct cvmx_pip_sft_rst_s cn56xx; | ||
918 | struct cvmx_pip_sft_rst_s cn56xxp1; | ||
919 | struct cvmx_pip_sft_rst_s cn58xx; | ||
920 | struct cvmx_pip_sft_rst_s cn58xxp1; | ||
921 | }; | ||
922 | |||
923 | union cvmx_pip_stat0_prtx { | ||
924 | uint64_t u64; | ||
925 | struct cvmx_pip_stat0_prtx_s { | ||
926 | uint64_t drp_pkts:32; | ||
927 | uint64_t drp_octs:32; | ||
928 | } s; | ||
929 | struct cvmx_pip_stat0_prtx_s cn30xx; | ||
930 | struct cvmx_pip_stat0_prtx_s cn31xx; | ||
931 | struct cvmx_pip_stat0_prtx_s cn38xx; | ||
932 | struct cvmx_pip_stat0_prtx_s cn38xxp2; | ||
933 | struct cvmx_pip_stat0_prtx_s cn50xx; | ||
934 | struct cvmx_pip_stat0_prtx_s cn52xx; | ||
935 | struct cvmx_pip_stat0_prtx_s cn52xxp1; | ||
936 | struct cvmx_pip_stat0_prtx_s cn56xx; | ||
937 | struct cvmx_pip_stat0_prtx_s cn56xxp1; | ||
938 | struct cvmx_pip_stat0_prtx_s cn58xx; | ||
939 | struct cvmx_pip_stat0_prtx_s cn58xxp1; | ||
940 | }; | ||
941 | |||
942 | union cvmx_pip_stat1_prtx { | ||
943 | uint64_t u64; | ||
944 | struct cvmx_pip_stat1_prtx_s { | ||
945 | uint64_t reserved_48_63:16; | ||
946 | uint64_t octs:48; | ||
947 | } s; | ||
948 | struct cvmx_pip_stat1_prtx_s cn30xx; | ||
949 | struct cvmx_pip_stat1_prtx_s cn31xx; | ||
950 | struct cvmx_pip_stat1_prtx_s cn38xx; | ||
951 | struct cvmx_pip_stat1_prtx_s cn38xxp2; | ||
952 | struct cvmx_pip_stat1_prtx_s cn50xx; | ||
953 | struct cvmx_pip_stat1_prtx_s cn52xx; | ||
954 | struct cvmx_pip_stat1_prtx_s cn52xxp1; | ||
955 | struct cvmx_pip_stat1_prtx_s cn56xx; | ||
956 | struct cvmx_pip_stat1_prtx_s cn56xxp1; | ||
957 | struct cvmx_pip_stat1_prtx_s cn58xx; | ||
958 | struct cvmx_pip_stat1_prtx_s cn58xxp1; | ||
959 | }; | ||
960 | |||
961 | union cvmx_pip_stat2_prtx { | ||
962 | uint64_t u64; | ||
963 | struct cvmx_pip_stat2_prtx_s { | ||
964 | uint64_t pkts:32; | ||
965 | uint64_t raw:32; | ||
966 | } s; | ||
967 | struct cvmx_pip_stat2_prtx_s cn30xx; | ||
968 | struct cvmx_pip_stat2_prtx_s cn31xx; | ||
969 | struct cvmx_pip_stat2_prtx_s cn38xx; | ||
970 | struct cvmx_pip_stat2_prtx_s cn38xxp2; | ||
971 | struct cvmx_pip_stat2_prtx_s cn50xx; | ||
972 | struct cvmx_pip_stat2_prtx_s cn52xx; | ||
973 | struct cvmx_pip_stat2_prtx_s cn52xxp1; | ||
974 | struct cvmx_pip_stat2_prtx_s cn56xx; | ||
975 | struct cvmx_pip_stat2_prtx_s cn56xxp1; | ||
976 | struct cvmx_pip_stat2_prtx_s cn58xx; | ||
977 | struct cvmx_pip_stat2_prtx_s cn58xxp1; | ||
978 | }; | ||
979 | |||
980 | union cvmx_pip_stat3_prtx { | ||
981 | uint64_t u64; | ||
982 | struct cvmx_pip_stat3_prtx_s { | ||
983 | uint64_t bcst:32; | ||
984 | uint64_t mcst:32; | ||
985 | } s; | ||
986 | struct cvmx_pip_stat3_prtx_s cn30xx; | ||
987 | struct cvmx_pip_stat3_prtx_s cn31xx; | ||
988 | struct cvmx_pip_stat3_prtx_s cn38xx; | ||
989 | struct cvmx_pip_stat3_prtx_s cn38xxp2; | ||
990 | struct cvmx_pip_stat3_prtx_s cn50xx; | ||
991 | struct cvmx_pip_stat3_prtx_s cn52xx; | ||
992 | struct cvmx_pip_stat3_prtx_s cn52xxp1; | ||
993 | struct cvmx_pip_stat3_prtx_s cn56xx; | ||
994 | struct cvmx_pip_stat3_prtx_s cn56xxp1; | ||
995 | struct cvmx_pip_stat3_prtx_s cn58xx; | ||
996 | struct cvmx_pip_stat3_prtx_s cn58xxp1; | ||
997 | }; | ||
998 | |||
999 | union cvmx_pip_stat4_prtx { | ||
1000 | uint64_t u64; | ||
1001 | struct cvmx_pip_stat4_prtx_s { | ||
1002 | uint64_t h65to127:32; | ||
1003 | uint64_t h64:32; | ||
1004 | } s; | ||
1005 | struct cvmx_pip_stat4_prtx_s cn30xx; | ||
1006 | struct cvmx_pip_stat4_prtx_s cn31xx; | ||
1007 | struct cvmx_pip_stat4_prtx_s cn38xx; | ||
1008 | struct cvmx_pip_stat4_prtx_s cn38xxp2; | ||
1009 | struct cvmx_pip_stat4_prtx_s cn50xx; | ||
1010 | struct cvmx_pip_stat4_prtx_s cn52xx; | ||
1011 | struct cvmx_pip_stat4_prtx_s cn52xxp1; | ||
1012 | struct cvmx_pip_stat4_prtx_s cn56xx; | ||
1013 | struct cvmx_pip_stat4_prtx_s cn56xxp1; | ||
1014 | struct cvmx_pip_stat4_prtx_s cn58xx; | ||
1015 | struct cvmx_pip_stat4_prtx_s cn58xxp1; | ||
1016 | }; | ||
1017 | |||
1018 | union cvmx_pip_stat5_prtx { | ||
1019 | uint64_t u64; | ||
1020 | struct cvmx_pip_stat5_prtx_s { | ||
1021 | uint64_t h256to511:32; | ||
1022 | uint64_t h128to255:32; | ||
1023 | } s; | ||
1024 | struct cvmx_pip_stat5_prtx_s cn30xx; | ||
1025 | struct cvmx_pip_stat5_prtx_s cn31xx; | ||
1026 | struct cvmx_pip_stat5_prtx_s cn38xx; | ||
1027 | struct cvmx_pip_stat5_prtx_s cn38xxp2; | ||
1028 | struct cvmx_pip_stat5_prtx_s cn50xx; | ||
1029 | struct cvmx_pip_stat5_prtx_s cn52xx; | ||
1030 | struct cvmx_pip_stat5_prtx_s cn52xxp1; | ||
1031 | struct cvmx_pip_stat5_prtx_s cn56xx; | ||
1032 | struct cvmx_pip_stat5_prtx_s cn56xxp1; | ||
1033 | struct cvmx_pip_stat5_prtx_s cn58xx; | ||
1034 | struct cvmx_pip_stat5_prtx_s cn58xxp1; | ||
1035 | }; | ||
1036 | |||
1037 | union cvmx_pip_stat6_prtx { | ||
1038 | uint64_t u64; | ||
1039 | struct cvmx_pip_stat6_prtx_s { | ||
1040 | uint64_t h1024to1518:32; | ||
1041 | uint64_t h512to1023:32; | ||
1042 | } s; | ||
1043 | struct cvmx_pip_stat6_prtx_s cn30xx; | ||
1044 | struct cvmx_pip_stat6_prtx_s cn31xx; | ||
1045 | struct cvmx_pip_stat6_prtx_s cn38xx; | ||
1046 | struct cvmx_pip_stat6_prtx_s cn38xxp2; | ||
1047 | struct cvmx_pip_stat6_prtx_s cn50xx; | ||
1048 | struct cvmx_pip_stat6_prtx_s cn52xx; | ||
1049 | struct cvmx_pip_stat6_prtx_s cn52xxp1; | ||
1050 | struct cvmx_pip_stat6_prtx_s cn56xx; | ||
1051 | struct cvmx_pip_stat6_prtx_s cn56xxp1; | ||
1052 | struct cvmx_pip_stat6_prtx_s cn58xx; | ||
1053 | struct cvmx_pip_stat6_prtx_s cn58xxp1; | ||
1054 | }; | ||
1055 | |||
1056 | union cvmx_pip_stat7_prtx { | ||
1057 | uint64_t u64; | ||
1058 | struct cvmx_pip_stat7_prtx_s { | ||
1059 | uint64_t fcs:32; | ||
1060 | uint64_t h1519:32; | ||
1061 | } s; | ||
1062 | struct cvmx_pip_stat7_prtx_s cn30xx; | ||
1063 | struct cvmx_pip_stat7_prtx_s cn31xx; | ||
1064 | struct cvmx_pip_stat7_prtx_s cn38xx; | ||
1065 | struct cvmx_pip_stat7_prtx_s cn38xxp2; | ||
1066 | struct cvmx_pip_stat7_prtx_s cn50xx; | ||
1067 | struct cvmx_pip_stat7_prtx_s cn52xx; | ||
1068 | struct cvmx_pip_stat7_prtx_s cn52xxp1; | ||
1069 | struct cvmx_pip_stat7_prtx_s cn56xx; | ||
1070 | struct cvmx_pip_stat7_prtx_s cn56xxp1; | ||
1071 | struct cvmx_pip_stat7_prtx_s cn58xx; | ||
1072 | struct cvmx_pip_stat7_prtx_s cn58xxp1; | ||
1073 | }; | ||
1074 | |||
1075 | union cvmx_pip_stat8_prtx { | ||
1076 | uint64_t u64; | ||
1077 | struct cvmx_pip_stat8_prtx_s { | ||
1078 | uint64_t frag:32; | ||
1079 | uint64_t undersz:32; | ||
1080 | } s; | ||
1081 | struct cvmx_pip_stat8_prtx_s cn30xx; | ||
1082 | struct cvmx_pip_stat8_prtx_s cn31xx; | ||
1083 | struct cvmx_pip_stat8_prtx_s cn38xx; | ||
1084 | struct cvmx_pip_stat8_prtx_s cn38xxp2; | ||
1085 | struct cvmx_pip_stat8_prtx_s cn50xx; | ||
1086 | struct cvmx_pip_stat8_prtx_s cn52xx; | ||
1087 | struct cvmx_pip_stat8_prtx_s cn52xxp1; | ||
1088 | struct cvmx_pip_stat8_prtx_s cn56xx; | ||
1089 | struct cvmx_pip_stat8_prtx_s cn56xxp1; | ||
1090 | struct cvmx_pip_stat8_prtx_s cn58xx; | ||
1091 | struct cvmx_pip_stat8_prtx_s cn58xxp1; | ||
1092 | }; | ||
1093 | |||
1094 | union cvmx_pip_stat9_prtx { | ||
1095 | uint64_t u64; | ||
1096 | struct cvmx_pip_stat9_prtx_s { | ||
1097 | uint64_t jabber:32; | ||
1098 | uint64_t oversz:32; | ||
1099 | } s; | ||
1100 | struct cvmx_pip_stat9_prtx_s cn30xx; | ||
1101 | struct cvmx_pip_stat9_prtx_s cn31xx; | ||
1102 | struct cvmx_pip_stat9_prtx_s cn38xx; | ||
1103 | struct cvmx_pip_stat9_prtx_s cn38xxp2; | ||
1104 | struct cvmx_pip_stat9_prtx_s cn50xx; | ||
1105 | struct cvmx_pip_stat9_prtx_s cn52xx; | ||
1106 | struct cvmx_pip_stat9_prtx_s cn52xxp1; | ||
1107 | struct cvmx_pip_stat9_prtx_s cn56xx; | ||
1108 | struct cvmx_pip_stat9_prtx_s cn56xxp1; | ||
1109 | struct cvmx_pip_stat9_prtx_s cn58xx; | ||
1110 | struct cvmx_pip_stat9_prtx_s cn58xxp1; | ||
1111 | }; | ||
1112 | |||
1113 | union cvmx_pip_stat_ctl { | ||
1114 | uint64_t u64; | ||
1115 | struct cvmx_pip_stat_ctl_s { | ||
1116 | uint64_t reserved_1_63:63; | ||
1117 | uint64_t rdclr:1; | ||
1118 | } s; | ||
1119 | struct cvmx_pip_stat_ctl_s cn30xx; | ||
1120 | struct cvmx_pip_stat_ctl_s cn31xx; | ||
1121 | struct cvmx_pip_stat_ctl_s cn38xx; | ||
1122 | struct cvmx_pip_stat_ctl_s cn38xxp2; | ||
1123 | struct cvmx_pip_stat_ctl_s cn50xx; | ||
1124 | struct cvmx_pip_stat_ctl_s cn52xx; | ||
1125 | struct cvmx_pip_stat_ctl_s cn52xxp1; | ||
1126 | struct cvmx_pip_stat_ctl_s cn56xx; | ||
1127 | struct cvmx_pip_stat_ctl_s cn56xxp1; | ||
1128 | struct cvmx_pip_stat_ctl_s cn58xx; | ||
1129 | struct cvmx_pip_stat_ctl_s cn58xxp1; | ||
1130 | }; | ||
1131 | |||
1132 | union cvmx_pip_stat_inb_errsx { | ||
1133 | uint64_t u64; | ||
1134 | struct cvmx_pip_stat_inb_errsx_s { | ||
1135 | uint64_t reserved_16_63:48; | ||
1136 | uint64_t errs:16; | ||
1137 | } s; | ||
1138 | struct cvmx_pip_stat_inb_errsx_s cn30xx; | ||
1139 | struct cvmx_pip_stat_inb_errsx_s cn31xx; | ||
1140 | struct cvmx_pip_stat_inb_errsx_s cn38xx; | ||
1141 | struct cvmx_pip_stat_inb_errsx_s cn38xxp2; | ||
1142 | struct cvmx_pip_stat_inb_errsx_s cn50xx; | ||
1143 | struct cvmx_pip_stat_inb_errsx_s cn52xx; | ||
1144 | struct cvmx_pip_stat_inb_errsx_s cn52xxp1; | ||
1145 | struct cvmx_pip_stat_inb_errsx_s cn56xx; | ||
1146 | struct cvmx_pip_stat_inb_errsx_s cn56xxp1; | ||
1147 | struct cvmx_pip_stat_inb_errsx_s cn58xx; | ||
1148 | struct cvmx_pip_stat_inb_errsx_s cn58xxp1; | ||
1149 | }; | ||
1150 | |||
1151 | union cvmx_pip_stat_inb_octsx { | ||
1152 | uint64_t u64; | ||
1153 | struct cvmx_pip_stat_inb_octsx_s { | ||
1154 | uint64_t reserved_48_63:16; | ||
1155 | uint64_t octs:48; | ||
1156 | } s; | ||
1157 | struct cvmx_pip_stat_inb_octsx_s cn30xx; | ||
1158 | struct cvmx_pip_stat_inb_octsx_s cn31xx; | ||
1159 | struct cvmx_pip_stat_inb_octsx_s cn38xx; | ||
1160 | struct cvmx_pip_stat_inb_octsx_s cn38xxp2; | ||
1161 | struct cvmx_pip_stat_inb_octsx_s cn50xx; | ||
1162 | struct cvmx_pip_stat_inb_octsx_s cn52xx; | ||
1163 | struct cvmx_pip_stat_inb_octsx_s cn52xxp1; | ||
1164 | struct cvmx_pip_stat_inb_octsx_s cn56xx; | ||
1165 | struct cvmx_pip_stat_inb_octsx_s cn56xxp1; | ||
1166 | struct cvmx_pip_stat_inb_octsx_s cn58xx; | ||
1167 | struct cvmx_pip_stat_inb_octsx_s cn58xxp1; | ||
1168 | }; | ||
1169 | |||
1170 | union cvmx_pip_stat_inb_pktsx { | ||
1171 | uint64_t u64; | ||
1172 | struct cvmx_pip_stat_inb_pktsx_s { | ||
1173 | uint64_t reserved_32_63:32; | ||
1174 | uint64_t pkts:32; | ||
1175 | } s; | ||
1176 | struct cvmx_pip_stat_inb_pktsx_s cn30xx; | ||
1177 | struct cvmx_pip_stat_inb_pktsx_s cn31xx; | ||
1178 | struct cvmx_pip_stat_inb_pktsx_s cn38xx; | ||
1179 | struct cvmx_pip_stat_inb_pktsx_s cn38xxp2; | ||
1180 | struct cvmx_pip_stat_inb_pktsx_s cn50xx; | ||
1181 | struct cvmx_pip_stat_inb_pktsx_s cn52xx; | ||
1182 | struct cvmx_pip_stat_inb_pktsx_s cn52xxp1; | ||
1183 | struct cvmx_pip_stat_inb_pktsx_s cn56xx; | ||
1184 | struct cvmx_pip_stat_inb_pktsx_s cn56xxp1; | ||
1185 | struct cvmx_pip_stat_inb_pktsx_s cn58xx; | ||
1186 | struct cvmx_pip_stat_inb_pktsx_s cn58xxp1; | ||
1187 | }; | ||
1188 | |||
1189 | union cvmx_pip_tag_incx { | ||
1190 | uint64_t u64; | ||
1191 | struct cvmx_pip_tag_incx_s { | ||
1192 | uint64_t reserved_8_63:56; | ||
1193 | uint64_t en:8; | ||
1194 | } s; | ||
1195 | struct cvmx_pip_tag_incx_s cn30xx; | ||
1196 | struct cvmx_pip_tag_incx_s cn31xx; | ||
1197 | struct cvmx_pip_tag_incx_s cn38xx; | ||
1198 | struct cvmx_pip_tag_incx_s cn38xxp2; | ||
1199 | struct cvmx_pip_tag_incx_s cn50xx; | ||
1200 | struct cvmx_pip_tag_incx_s cn52xx; | ||
1201 | struct cvmx_pip_tag_incx_s cn52xxp1; | ||
1202 | struct cvmx_pip_tag_incx_s cn56xx; | ||
1203 | struct cvmx_pip_tag_incx_s cn56xxp1; | ||
1204 | struct cvmx_pip_tag_incx_s cn58xx; | ||
1205 | struct cvmx_pip_tag_incx_s cn58xxp1; | ||
1206 | }; | ||
1207 | |||
1208 | union cvmx_pip_tag_mask { | ||
1209 | uint64_t u64; | ||
1210 | struct cvmx_pip_tag_mask_s { | ||
1211 | uint64_t reserved_16_63:48; | ||
1212 | uint64_t mask:16; | ||
1213 | } s; | ||
1214 | struct cvmx_pip_tag_mask_s cn30xx; | ||
1215 | struct cvmx_pip_tag_mask_s cn31xx; | ||
1216 | struct cvmx_pip_tag_mask_s cn38xx; | ||
1217 | struct cvmx_pip_tag_mask_s cn38xxp2; | ||
1218 | struct cvmx_pip_tag_mask_s cn50xx; | ||
1219 | struct cvmx_pip_tag_mask_s cn52xx; | ||
1220 | struct cvmx_pip_tag_mask_s cn52xxp1; | ||
1221 | struct cvmx_pip_tag_mask_s cn56xx; | ||
1222 | struct cvmx_pip_tag_mask_s cn56xxp1; | ||
1223 | struct cvmx_pip_tag_mask_s cn58xx; | ||
1224 | struct cvmx_pip_tag_mask_s cn58xxp1; | ||
1225 | }; | ||
1226 | |||
1227 | union cvmx_pip_tag_secret { | ||
1228 | uint64_t u64; | ||
1229 | struct cvmx_pip_tag_secret_s { | ||
1230 | uint64_t reserved_32_63:32; | ||
1231 | uint64_t dst:16; | ||
1232 | uint64_t src:16; | ||
1233 | } s; | ||
1234 | struct cvmx_pip_tag_secret_s cn30xx; | ||
1235 | struct cvmx_pip_tag_secret_s cn31xx; | ||
1236 | struct cvmx_pip_tag_secret_s cn38xx; | ||
1237 | struct cvmx_pip_tag_secret_s cn38xxp2; | ||
1238 | struct cvmx_pip_tag_secret_s cn50xx; | ||
1239 | struct cvmx_pip_tag_secret_s cn52xx; | ||
1240 | struct cvmx_pip_tag_secret_s cn52xxp1; | ||
1241 | struct cvmx_pip_tag_secret_s cn56xx; | ||
1242 | struct cvmx_pip_tag_secret_s cn56xxp1; | ||
1243 | struct cvmx_pip_tag_secret_s cn58xx; | ||
1244 | struct cvmx_pip_tag_secret_s cn58xxp1; | ||
1245 | }; | ||
1246 | |||
1247 | union cvmx_pip_todo_entry { | ||
1248 | uint64_t u64; | ||
1249 | struct cvmx_pip_todo_entry_s { | ||
1250 | uint64_t val:1; | ||
1251 | uint64_t reserved_62_62:1; | ||
1252 | uint64_t entry:62; | ||
1253 | } s; | ||
1254 | struct cvmx_pip_todo_entry_s cn30xx; | ||
1255 | struct cvmx_pip_todo_entry_s cn31xx; | ||
1256 | struct cvmx_pip_todo_entry_s cn38xx; | ||
1257 | struct cvmx_pip_todo_entry_s cn38xxp2; | ||
1258 | struct cvmx_pip_todo_entry_s cn50xx; | ||
1259 | struct cvmx_pip_todo_entry_s cn52xx; | ||
1260 | struct cvmx_pip_todo_entry_s cn52xxp1; | ||
1261 | struct cvmx_pip_todo_entry_s cn56xx; | ||
1262 | struct cvmx_pip_todo_entry_s cn56xxp1; | ||
1263 | struct cvmx_pip_todo_entry_s cn58xx; | ||
1264 | struct cvmx_pip_todo_entry_s cn58xxp1; | ||
1265 | }; | ||
1266 | |||
1267 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-pip.h b/drivers/staging/octeon/cvmx-pip.h new file mode 100644 index 000000000000..78dbce8f2c5e --- /dev/null +++ b/drivers/staging/octeon/cvmx-pip.h | |||
@@ -0,0 +1,524 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Interface to the hardware Packet Input Processing unit. | ||
30 | * | ||
31 | */ | ||
32 | |||
33 | #ifndef __CVMX_PIP_H__ | ||
34 | #define __CVMX_PIP_H__ | ||
35 | |||
36 | #include "cvmx-wqe.h" | ||
37 | #include "cvmx-fpa.h" | ||
38 | #include "cvmx-pip-defs.h" | ||
39 | |||
40 | #define CVMX_PIP_NUM_INPUT_PORTS 40 | ||
41 | #define CVMX_PIP_NUM_WATCHERS 4 | ||
42 | |||
43 | /* | ||
44 | * Encodes the different error and exception codes | ||
45 | */ | ||
46 | typedef enum { | ||
47 | CVMX_PIP_L4_NO_ERR = 0ull, | ||
48 | /* | ||
49 | * 1 = TCP (UDP) packet not long enough to cover TCP (UDP) | ||
50 | * header | ||
51 | */ | ||
52 | CVMX_PIP_L4_MAL_ERR = 1ull, | ||
53 | /* 2 = TCP/UDP checksum failure */ | ||
54 | CVMX_PIP_CHK_ERR = 2ull, | ||
55 | /* | ||
56 | * 3 = TCP/UDP length check (TCP/UDP length does not match IP | ||
57 | * length). | ||
58 | */ | ||
59 | CVMX_PIP_L4_LENGTH_ERR = 3ull, | ||
60 | /* 4 = illegal TCP/UDP port (either source or dest port is zero) */ | ||
61 | CVMX_PIP_BAD_PRT_ERR = 4ull, | ||
62 | /* 8 = TCP flags = FIN only */ | ||
63 | CVMX_PIP_TCP_FLG8_ERR = 8ull, | ||
64 | /* 9 = TCP flags = 0 */ | ||
65 | CVMX_PIP_TCP_FLG9_ERR = 9ull, | ||
66 | /* 10 = TCP flags = FIN+RST+* */ | ||
67 | CVMX_PIP_TCP_FLG10_ERR = 10ull, | ||
68 | /* 11 = TCP flags = SYN+URG+* */ | ||
69 | CVMX_PIP_TCP_FLG11_ERR = 11ull, | ||
70 | /* 12 = TCP flags = SYN+RST+* */ | ||
71 | CVMX_PIP_TCP_FLG12_ERR = 12ull, | ||
72 | /* 13 = TCP flags = SYN+FIN+* */ | ||
73 | CVMX_PIP_TCP_FLG13_ERR = 13ull | ||
74 | } cvmx_pip_l4_err_t; | ||
75 | |||
76 | typedef enum { | ||
77 | |||
78 | CVMX_PIP_IP_NO_ERR = 0ull, | ||
79 | /* 1 = not IPv4 or IPv6 */ | ||
80 | CVMX_PIP_NOT_IP = 1ull, | ||
81 | /* 2 = IPv4 header checksum violation */ | ||
82 | CVMX_PIP_IPV4_HDR_CHK = 2ull, | ||
83 | /* 3 = malformed (packet not long enough to cover IP hdr) */ | ||
84 | CVMX_PIP_IP_MAL_HDR = 3ull, | ||
85 | /* 4 = malformed (packet not long enough to cover len in IP hdr) */ | ||
86 | CVMX_PIP_IP_MAL_PKT = 4ull, | ||
87 | /* 5 = TTL / hop count equal zero */ | ||
88 | CVMX_PIP_TTL_HOP = 5ull, | ||
89 | /* 6 = IPv4 options / IPv6 early extension headers */ | ||
90 | CVMX_PIP_OPTS = 6ull | ||
91 | } cvmx_pip_ip_exc_t; | ||
92 | |||
93 | /** | ||
94 | * NOTES | ||
95 | * late collision (data received before collision) | ||
96 | * late collisions cannot be detected by the receiver | ||
97 | * they would appear as JAM bits which would appear as bad FCS | ||
98 | * or carrier extend error which is CVMX_PIP_EXTEND_ERR | ||
99 | */ | ||
100 | typedef enum { | ||
101 | /* No error */ | ||
102 | CVMX_PIP_RX_NO_ERR = 0ull, | ||
103 | /* RGM+SPI 1 = partially received packet (buffering/bandwidth | ||
104 | * not adequate) */ | ||
105 | CVMX_PIP_PARTIAL_ERR = 1ull, | ||
106 | /* RGM+SPI 2 = receive packet too large and truncated */ | ||
107 | CVMX_PIP_JABBER_ERR = 2ull, | ||
108 | /* | ||
109 | * RGM 3 = max frame error (pkt len > max frame len) (with FCS | ||
110 | * error) | ||
111 | */ | ||
112 | CVMX_PIP_OVER_FCS_ERR = 3ull, | ||
113 | /* RGM+SPI 4 = max frame error (pkt len > max frame len) */ | ||
114 | CVMX_PIP_OVER_ERR = 4ull, | ||
115 | /* | ||
116 | * RGM 5 = nibble error (data not byte multiple - 100M and 10M | ||
117 | * only) | ||
118 | */ | ||
119 | CVMX_PIP_ALIGN_ERR = 5ull, | ||
120 | /* | ||
121 | * RGM 6 = min frame error (pkt len < min frame len) (with FCS | ||
122 | * error) | ||
123 | */ | ||
124 | CVMX_PIP_UNDER_FCS_ERR = 6ull, | ||
125 | /* RGM 7 = FCS error */ | ||
126 | CVMX_PIP_GMX_FCS_ERR = 7ull, | ||
127 | /* RGM+SPI 8 = min frame error (pkt len < min frame len) */ | ||
128 | CVMX_PIP_UNDER_ERR = 8ull, | ||
129 | /* RGM 9 = Frame carrier extend error */ | ||
130 | CVMX_PIP_EXTEND_ERR = 9ull, | ||
131 | /* | ||
132 | * RGM 10 = length mismatch (len did not match len in L2 | ||
133 | * length/type) | ||
134 | */ | ||
135 | CVMX_PIP_LENGTH_ERR = 10ull, | ||
136 | /* RGM 11 = Frame error (some or all data bits marked err) */ | ||
137 | CVMX_PIP_DAT_ERR = 11ull, | ||
138 | /* SPI 11 = DIP4 error */ | ||
139 | CVMX_PIP_DIP_ERR = 11ull, | ||
140 | /* | ||
141 | * RGM 12 = packet was not large enough to pass the skipper - | ||
142 | * no inspection could occur. | ||
143 | */ | ||
144 | CVMX_PIP_SKIP_ERR = 12ull, | ||
145 | /* | ||
146 | * RGM 13 = studder error (data not repeated - 100M and 10M | ||
147 | * only) | ||
148 | */ | ||
149 | CVMX_PIP_NIBBLE_ERR = 13ull, | ||
150 | /* RGM+SPI 16 = FCS error */ | ||
151 | CVMX_PIP_PIP_FCS = 16L, | ||
152 | /* | ||
153 | * RGM+SPI+PCI 17 = packet was not large enough to pass the | ||
154 | * skipper - no inspection could occur. | ||
155 | */ | ||
156 | CVMX_PIP_PIP_SKIP_ERR = 17L, | ||
157 | /* | ||
158 | * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to | ||
159 | * cover L2 hdr). | ||
160 | */ | ||
161 | CVMX_PIP_PIP_L2_MAL_HDR = 18L | ||
162 | /* | ||
163 | * NOTES: xx = late collision (data received before collision) | ||
164 | * late collisions cannot be detected by the receiver | ||
165 | * they would appear as JAM bits which would appear as | ||
166 | * bad FCS or carrier extend error which is | ||
167 | * CVMX_PIP_EXTEND_ERR | ||
168 | */ | ||
169 | } cvmx_pip_rcv_err_t; | ||
170 | |||
171 | /** | ||
172 | * This defines the err_code field errors in the work Q entry | ||
173 | */ | ||
174 | typedef union { | ||
175 | cvmx_pip_l4_err_t l4_err; | ||
176 | cvmx_pip_ip_exc_t ip_exc; | ||
177 | cvmx_pip_rcv_err_t rcv_err; | ||
178 | } cvmx_pip_err_t; | ||
179 | |||
180 | /** | ||
181 | * Status statistics for a port | ||
182 | */ | ||
183 | typedef struct { | ||
184 | /* Inbound octets marked to be dropped by the IPD */ | ||
185 | uint32_t dropped_octets; | ||
186 | /* Inbound packets marked to be dropped by the IPD */ | ||
187 | uint32_t dropped_packets; | ||
188 | /* RAW PCI Packets received by PIP per port */ | ||
189 | uint32_t pci_raw_packets; | ||
190 | /* Number of octets processed by PIP */ | ||
191 | uint32_t octets; | ||
192 | /* Number of packets processed by PIP */ | ||
193 | uint32_t packets; | ||
194 | /* | ||
195 | * Number of indentified L2 multicast packets. Does not | ||
196 | * include broadcast packets. Only includes packets whose | ||
197 | * parse mode is SKIP_TO_L2 | ||
198 | */ | ||
199 | uint32_t multicast_packets; | ||
200 | /* | ||
201 | * Number of indentified L2 broadcast packets. Does not | ||
202 | * include multicast packets. Only includes packets whose | ||
203 | * parse mode is SKIP_TO_L2 | ||
204 | */ | ||
205 | uint32_t broadcast_packets; | ||
206 | /* Number of 64B packets */ | ||
207 | uint32_t len_64_packets; | ||
208 | /* Number of 65-127B packets */ | ||
209 | uint32_t len_65_127_packets; | ||
210 | /* Number of 128-255B packets */ | ||
211 | uint32_t len_128_255_packets; | ||
212 | /* Number of 256-511B packets */ | ||
213 | uint32_t len_256_511_packets; | ||
214 | /* Number of 512-1023B packets */ | ||
215 | uint32_t len_512_1023_packets; | ||
216 | /* Number of 1024-1518B packets */ | ||
217 | uint32_t len_1024_1518_packets; | ||
218 | /* Number of 1519-max packets */ | ||
219 | uint32_t len_1519_max_packets; | ||
220 | /* Number of packets with FCS or Align opcode errors */ | ||
221 | uint32_t fcs_align_err_packets; | ||
222 | /* Number of packets with length < min */ | ||
223 | uint32_t runt_packets; | ||
224 | /* Number of packets with length < min and FCS error */ | ||
225 | uint32_t runt_crc_packets; | ||
226 | /* Number of packets with length > max */ | ||
227 | uint32_t oversize_packets; | ||
228 | /* Number of packets with length > max and FCS error */ | ||
229 | uint32_t oversize_crc_packets; | ||
230 | /* Number of packets without GMX/SPX/PCI errors received by PIP */ | ||
231 | uint32_t inb_packets; | ||
232 | /* | ||
233 | * Total number of octets from all packets received by PIP, | ||
234 | * including CRC | ||
235 | */ | ||
236 | uint64_t inb_octets; | ||
237 | /* Number of packets with GMX/SPX/PCI errors received by PIP */ | ||
238 | uint16_t inb_errors; | ||
239 | } cvmx_pip_port_status_t; | ||
240 | |||
241 | /** | ||
242 | * Definition of the PIP custom header that can be prepended | ||
243 | * to a packet by external hardware. | ||
244 | */ | ||
245 | typedef union { | ||
246 | uint64_t u64; | ||
247 | struct { | ||
248 | /* | ||
249 | * Documented as R - Set if the Packet is RAWFULL. If | ||
250 | * set, this header must be the full 8 bytes. | ||
251 | */ | ||
252 | uint64_t rawfull:1; | ||
253 | /* Must be zero */ | ||
254 | uint64_t reserved0:5; | ||
255 | /* PIP parse mode for this packet */ | ||
256 | uint64_t parse_mode:2; | ||
257 | /* Must be zero */ | ||
258 | uint64_t reserved1:1; | ||
259 | /* | ||
260 | * Skip amount, including this header, to the | ||
261 | * beginning of the packet | ||
262 | */ | ||
263 | uint64_t skip_len:7; | ||
264 | /* Must be zero */ | ||
265 | uint64_t reserved2:6; | ||
266 | /* POW input queue for this packet */ | ||
267 | uint64_t qos:3; | ||
268 | /* POW input group for this packet */ | ||
269 | uint64_t grp:4; | ||
270 | /* | ||
271 | * Flag to store this packet in the work queue entry, | ||
272 | * if possible | ||
273 | */ | ||
274 | uint64_t rs:1; | ||
275 | /* POW input tag type */ | ||
276 | uint64_t tag_type:2; | ||
277 | /* POW input tag */ | ||
278 | uint64_t tag:32; | ||
279 | } s; | ||
280 | } cvmx_pip_pkt_inst_hdr_t; | ||
281 | |||
282 | /* CSR typedefs have been moved to cvmx-csr-*.h */ | ||
283 | |||
284 | /** | ||
285 | * Configure an ethernet input port | ||
286 | * | ||
287 | * @port_num: Port number to configure | ||
288 | * @port_cfg: Port hardware configuration | ||
289 | * @port_tag_cfg: | ||
290 | * Port POW tagging configuration | ||
291 | */ | ||
292 | static inline void cvmx_pip_config_port(uint64_t port_num, | ||
293 | union cvmx_pip_prt_cfgx port_cfg, | ||
294 | union cvmx_pip_prt_tagx port_tag_cfg) | ||
295 | { | ||
296 | cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64); | ||
297 | cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64); | ||
298 | } | ||
299 | #if 0 | ||
300 | /** | ||
301 | * @deprecated This function is a thin wrapper around the Pass1 version | ||
302 | * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for | ||
303 | * setting the group that is incompatible with this function, | ||
304 | * the preferred upgrade path is to use the CSR directly. | ||
305 | * | ||
306 | * Configure the global QoS packet watchers. Each watcher is | ||
307 | * capable of matching a field in a packet to determine the | ||
308 | * QoS queue for scheduling. | ||
309 | * | ||
310 | * @watcher: Watcher number to configure (0 - 3). | ||
311 | * @match_type: Watcher match type | ||
312 | * @match_value: | ||
313 | * Value the watcher will match against | ||
314 | * @qos: QoS queue for packets matching this watcher | ||
315 | */ | ||
316 | static inline void cvmx_pip_config_watcher(uint64_t watcher, | ||
317 | cvmx_pip_qos_watch_types match_type, | ||
318 | uint64_t match_value, uint64_t qos) | ||
319 | { | ||
320 | cvmx_pip_port_watcher_cfg_t watcher_config; | ||
321 | |||
322 | watcher_config.u64 = 0; | ||
323 | watcher_config.s.match_type = match_type; | ||
324 | watcher_config.s.match_value = match_value; | ||
325 | watcher_config.s.qos = qos; | ||
326 | |||
327 | cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64); | ||
328 | } | ||
329 | #endif | ||
330 | /** | ||
331 | * Configure the VLAN priority to QoS queue mapping. | ||
332 | * | ||
333 | * @vlan_priority: | ||
334 | * VLAN priority (0-7) | ||
335 | * @qos: QoS queue for packets matching this watcher | ||
336 | */ | ||
337 | static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, | ||
338 | uint64_t qos) | ||
339 | { | ||
340 | union cvmx_pip_qos_vlanx pip_qos_vlanx; | ||
341 | pip_qos_vlanx.u64 = 0; | ||
342 | pip_qos_vlanx.s.qos = qos; | ||
343 | cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); | ||
344 | } | ||
345 | |||
346 | /** | ||
347 | * Configure the Diffserv to QoS queue mapping. | ||
348 | * | ||
349 | * @diffserv: Diffserv field value (0-63) | ||
350 | * @qos: QoS queue for packets matching this watcher | ||
351 | */ | ||
352 | static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos) | ||
353 | { | ||
354 | union cvmx_pip_qos_diffx pip_qos_diffx; | ||
355 | pip_qos_diffx.u64 = 0; | ||
356 | pip_qos_diffx.s.qos = qos; | ||
357 | cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); | ||
358 | } | ||
359 | |||
360 | /** | ||
361 | * Get the status counters for a port. | ||
362 | * | ||
363 | * @port_num: Port number to get statistics for. | ||
364 | * @clear: Set to 1 to clear the counters after they are read | ||
365 | * @status: Where to put the results. | ||
366 | */ | ||
367 | static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, | ||
368 | cvmx_pip_port_status_t *status) | ||
369 | { | ||
370 | union cvmx_pip_stat_ctl pip_stat_ctl; | ||
371 | union cvmx_pip_stat0_prtx stat0; | ||
372 | union cvmx_pip_stat1_prtx stat1; | ||
373 | union cvmx_pip_stat2_prtx stat2; | ||
374 | union cvmx_pip_stat3_prtx stat3; | ||
375 | union cvmx_pip_stat4_prtx stat4; | ||
376 | union cvmx_pip_stat5_prtx stat5; | ||
377 | union cvmx_pip_stat6_prtx stat6; | ||
378 | union cvmx_pip_stat7_prtx stat7; | ||
379 | union cvmx_pip_stat8_prtx stat8; | ||
380 | union cvmx_pip_stat9_prtx stat9; | ||
381 | union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx; | ||
382 | union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx; | ||
383 | union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx; | ||
384 | |||
385 | pip_stat_ctl.u64 = 0; | ||
386 | pip_stat_ctl.s.rdclr = clear; | ||
387 | cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); | ||
388 | |||
389 | stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num)); | ||
390 | stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num)); | ||
391 | stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num)); | ||
392 | stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num)); | ||
393 | stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num)); | ||
394 | stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num)); | ||
395 | stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num)); | ||
396 | stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num)); | ||
397 | stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num)); | ||
398 | stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num)); | ||
399 | pip_stat_inb_pktsx.u64 = | ||
400 | cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num)); | ||
401 | pip_stat_inb_octsx.u64 = | ||
402 | cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num)); | ||
403 | pip_stat_inb_errsx.u64 = | ||
404 | cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num)); | ||
405 | |||
406 | status->dropped_octets = stat0.s.drp_octs; | ||
407 | status->dropped_packets = stat0.s.drp_pkts; | ||
408 | status->octets = stat1.s.octs; | ||
409 | status->pci_raw_packets = stat2.s.raw; | ||
410 | status->packets = stat2.s.pkts; | ||
411 | status->multicast_packets = stat3.s.mcst; | ||
412 | status->broadcast_packets = stat3.s.bcst; | ||
413 | status->len_64_packets = stat4.s.h64; | ||
414 | status->len_65_127_packets = stat4.s.h65to127; | ||
415 | status->len_128_255_packets = stat5.s.h128to255; | ||
416 | status->len_256_511_packets = stat5.s.h256to511; | ||
417 | status->len_512_1023_packets = stat6.s.h512to1023; | ||
418 | status->len_1024_1518_packets = stat6.s.h1024to1518; | ||
419 | status->len_1519_max_packets = stat7.s.h1519; | ||
420 | status->fcs_align_err_packets = stat7.s.fcs; | ||
421 | status->runt_packets = stat8.s.undersz; | ||
422 | status->runt_crc_packets = stat8.s.frag; | ||
423 | status->oversize_packets = stat9.s.oversz; | ||
424 | status->oversize_crc_packets = stat9.s.jabber; | ||
425 | status->inb_packets = pip_stat_inb_pktsx.s.pkts; | ||
426 | status->inb_octets = pip_stat_inb_octsx.s.octs; | ||
427 | status->inb_errors = pip_stat_inb_errsx.s.errs; | ||
428 | |||
429 | if (cvmx_octeon_is_pass1()) { | ||
430 | /* | ||
431 | * Kludge to fix Octeon Pass 1 errata - Drop counts | ||
432 | * don't work. | ||
433 | */ | ||
434 | if (status->inb_packets > status->packets) | ||
435 | status->dropped_packets = | ||
436 | status->inb_packets - status->packets; | ||
437 | else | ||
438 | status->dropped_packets = 0; | ||
439 | if (status->inb_octets - status->inb_packets * 4 > | ||
440 | status->octets) | ||
441 | status->dropped_octets = | ||
442 | status->inb_octets - status->inb_packets * 4 - | ||
443 | status->octets; | ||
444 | else | ||
445 | status->dropped_octets = 0; | ||
446 | } | ||
447 | } | ||
448 | |||
449 | /** | ||
450 | * Configure the hardware CRC engine | ||
451 | * | ||
452 | * @interface: Interface to configure (0 or 1) | ||
453 | * @invert_result: | ||
454 | * Invert the result of the CRC | ||
455 | * @reflect: Reflect | ||
456 | * @initialization_vector: | ||
457 | * CRC initialization vector | ||
458 | */ | ||
459 | static inline void cvmx_pip_config_crc(uint64_t interface, | ||
460 | uint64_t invert_result, uint64_t reflect, | ||
461 | uint32_t initialization_vector) | ||
462 | { | ||
463 | if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) { | ||
464 | union cvmx_pip_crc_ctlx config; | ||
465 | union cvmx_pip_crc_ivx pip_crc_ivx; | ||
466 | |||
467 | config.u64 = 0; | ||
468 | config.s.invres = invert_result; | ||
469 | config.s.reflect = reflect; | ||
470 | cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64); | ||
471 | |||
472 | pip_crc_ivx.u64 = 0; | ||
473 | pip_crc_ivx.s.iv = initialization_vector; | ||
474 | cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64); | ||
475 | } | ||
476 | } | ||
477 | |||
478 | /** | ||
479 | * Clear all bits in a tag mask. This should be called on | ||
480 | * startup before any calls to cvmx_pip_tag_mask_set. Each bit | ||
481 | * set in the final mask represent a byte used in the packet for | ||
482 | * tag generation. | ||
483 | * | ||
484 | * @mask_index: Which tag mask to clear (0..3) | ||
485 | */ | ||
486 | static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index) | ||
487 | { | ||
488 | uint64_t index; | ||
489 | union cvmx_pip_tag_incx pip_tag_incx; | ||
490 | pip_tag_incx.u64 = 0; | ||
491 | pip_tag_incx.s.en = 0; | ||
492 | for (index = mask_index * 16; index < (mask_index + 1) * 16; index++) | ||
493 | cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); | ||
494 | } | ||
495 | |||
496 | /** | ||
497 | * Sets a range of bits in the tag mask. The tag mask is used | ||
498 | * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero. | ||
499 | * There are four separate masks that can be configured. | ||
500 | * | ||
501 | * @mask_index: Which tag mask to modify (0..3) | ||
502 | * @offset: Offset into the bitmask to set bits at. Use the GCC macro | ||
503 | * offsetof() to determine the offsets into packet headers. | ||
504 | * For example, offsetof(ethhdr, protocol) returns the offset | ||
505 | * of the ethernet protocol field. The bitmask selects which | ||
506 | * bytes to include the the tag, with bit offset X selecting | ||
507 | * byte at offset X from the beginning of the packet data. | ||
508 | * @len: Number of bytes to include. Usually this is the sizeof() | ||
509 | * the field. | ||
510 | */ | ||
511 | static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, | ||
512 | uint64_t len) | ||
513 | { | ||
514 | while (len--) { | ||
515 | union cvmx_pip_tag_incx pip_tag_incx; | ||
516 | uint64_t index = mask_index * 16 + offset / 8; | ||
517 | pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index)); | ||
518 | pip_tag_incx.s.en |= 0x80 >> (offset & 0x7); | ||
519 | cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); | ||
520 | offset++; | ||
521 | } | ||
522 | } | ||
523 | |||
524 | #endif /* __CVMX_PIP_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-pko-defs.h b/drivers/staging/octeon/cvmx-pko-defs.h new file mode 100644 index 000000000000..50e779cf1ad8 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pko-defs.h | |||
@@ -0,0 +1,1133 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_PKO_DEFS_H__ | ||
29 | #define __CVMX_PKO_DEFS_H__ | ||
30 | |||
31 | #define CVMX_PKO_MEM_COUNT0 \ | ||
32 | CVMX_ADD_IO_SEG(0x0001180050001080ull) | ||
33 | #define CVMX_PKO_MEM_COUNT1 \ | ||
34 | CVMX_ADD_IO_SEG(0x0001180050001088ull) | ||
35 | #define CVMX_PKO_MEM_DEBUG0 \ | ||
36 | CVMX_ADD_IO_SEG(0x0001180050001100ull) | ||
37 | #define CVMX_PKO_MEM_DEBUG1 \ | ||
38 | CVMX_ADD_IO_SEG(0x0001180050001108ull) | ||
39 | #define CVMX_PKO_MEM_DEBUG10 \ | ||
40 | CVMX_ADD_IO_SEG(0x0001180050001150ull) | ||
41 | #define CVMX_PKO_MEM_DEBUG11 \ | ||
42 | CVMX_ADD_IO_SEG(0x0001180050001158ull) | ||
43 | #define CVMX_PKO_MEM_DEBUG12 \ | ||
44 | CVMX_ADD_IO_SEG(0x0001180050001160ull) | ||
45 | #define CVMX_PKO_MEM_DEBUG13 \ | ||
46 | CVMX_ADD_IO_SEG(0x0001180050001168ull) | ||
47 | #define CVMX_PKO_MEM_DEBUG14 \ | ||
48 | CVMX_ADD_IO_SEG(0x0001180050001170ull) | ||
49 | #define CVMX_PKO_MEM_DEBUG2 \ | ||
50 | CVMX_ADD_IO_SEG(0x0001180050001110ull) | ||
51 | #define CVMX_PKO_MEM_DEBUG3 \ | ||
52 | CVMX_ADD_IO_SEG(0x0001180050001118ull) | ||
53 | #define CVMX_PKO_MEM_DEBUG4 \ | ||
54 | CVMX_ADD_IO_SEG(0x0001180050001120ull) | ||
55 | #define CVMX_PKO_MEM_DEBUG5 \ | ||
56 | CVMX_ADD_IO_SEG(0x0001180050001128ull) | ||
57 | #define CVMX_PKO_MEM_DEBUG6 \ | ||
58 | CVMX_ADD_IO_SEG(0x0001180050001130ull) | ||
59 | #define CVMX_PKO_MEM_DEBUG7 \ | ||
60 | CVMX_ADD_IO_SEG(0x0001180050001138ull) | ||
61 | #define CVMX_PKO_MEM_DEBUG8 \ | ||
62 | CVMX_ADD_IO_SEG(0x0001180050001140ull) | ||
63 | #define CVMX_PKO_MEM_DEBUG9 \ | ||
64 | CVMX_ADD_IO_SEG(0x0001180050001148ull) | ||
65 | #define CVMX_PKO_MEM_PORT_PTRS \ | ||
66 | CVMX_ADD_IO_SEG(0x0001180050001010ull) | ||
67 | #define CVMX_PKO_MEM_PORT_QOS \ | ||
68 | CVMX_ADD_IO_SEG(0x0001180050001018ull) | ||
69 | #define CVMX_PKO_MEM_PORT_RATE0 \ | ||
70 | CVMX_ADD_IO_SEG(0x0001180050001020ull) | ||
71 | #define CVMX_PKO_MEM_PORT_RATE1 \ | ||
72 | CVMX_ADD_IO_SEG(0x0001180050001028ull) | ||
73 | #define CVMX_PKO_MEM_QUEUE_PTRS \ | ||
74 | CVMX_ADD_IO_SEG(0x0001180050001000ull) | ||
75 | #define CVMX_PKO_MEM_QUEUE_QOS \ | ||
76 | CVMX_ADD_IO_SEG(0x0001180050001008ull) | ||
77 | #define CVMX_PKO_REG_BIST_RESULT \ | ||
78 | CVMX_ADD_IO_SEG(0x0001180050000080ull) | ||
79 | #define CVMX_PKO_REG_CMD_BUF \ | ||
80 | CVMX_ADD_IO_SEG(0x0001180050000010ull) | ||
81 | #define CVMX_PKO_REG_CRC_CTLX(offset) \ | ||
82 | CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8)) | ||
83 | #define CVMX_PKO_REG_CRC_ENABLE \ | ||
84 | CVMX_ADD_IO_SEG(0x0001180050000020ull) | ||
85 | #define CVMX_PKO_REG_CRC_IVX(offset) \ | ||
86 | CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8)) | ||
87 | #define CVMX_PKO_REG_DEBUG0 \ | ||
88 | CVMX_ADD_IO_SEG(0x0001180050000098ull) | ||
89 | #define CVMX_PKO_REG_DEBUG1 \ | ||
90 | CVMX_ADD_IO_SEG(0x00011800500000A0ull) | ||
91 | #define CVMX_PKO_REG_DEBUG2 \ | ||
92 | CVMX_ADD_IO_SEG(0x00011800500000A8ull) | ||
93 | #define CVMX_PKO_REG_DEBUG3 \ | ||
94 | CVMX_ADD_IO_SEG(0x00011800500000B0ull) | ||
95 | #define CVMX_PKO_REG_ENGINE_INFLIGHT \ | ||
96 | CVMX_ADD_IO_SEG(0x0001180050000050ull) | ||
97 | #define CVMX_PKO_REG_ENGINE_THRESH \ | ||
98 | CVMX_ADD_IO_SEG(0x0001180050000058ull) | ||
99 | #define CVMX_PKO_REG_ERROR \ | ||
100 | CVMX_ADD_IO_SEG(0x0001180050000088ull) | ||
101 | #define CVMX_PKO_REG_FLAGS \ | ||
102 | CVMX_ADD_IO_SEG(0x0001180050000000ull) | ||
103 | #define CVMX_PKO_REG_GMX_PORT_MODE \ | ||
104 | CVMX_ADD_IO_SEG(0x0001180050000018ull) | ||
105 | #define CVMX_PKO_REG_INT_MASK \ | ||
106 | CVMX_ADD_IO_SEG(0x0001180050000090ull) | ||
107 | #define CVMX_PKO_REG_QUEUE_MODE \ | ||
108 | CVMX_ADD_IO_SEG(0x0001180050000048ull) | ||
109 | #define CVMX_PKO_REG_QUEUE_PTRS1 \ | ||
110 | CVMX_ADD_IO_SEG(0x0001180050000100ull) | ||
111 | #define CVMX_PKO_REG_READ_IDX \ | ||
112 | CVMX_ADD_IO_SEG(0x0001180050000008ull) | ||
113 | |||
114 | union cvmx_pko_mem_count0 { | ||
115 | uint64_t u64; | ||
116 | struct cvmx_pko_mem_count0_s { | ||
117 | uint64_t reserved_32_63:32; | ||
118 | uint64_t count:32; | ||
119 | } s; | ||
120 | struct cvmx_pko_mem_count0_s cn30xx; | ||
121 | struct cvmx_pko_mem_count0_s cn31xx; | ||
122 | struct cvmx_pko_mem_count0_s cn38xx; | ||
123 | struct cvmx_pko_mem_count0_s cn38xxp2; | ||
124 | struct cvmx_pko_mem_count0_s cn50xx; | ||
125 | struct cvmx_pko_mem_count0_s cn52xx; | ||
126 | struct cvmx_pko_mem_count0_s cn52xxp1; | ||
127 | struct cvmx_pko_mem_count0_s cn56xx; | ||
128 | struct cvmx_pko_mem_count0_s cn56xxp1; | ||
129 | struct cvmx_pko_mem_count0_s cn58xx; | ||
130 | struct cvmx_pko_mem_count0_s cn58xxp1; | ||
131 | }; | ||
132 | |||
133 | union cvmx_pko_mem_count1 { | ||
134 | uint64_t u64; | ||
135 | struct cvmx_pko_mem_count1_s { | ||
136 | uint64_t reserved_48_63:16; | ||
137 | uint64_t count:48; | ||
138 | } s; | ||
139 | struct cvmx_pko_mem_count1_s cn30xx; | ||
140 | struct cvmx_pko_mem_count1_s cn31xx; | ||
141 | struct cvmx_pko_mem_count1_s cn38xx; | ||
142 | struct cvmx_pko_mem_count1_s cn38xxp2; | ||
143 | struct cvmx_pko_mem_count1_s cn50xx; | ||
144 | struct cvmx_pko_mem_count1_s cn52xx; | ||
145 | struct cvmx_pko_mem_count1_s cn52xxp1; | ||
146 | struct cvmx_pko_mem_count1_s cn56xx; | ||
147 | struct cvmx_pko_mem_count1_s cn56xxp1; | ||
148 | struct cvmx_pko_mem_count1_s cn58xx; | ||
149 | struct cvmx_pko_mem_count1_s cn58xxp1; | ||
150 | }; | ||
151 | |||
152 | union cvmx_pko_mem_debug0 { | ||
153 | uint64_t u64; | ||
154 | struct cvmx_pko_mem_debug0_s { | ||
155 | uint64_t fau:28; | ||
156 | uint64_t cmd:14; | ||
157 | uint64_t segs:6; | ||
158 | uint64_t size:16; | ||
159 | } s; | ||
160 | struct cvmx_pko_mem_debug0_s cn30xx; | ||
161 | struct cvmx_pko_mem_debug0_s cn31xx; | ||
162 | struct cvmx_pko_mem_debug0_s cn38xx; | ||
163 | struct cvmx_pko_mem_debug0_s cn38xxp2; | ||
164 | struct cvmx_pko_mem_debug0_s cn50xx; | ||
165 | struct cvmx_pko_mem_debug0_s cn52xx; | ||
166 | struct cvmx_pko_mem_debug0_s cn52xxp1; | ||
167 | struct cvmx_pko_mem_debug0_s cn56xx; | ||
168 | struct cvmx_pko_mem_debug0_s cn56xxp1; | ||
169 | struct cvmx_pko_mem_debug0_s cn58xx; | ||
170 | struct cvmx_pko_mem_debug0_s cn58xxp1; | ||
171 | }; | ||
172 | |||
173 | union cvmx_pko_mem_debug1 { | ||
174 | uint64_t u64; | ||
175 | struct cvmx_pko_mem_debug1_s { | ||
176 | uint64_t i:1; | ||
177 | uint64_t back:4; | ||
178 | uint64_t pool:3; | ||
179 | uint64_t size:16; | ||
180 | uint64_t ptr:40; | ||
181 | } s; | ||
182 | struct cvmx_pko_mem_debug1_s cn30xx; | ||
183 | struct cvmx_pko_mem_debug1_s cn31xx; | ||
184 | struct cvmx_pko_mem_debug1_s cn38xx; | ||
185 | struct cvmx_pko_mem_debug1_s cn38xxp2; | ||
186 | struct cvmx_pko_mem_debug1_s cn50xx; | ||
187 | struct cvmx_pko_mem_debug1_s cn52xx; | ||
188 | struct cvmx_pko_mem_debug1_s cn52xxp1; | ||
189 | struct cvmx_pko_mem_debug1_s cn56xx; | ||
190 | struct cvmx_pko_mem_debug1_s cn56xxp1; | ||
191 | struct cvmx_pko_mem_debug1_s cn58xx; | ||
192 | struct cvmx_pko_mem_debug1_s cn58xxp1; | ||
193 | }; | ||
194 | |||
195 | union cvmx_pko_mem_debug10 { | ||
196 | uint64_t u64; | ||
197 | struct cvmx_pko_mem_debug10_s { | ||
198 | uint64_t reserved_0_63:64; | ||
199 | } s; | ||
200 | struct cvmx_pko_mem_debug10_cn30xx { | ||
201 | uint64_t fau:28; | ||
202 | uint64_t cmd:14; | ||
203 | uint64_t segs:6; | ||
204 | uint64_t size:16; | ||
205 | } cn30xx; | ||
206 | struct cvmx_pko_mem_debug10_cn30xx cn31xx; | ||
207 | struct cvmx_pko_mem_debug10_cn30xx cn38xx; | ||
208 | struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; | ||
209 | struct cvmx_pko_mem_debug10_cn50xx { | ||
210 | uint64_t reserved_49_63:15; | ||
211 | uint64_t ptrs1:17; | ||
212 | uint64_t reserved_17_31:15; | ||
213 | uint64_t ptrs2:17; | ||
214 | } cn50xx; | ||
215 | struct cvmx_pko_mem_debug10_cn50xx cn52xx; | ||
216 | struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; | ||
217 | struct cvmx_pko_mem_debug10_cn50xx cn56xx; | ||
218 | struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; | ||
219 | struct cvmx_pko_mem_debug10_cn50xx cn58xx; | ||
220 | struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; | ||
221 | }; | ||
222 | |||
223 | union cvmx_pko_mem_debug11 { | ||
224 | uint64_t u64; | ||
225 | struct cvmx_pko_mem_debug11_s { | ||
226 | uint64_t i:1; | ||
227 | uint64_t back:4; | ||
228 | uint64_t pool:3; | ||
229 | uint64_t size:16; | ||
230 | uint64_t reserved_0_39:40; | ||
231 | } s; | ||
232 | struct cvmx_pko_mem_debug11_cn30xx { | ||
233 | uint64_t i:1; | ||
234 | uint64_t back:4; | ||
235 | uint64_t pool:3; | ||
236 | uint64_t size:16; | ||
237 | uint64_t ptr:40; | ||
238 | } cn30xx; | ||
239 | struct cvmx_pko_mem_debug11_cn30xx cn31xx; | ||
240 | struct cvmx_pko_mem_debug11_cn30xx cn38xx; | ||
241 | struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; | ||
242 | struct cvmx_pko_mem_debug11_cn50xx { | ||
243 | uint64_t reserved_23_63:41; | ||
244 | uint64_t maj:1; | ||
245 | uint64_t uid:3; | ||
246 | uint64_t sop:1; | ||
247 | uint64_t len:1; | ||
248 | uint64_t chk:1; | ||
249 | uint64_t cnt:13; | ||
250 | uint64_t mod:3; | ||
251 | } cn50xx; | ||
252 | struct cvmx_pko_mem_debug11_cn50xx cn52xx; | ||
253 | struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; | ||
254 | struct cvmx_pko_mem_debug11_cn50xx cn56xx; | ||
255 | struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; | ||
256 | struct cvmx_pko_mem_debug11_cn50xx cn58xx; | ||
257 | struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; | ||
258 | }; | ||
259 | |||
260 | union cvmx_pko_mem_debug12 { | ||
261 | uint64_t u64; | ||
262 | struct cvmx_pko_mem_debug12_s { | ||
263 | uint64_t reserved_0_63:64; | ||
264 | } s; | ||
265 | struct cvmx_pko_mem_debug12_cn30xx { | ||
266 | uint64_t data:64; | ||
267 | } cn30xx; | ||
268 | struct cvmx_pko_mem_debug12_cn30xx cn31xx; | ||
269 | struct cvmx_pko_mem_debug12_cn30xx cn38xx; | ||
270 | struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; | ||
271 | struct cvmx_pko_mem_debug12_cn50xx { | ||
272 | uint64_t fau:28; | ||
273 | uint64_t cmd:14; | ||
274 | uint64_t segs:6; | ||
275 | uint64_t size:16; | ||
276 | } cn50xx; | ||
277 | struct cvmx_pko_mem_debug12_cn50xx cn52xx; | ||
278 | struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; | ||
279 | struct cvmx_pko_mem_debug12_cn50xx cn56xx; | ||
280 | struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; | ||
281 | struct cvmx_pko_mem_debug12_cn50xx cn58xx; | ||
282 | struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; | ||
283 | }; | ||
284 | |||
285 | union cvmx_pko_mem_debug13 { | ||
286 | uint64_t u64; | ||
287 | struct cvmx_pko_mem_debug13_s { | ||
288 | uint64_t i:1; | ||
289 | uint64_t back:4; | ||
290 | uint64_t pool:3; | ||
291 | uint64_t reserved_0_55:56; | ||
292 | } s; | ||
293 | struct cvmx_pko_mem_debug13_cn30xx { | ||
294 | uint64_t reserved_51_63:13; | ||
295 | uint64_t widx:17; | ||
296 | uint64_t ridx2:17; | ||
297 | uint64_t widx2:17; | ||
298 | } cn30xx; | ||
299 | struct cvmx_pko_mem_debug13_cn30xx cn31xx; | ||
300 | struct cvmx_pko_mem_debug13_cn30xx cn38xx; | ||
301 | struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; | ||
302 | struct cvmx_pko_mem_debug13_cn50xx { | ||
303 | uint64_t i:1; | ||
304 | uint64_t back:4; | ||
305 | uint64_t pool:3; | ||
306 | uint64_t size:16; | ||
307 | uint64_t ptr:40; | ||
308 | } cn50xx; | ||
309 | struct cvmx_pko_mem_debug13_cn50xx cn52xx; | ||
310 | struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; | ||
311 | struct cvmx_pko_mem_debug13_cn50xx cn56xx; | ||
312 | struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; | ||
313 | struct cvmx_pko_mem_debug13_cn50xx cn58xx; | ||
314 | struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; | ||
315 | }; | ||
316 | |||
317 | union cvmx_pko_mem_debug14 { | ||
318 | uint64_t u64; | ||
319 | struct cvmx_pko_mem_debug14_s { | ||
320 | uint64_t reserved_0_63:64; | ||
321 | } s; | ||
322 | struct cvmx_pko_mem_debug14_cn30xx { | ||
323 | uint64_t reserved_17_63:47; | ||
324 | uint64_t ridx:17; | ||
325 | } cn30xx; | ||
326 | struct cvmx_pko_mem_debug14_cn30xx cn31xx; | ||
327 | struct cvmx_pko_mem_debug14_cn30xx cn38xx; | ||
328 | struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; | ||
329 | struct cvmx_pko_mem_debug14_cn52xx { | ||
330 | uint64_t data:64; | ||
331 | } cn52xx; | ||
332 | struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; | ||
333 | struct cvmx_pko_mem_debug14_cn52xx cn56xx; | ||
334 | struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; | ||
335 | }; | ||
336 | |||
337 | union cvmx_pko_mem_debug2 { | ||
338 | uint64_t u64; | ||
339 | struct cvmx_pko_mem_debug2_s { | ||
340 | uint64_t i:1; | ||
341 | uint64_t back:4; | ||
342 | uint64_t pool:3; | ||
343 | uint64_t size:16; | ||
344 | uint64_t ptr:40; | ||
345 | } s; | ||
346 | struct cvmx_pko_mem_debug2_s cn30xx; | ||
347 | struct cvmx_pko_mem_debug2_s cn31xx; | ||
348 | struct cvmx_pko_mem_debug2_s cn38xx; | ||
349 | struct cvmx_pko_mem_debug2_s cn38xxp2; | ||
350 | struct cvmx_pko_mem_debug2_s cn50xx; | ||
351 | struct cvmx_pko_mem_debug2_s cn52xx; | ||
352 | struct cvmx_pko_mem_debug2_s cn52xxp1; | ||
353 | struct cvmx_pko_mem_debug2_s cn56xx; | ||
354 | struct cvmx_pko_mem_debug2_s cn56xxp1; | ||
355 | struct cvmx_pko_mem_debug2_s cn58xx; | ||
356 | struct cvmx_pko_mem_debug2_s cn58xxp1; | ||
357 | }; | ||
358 | |||
359 | union cvmx_pko_mem_debug3 { | ||
360 | uint64_t u64; | ||
361 | struct cvmx_pko_mem_debug3_s { | ||
362 | uint64_t reserved_0_63:64; | ||
363 | } s; | ||
364 | struct cvmx_pko_mem_debug3_cn30xx { | ||
365 | uint64_t i:1; | ||
366 | uint64_t back:4; | ||
367 | uint64_t pool:3; | ||
368 | uint64_t size:16; | ||
369 | uint64_t ptr:40; | ||
370 | } cn30xx; | ||
371 | struct cvmx_pko_mem_debug3_cn30xx cn31xx; | ||
372 | struct cvmx_pko_mem_debug3_cn30xx cn38xx; | ||
373 | struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; | ||
374 | struct cvmx_pko_mem_debug3_cn50xx { | ||
375 | uint64_t data:64; | ||
376 | } cn50xx; | ||
377 | struct cvmx_pko_mem_debug3_cn50xx cn52xx; | ||
378 | struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; | ||
379 | struct cvmx_pko_mem_debug3_cn50xx cn56xx; | ||
380 | struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; | ||
381 | struct cvmx_pko_mem_debug3_cn50xx cn58xx; | ||
382 | struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; | ||
383 | }; | ||
384 | |||
385 | union cvmx_pko_mem_debug4 { | ||
386 | uint64_t u64; | ||
387 | struct cvmx_pko_mem_debug4_s { | ||
388 | uint64_t reserved_0_63:64; | ||
389 | } s; | ||
390 | struct cvmx_pko_mem_debug4_cn30xx { | ||
391 | uint64_t data:64; | ||
392 | } cn30xx; | ||
393 | struct cvmx_pko_mem_debug4_cn30xx cn31xx; | ||
394 | struct cvmx_pko_mem_debug4_cn30xx cn38xx; | ||
395 | struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; | ||
396 | struct cvmx_pko_mem_debug4_cn50xx { | ||
397 | uint64_t cmnd_segs:3; | ||
398 | uint64_t cmnd_siz:16; | ||
399 | uint64_t cmnd_off:6; | ||
400 | uint64_t uid:3; | ||
401 | uint64_t dread_sop:1; | ||
402 | uint64_t init_dwrite:1; | ||
403 | uint64_t chk_once:1; | ||
404 | uint64_t chk_mode:1; | ||
405 | uint64_t active:1; | ||
406 | uint64_t static_p:1; | ||
407 | uint64_t qos:3; | ||
408 | uint64_t qcb_ridx:5; | ||
409 | uint64_t qid_off_max:4; | ||
410 | uint64_t qid_off:4; | ||
411 | uint64_t qid_base:8; | ||
412 | uint64_t wait:1; | ||
413 | uint64_t minor:2; | ||
414 | uint64_t major:3; | ||
415 | } cn50xx; | ||
416 | struct cvmx_pko_mem_debug4_cn52xx { | ||
417 | uint64_t curr_siz:8; | ||
418 | uint64_t curr_off:16; | ||
419 | uint64_t cmnd_segs:6; | ||
420 | uint64_t cmnd_siz:16; | ||
421 | uint64_t cmnd_off:6; | ||
422 | uint64_t uid:2; | ||
423 | uint64_t dread_sop:1; | ||
424 | uint64_t init_dwrite:1; | ||
425 | uint64_t chk_once:1; | ||
426 | uint64_t chk_mode:1; | ||
427 | uint64_t wait:1; | ||
428 | uint64_t minor:2; | ||
429 | uint64_t major:3; | ||
430 | } cn52xx; | ||
431 | struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; | ||
432 | struct cvmx_pko_mem_debug4_cn52xx cn56xx; | ||
433 | struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; | ||
434 | struct cvmx_pko_mem_debug4_cn50xx cn58xx; | ||
435 | struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; | ||
436 | }; | ||
437 | |||
438 | union cvmx_pko_mem_debug5 { | ||
439 | uint64_t u64; | ||
440 | struct cvmx_pko_mem_debug5_s { | ||
441 | uint64_t reserved_0_63:64; | ||
442 | } s; | ||
443 | struct cvmx_pko_mem_debug5_cn30xx { | ||
444 | uint64_t dwri_mod:1; | ||
445 | uint64_t dwri_sop:1; | ||
446 | uint64_t dwri_len:1; | ||
447 | uint64_t dwri_cnt:13; | ||
448 | uint64_t cmnd_siz:16; | ||
449 | uint64_t uid:1; | ||
450 | uint64_t xfer_wor:1; | ||
451 | uint64_t xfer_dwr:1; | ||
452 | uint64_t cbuf_fre:1; | ||
453 | uint64_t reserved_27_27:1; | ||
454 | uint64_t chk_mode:1; | ||
455 | uint64_t active:1; | ||
456 | uint64_t qos:3; | ||
457 | uint64_t qcb_ridx:5; | ||
458 | uint64_t qid_off:3; | ||
459 | uint64_t qid_base:7; | ||
460 | uint64_t wait:1; | ||
461 | uint64_t minor:2; | ||
462 | uint64_t major:4; | ||
463 | } cn30xx; | ||
464 | struct cvmx_pko_mem_debug5_cn30xx cn31xx; | ||
465 | struct cvmx_pko_mem_debug5_cn30xx cn38xx; | ||
466 | struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; | ||
467 | struct cvmx_pko_mem_debug5_cn50xx { | ||
468 | uint64_t curr_ptr:29; | ||
469 | uint64_t curr_siz:16; | ||
470 | uint64_t curr_off:16; | ||
471 | uint64_t cmnd_segs:3; | ||
472 | } cn50xx; | ||
473 | struct cvmx_pko_mem_debug5_cn52xx { | ||
474 | uint64_t reserved_54_63:10; | ||
475 | uint64_t nxt_inflt:6; | ||
476 | uint64_t curr_ptr:40; | ||
477 | uint64_t curr_siz:8; | ||
478 | } cn52xx; | ||
479 | struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; | ||
480 | struct cvmx_pko_mem_debug5_cn52xx cn56xx; | ||
481 | struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; | ||
482 | struct cvmx_pko_mem_debug5_cn50xx cn58xx; | ||
483 | struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; | ||
484 | }; | ||
485 | |||
486 | union cvmx_pko_mem_debug6 { | ||
487 | uint64_t u64; | ||
488 | struct cvmx_pko_mem_debug6_s { | ||
489 | uint64_t reserved_37_63:27; | ||
490 | uint64_t qid_offres:4; | ||
491 | uint64_t qid_offths:4; | ||
492 | uint64_t preempter:1; | ||
493 | uint64_t preemptee:1; | ||
494 | uint64_t preempted:1; | ||
495 | uint64_t active:1; | ||
496 | uint64_t statc:1; | ||
497 | uint64_t qos:3; | ||
498 | uint64_t qcb_ridx:5; | ||
499 | uint64_t qid_offmax:4; | ||
500 | uint64_t reserved_0_11:12; | ||
501 | } s; | ||
502 | struct cvmx_pko_mem_debug6_cn30xx { | ||
503 | uint64_t reserved_11_63:53; | ||
504 | uint64_t qid_offm:3; | ||
505 | uint64_t static_p:1; | ||
506 | uint64_t work_min:3; | ||
507 | uint64_t dwri_chk:1; | ||
508 | uint64_t dwri_uid:1; | ||
509 | uint64_t dwri_mod:2; | ||
510 | } cn30xx; | ||
511 | struct cvmx_pko_mem_debug6_cn30xx cn31xx; | ||
512 | struct cvmx_pko_mem_debug6_cn30xx cn38xx; | ||
513 | struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; | ||
514 | struct cvmx_pko_mem_debug6_cn50xx { | ||
515 | uint64_t reserved_11_63:53; | ||
516 | uint64_t curr_ptr:11; | ||
517 | } cn50xx; | ||
518 | struct cvmx_pko_mem_debug6_cn52xx { | ||
519 | uint64_t reserved_37_63:27; | ||
520 | uint64_t qid_offres:4; | ||
521 | uint64_t qid_offths:4; | ||
522 | uint64_t preempter:1; | ||
523 | uint64_t preemptee:1; | ||
524 | uint64_t preempted:1; | ||
525 | uint64_t active:1; | ||
526 | uint64_t statc:1; | ||
527 | uint64_t qos:3; | ||
528 | uint64_t qcb_ridx:5; | ||
529 | uint64_t qid_offmax:4; | ||
530 | uint64_t qid_off:4; | ||
531 | uint64_t qid_base:8; | ||
532 | } cn52xx; | ||
533 | struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; | ||
534 | struct cvmx_pko_mem_debug6_cn52xx cn56xx; | ||
535 | struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; | ||
536 | struct cvmx_pko_mem_debug6_cn50xx cn58xx; | ||
537 | struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; | ||
538 | }; | ||
539 | |||
540 | union cvmx_pko_mem_debug7 { | ||
541 | uint64_t u64; | ||
542 | struct cvmx_pko_mem_debug7_s { | ||
543 | uint64_t qos:5; | ||
544 | uint64_t tail:1; | ||
545 | uint64_t reserved_0_57:58; | ||
546 | } s; | ||
547 | struct cvmx_pko_mem_debug7_cn30xx { | ||
548 | uint64_t reserved_58_63:6; | ||
549 | uint64_t dwb:9; | ||
550 | uint64_t start:33; | ||
551 | uint64_t size:16; | ||
552 | } cn30xx; | ||
553 | struct cvmx_pko_mem_debug7_cn30xx cn31xx; | ||
554 | struct cvmx_pko_mem_debug7_cn30xx cn38xx; | ||
555 | struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; | ||
556 | struct cvmx_pko_mem_debug7_cn50xx { | ||
557 | uint64_t qos:5; | ||
558 | uint64_t tail:1; | ||
559 | uint64_t buf_siz:13; | ||
560 | uint64_t buf_ptr:33; | ||
561 | uint64_t qcb_widx:6; | ||
562 | uint64_t qcb_ridx:6; | ||
563 | } cn50xx; | ||
564 | struct cvmx_pko_mem_debug7_cn50xx cn52xx; | ||
565 | struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; | ||
566 | struct cvmx_pko_mem_debug7_cn50xx cn56xx; | ||
567 | struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; | ||
568 | struct cvmx_pko_mem_debug7_cn50xx cn58xx; | ||
569 | struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; | ||
570 | }; | ||
571 | |||
572 | union cvmx_pko_mem_debug8 { | ||
573 | uint64_t u64; | ||
574 | struct cvmx_pko_mem_debug8_s { | ||
575 | uint64_t reserved_59_63:5; | ||
576 | uint64_t tail:1; | ||
577 | uint64_t buf_siz:13; | ||
578 | uint64_t reserved_0_44:45; | ||
579 | } s; | ||
580 | struct cvmx_pko_mem_debug8_cn30xx { | ||
581 | uint64_t qos:5; | ||
582 | uint64_t tail:1; | ||
583 | uint64_t buf_siz:13; | ||
584 | uint64_t buf_ptr:33; | ||
585 | uint64_t qcb_widx:6; | ||
586 | uint64_t qcb_ridx:6; | ||
587 | } cn30xx; | ||
588 | struct cvmx_pko_mem_debug8_cn30xx cn31xx; | ||
589 | struct cvmx_pko_mem_debug8_cn30xx cn38xx; | ||
590 | struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; | ||
591 | struct cvmx_pko_mem_debug8_cn50xx { | ||
592 | uint64_t reserved_28_63:36; | ||
593 | uint64_t doorbell:20; | ||
594 | uint64_t reserved_6_7:2; | ||
595 | uint64_t static_p:1; | ||
596 | uint64_t s_tail:1; | ||
597 | uint64_t static_q:1; | ||
598 | uint64_t qos:3; | ||
599 | } cn50xx; | ||
600 | struct cvmx_pko_mem_debug8_cn52xx { | ||
601 | uint64_t reserved_29_63:35; | ||
602 | uint64_t preempter:1; | ||
603 | uint64_t doorbell:20; | ||
604 | uint64_t reserved_7_7:1; | ||
605 | uint64_t preemptee:1; | ||
606 | uint64_t static_p:1; | ||
607 | uint64_t s_tail:1; | ||
608 | uint64_t static_q:1; | ||
609 | uint64_t qos:3; | ||
610 | } cn52xx; | ||
611 | struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; | ||
612 | struct cvmx_pko_mem_debug8_cn52xx cn56xx; | ||
613 | struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; | ||
614 | struct cvmx_pko_mem_debug8_cn50xx cn58xx; | ||
615 | struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; | ||
616 | }; | ||
617 | |||
618 | union cvmx_pko_mem_debug9 { | ||
619 | uint64_t u64; | ||
620 | struct cvmx_pko_mem_debug9_s { | ||
621 | uint64_t reserved_49_63:15; | ||
622 | uint64_t ptrs0:17; | ||
623 | uint64_t reserved_0_31:32; | ||
624 | } s; | ||
625 | struct cvmx_pko_mem_debug9_cn30xx { | ||
626 | uint64_t reserved_28_63:36; | ||
627 | uint64_t doorbell:20; | ||
628 | uint64_t reserved_5_7:3; | ||
629 | uint64_t s_tail:1; | ||
630 | uint64_t static_q:1; | ||
631 | uint64_t qos:3; | ||
632 | } cn30xx; | ||
633 | struct cvmx_pko_mem_debug9_cn30xx cn31xx; | ||
634 | struct cvmx_pko_mem_debug9_cn38xx { | ||
635 | uint64_t reserved_28_63:36; | ||
636 | uint64_t doorbell:20; | ||
637 | uint64_t reserved_6_7:2; | ||
638 | uint64_t static_p:1; | ||
639 | uint64_t s_tail:1; | ||
640 | uint64_t static_q:1; | ||
641 | uint64_t qos:3; | ||
642 | } cn38xx; | ||
643 | struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; | ||
644 | struct cvmx_pko_mem_debug9_cn50xx { | ||
645 | uint64_t reserved_49_63:15; | ||
646 | uint64_t ptrs0:17; | ||
647 | uint64_t reserved_17_31:15; | ||
648 | uint64_t ptrs3:17; | ||
649 | } cn50xx; | ||
650 | struct cvmx_pko_mem_debug9_cn50xx cn52xx; | ||
651 | struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; | ||
652 | struct cvmx_pko_mem_debug9_cn50xx cn56xx; | ||
653 | struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; | ||
654 | struct cvmx_pko_mem_debug9_cn50xx cn58xx; | ||
655 | struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; | ||
656 | }; | ||
657 | |||
658 | union cvmx_pko_mem_port_ptrs { | ||
659 | uint64_t u64; | ||
660 | struct cvmx_pko_mem_port_ptrs_s { | ||
661 | uint64_t reserved_62_63:2; | ||
662 | uint64_t static_p:1; | ||
663 | uint64_t qos_mask:8; | ||
664 | uint64_t reserved_16_52:37; | ||
665 | uint64_t bp_port:6; | ||
666 | uint64_t eid:4; | ||
667 | uint64_t pid:6; | ||
668 | } s; | ||
669 | struct cvmx_pko_mem_port_ptrs_s cn52xx; | ||
670 | struct cvmx_pko_mem_port_ptrs_s cn52xxp1; | ||
671 | struct cvmx_pko_mem_port_ptrs_s cn56xx; | ||
672 | struct cvmx_pko_mem_port_ptrs_s cn56xxp1; | ||
673 | }; | ||
674 | |||
675 | union cvmx_pko_mem_port_qos { | ||
676 | uint64_t u64; | ||
677 | struct cvmx_pko_mem_port_qos_s { | ||
678 | uint64_t reserved_61_63:3; | ||
679 | uint64_t qos_mask:8; | ||
680 | uint64_t reserved_10_52:43; | ||
681 | uint64_t eid:4; | ||
682 | uint64_t pid:6; | ||
683 | } s; | ||
684 | struct cvmx_pko_mem_port_qos_s cn52xx; | ||
685 | struct cvmx_pko_mem_port_qos_s cn52xxp1; | ||
686 | struct cvmx_pko_mem_port_qos_s cn56xx; | ||
687 | struct cvmx_pko_mem_port_qos_s cn56xxp1; | ||
688 | }; | ||
689 | |||
690 | union cvmx_pko_mem_port_rate0 { | ||
691 | uint64_t u64; | ||
692 | struct cvmx_pko_mem_port_rate0_s { | ||
693 | uint64_t reserved_51_63:13; | ||
694 | uint64_t rate_word:19; | ||
695 | uint64_t rate_pkt:24; | ||
696 | uint64_t reserved_6_7:2; | ||
697 | uint64_t pid:6; | ||
698 | } s; | ||
699 | struct cvmx_pko_mem_port_rate0_s cn52xx; | ||
700 | struct cvmx_pko_mem_port_rate0_s cn52xxp1; | ||
701 | struct cvmx_pko_mem_port_rate0_s cn56xx; | ||
702 | struct cvmx_pko_mem_port_rate0_s cn56xxp1; | ||
703 | }; | ||
704 | |||
705 | union cvmx_pko_mem_port_rate1 { | ||
706 | uint64_t u64; | ||
707 | struct cvmx_pko_mem_port_rate1_s { | ||
708 | uint64_t reserved_32_63:32; | ||
709 | uint64_t rate_lim:24; | ||
710 | uint64_t reserved_6_7:2; | ||
711 | uint64_t pid:6; | ||
712 | } s; | ||
713 | struct cvmx_pko_mem_port_rate1_s cn52xx; | ||
714 | struct cvmx_pko_mem_port_rate1_s cn52xxp1; | ||
715 | struct cvmx_pko_mem_port_rate1_s cn56xx; | ||
716 | struct cvmx_pko_mem_port_rate1_s cn56xxp1; | ||
717 | }; | ||
718 | |||
719 | union cvmx_pko_mem_queue_ptrs { | ||
720 | uint64_t u64; | ||
721 | struct cvmx_pko_mem_queue_ptrs_s { | ||
722 | uint64_t s_tail:1; | ||
723 | uint64_t static_p:1; | ||
724 | uint64_t static_q:1; | ||
725 | uint64_t qos_mask:8; | ||
726 | uint64_t buf_ptr:36; | ||
727 | uint64_t tail:1; | ||
728 | uint64_t index:3; | ||
729 | uint64_t port:6; | ||
730 | uint64_t queue:7; | ||
731 | } s; | ||
732 | struct cvmx_pko_mem_queue_ptrs_s cn30xx; | ||
733 | struct cvmx_pko_mem_queue_ptrs_s cn31xx; | ||
734 | struct cvmx_pko_mem_queue_ptrs_s cn38xx; | ||
735 | struct cvmx_pko_mem_queue_ptrs_s cn38xxp2; | ||
736 | struct cvmx_pko_mem_queue_ptrs_s cn50xx; | ||
737 | struct cvmx_pko_mem_queue_ptrs_s cn52xx; | ||
738 | struct cvmx_pko_mem_queue_ptrs_s cn52xxp1; | ||
739 | struct cvmx_pko_mem_queue_ptrs_s cn56xx; | ||
740 | struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; | ||
741 | struct cvmx_pko_mem_queue_ptrs_s cn58xx; | ||
742 | struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; | ||
743 | }; | ||
744 | |||
745 | union cvmx_pko_mem_queue_qos { | ||
746 | uint64_t u64; | ||
747 | struct cvmx_pko_mem_queue_qos_s { | ||
748 | uint64_t reserved_61_63:3; | ||
749 | uint64_t qos_mask:8; | ||
750 | uint64_t reserved_13_52:40; | ||
751 | uint64_t pid:6; | ||
752 | uint64_t qid:7; | ||
753 | } s; | ||
754 | struct cvmx_pko_mem_queue_qos_s cn30xx; | ||
755 | struct cvmx_pko_mem_queue_qos_s cn31xx; | ||
756 | struct cvmx_pko_mem_queue_qos_s cn38xx; | ||
757 | struct cvmx_pko_mem_queue_qos_s cn38xxp2; | ||
758 | struct cvmx_pko_mem_queue_qos_s cn50xx; | ||
759 | struct cvmx_pko_mem_queue_qos_s cn52xx; | ||
760 | struct cvmx_pko_mem_queue_qos_s cn52xxp1; | ||
761 | struct cvmx_pko_mem_queue_qos_s cn56xx; | ||
762 | struct cvmx_pko_mem_queue_qos_s cn56xxp1; | ||
763 | struct cvmx_pko_mem_queue_qos_s cn58xx; | ||
764 | struct cvmx_pko_mem_queue_qos_s cn58xxp1; | ||
765 | }; | ||
766 | |||
767 | union cvmx_pko_reg_bist_result { | ||
768 | uint64_t u64; | ||
769 | struct cvmx_pko_reg_bist_result_s { | ||
770 | uint64_t reserved_0_63:64; | ||
771 | } s; | ||
772 | struct cvmx_pko_reg_bist_result_cn30xx { | ||
773 | uint64_t reserved_27_63:37; | ||
774 | uint64_t psb2:5; | ||
775 | uint64_t count:1; | ||
776 | uint64_t rif:1; | ||
777 | uint64_t wif:1; | ||
778 | uint64_t ncb:1; | ||
779 | uint64_t out:1; | ||
780 | uint64_t crc:1; | ||
781 | uint64_t chk:1; | ||
782 | uint64_t qsb:2; | ||
783 | uint64_t qcb:2; | ||
784 | uint64_t pdb:4; | ||
785 | uint64_t psb:7; | ||
786 | } cn30xx; | ||
787 | struct cvmx_pko_reg_bist_result_cn30xx cn31xx; | ||
788 | struct cvmx_pko_reg_bist_result_cn30xx cn38xx; | ||
789 | struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; | ||
790 | struct cvmx_pko_reg_bist_result_cn50xx { | ||
791 | uint64_t reserved_33_63:31; | ||
792 | uint64_t csr:1; | ||
793 | uint64_t iob:1; | ||
794 | uint64_t out_crc:1; | ||
795 | uint64_t out_ctl:3; | ||
796 | uint64_t out_sta:1; | ||
797 | uint64_t out_wif:1; | ||
798 | uint64_t prt_chk:3; | ||
799 | uint64_t prt_nxt:1; | ||
800 | uint64_t prt_psb:6; | ||
801 | uint64_t ncb_inb:2; | ||
802 | uint64_t prt_qcb:2; | ||
803 | uint64_t prt_qsb:3; | ||
804 | uint64_t dat_dat:4; | ||
805 | uint64_t dat_ptr:4; | ||
806 | } cn50xx; | ||
807 | struct cvmx_pko_reg_bist_result_cn52xx { | ||
808 | uint64_t reserved_35_63:29; | ||
809 | uint64_t csr:1; | ||
810 | uint64_t iob:1; | ||
811 | uint64_t out_dat:1; | ||
812 | uint64_t out_ctl:3; | ||
813 | uint64_t out_sta:1; | ||
814 | uint64_t out_wif:1; | ||
815 | uint64_t prt_chk:3; | ||
816 | uint64_t prt_nxt:1; | ||
817 | uint64_t prt_psb:8; | ||
818 | uint64_t ncb_inb:2; | ||
819 | uint64_t prt_qcb:2; | ||
820 | uint64_t prt_qsb:3; | ||
821 | uint64_t prt_ctl:2; | ||
822 | uint64_t dat_dat:2; | ||
823 | uint64_t dat_ptr:4; | ||
824 | } cn52xx; | ||
825 | struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; | ||
826 | struct cvmx_pko_reg_bist_result_cn52xx cn56xx; | ||
827 | struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; | ||
828 | struct cvmx_pko_reg_bist_result_cn50xx cn58xx; | ||
829 | struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; | ||
830 | }; | ||
831 | |||
832 | union cvmx_pko_reg_cmd_buf { | ||
833 | uint64_t u64; | ||
834 | struct cvmx_pko_reg_cmd_buf_s { | ||
835 | uint64_t reserved_23_63:41; | ||
836 | uint64_t pool:3; | ||
837 | uint64_t reserved_13_19:7; | ||
838 | uint64_t size:13; | ||
839 | } s; | ||
840 | struct cvmx_pko_reg_cmd_buf_s cn30xx; | ||
841 | struct cvmx_pko_reg_cmd_buf_s cn31xx; | ||
842 | struct cvmx_pko_reg_cmd_buf_s cn38xx; | ||
843 | struct cvmx_pko_reg_cmd_buf_s cn38xxp2; | ||
844 | struct cvmx_pko_reg_cmd_buf_s cn50xx; | ||
845 | struct cvmx_pko_reg_cmd_buf_s cn52xx; | ||
846 | struct cvmx_pko_reg_cmd_buf_s cn52xxp1; | ||
847 | struct cvmx_pko_reg_cmd_buf_s cn56xx; | ||
848 | struct cvmx_pko_reg_cmd_buf_s cn56xxp1; | ||
849 | struct cvmx_pko_reg_cmd_buf_s cn58xx; | ||
850 | struct cvmx_pko_reg_cmd_buf_s cn58xxp1; | ||
851 | }; | ||
852 | |||
853 | union cvmx_pko_reg_crc_ctlx { | ||
854 | uint64_t u64; | ||
855 | struct cvmx_pko_reg_crc_ctlx_s { | ||
856 | uint64_t reserved_2_63:62; | ||
857 | uint64_t invres:1; | ||
858 | uint64_t refin:1; | ||
859 | } s; | ||
860 | struct cvmx_pko_reg_crc_ctlx_s cn38xx; | ||
861 | struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; | ||
862 | struct cvmx_pko_reg_crc_ctlx_s cn58xx; | ||
863 | struct cvmx_pko_reg_crc_ctlx_s cn58xxp1; | ||
864 | }; | ||
865 | |||
866 | union cvmx_pko_reg_crc_enable { | ||
867 | uint64_t u64; | ||
868 | struct cvmx_pko_reg_crc_enable_s { | ||
869 | uint64_t reserved_32_63:32; | ||
870 | uint64_t enable:32; | ||
871 | } s; | ||
872 | struct cvmx_pko_reg_crc_enable_s cn38xx; | ||
873 | struct cvmx_pko_reg_crc_enable_s cn38xxp2; | ||
874 | struct cvmx_pko_reg_crc_enable_s cn58xx; | ||
875 | struct cvmx_pko_reg_crc_enable_s cn58xxp1; | ||
876 | }; | ||
877 | |||
878 | union cvmx_pko_reg_crc_ivx { | ||
879 | uint64_t u64; | ||
880 | struct cvmx_pko_reg_crc_ivx_s { | ||
881 | uint64_t reserved_32_63:32; | ||
882 | uint64_t iv:32; | ||
883 | } s; | ||
884 | struct cvmx_pko_reg_crc_ivx_s cn38xx; | ||
885 | struct cvmx_pko_reg_crc_ivx_s cn38xxp2; | ||
886 | struct cvmx_pko_reg_crc_ivx_s cn58xx; | ||
887 | struct cvmx_pko_reg_crc_ivx_s cn58xxp1; | ||
888 | }; | ||
889 | |||
890 | union cvmx_pko_reg_debug0 { | ||
891 | uint64_t u64; | ||
892 | struct cvmx_pko_reg_debug0_s { | ||
893 | uint64_t asserts:64; | ||
894 | } s; | ||
895 | struct cvmx_pko_reg_debug0_cn30xx { | ||
896 | uint64_t reserved_17_63:47; | ||
897 | uint64_t asserts:17; | ||
898 | } cn30xx; | ||
899 | struct cvmx_pko_reg_debug0_cn30xx cn31xx; | ||
900 | struct cvmx_pko_reg_debug0_cn30xx cn38xx; | ||
901 | struct cvmx_pko_reg_debug0_cn30xx cn38xxp2; | ||
902 | struct cvmx_pko_reg_debug0_s cn50xx; | ||
903 | struct cvmx_pko_reg_debug0_s cn52xx; | ||
904 | struct cvmx_pko_reg_debug0_s cn52xxp1; | ||
905 | struct cvmx_pko_reg_debug0_s cn56xx; | ||
906 | struct cvmx_pko_reg_debug0_s cn56xxp1; | ||
907 | struct cvmx_pko_reg_debug0_s cn58xx; | ||
908 | struct cvmx_pko_reg_debug0_s cn58xxp1; | ||
909 | }; | ||
910 | |||
911 | union cvmx_pko_reg_debug1 { | ||
912 | uint64_t u64; | ||
913 | struct cvmx_pko_reg_debug1_s { | ||
914 | uint64_t asserts:64; | ||
915 | } s; | ||
916 | struct cvmx_pko_reg_debug1_s cn50xx; | ||
917 | struct cvmx_pko_reg_debug1_s cn52xx; | ||
918 | struct cvmx_pko_reg_debug1_s cn52xxp1; | ||
919 | struct cvmx_pko_reg_debug1_s cn56xx; | ||
920 | struct cvmx_pko_reg_debug1_s cn56xxp1; | ||
921 | struct cvmx_pko_reg_debug1_s cn58xx; | ||
922 | struct cvmx_pko_reg_debug1_s cn58xxp1; | ||
923 | }; | ||
924 | |||
925 | union cvmx_pko_reg_debug2 { | ||
926 | uint64_t u64; | ||
927 | struct cvmx_pko_reg_debug2_s { | ||
928 | uint64_t asserts:64; | ||
929 | } s; | ||
930 | struct cvmx_pko_reg_debug2_s cn50xx; | ||
931 | struct cvmx_pko_reg_debug2_s cn52xx; | ||
932 | struct cvmx_pko_reg_debug2_s cn52xxp1; | ||
933 | struct cvmx_pko_reg_debug2_s cn56xx; | ||
934 | struct cvmx_pko_reg_debug2_s cn56xxp1; | ||
935 | struct cvmx_pko_reg_debug2_s cn58xx; | ||
936 | struct cvmx_pko_reg_debug2_s cn58xxp1; | ||
937 | }; | ||
938 | |||
939 | union cvmx_pko_reg_debug3 { | ||
940 | uint64_t u64; | ||
941 | struct cvmx_pko_reg_debug3_s { | ||
942 | uint64_t asserts:64; | ||
943 | } s; | ||
944 | struct cvmx_pko_reg_debug3_s cn50xx; | ||
945 | struct cvmx_pko_reg_debug3_s cn52xx; | ||
946 | struct cvmx_pko_reg_debug3_s cn52xxp1; | ||
947 | struct cvmx_pko_reg_debug3_s cn56xx; | ||
948 | struct cvmx_pko_reg_debug3_s cn56xxp1; | ||
949 | struct cvmx_pko_reg_debug3_s cn58xx; | ||
950 | struct cvmx_pko_reg_debug3_s cn58xxp1; | ||
951 | }; | ||
952 | |||
953 | union cvmx_pko_reg_engine_inflight { | ||
954 | uint64_t u64; | ||
955 | struct cvmx_pko_reg_engine_inflight_s { | ||
956 | uint64_t reserved_40_63:24; | ||
957 | uint64_t engine9:4; | ||
958 | uint64_t engine8:4; | ||
959 | uint64_t engine7:4; | ||
960 | uint64_t engine6:4; | ||
961 | uint64_t engine5:4; | ||
962 | uint64_t engine4:4; | ||
963 | uint64_t engine3:4; | ||
964 | uint64_t engine2:4; | ||
965 | uint64_t engine1:4; | ||
966 | uint64_t engine0:4; | ||
967 | } s; | ||
968 | struct cvmx_pko_reg_engine_inflight_s cn52xx; | ||
969 | struct cvmx_pko_reg_engine_inflight_s cn52xxp1; | ||
970 | struct cvmx_pko_reg_engine_inflight_s cn56xx; | ||
971 | struct cvmx_pko_reg_engine_inflight_s cn56xxp1; | ||
972 | }; | ||
973 | |||
974 | union cvmx_pko_reg_engine_thresh { | ||
975 | uint64_t u64; | ||
976 | struct cvmx_pko_reg_engine_thresh_s { | ||
977 | uint64_t reserved_10_63:54; | ||
978 | uint64_t mask:10; | ||
979 | } s; | ||
980 | struct cvmx_pko_reg_engine_thresh_s cn52xx; | ||
981 | struct cvmx_pko_reg_engine_thresh_s cn52xxp1; | ||
982 | struct cvmx_pko_reg_engine_thresh_s cn56xx; | ||
983 | struct cvmx_pko_reg_engine_thresh_s cn56xxp1; | ||
984 | }; | ||
985 | |||
986 | union cvmx_pko_reg_error { | ||
987 | uint64_t u64; | ||
988 | struct cvmx_pko_reg_error_s { | ||
989 | uint64_t reserved_3_63:61; | ||
990 | uint64_t currzero:1; | ||
991 | uint64_t doorbell:1; | ||
992 | uint64_t parity:1; | ||
993 | } s; | ||
994 | struct cvmx_pko_reg_error_cn30xx { | ||
995 | uint64_t reserved_2_63:62; | ||
996 | uint64_t doorbell:1; | ||
997 | uint64_t parity:1; | ||
998 | } cn30xx; | ||
999 | struct cvmx_pko_reg_error_cn30xx cn31xx; | ||
1000 | struct cvmx_pko_reg_error_cn30xx cn38xx; | ||
1001 | struct cvmx_pko_reg_error_cn30xx cn38xxp2; | ||
1002 | struct cvmx_pko_reg_error_s cn50xx; | ||
1003 | struct cvmx_pko_reg_error_s cn52xx; | ||
1004 | struct cvmx_pko_reg_error_s cn52xxp1; | ||
1005 | struct cvmx_pko_reg_error_s cn56xx; | ||
1006 | struct cvmx_pko_reg_error_s cn56xxp1; | ||
1007 | struct cvmx_pko_reg_error_s cn58xx; | ||
1008 | struct cvmx_pko_reg_error_s cn58xxp1; | ||
1009 | }; | ||
1010 | |||
1011 | union cvmx_pko_reg_flags { | ||
1012 | uint64_t u64; | ||
1013 | struct cvmx_pko_reg_flags_s { | ||
1014 | uint64_t reserved_4_63:60; | ||
1015 | uint64_t reset:1; | ||
1016 | uint64_t store_be:1; | ||
1017 | uint64_t ena_dwb:1; | ||
1018 | uint64_t ena_pko:1; | ||
1019 | } s; | ||
1020 | struct cvmx_pko_reg_flags_s cn30xx; | ||
1021 | struct cvmx_pko_reg_flags_s cn31xx; | ||
1022 | struct cvmx_pko_reg_flags_s cn38xx; | ||
1023 | struct cvmx_pko_reg_flags_s cn38xxp2; | ||
1024 | struct cvmx_pko_reg_flags_s cn50xx; | ||
1025 | struct cvmx_pko_reg_flags_s cn52xx; | ||
1026 | struct cvmx_pko_reg_flags_s cn52xxp1; | ||
1027 | struct cvmx_pko_reg_flags_s cn56xx; | ||
1028 | struct cvmx_pko_reg_flags_s cn56xxp1; | ||
1029 | struct cvmx_pko_reg_flags_s cn58xx; | ||
1030 | struct cvmx_pko_reg_flags_s cn58xxp1; | ||
1031 | }; | ||
1032 | |||
1033 | union cvmx_pko_reg_gmx_port_mode { | ||
1034 | uint64_t u64; | ||
1035 | struct cvmx_pko_reg_gmx_port_mode_s { | ||
1036 | uint64_t reserved_6_63:58; | ||
1037 | uint64_t mode1:3; | ||
1038 | uint64_t mode0:3; | ||
1039 | } s; | ||
1040 | struct cvmx_pko_reg_gmx_port_mode_s cn30xx; | ||
1041 | struct cvmx_pko_reg_gmx_port_mode_s cn31xx; | ||
1042 | struct cvmx_pko_reg_gmx_port_mode_s cn38xx; | ||
1043 | struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2; | ||
1044 | struct cvmx_pko_reg_gmx_port_mode_s cn50xx; | ||
1045 | struct cvmx_pko_reg_gmx_port_mode_s cn52xx; | ||
1046 | struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1; | ||
1047 | struct cvmx_pko_reg_gmx_port_mode_s cn56xx; | ||
1048 | struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; | ||
1049 | struct cvmx_pko_reg_gmx_port_mode_s cn58xx; | ||
1050 | struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; | ||
1051 | }; | ||
1052 | |||
1053 | union cvmx_pko_reg_int_mask { | ||
1054 | uint64_t u64; | ||
1055 | struct cvmx_pko_reg_int_mask_s { | ||
1056 | uint64_t reserved_3_63:61; | ||
1057 | uint64_t currzero:1; | ||
1058 | uint64_t doorbell:1; | ||
1059 | uint64_t parity:1; | ||
1060 | } s; | ||
1061 | struct cvmx_pko_reg_int_mask_cn30xx { | ||
1062 | uint64_t reserved_2_63:62; | ||
1063 | uint64_t doorbell:1; | ||
1064 | uint64_t parity:1; | ||
1065 | } cn30xx; | ||
1066 | struct cvmx_pko_reg_int_mask_cn30xx cn31xx; | ||
1067 | struct cvmx_pko_reg_int_mask_cn30xx cn38xx; | ||
1068 | struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; | ||
1069 | struct cvmx_pko_reg_int_mask_s cn50xx; | ||
1070 | struct cvmx_pko_reg_int_mask_s cn52xx; | ||
1071 | struct cvmx_pko_reg_int_mask_s cn52xxp1; | ||
1072 | struct cvmx_pko_reg_int_mask_s cn56xx; | ||
1073 | struct cvmx_pko_reg_int_mask_s cn56xxp1; | ||
1074 | struct cvmx_pko_reg_int_mask_s cn58xx; | ||
1075 | struct cvmx_pko_reg_int_mask_s cn58xxp1; | ||
1076 | }; | ||
1077 | |||
1078 | union cvmx_pko_reg_queue_mode { | ||
1079 | uint64_t u64; | ||
1080 | struct cvmx_pko_reg_queue_mode_s { | ||
1081 | uint64_t reserved_2_63:62; | ||
1082 | uint64_t mode:2; | ||
1083 | } s; | ||
1084 | struct cvmx_pko_reg_queue_mode_s cn30xx; | ||
1085 | struct cvmx_pko_reg_queue_mode_s cn31xx; | ||
1086 | struct cvmx_pko_reg_queue_mode_s cn38xx; | ||
1087 | struct cvmx_pko_reg_queue_mode_s cn38xxp2; | ||
1088 | struct cvmx_pko_reg_queue_mode_s cn50xx; | ||
1089 | struct cvmx_pko_reg_queue_mode_s cn52xx; | ||
1090 | struct cvmx_pko_reg_queue_mode_s cn52xxp1; | ||
1091 | struct cvmx_pko_reg_queue_mode_s cn56xx; | ||
1092 | struct cvmx_pko_reg_queue_mode_s cn56xxp1; | ||
1093 | struct cvmx_pko_reg_queue_mode_s cn58xx; | ||
1094 | struct cvmx_pko_reg_queue_mode_s cn58xxp1; | ||
1095 | }; | ||
1096 | |||
1097 | union cvmx_pko_reg_queue_ptrs1 { | ||
1098 | uint64_t u64; | ||
1099 | struct cvmx_pko_reg_queue_ptrs1_s { | ||
1100 | uint64_t reserved_2_63:62; | ||
1101 | uint64_t idx3:1; | ||
1102 | uint64_t qid7:1; | ||
1103 | } s; | ||
1104 | struct cvmx_pko_reg_queue_ptrs1_s cn50xx; | ||
1105 | struct cvmx_pko_reg_queue_ptrs1_s cn52xx; | ||
1106 | struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1; | ||
1107 | struct cvmx_pko_reg_queue_ptrs1_s cn56xx; | ||
1108 | struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; | ||
1109 | struct cvmx_pko_reg_queue_ptrs1_s cn58xx; | ||
1110 | struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; | ||
1111 | }; | ||
1112 | |||
1113 | union cvmx_pko_reg_read_idx { | ||
1114 | uint64_t u64; | ||
1115 | struct cvmx_pko_reg_read_idx_s { | ||
1116 | uint64_t reserved_16_63:48; | ||
1117 | uint64_t inc:8; | ||
1118 | uint64_t index:8; | ||
1119 | } s; | ||
1120 | struct cvmx_pko_reg_read_idx_s cn30xx; | ||
1121 | struct cvmx_pko_reg_read_idx_s cn31xx; | ||
1122 | struct cvmx_pko_reg_read_idx_s cn38xx; | ||
1123 | struct cvmx_pko_reg_read_idx_s cn38xxp2; | ||
1124 | struct cvmx_pko_reg_read_idx_s cn50xx; | ||
1125 | struct cvmx_pko_reg_read_idx_s cn52xx; | ||
1126 | struct cvmx_pko_reg_read_idx_s cn52xxp1; | ||
1127 | struct cvmx_pko_reg_read_idx_s cn56xx; | ||
1128 | struct cvmx_pko_reg_read_idx_s cn56xxp1; | ||
1129 | struct cvmx_pko_reg_read_idx_s cn58xx; | ||
1130 | struct cvmx_pko_reg_read_idx_s cn58xxp1; | ||
1131 | }; | ||
1132 | |||
1133 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-pko.c b/drivers/staging/octeon/cvmx-pko.c new file mode 100644 index 000000000000..00db91529b19 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pko.c | |||
@@ -0,0 +1,506 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * Support library for the hardware Packet Output unit. | ||
30 | */ | ||
31 | |||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "cvmx-config.h" | ||
35 | #include "cvmx-pko.h" | ||
36 | #include "cvmx-helper.h" | ||
37 | |||
38 | /** | ||
39 | * Internal state of packet output | ||
40 | */ | ||
41 | |||
42 | /** | ||
43 | * Call before any other calls to initialize the packet | ||
44 | * output system. This does chip global config, and should only be | ||
45 | * done by one core. | ||
46 | */ | ||
47 | |||
48 | void cvmx_pko_initialize_global(void) | ||
49 | { | ||
50 | int i; | ||
51 | uint64_t priority = 8; | ||
52 | union cvmx_pko_reg_cmd_buf config; | ||
53 | |||
54 | /* | ||
55 | * Set the size of the PKO command buffers to an odd number of | ||
56 | * 64bit words. This allows the normal two word send to stay | ||
57 | * aligned and never span a comamnd word buffer. | ||
58 | */ | ||
59 | config.u64 = 0; | ||
60 | config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL; | ||
61 | config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1; | ||
62 | |||
63 | cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64); | ||
64 | |||
65 | for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++) | ||
66 | cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, | ||
67 | &priority); | ||
68 | |||
69 | /* | ||
70 | * If we aren't using all of the queues optimize PKO's | ||
71 | * internal memory. | ||
72 | */ | ||
73 | if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) | ||
74 | || OCTEON_IS_MODEL(OCTEON_CN56XX) | ||
75 | || OCTEON_IS_MODEL(OCTEON_CN52XX)) { | ||
76 | int num_interfaces = cvmx_helper_get_number_of_interfaces(); | ||
77 | int last_port = | ||
78 | cvmx_helper_get_last_ipd_port(num_interfaces - 1); | ||
79 | int max_queues = | ||
80 | cvmx_pko_get_base_queue(last_port) + | ||
81 | cvmx_pko_get_num_queues(last_port); | ||
82 | if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { | ||
83 | if (max_queues <= 32) | ||
84 | cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); | ||
85 | else if (max_queues <= 64) | ||
86 | cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); | ||
87 | } else { | ||
88 | if (max_queues <= 64) | ||
89 | cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); | ||
90 | else if (max_queues <= 128) | ||
91 | cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); | ||
92 | } | ||
93 | } | ||
94 | } | ||
95 | |||
96 | /** | ||
97 | * This function does per-core initialization required by the PKO routines. | ||
98 | * This must be called on all cores that will do packet output, and must | ||
99 | * be called after the FPA has been initialized and filled with pages. | ||
100 | * | ||
101 | * Returns 0 on success | ||
102 | * !0 on failure | ||
103 | */ | ||
104 | int cvmx_pko_initialize_local(void) | ||
105 | { | ||
106 | /* Nothing to do */ | ||
107 | return 0; | ||
108 | } | ||
109 | |||
110 | /** | ||
111 | * Enables the packet output hardware. It must already be | ||
112 | * configured. | ||
113 | */ | ||
114 | void cvmx_pko_enable(void) | ||
115 | { | ||
116 | union cvmx_pko_reg_flags flags; | ||
117 | |||
118 | flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); | ||
119 | if (flags.s.ena_pko) | ||
120 | cvmx_dprintf | ||
121 | ("Warning: Enabling PKO when PKO already enabled.\n"); | ||
122 | |||
123 | flags.s.ena_dwb = 1; | ||
124 | flags.s.ena_pko = 1; | ||
125 | /* | ||
126 | * always enable big endian for 3-word command. Does nothing | ||
127 | * for 2-word. | ||
128 | */ | ||
129 | flags.s.store_be = 1; | ||
130 | cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64); | ||
131 | } | ||
132 | |||
133 | /** | ||
134 | * Disables the packet output. Does not affect any configuration. | ||
135 | */ | ||
136 | void cvmx_pko_disable(void) | ||
137 | { | ||
138 | union cvmx_pko_reg_flags pko_reg_flags; | ||
139 | pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); | ||
140 | pko_reg_flags.s.ena_pko = 0; | ||
141 | cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); | ||
142 | } | ||
143 | |||
144 | |||
145 | /** | ||
146 | * Reset the packet output. | ||
147 | */ | ||
148 | static void __cvmx_pko_reset(void) | ||
149 | { | ||
150 | union cvmx_pko_reg_flags pko_reg_flags; | ||
151 | pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); | ||
152 | pko_reg_flags.s.reset = 1; | ||
153 | cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); | ||
154 | } | ||
155 | |||
156 | /** | ||
157 | * Shutdown and free resources required by packet output. | ||
158 | */ | ||
159 | void cvmx_pko_shutdown(void) | ||
160 | { | ||
161 | union cvmx_pko_mem_queue_ptrs config; | ||
162 | int queue; | ||
163 | |||
164 | cvmx_pko_disable(); | ||
165 | |||
166 | for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++) { | ||
167 | config.u64 = 0; | ||
168 | config.s.tail = 1; | ||
169 | config.s.index = 0; | ||
170 | config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID; | ||
171 | config.s.queue = queue & 0x7f; | ||
172 | config.s.qos_mask = 0; | ||
173 | config.s.buf_ptr = 0; | ||
174 | if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { | ||
175 | union cvmx_pko_reg_queue_ptrs1 config1; | ||
176 | config1.u64 = 0; | ||
177 | config1.s.qid7 = queue >> 7; | ||
178 | cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); | ||
179 | } | ||
180 | cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); | ||
181 | cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue)); | ||
182 | } | ||
183 | __cvmx_pko_reset(); | ||
184 | } | ||
185 | |||
186 | /** | ||
187 | * Configure a output port and the associated queues for use. | ||
188 | * | ||
189 | * @port: Port to configure. | ||
190 | * @base_queue: First queue number to associate with this port. | ||
191 | * @num_queues: Number of queues to associate with this port | ||
192 | * @priority: Array of priority levels for each queue. Values are | ||
193 | * allowed to be 0-8. A value of 8 get 8 times the traffic | ||
194 | * of a value of 1. A value of 0 indicates that no rounds | ||
195 | * will be participated in. These priorities can be changed | ||
196 | * on the fly while the pko is enabled. A priority of 9 | ||
197 | * indicates that static priority should be used. If static | ||
198 | * priority is used all queues with static priority must be | ||
199 | * contiguous starting at the base_queue, and lower numbered | ||
200 | * queues have higher priority than higher numbered queues. | ||
201 | * There must be num_queues elements in the array. | ||
202 | */ | ||
203 | cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, | ||
204 | uint64_t num_queues, | ||
205 | const uint64_t priority[]) | ||
206 | { | ||
207 | cvmx_pko_status_t result_code; | ||
208 | uint64_t queue; | ||
209 | union cvmx_pko_mem_queue_ptrs config; | ||
210 | union cvmx_pko_reg_queue_ptrs1 config1; | ||
211 | int static_priority_base = -1; | ||
212 | int static_priority_end = -1; | ||
213 | |||
214 | if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) | ||
215 | && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) { | ||
216 | cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n", | ||
217 | (unsigned long long)port); | ||
218 | return CVMX_PKO_INVALID_PORT; | ||
219 | } | ||
220 | |||
221 | if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES) { | ||
222 | cvmx_dprintf | ||
223 | ("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n", | ||
224 | (unsigned long long)(base_queue + num_queues)); | ||
225 | return CVMX_PKO_INVALID_QUEUE; | ||
226 | } | ||
227 | |||
228 | if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) { | ||
229 | /* | ||
230 | * Validate the static queue priority setup and set | ||
231 | * static_priority_base and static_priority_end | ||
232 | * accordingly. | ||
233 | */ | ||
234 | for (queue = 0; queue < num_queues; queue++) { | ||
235 | /* Find first queue of static priority */ | ||
236 | if (static_priority_base == -1 | ||
237 | && priority[queue] == | ||
238 | CVMX_PKO_QUEUE_STATIC_PRIORITY) | ||
239 | static_priority_base = queue; | ||
240 | /* Find last queue of static priority */ | ||
241 | if (static_priority_base != -1 | ||
242 | && static_priority_end == -1 | ||
243 | && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY | ||
244 | && queue) | ||
245 | static_priority_end = queue - 1; | ||
246 | else if (static_priority_base != -1 | ||
247 | && static_priority_end == -1 | ||
248 | && queue == num_queues - 1) | ||
249 | /* all queues are static priority */ | ||
250 | static_priority_end = queue; | ||
251 | /* | ||
252 | * Check to make sure all static priority | ||
253 | * queues are contiguous. Also catches some | ||
254 | * cases of static priorites not starting at | ||
255 | * queue 0. | ||
256 | */ | ||
257 | if (static_priority_end != -1 | ||
258 | && (int)queue > static_priority_end | ||
259 | && priority[queue] == | ||
260 | CVMX_PKO_QUEUE_STATIC_PRIORITY) { | ||
261 | cvmx_dprintf("ERROR: cvmx_pko_config_port: " | ||
262 | "Static priority queues aren't " | ||
263 | "contiguous or don't start at " | ||
264 | "base queue. q: %d, eq: %d\n", | ||
265 | (int)queue, static_priority_end); | ||
266 | return CVMX_PKO_INVALID_PRIORITY; | ||
267 | } | ||
268 | } | ||
269 | if (static_priority_base > 0) { | ||
270 | cvmx_dprintf("ERROR: cvmx_pko_config_port: Static " | ||
271 | "priority queues don't start at base " | ||
272 | "queue. sq: %d\n", | ||
273 | static_priority_base); | ||
274 | return CVMX_PKO_INVALID_PRIORITY; | ||
275 | } | ||
276 | #if 0 | ||
277 | cvmx_dprintf("Port %d: Static priority queue base: %d, " | ||
278 | "end: %d\n", port, | ||
279 | static_priority_base, static_priority_end); | ||
280 | #endif | ||
281 | } | ||
282 | /* | ||
283 | * At this point, static_priority_base and static_priority_end | ||
284 | * are either both -1, or are valid start/end queue | ||
285 | * numbers. | ||
286 | */ | ||
287 | |||
288 | result_code = CVMX_PKO_SUCCESS; | ||
289 | |||
290 | #ifdef PKO_DEBUG | ||
291 | cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues, | ||
292 | CVMX_PKO_QUEUES_PER_PORT_INTERFACE0, | ||
293 | CVMX_PKO_QUEUES_PER_PORT_INTERFACE1); | ||
294 | #endif | ||
295 | |||
296 | for (queue = 0; queue < num_queues; queue++) { | ||
297 | uint64_t *buf_ptr = NULL; | ||
298 | |||
299 | config1.u64 = 0; | ||
300 | config1.s.idx3 = queue >> 3; | ||
301 | config1.s.qid7 = (base_queue + queue) >> 7; | ||
302 | |||
303 | config.u64 = 0; | ||
304 | config.s.tail = queue == (num_queues - 1); | ||
305 | config.s.index = queue; | ||
306 | config.s.port = port; | ||
307 | config.s.queue = base_queue + queue; | ||
308 | |||
309 | if (!cvmx_octeon_is_pass1()) { | ||
310 | config.s.static_p = static_priority_base >= 0; | ||
311 | config.s.static_q = (int)queue <= static_priority_end; | ||
312 | config.s.s_tail = (int)queue == static_priority_end; | ||
313 | } | ||
314 | /* | ||
315 | * Convert the priority into an enable bit field. Try | ||
316 | * to space the bits out evenly so the packet don't | ||
317 | * get grouped up | ||
318 | */ | ||
319 | switch ((int)priority[queue]) { | ||
320 | case 0: | ||
321 | config.s.qos_mask = 0x00; | ||
322 | break; | ||
323 | case 1: | ||
324 | config.s.qos_mask = 0x01; | ||
325 | break; | ||
326 | case 2: | ||
327 | config.s.qos_mask = 0x11; | ||
328 | break; | ||
329 | case 3: | ||
330 | config.s.qos_mask = 0x49; | ||
331 | break; | ||
332 | case 4: | ||
333 | config.s.qos_mask = 0x55; | ||
334 | break; | ||
335 | case 5: | ||
336 | config.s.qos_mask = 0x57; | ||
337 | break; | ||
338 | case 6: | ||
339 | config.s.qos_mask = 0x77; | ||
340 | break; | ||
341 | case 7: | ||
342 | config.s.qos_mask = 0x7f; | ||
343 | break; | ||
344 | case 8: | ||
345 | config.s.qos_mask = 0xff; | ||
346 | break; | ||
347 | case CVMX_PKO_QUEUE_STATIC_PRIORITY: | ||
348 | /* Pass 1 will fall through to the error case */ | ||
349 | if (!cvmx_octeon_is_pass1()) { | ||
350 | config.s.qos_mask = 0xff; | ||
351 | break; | ||
352 | } | ||
353 | default: | ||
354 | cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid " | ||
355 | "priority %llu\n", | ||
356 | (unsigned long long)priority[queue]); | ||
357 | config.s.qos_mask = 0xff; | ||
358 | result_code = CVMX_PKO_INVALID_PRIORITY; | ||
359 | break; | ||
360 | } | ||
361 | |||
362 | if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) { | ||
363 | cvmx_cmd_queue_result_t cmd_res = | ||
364 | cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO | ||
365 | (base_queue + queue), | ||
366 | CVMX_PKO_MAX_QUEUE_DEPTH, | ||
367 | CVMX_FPA_OUTPUT_BUFFER_POOL, | ||
368 | CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE | ||
369 | - | ||
370 | CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST | ||
371 | * 8); | ||
372 | if (cmd_res != CVMX_CMD_QUEUE_SUCCESS) { | ||
373 | switch (cmd_res) { | ||
374 | case CVMX_CMD_QUEUE_NO_MEMORY: | ||
375 | cvmx_dprintf("ERROR: " | ||
376 | "cvmx_pko_config_port: " | ||
377 | "Unable to allocate " | ||
378 | "output buffer.\n"); | ||
379 | return CVMX_PKO_NO_MEMORY; | ||
380 | case CVMX_CMD_QUEUE_ALREADY_SETUP: | ||
381 | cvmx_dprintf | ||
382 | ("ERROR: cvmx_pko_config_port: Port already setup.\n"); | ||
383 | return CVMX_PKO_PORT_ALREADY_SETUP; | ||
384 | case CVMX_CMD_QUEUE_INVALID_PARAM: | ||
385 | default: | ||
386 | cvmx_dprintf | ||
387 | ("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n"); | ||
388 | return CVMX_PKO_CMD_QUEUE_INIT_ERROR; | ||
389 | } | ||
390 | } | ||
391 | |||
392 | buf_ptr = | ||
393 | (uint64_t *) | ||
394 | cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO | ||
395 | (base_queue + queue)); | ||
396 | config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr); | ||
397 | } else | ||
398 | config.s.buf_ptr = 0; | ||
399 | |||
400 | CVMX_SYNCWS; | ||
401 | |||
402 | if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) | ||
403 | cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); | ||
404 | cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); | ||
405 | } | ||
406 | |||
407 | return result_code; | ||
408 | } | ||
409 | |||
410 | #ifdef PKO_DEBUG | ||
411 | /** | ||
412 | * Show map of ports -> queues for different cores. | ||
413 | */ | ||
414 | void cvmx_pko_show_queue_map() | ||
415 | { | ||
416 | int core, port; | ||
417 | int pko_output_ports = 36; | ||
418 | |||
419 | cvmx_dprintf("port"); | ||
420 | for (port = 0; port < pko_output_ports; port++) | ||
421 | cvmx_dprintf("%3d ", port); | ||
422 | cvmx_dprintf("\n"); | ||
423 | |||
424 | for (core = 0; core < CVMX_MAX_CORES; core++) { | ||
425 | cvmx_dprintf("\n%2d: ", core); | ||
426 | for (port = 0; port < pko_output_ports; port++) { | ||
427 | cvmx_dprintf("%3d ", | ||
428 | cvmx_pko_get_base_queue_per_core(port, | ||
429 | core)); | ||
430 | } | ||
431 | } | ||
432 | cvmx_dprintf("\n"); | ||
433 | } | ||
434 | #endif | ||
435 | |||
436 | /** | ||
437 | * Rate limit a PKO port to a max packets/sec. This function is only | ||
438 | * supported on CN51XX and higher, excluding CN58XX. | ||
439 | * | ||
440 | * @port: Port to rate limit | ||
441 | * @packets_s: Maximum packet/sec | ||
442 | * @burst: Maximum number of packets to burst in a row before rate | ||
443 | * limiting cuts in. | ||
444 | * | ||
445 | * Returns Zero on success, negative on failure | ||
446 | */ | ||
447 | int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst) | ||
448 | { | ||
449 | union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; | ||
450 | union cvmx_pko_mem_port_rate1 pko_mem_port_rate1; | ||
451 | |||
452 | pko_mem_port_rate0.u64 = 0; | ||
453 | pko_mem_port_rate0.s.pid = port; | ||
454 | pko_mem_port_rate0.s.rate_pkt = | ||
455 | cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16; | ||
456 | /* No cost per word since we are limited by packets/sec, not bits/sec */ | ||
457 | pko_mem_port_rate0.s.rate_word = 0; | ||
458 | |||
459 | pko_mem_port_rate1.u64 = 0; | ||
460 | pko_mem_port_rate1.s.pid = port; | ||
461 | pko_mem_port_rate1.s.rate_lim = | ||
462 | ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8; | ||
463 | |||
464 | cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); | ||
465 | cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); | ||
466 | return 0; | ||
467 | } | ||
468 | |||
469 | /** | ||
470 | * Rate limit a PKO port to a max bits/sec. This function is only | ||
471 | * supported on CN51XX and higher, excluding CN58XX. | ||
472 | * | ||
473 | * @port: Port to rate limit | ||
474 | * @bits_s: PKO rate limit in bits/sec | ||
475 | * @burst: Maximum number of bits to burst before rate | ||
476 | * limiting cuts in. | ||
477 | * | ||
478 | * Returns Zero on success, negative on failure | ||
479 | */ | ||
480 | int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst) | ||
481 | { | ||
482 | union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; | ||
483 | union cvmx_pko_mem_port_rate1 pko_mem_port_rate1; | ||
484 | uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz; | ||
485 | uint64_t tokens_per_bit = clock_rate * 16 / bits_s; | ||
486 | |||
487 | pko_mem_port_rate0.u64 = 0; | ||
488 | pko_mem_port_rate0.s.pid = port; | ||
489 | /* | ||
490 | * Each packet has a 12 bytes of interframe gap, an 8 byte | ||
491 | * preamble, and a 4 byte CRC. These are not included in the | ||
492 | * per word count. Multiply by 8 to covert to bits and divide | ||
493 | * by 256 for limit granularity. | ||
494 | */ | ||
495 | pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256; | ||
496 | /* Each 8 byte word has 64bits */ | ||
497 | pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit; | ||
498 | |||
499 | pko_mem_port_rate1.u64 = 0; | ||
500 | pko_mem_port_rate1.s.pid = port; | ||
501 | pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256; | ||
502 | |||
503 | cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); | ||
504 | cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); | ||
505 | return 0; | ||
506 | } | ||
diff --git a/drivers/staging/octeon/cvmx-pko.h b/drivers/staging/octeon/cvmx-pko.h new file mode 100644 index 000000000000..f068c1982497 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pko.h | |||
@@ -0,0 +1,610 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * | ||
30 | * Interface to the hardware Packet Output unit. | ||
31 | * | ||
32 | * Starting with SDK 1.7.0, the PKO output functions now support | ||
33 | * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to | ||
34 | * function similarly to previous SDKs by using POW atomic tags | ||
35 | * to preserve ordering and exclusivity. As a new option, you | ||
36 | * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc | ||
37 | * memory based locking instead. This locking has the advantage | ||
38 | * of not affecting the tag state but doesn't preserve packet | ||
39 | * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most | ||
40 | * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used | ||
41 | * with hand tuned fast path code. | ||
42 | * | ||
43 | * Some of other SDK differences visible to the command command | ||
44 | * queuing: | ||
45 | * - PKO indexes are no longer stored in the FAU. A large | ||
46 | * percentage of the FAU register block used to be tied up | ||
47 | * maintaining PKO queue pointers. These are now stored in a | ||
48 | * global named block. | ||
49 | * - The PKO <b>use_locking</b> parameter can now have a global | ||
50 | * effect. Since all application use the same named block, | ||
51 | * queue locking correctly applies across all operating | ||
52 | * systems when using CVMX_PKO_LOCK_CMD_QUEUE. | ||
53 | * - PKO 3 word commands are now supported. Use | ||
54 | * cvmx_pko_send_packet_finish3(). | ||
55 | * | ||
56 | */ | ||
57 | |||
58 | #ifndef __CVMX_PKO_H__ | ||
59 | #define __CVMX_PKO_H__ | ||
60 | |||
61 | #include "cvmx-fpa.h" | ||
62 | #include "cvmx-pow.h" | ||
63 | #include "cvmx-cmd-queue.h" | ||
64 | #include "cvmx-pko-defs.h" | ||
65 | |||
66 | /* Adjust the command buffer size by 1 word so that in the case of using only | ||
67 | * two word PKO commands no command words stradle buffers. The useful values | ||
68 | * for this are 0 and 1. */ | ||
69 | #define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1) | ||
70 | |||
71 | #define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256 | ||
72 | #define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \ | ||
73 | OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \ | ||
74 | OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \ | ||
75 | (OCTEON_IS_MODEL(OCTEON_CN58XX) || \ | ||
76 | OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128) | ||
77 | #define CVMX_PKO_NUM_OUTPUT_PORTS 40 | ||
78 | /* use this for queues that are not used */ | ||
79 | #define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 | ||
80 | #define CVMX_PKO_QUEUE_STATIC_PRIORITY 9 | ||
81 | #define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF | ||
82 | #define CVMX_PKO_MAX_QUEUE_DEPTH 0 | ||
83 | |||
84 | typedef enum { | ||
85 | CVMX_PKO_SUCCESS, | ||
86 | CVMX_PKO_INVALID_PORT, | ||
87 | CVMX_PKO_INVALID_QUEUE, | ||
88 | CVMX_PKO_INVALID_PRIORITY, | ||
89 | CVMX_PKO_NO_MEMORY, | ||
90 | CVMX_PKO_PORT_ALREADY_SETUP, | ||
91 | CVMX_PKO_CMD_QUEUE_INIT_ERROR | ||
92 | } cvmx_pko_status_t; | ||
93 | |||
94 | /** | ||
95 | * This enumeration represents the differnet locking modes supported by PKO. | ||
96 | */ | ||
97 | typedef enum { | ||
98 | /* | ||
99 | * PKO doesn't do any locking. It is the responsibility of the | ||
100 | * application to make sure that no other core is accessing | ||
101 | * the same queue at the smae time | ||
102 | */ | ||
103 | CVMX_PKO_LOCK_NONE = 0, | ||
104 | /* | ||
105 | * PKO performs an atomic tagswitch to insure exclusive access | ||
106 | * to the output queue. This will maintain packet ordering on | ||
107 | * output. | ||
108 | */ | ||
109 | CVMX_PKO_LOCK_ATOMIC_TAG = 1, | ||
110 | /* | ||
111 | * PKO uses the common command queue locks to insure exclusive | ||
112 | * access to the output queue. This is a memory based | ||
113 | * ll/sc. This is the most portable locking mechanism. | ||
114 | */ | ||
115 | CVMX_PKO_LOCK_CMD_QUEUE = 2, | ||
116 | } cvmx_pko_lock_t; | ||
117 | |||
118 | typedef struct { | ||
119 | uint32_t packets; | ||
120 | uint64_t octets; | ||
121 | uint64_t doorbell; | ||
122 | } cvmx_pko_port_status_t; | ||
123 | |||
124 | /** | ||
125 | * This structure defines the address to use on a packet enqueue | ||
126 | */ | ||
127 | typedef union { | ||
128 | uint64_t u64; | ||
129 | struct { | ||
130 | /* Must CVMX_IO_SEG */ | ||
131 | uint64_t mem_space:2; | ||
132 | /* Must be zero */ | ||
133 | uint64_t reserved:13; | ||
134 | /* Must be one */ | ||
135 | uint64_t is_io:1; | ||
136 | /* The ID of the device on the non-coherent bus */ | ||
137 | uint64_t did:8; | ||
138 | /* Must be zero */ | ||
139 | uint64_t reserved2:4; | ||
140 | /* Must be zero */ | ||
141 | uint64_t reserved3:18; | ||
142 | /* | ||
143 | * The hardware likes to have the output port in | ||
144 | * addition to the output queue, | ||
145 | */ | ||
146 | uint64_t port:6; | ||
147 | /* | ||
148 | * The output queue to send the packet to (0-127 are | ||
149 | * legal) | ||
150 | */ | ||
151 | uint64_t queue:9; | ||
152 | /* Must be zero */ | ||
153 | uint64_t reserved4:3; | ||
154 | } s; | ||
155 | } cvmx_pko_doorbell_address_t; | ||
156 | |||
157 | /** | ||
158 | * Structure of the first packet output command word. | ||
159 | */ | ||
160 | typedef union { | ||
161 | uint64_t u64; | ||
162 | struct { | ||
163 | /* | ||
164 | * The size of the reg1 operation - could be 8, 16, | ||
165 | * 32, or 64 bits. | ||
166 | */ | ||
167 | uint64_t size1:2; | ||
168 | /* | ||
169 | * The size of the reg0 operation - could be 8, 16, | ||
170 | * 32, or 64 bits. | ||
171 | */ | ||
172 | uint64_t size0:2; | ||
173 | /* | ||
174 | * If set, subtract 1, if clear, subtract packet | ||
175 | * size. | ||
176 | */ | ||
177 | uint64_t subone1:1; | ||
178 | /* | ||
179 | * The register, subtract will be done if reg1 is | ||
180 | * non-zero. | ||
181 | */ | ||
182 | uint64_t reg1:11; | ||
183 | /* If set, subtract 1, if clear, subtract packet size */ | ||
184 | uint64_t subone0:1; | ||
185 | /* The register, subtract will be done if reg0 is non-zero */ | ||
186 | uint64_t reg0:11; | ||
187 | /* | ||
188 | * When set, interpret segment pointer and segment | ||
189 | * bytes in little endian order. | ||
190 | */ | ||
191 | uint64_t le:1; | ||
192 | /* | ||
193 | * When set, packet data not allocated in L2 cache by | ||
194 | * PKO. | ||
195 | */ | ||
196 | uint64_t n2:1; | ||
197 | /* | ||
198 | * If set and rsp is set, word3 contains a pointer to | ||
199 | * a work queue entry. | ||
200 | */ | ||
201 | uint64_t wqp:1; | ||
202 | /* If set, the hardware will send a response when done */ | ||
203 | uint64_t rsp:1; | ||
204 | /* | ||
205 | * If set, the supplied pkt_ptr is really a pointer to | ||
206 | * a list of pkt_ptr's. | ||
207 | */ | ||
208 | uint64_t gather:1; | ||
209 | /* | ||
210 | * If ipoffp1 is non zero, (ipoffp1-1) is the number | ||
211 | * of bytes to IP header, and the hardware will | ||
212 | * calculate and insert the UDP/TCP checksum. | ||
213 | */ | ||
214 | uint64_t ipoffp1:7; | ||
215 | /* | ||
216 | * If set, ignore the I bit (force to zero) from all | ||
217 | * pointer structures. | ||
218 | */ | ||
219 | uint64_t ignore_i:1; | ||
220 | /* | ||
221 | * If clear, the hardware will attempt to free the | ||
222 | * buffers containing the packet. | ||
223 | */ | ||
224 | uint64_t dontfree:1; | ||
225 | /* | ||
226 | * The total number of segs in the packet, if gather | ||
227 | * set, also gather list length. | ||
228 | */ | ||
229 | uint64_t segs:6; | ||
230 | /* Including L2, but no trailing CRC */ | ||
231 | uint64_t total_bytes:16; | ||
232 | } s; | ||
233 | } cvmx_pko_command_word0_t; | ||
234 | |||
235 | /* CSR typedefs have been moved to cvmx-csr-*.h */ | ||
236 | |||
237 | /** | ||
238 | * Definition of internal state for Packet output processing | ||
239 | */ | ||
240 | typedef struct { | ||
241 | /* ptr to start of buffer, offset kept in FAU reg */ | ||
242 | uint64_t *start_ptr; | ||
243 | } cvmx_pko_state_elem_t; | ||
244 | |||
245 | /** | ||
246 | * Call before any other calls to initialize the packet | ||
247 | * output system. | ||
248 | */ | ||
249 | extern void cvmx_pko_initialize_global(void); | ||
250 | extern int cvmx_pko_initialize_local(void); | ||
251 | |||
252 | /** | ||
253 | * Enables the packet output hardware. It must already be | ||
254 | * configured. | ||
255 | */ | ||
256 | extern void cvmx_pko_enable(void); | ||
257 | |||
258 | /** | ||
259 | * Disables the packet output. Does not affect any configuration. | ||
260 | */ | ||
261 | extern void cvmx_pko_disable(void); | ||
262 | |||
263 | /** | ||
264 | * Shutdown and free resources required by packet output. | ||
265 | */ | ||
266 | |||
267 | extern void cvmx_pko_shutdown(void); | ||
268 | |||
269 | /** | ||
270 | * Configure a output port and the associated queues for use. | ||
271 | * | ||
272 | * @port: Port to configure. | ||
273 | * @base_queue: First queue number to associate with this port. | ||
274 | * @num_queues: Number of queues t oassociate with this port | ||
275 | * @priority: Array of priority levels for each queue. Values are | ||
276 | * allowed to be 1-8. A value of 8 get 8 times the traffic | ||
277 | * of a value of 1. There must be num_queues elements in the | ||
278 | * array. | ||
279 | */ | ||
280 | extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, | ||
281 | uint64_t base_queue, | ||
282 | uint64_t num_queues, | ||
283 | const uint64_t priority[]); | ||
284 | |||
285 | /** | ||
286 | * Ring the packet output doorbell. This tells the packet | ||
287 | * output hardware that "len" command words have been added | ||
288 | * to its pending list. This command includes the required | ||
289 | * CVMX_SYNCWS before the doorbell ring. | ||
290 | * | ||
291 | * @port: Port the packet is for | ||
292 | * @queue: Queue the packet is for | ||
293 | * @len: Length of the command in 64 bit words | ||
294 | */ | ||
295 | static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, | ||
296 | uint64_t len) | ||
297 | { | ||
298 | cvmx_pko_doorbell_address_t ptr; | ||
299 | |||
300 | ptr.u64 = 0; | ||
301 | ptr.s.mem_space = CVMX_IO_SEG; | ||
302 | ptr.s.did = CVMX_OCT_DID_PKT_SEND; | ||
303 | ptr.s.is_io = 1; | ||
304 | ptr.s.port = port; | ||
305 | ptr.s.queue = queue; | ||
306 | /* | ||
307 | * Need to make sure output queue data is in DRAM before | ||
308 | * doorbell write. | ||
309 | */ | ||
310 | CVMX_SYNCWS; | ||
311 | cvmx_write_io(ptr.u64, len); | ||
312 | } | ||
313 | |||
314 | /** | ||
315 | * Prepare to send a packet. This may initiate a tag switch to | ||
316 | * get exclusive access to the output queue structure, and | ||
317 | * performs other prep work for the packet send operation. | ||
318 | * | ||
319 | * cvmx_pko_send_packet_finish() MUST be called after this function is called, | ||
320 | * and must be called with the same port/queue/use_locking arguments. | ||
321 | * | ||
322 | * The use_locking parameter allows the caller to use three | ||
323 | * possible locking modes. | ||
324 | * - CVMX_PKO_LOCK_NONE | ||
325 | * - PKO doesn't do any locking. It is the responsibility | ||
326 | * of the application to make sure that no other core | ||
327 | * is accessing the same queue at the smae time. | ||
328 | * - CVMX_PKO_LOCK_ATOMIC_TAG | ||
329 | * - PKO performs an atomic tagswitch to insure exclusive | ||
330 | * access to the output queue. This will maintain | ||
331 | * packet ordering on output. | ||
332 | * - CVMX_PKO_LOCK_CMD_QUEUE | ||
333 | * - PKO uses the common command queue locks to insure | ||
334 | * exclusive access to the output queue. This is a | ||
335 | * memory based ll/sc. This is the most portable | ||
336 | * locking mechanism. | ||
337 | * | ||
338 | * NOTE: If atomic locking is used, the POW entry CANNOT be | ||
339 | * descheduled, as it does not contain a valid WQE pointer. | ||
340 | * | ||
341 | * @port: Port to send it on | ||
342 | * @queue: Queue to use | ||
343 | * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or | ||
344 | * CVMX_PKO_LOCK_CMD_QUEUE | ||
345 | */ | ||
346 | |||
347 | static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, | ||
348 | cvmx_pko_lock_t use_locking) | ||
349 | { | ||
350 | if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) { | ||
351 | /* | ||
352 | * Must do a full switch here to handle all cases. We | ||
353 | * use a fake WQE pointer, as the POW does not access | ||
354 | * this memory. The WQE pointer and group are only | ||
355 | * used if this work is descheduled, which is not | ||
356 | * supported by the | ||
357 | * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish | ||
358 | * combination. Note that this is a special case in | ||
359 | * which these fake values can be used - this is not a | ||
360 | * general technique. | ||
361 | */ | ||
362 | uint32_t tag = | ||
363 | CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT | | ||
364 | CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT | | ||
365 | (CVMX_TAG_SUBGROUP_MASK & queue); | ||
366 | cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag, | ||
367 | CVMX_POW_TAG_TYPE_ATOMIC, 0); | ||
368 | } | ||
369 | } | ||
370 | |||
371 | /** | ||
372 | * Complete packet output. cvmx_pko_send_packet_prepare() must be | ||
373 | * called exactly once before this, and the same parameters must be | ||
374 | * passed to both cvmx_pko_send_packet_prepare() and | ||
375 | * cvmx_pko_send_packet_finish(). | ||
376 | * | ||
377 | * @port: Port to send it on | ||
378 | * @queue: Queue to use | ||
379 | * @pko_command: | ||
380 | * PKO HW command word | ||
381 | * @packet: Packet to send | ||
382 | * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or | ||
383 | * CVMX_PKO_LOCK_CMD_QUEUE | ||
384 | * | ||
385 | * Returns returns CVMX_PKO_SUCCESS on success, or error code on | ||
386 | * failure of output | ||
387 | */ | ||
388 | static inline cvmx_pko_status_t cvmx_pko_send_packet_finish( | ||
389 | uint64_t port, | ||
390 | uint64_t queue, | ||
391 | cvmx_pko_command_word0_t pko_command, | ||
392 | union cvmx_buf_ptr packet, | ||
393 | cvmx_pko_lock_t use_locking) | ||
394 | { | ||
395 | cvmx_cmd_queue_result_t result; | ||
396 | if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) | ||
397 | cvmx_pow_tag_sw_wait(); | ||
398 | result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue), | ||
399 | (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), | ||
400 | pko_command.u64, packet.u64); | ||
401 | if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { | ||
402 | cvmx_pko_doorbell(port, queue, 2); | ||
403 | return CVMX_PKO_SUCCESS; | ||
404 | } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) | ||
405 | || (result == CVMX_CMD_QUEUE_FULL)) { | ||
406 | return CVMX_PKO_NO_MEMORY; | ||
407 | } else { | ||
408 | return CVMX_PKO_INVALID_QUEUE; | ||
409 | } | ||
410 | } | ||
411 | |||
412 | /** | ||
413 | * Complete packet output. cvmx_pko_send_packet_prepare() must be | ||
414 | * called exactly once before this, and the same parameters must be | ||
415 | * passed to both cvmx_pko_send_packet_prepare() and | ||
416 | * cvmx_pko_send_packet_finish(). | ||
417 | * | ||
418 | * @port: Port to send it on | ||
419 | * @queue: Queue to use | ||
420 | * @pko_command: | ||
421 | * PKO HW command word | ||
422 | * @packet: Packet to send | ||
423 | * @addr: Plysical address of a work queue entry or physical address | ||
424 | * to zero on complete. | ||
425 | * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or | ||
426 | * CVMX_PKO_LOCK_CMD_QUEUE | ||
427 | * | ||
428 | * Returns returns CVMX_PKO_SUCCESS on success, or error code on | ||
429 | * failure of output | ||
430 | */ | ||
431 | static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3( | ||
432 | uint64_t port, | ||
433 | uint64_t queue, | ||
434 | cvmx_pko_command_word0_t pko_command, | ||
435 | union cvmx_buf_ptr packet, | ||
436 | uint64_t addr, | ||
437 | cvmx_pko_lock_t use_locking) | ||
438 | { | ||
439 | cvmx_cmd_queue_result_t result; | ||
440 | if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) | ||
441 | cvmx_pow_tag_sw_wait(); | ||
442 | result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue), | ||
443 | (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), | ||
444 | pko_command.u64, packet.u64, addr); | ||
445 | if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { | ||
446 | cvmx_pko_doorbell(port, queue, 3); | ||
447 | return CVMX_PKO_SUCCESS; | ||
448 | } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) | ||
449 | || (result == CVMX_CMD_QUEUE_FULL)) { | ||
450 | return CVMX_PKO_NO_MEMORY; | ||
451 | } else { | ||
452 | return CVMX_PKO_INVALID_QUEUE; | ||
453 | } | ||
454 | } | ||
455 | |||
456 | /** | ||
457 | * Return the pko output queue associated with a port and a specific core. | ||
458 | * In normal mode (PKO lockless operation is disabled), the value returned | ||
459 | * is the base queue. | ||
460 | * | ||
461 | * @port: Port number | ||
462 | * @core: Core to get queue for | ||
463 | * | ||
464 | * Returns Core-specific output queue | ||
465 | */ | ||
466 | static inline int cvmx_pko_get_base_queue_per_core(int port, int core) | ||
467 | { | ||
468 | #ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 | ||
469 | #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16 | ||
470 | #endif | ||
471 | #ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 | ||
472 | #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16 | ||
473 | #endif | ||
474 | |||
475 | if (port < CVMX_PKO_MAX_PORTS_INTERFACE0) | ||
476 | return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core; | ||
477 | else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1) | ||
478 | return CVMX_PKO_MAX_PORTS_INTERFACE0 * | ||
479 | CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port - | ||
480 | 16) * | ||
481 | CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core; | ||
482 | else if ((port >= 32) && (port < 36)) | ||
483 | return CVMX_PKO_MAX_PORTS_INTERFACE0 * | ||
484 | CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + | ||
485 | CVMX_PKO_MAX_PORTS_INTERFACE1 * | ||
486 | CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port - | ||
487 | 32) * | ||
488 | CVMX_PKO_QUEUES_PER_PORT_PCI; | ||
489 | else if ((port >= 36) && (port < 40)) | ||
490 | return CVMX_PKO_MAX_PORTS_INTERFACE0 * | ||
491 | CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + | ||
492 | CVMX_PKO_MAX_PORTS_INTERFACE1 * | ||
493 | CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + | ||
494 | 4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port - | ||
495 | 36) * | ||
496 | CVMX_PKO_QUEUES_PER_PORT_LOOP; | ||
497 | else | ||
498 | /* Given the limit on the number of ports we can map to | ||
499 | * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256, | ||
500 | * divided among all cores), the remaining unmapped ports | ||
501 | * are assigned an illegal queue number */ | ||
502 | return CVMX_PKO_ILLEGAL_QUEUE; | ||
503 | } | ||
504 | |||
505 | /** | ||
506 | * For a given port number, return the base pko output queue | ||
507 | * for the port. | ||
508 | * | ||
509 | * @port: Port number | ||
510 | * Returns Base output queue | ||
511 | */ | ||
512 | static inline int cvmx_pko_get_base_queue(int port) | ||
513 | { | ||
514 | return cvmx_pko_get_base_queue_per_core(port, 0); | ||
515 | } | ||
516 | |||
517 | /** | ||
518 | * For a given port number, return the number of pko output queues. | ||
519 | * | ||
520 | * @port: Port number | ||
521 | * Returns Number of output queues | ||
522 | */ | ||
523 | static inline int cvmx_pko_get_num_queues(int port) | ||
524 | { | ||
525 | if (port < 16) | ||
526 | return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0; | ||
527 | else if (port < 32) | ||
528 | return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1; | ||
529 | else if (port < 36) | ||
530 | return CVMX_PKO_QUEUES_PER_PORT_PCI; | ||
531 | else if (port < 40) | ||
532 | return CVMX_PKO_QUEUES_PER_PORT_LOOP; | ||
533 | else | ||
534 | return 0; | ||
535 | } | ||
536 | |||
537 | /** | ||
538 | * Get the status counters for a port. | ||
539 | * | ||
540 | * @port_num: Port number to get statistics for. | ||
541 | * @clear: Set to 1 to clear the counters after they are read | ||
542 | * @status: Where to put the results. | ||
543 | */ | ||
544 | static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, | ||
545 | cvmx_pko_port_status_t *status) | ||
546 | { | ||
547 | union cvmx_pko_reg_read_idx pko_reg_read_idx; | ||
548 | union cvmx_pko_mem_count0 pko_mem_count0; | ||
549 | union cvmx_pko_mem_count1 pko_mem_count1; | ||
550 | |||
551 | pko_reg_read_idx.u64 = 0; | ||
552 | pko_reg_read_idx.s.index = port_num; | ||
553 | cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); | ||
554 | |||
555 | pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0); | ||
556 | status->packets = pko_mem_count0.s.count; | ||
557 | if (clear) { | ||
558 | pko_mem_count0.s.count = port_num; | ||
559 | cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64); | ||
560 | } | ||
561 | |||
562 | pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1); | ||
563 | status->octets = pko_mem_count1.s.count; | ||
564 | if (clear) { | ||
565 | pko_mem_count1.s.count = port_num; | ||
566 | cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64); | ||
567 | } | ||
568 | |||
569 | if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { | ||
570 | union cvmx_pko_mem_debug9 debug9; | ||
571 | pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); | ||
572 | cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); | ||
573 | debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); | ||
574 | status->doorbell = debug9.cn38xx.doorbell; | ||
575 | } else { | ||
576 | union cvmx_pko_mem_debug8 debug8; | ||
577 | pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); | ||
578 | cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); | ||
579 | debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); | ||
580 | status->doorbell = debug8.cn58xx.doorbell; | ||
581 | } | ||
582 | } | ||
583 | |||
584 | /** | ||
585 | * Rate limit a PKO port to a max packets/sec. This function is only | ||
586 | * supported on CN57XX, CN56XX, CN55XX, and CN54XX. | ||
587 | * | ||
588 | * @port: Port to rate limit | ||
589 | * @packets_s: Maximum packet/sec | ||
590 | * @burst: Maximum number of packets to burst in a row before rate | ||
591 | * limiting cuts in. | ||
592 | * | ||
593 | * Returns Zero on success, negative on failure | ||
594 | */ | ||
595 | extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst); | ||
596 | |||
597 | /** | ||
598 | * Rate limit a PKO port to a max bits/sec. This function is only | ||
599 | * supported on CN57XX, CN56XX, CN55XX, and CN54XX. | ||
600 | * | ||
601 | * @port: Port to rate limit | ||
602 | * @bits_s: PKO rate limit in bits/sec | ||
603 | * @burst: Maximum number of bits to burst before rate | ||
604 | * limiting cuts in. | ||
605 | * | ||
606 | * Returns Zero on success, negative on failure | ||
607 | */ | ||
608 | extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst); | ||
609 | |||
610 | #endif /* __CVMX_PKO_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-pow.h b/drivers/staging/octeon/cvmx-pow.h new file mode 100644 index 000000000000..c5d66f272b0d --- /dev/null +++ b/drivers/staging/octeon/cvmx-pow.h | |||
@@ -0,0 +1,1982 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * Interface to the hardware Packet Order / Work unit. | ||
30 | * | ||
31 | * New, starting with SDK 1.7.0, cvmx-pow supports a number of | ||
32 | * extended consistency checks. The define | ||
33 | * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW | ||
34 | * internal state checks to find common programming errors. If | ||
35 | * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default | ||
36 | * enabled. For example, cvmx-pow will check for the following | ||
37 | * program errors or POW state inconsistency. | ||
38 | * - Requesting a POW operation with an active tag switch in | ||
39 | * progress. | ||
40 | * - Waiting for a tag switch to complete for an excessively | ||
41 | * long period. This is normally a sign of an error in locking | ||
42 | * causing deadlock. | ||
43 | * - Illegal tag switches from NULL_NULL. | ||
44 | * - Illegal tag switches from NULL. | ||
45 | * - Illegal deschedule request. | ||
46 | * - WQE pointer not matching the one attached to the core by | ||
47 | * the POW. | ||
48 | * | ||
49 | */ | ||
50 | |||
51 | #ifndef __CVMX_POW_H__ | ||
52 | #define __CVMX_POW_H__ | ||
53 | |||
54 | #include <asm/octeon/cvmx-pow-defs.h> | ||
55 | |||
56 | #include "cvmx-scratch.h" | ||
57 | #include "cvmx-wqe.h" | ||
58 | |||
59 | /* Default to having all POW constancy checks turned on */ | ||
60 | #ifndef CVMX_ENABLE_POW_CHECKS | ||
61 | #define CVMX_ENABLE_POW_CHECKS 1 | ||
62 | #endif | ||
63 | |||
64 | enum cvmx_pow_tag_type { | ||
65 | /* Tag ordering is maintained */ | ||
66 | CVMX_POW_TAG_TYPE_ORDERED = 0L, | ||
67 | /* Tag ordering is maintained, and at most one PP has the tag */ | ||
68 | CVMX_POW_TAG_TYPE_ATOMIC = 1L, | ||
69 | /* | ||
70 | * The work queue entry from the order - NEVER tag switch from | ||
71 | * NULL to NULL | ||
72 | */ | ||
73 | CVMX_POW_TAG_TYPE_NULL = 2L, | ||
74 | /* A tag switch to NULL, and there is no space reserved in POW | ||
75 | * - NEVER tag switch to NULL_NULL | ||
76 | * - NEVER tag switch from NULL_NULL | ||
77 | * - NULL_NULL is entered at the beginning of time and on a deschedule. | ||
78 | * - NULL_NULL can be exited by a new work request. A NULL_SWITCH | ||
79 | * load can also switch the state to NULL | ||
80 | */ | ||
81 | CVMX_POW_TAG_TYPE_NULL_NULL = 3L | ||
82 | }; | ||
83 | |||
84 | /** | ||
85 | * Wait flag values for pow functions. | ||
86 | */ | ||
87 | typedef enum { | ||
88 | CVMX_POW_WAIT = 1, | ||
89 | CVMX_POW_NO_WAIT = 0, | ||
90 | } cvmx_pow_wait_t; | ||
91 | |||
92 | /** | ||
93 | * POW tag operations. These are used in the data stored to the POW. | ||
94 | */ | ||
95 | typedef enum { | ||
96 | /* | ||
97 | * switch the tag (only) for this PP | ||
98 | * - the previous tag should be non-NULL in this case | ||
99 | * - tag switch response required | ||
100 | * - fields used: op, type, tag | ||
101 | */ | ||
102 | CVMX_POW_TAG_OP_SWTAG = 0L, | ||
103 | /* | ||
104 | * switch the tag for this PP, with full information | ||
105 | * - this should be used when the previous tag is NULL | ||
106 | * - tag switch response required | ||
107 | * - fields used: address, op, grp, type, tag | ||
108 | */ | ||
109 | CVMX_POW_TAG_OP_SWTAG_FULL = 1L, | ||
110 | /* | ||
111 | * switch the tag (and/or group) for this PP and de-schedule | ||
112 | * - OK to keep the tag the same and only change the group | ||
113 | * - fields used: op, no_sched, grp, type, tag | ||
114 | */ | ||
115 | CVMX_POW_TAG_OP_SWTAG_DESCH = 2L, | ||
116 | /* | ||
117 | * just de-schedule | ||
118 | * - fields used: op, no_sched | ||
119 | */ | ||
120 | CVMX_POW_TAG_OP_DESCH = 3L, | ||
121 | /* | ||
122 | * create an entirely new work queue entry | ||
123 | * - fields used: address, op, qos, grp, type, tag | ||
124 | */ | ||
125 | CVMX_POW_TAG_OP_ADDWQ = 4L, | ||
126 | /* | ||
127 | * just update the work queue pointer and grp for this PP | ||
128 | * - fields used: address, op, grp | ||
129 | */ | ||
130 | CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L, | ||
131 | /* | ||
132 | * set the no_sched bit on the de-schedule list | ||
133 | * | ||
134 | * - does nothing if the selected entry is not on the | ||
135 | * de-schedule list | ||
136 | * | ||
137 | * - does nothing if the stored work queue pointer does not | ||
138 | * match the address field | ||
139 | * | ||
140 | * - fields used: address, index, op | ||
141 | * | ||
142 | * Before issuing a *_NSCHED operation, SW must guarantee | ||
143 | * that all prior deschedules and set/clr NSCHED operations | ||
144 | * are complete and all prior switches are complete. The | ||
145 | * hardware provides the opsdone bit and swdone bit for SW | ||
146 | * polling. After issuing a *_NSCHED operation, SW must | ||
147 | * guarantee that the set/clr NSCHED is complete before any | ||
148 | * subsequent operations. | ||
149 | */ | ||
150 | CVMX_POW_TAG_OP_SET_NSCHED = 6L, | ||
151 | /* | ||
152 | * clears the no_sched bit on the de-schedule list | ||
153 | * | ||
154 | * - does nothing if the selected entry is not on the | ||
155 | * de-schedule list | ||
156 | * | ||
157 | * - does nothing if the stored work queue pointer does not | ||
158 | * match the address field | ||
159 | * | ||
160 | * - fields used: address, index, op | ||
161 | * | ||
162 | * Before issuing a *_NSCHED operation, SW must guarantee that | ||
163 | * all prior deschedules and set/clr NSCHED operations are | ||
164 | * complete and all prior switches are complete. The hardware | ||
165 | * provides the opsdone bit and swdone bit for SW | ||
166 | * polling. After issuing a *_NSCHED operation, SW must | ||
167 | * guarantee that the set/clr NSCHED is complete before any | ||
168 | * subsequent operations. | ||
169 | */ | ||
170 | CVMX_POW_TAG_OP_CLR_NSCHED = 7L, | ||
171 | /* do nothing */ | ||
172 | CVMX_POW_TAG_OP_NOP = 15L | ||
173 | } cvmx_pow_tag_op_t; | ||
174 | |||
175 | /** | ||
176 | * This structure defines the store data on a store to POW | ||
177 | */ | ||
178 | typedef union { | ||
179 | uint64_t u64; | ||
180 | struct { | ||
181 | /* | ||
182 | * Don't reschedule this entry. no_sched is used for | ||
183 | * CVMX_POW_TAG_OP_SWTAG_DESCH and | ||
184 | * CVMX_POW_TAG_OP_DESCH | ||
185 | */ | ||
186 | uint64_t no_sched:1; | ||
187 | uint64_t unused:2; | ||
188 | /* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */ | ||
189 | uint64_t index:13; | ||
190 | /* The operation to perform */ | ||
191 | cvmx_pow_tag_op_t op:4; | ||
192 | uint64_t unused2:2; | ||
193 | /* | ||
194 | * The QOS level for the packet. qos is only used for | ||
195 | * CVMX_POW_TAG_OP_ADDWQ | ||
196 | */ | ||
197 | uint64_t qos:3; | ||
198 | /* | ||
199 | * The group that the work queue entry will be | ||
200 | * scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ, | ||
201 | * CVMX_POW_TAG_OP_SWTAG_FULL, | ||
202 | * CVMX_POW_TAG_OP_SWTAG_DESCH, and | ||
203 | * CVMX_POW_TAG_OP_UPDATE_WQP_GRP | ||
204 | */ | ||
205 | uint64_t grp:4; | ||
206 | /* | ||
207 | * The type of the tag. type is used for everything | ||
208 | * except CVMX_POW_TAG_OP_DESCH, | ||
209 | * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and | ||
210 | * CVMX_POW_TAG_OP_*_NSCHED | ||
211 | */ | ||
212 | uint64_t type:3; | ||
213 | /* | ||
214 | * The actual tag. tag is used for everything except | ||
215 | * CVMX_POW_TAG_OP_DESCH, | ||
216 | * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and | ||
217 | * CVMX_POW_TAG_OP_*_NSCHED | ||
218 | */ | ||
219 | uint64_t tag:32; | ||
220 | } s; | ||
221 | } cvmx_pow_tag_req_t; | ||
222 | |||
223 | /** | ||
224 | * This structure describes the address to load stuff from POW | ||
225 | */ | ||
226 | typedef union { | ||
227 | uint64_t u64; | ||
228 | |||
229 | /** | ||
230 | * Address for new work request loads (did<2:0> == 0) | ||
231 | */ | ||
232 | struct { | ||
233 | /* Mips64 address region. Should be CVMX_IO_SEG */ | ||
234 | uint64_t mem_region:2; | ||
235 | /* Must be zero */ | ||
236 | uint64_t reserved_49_61:13; | ||
237 | /* Must be one */ | ||
238 | uint64_t is_io:1; | ||
239 | /* the ID of POW -- did<2:0> == 0 in this case */ | ||
240 | uint64_t did:8; | ||
241 | /* Must be zero */ | ||
242 | uint64_t reserved_4_39:36; | ||
243 | /* | ||
244 | * If set, don't return load response until work is | ||
245 | * available. | ||
246 | */ | ||
247 | uint64_t wait:1; | ||
248 | /* Must be zero */ | ||
249 | uint64_t reserved_0_2:3; | ||
250 | } swork; | ||
251 | |||
252 | /** | ||
253 | * Address for loads to get POW internal status | ||
254 | */ | ||
255 | struct { | ||
256 | /* Mips64 address region. Should be CVMX_IO_SEG */ | ||
257 | uint64_t mem_region:2; | ||
258 | /* Must be zero */ | ||
259 | uint64_t reserved_49_61:13; | ||
260 | /* Must be one */ | ||
261 | uint64_t is_io:1; | ||
262 | /* the ID of POW -- did<2:0> == 1 in this case */ | ||
263 | uint64_t did:8; | ||
264 | /* Must be zero */ | ||
265 | uint64_t reserved_10_39:30; | ||
266 | /* The core id to get status for */ | ||
267 | uint64_t coreid:4; | ||
268 | /* | ||
269 | * If set and get_cur is set, return reverse tag-list | ||
270 | * pointer rather than forward tag-list pointer. | ||
271 | */ | ||
272 | uint64_t get_rev:1; | ||
273 | /* | ||
274 | * If set, return current status rather than pending | ||
275 | * status. | ||
276 | */ | ||
277 | uint64_t get_cur:1; | ||
278 | /* | ||
279 | * If set, get the work-queue pointer rather than | ||
280 | * tag/type. | ||
281 | */ | ||
282 | uint64_t get_wqp:1; | ||
283 | /* Must be zero */ | ||
284 | uint64_t reserved_0_2:3; | ||
285 | } sstatus; | ||
286 | |||
287 | /** | ||
288 | * Address for memory loads to get POW internal state | ||
289 | */ | ||
290 | struct { | ||
291 | /* Mips64 address region. Should be CVMX_IO_SEG */ | ||
292 | uint64_t mem_region:2; | ||
293 | /* Must be zero */ | ||
294 | uint64_t reserved_49_61:13; | ||
295 | /* Must be one */ | ||
296 | uint64_t is_io:1; | ||
297 | /* the ID of POW -- did<2:0> == 2 in this case */ | ||
298 | uint64_t did:8; | ||
299 | /* Must be zero */ | ||
300 | uint64_t reserved_16_39:24; | ||
301 | /* POW memory index */ | ||
302 | uint64_t index:11; | ||
303 | /* | ||
304 | * If set, return deschedule information rather than | ||
305 | * the standard response for work-queue index (invalid | ||
306 | * if the work-queue entry is not on the deschedule | ||
307 | * list). | ||
308 | */ | ||
309 | uint64_t get_des:1; | ||
310 | /* | ||
311 | * If set, get the work-queue pointer rather than | ||
312 | * tag/type (no effect when get_des set). | ||
313 | */ | ||
314 | uint64_t get_wqp:1; | ||
315 | /* Must be zero */ | ||
316 | uint64_t reserved_0_2:3; | ||
317 | } smemload; | ||
318 | |||
319 | /** | ||
320 | * Address for index/pointer loads | ||
321 | */ | ||
322 | struct { | ||
323 | /* Mips64 address region. Should be CVMX_IO_SEG */ | ||
324 | uint64_t mem_region:2; | ||
325 | /* Must be zero */ | ||
326 | uint64_t reserved_49_61:13; | ||
327 | /* Must be one */ | ||
328 | uint64_t is_io:1; | ||
329 | /* the ID of POW -- did<2:0> == 3 in this case */ | ||
330 | uint64_t did:8; | ||
331 | /* Must be zero */ | ||
332 | uint64_t reserved_9_39:31; | ||
333 | /* | ||
334 | * when {get_rmt ==0 AND get_des_get_tail == 0}, this | ||
335 | * field selects one of eight POW internal-input | ||
336 | * queues (0-7), one per QOS level; values 8-15 are | ||
337 | * illegal in this case; when {get_rmt ==0 AND | ||
338 | * get_des_get_tail == 1}, this field selects one of | ||
339 | * 16 deschedule lists (per group); when get_rmt ==1, | ||
340 | * this field selects one of 16 memory-input queue | ||
341 | * lists. The two memory-input queue lists associated | ||
342 | * with each QOS level are: | ||
343 | * | ||
344 | * - qosgrp = 0, qosgrp = 8: QOS0 | ||
345 | * - qosgrp = 1, qosgrp = 9: QOS1 | ||
346 | * - qosgrp = 2, qosgrp = 10: QOS2 | ||
347 | * - qosgrp = 3, qosgrp = 11: QOS3 | ||
348 | * - qosgrp = 4, qosgrp = 12: QOS4 | ||
349 | * - qosgrp = 5, qosgrp = 13: QOS5 | ||
350 | * - qosgrp = 6, qosgrp = 14: QOS6 | ||
351 | * - qosgrp = 7, qosgrp = 15: QOS7 | ||
352 | */ | ||
353 | uint64_t qosgrp:4; | ||
354 | /* | ||
355 | * If set and get_rmt is clear, return deschedule list | ||
356 | * indexes rather than indexes for the specified qos | ||
357 | * level; if set and get_rmt is set, return the tail | ||
358 | * pointer rather than the head pointer for the | ||
359 | * specified qos level. | ||
360 | */ | ||
361 | uint64_t get_des_get_tail:1; | ||
362 | /* | ||
363 | * If set, return remote pointers rather than the | ||
364 | * local indexes for the specified qos level. | ||
365 | */ | ||
366 | uint64_t get_rmt:1; | ||
367 | /* Must be zero */ | ||
368 | uint64_t reserved_0_2:3; | ||
369 | } sindexload; | ||
370 | |||
371 | /** | ||
372 | * address for NULL_RD request (did<2:0> == 4) when this is read, | ||
373 | * HW attempts to change the state to NULL if it is NULL_NULL (the | ||
374 | * hardware cannot switch from NULL_NULL to NULL if a POW entry is | ||
375 | * not available - software may need to recover by finishing | ||
376 | * another piece of work before a POW entry can ever become | ||
377 | * available.) | ||
378 | */ | ||
379 | struct { | ||
380 | /* Mips64 address region. Should be CVMX_IO_SEG */ | ||
381 | uint64_t mem_region:2; | ||
382 | /* Must be zero */ | ||
383 | uint64_t reserved_49_61:13; | ||
384 | /* Must be one */ | ||
385 | uint64_t is_io:1; | ||
386 | /* the ID of POW -- did<2:0> == 4 in this case */ | ||
387 | uint64_t did:8; | ||
388 | /* Must be zero */ | ||
389 | uint64_t reserved_0_39:40; | ||
390 | } snull_rd; | ||
391 | } cvmx_pow_load_addr_t; | ||
392 | |||
393 | /** | ||
394 | * This structure defines the response to a load/SENDSINGLE to POW | ||
395 | * (except CSR reads) | ||
396 | */ | ||
397 | typedef union { | ||
398 | uint64_t u64; | ||
399 | |||
400 | /** | ||
401 | * Response to new work request loads | ||
402 | */ | ||
403 | struct { | ||
404 | /* | ||
405 | * Set when no new work queue entry was returned. * | ||
406 | * If there was de-scheduled work, the HW will | ||
407 | * definitely return it. When this bit is set, it | ||
408 | * could mean either mean: | ||
409 | * | ||
410 | * - There was no work, or | ||
411 | * | ||
412 | * - There was no work that the HW could find. This | ||
413 | * case can happen, regardless of the wait bit value | ||
414 | * in the original request, when there is work in | ||
415 | * the IQ's that is too deep down the list. | ||
416 | */ | ||
417 | uint64_t no_work:1; | ||
418 | /* Must be zero */ | ||
419 | uint64_t reserved_40_62:23; | ||
420 | /* 36 in O1 -- the work queue pointer */ | ||
421 | uint64_t addr:40; | ||
422 | } s_work; | ||
423 | |||
424 | /** | ||
425 | * Result for a POW Status Load (when get_cur==0 and get_wqp==0) | ||
426 | */ | ||
427 | struct { | ||
428 | uint64_t reserved_62_63:2; | ||
429 | /* Set when there is a pending non-NULL SWTAG or | ||
430 | * SWTAG_FULL, and the POW entry has not left the list | ||
431 | * for the original tag. */ | ||
432 | uint64_t pend_switch:1; | ||
433 | /* Set when SWTAG_FULL and pend_switch is set. */ | ||
434 | uint64_t pend_switch_full:1; | ||
435 | /* | ||
436 | * Set when there is a pending NULL SWTAG, or an | ||
437 | * implicit switch to NULL. | ||
438 | */ | ||
439 | uint64_t pend_switch_null:1; | ||
440 | /* Set when there is a pending DESCHED or SWTAG_DESCHED. */ | ||
441 | uint64_t pend_desched:1; | ||
442 | /* | ||
443 | * Set when there is a pending SWTAG_DESCHED and | ||
444 | * pend_desched is set. | ||
445 | */ | ||
446 | uint64_t pend_desched_switch:1; | ||
447 | /* Set when nosched is desired and pend_desched is set. */ | ||
448 | uint64_t pend_nosched:1; | ||
449 | /* Set when there is a pending GET_WORK. */ | ||
450 | uint64_t pend_new_work:1; | ||
451 | /* | ||
452 | * When pend_new_work is set, this bit indicates that | ||
453 | * the wait bit was set. | ||
454 | */ | ||
455 | uint64_t pend_new_work_wait:1; | ||
456 | /* Set when there is a pending NULL_RD. */ | ||
457 | uint64_t pend_null_rd:1; | ||
458 | /* Set when there is a pending CLR_NSCHED. */ | ||
459 | uint64_t pend_nosched_clr:1; | ||
460 | uint64_t reserved_51:1; | ||
461 | /* This is the index when pend_nosched_clr is set. */ | ||
462 | uint64_t pend_index:11; | ||
463 | /* | ||
464 | * This is the new_grp when (pend_desched AND | ||
465 | * pend_desched_switch) is set. | ||
466 | */ | ||
467 | uint64_t pend_grp:4; | ||
468 | uint64_t reserved_34_35:2; | ||
469 | /* | ||
470 | * This is the tag type when pend_switch or | ||
471 | * (pend_desched AND pend_desched_switch) are set. | ||
472 | */ | ||
473 | uint64_t pend_type:2; | ||
474 | /* | ||
475 | * - this is the tag when pend_switch or (pend_desched | ||
476 | * AND pend_desched_switch) are set. | ||
477 | */ | ||
478 | uint64_t pend_tag:32; | ||
479 | } s_sstatus0; | ||
480 | |||
481 | /** | ||
482 | * Result for a POW Status Load (when get_cur==0 and get_wqp==1) | ||
483 | */ | ||
484 | struct { | ||
485 | uint64_t reserved_62_63:2; | ||
486 | /* | ||
487 | * Set when there is a pending non-NULL SWTAG or | ||
488 | * SWTAG_FULL, and the POW entry has not left the list | ||
489 | * for the original tag. | ||
490 | */ | ||
491 | uint64_t pend_switch:1; | ||
492 | /* Set when SWTAG_FULL and pend_switch is set. */ | ||
493 | uint64_t pend_switch_full:1; | ||
494 | /* | ||
495 | * Set when there is a pending NULL SWTAG, or an | ||
496 | * implicit switch to NULL. | ||
497 | */ | ||
498 | uint64_t pend_switch_null:1; | ||
499 | /* | ||
500 | * Set when there is a pending DESCHED or | ||
501 | * SWTAG_DESCHED. | ||
502 | */ | ||
503 | uint64_t pend_desched:1; | ||
504 | /* | ||
505 | * Set when there is a pending SWTAG_DESCHED and | ||
506 | * pend_desched is set. | ||
507 | */ | ||
508 | uint64_t pend_desched_switch:1; | ||
509 | /* Set when nosched is desired and pend_desched is set. */ | ||
510 | uint64_t pend_nosched:1; | ||
511 | /* Set when there is a pending GET_WORK. */ | ||
512 | uint64_t pend_new_work:1; | ||
513 | /* | ||
514 | * When pend_new_work is set, this bit indicates that | ||
515 | * the wait bit was set. | ||
516 | */ | ||
517 | uint64_t pend_new_work_wait:1; | ||
518 | /* Set when there is a pending NULL_RD. */ | ||
519 | uint64_t pend_null_rd:1; | ||
520 | /* Set when there is a pending CLR_NSCHED. */ | ||
521 | uint64_t pend_nosched_clr:1; | ||
522 | uint64_t reserved_51:1; | ||
523 | /* This is the index when pend_nosched_clr is set. */ | ||
524 | uint64_t pend_index:11; | ||
525 | /* | ||
526 | * This is the new_grp when (pend_desched AND | ||
527 | * pend_desched_switch) is set. | ||
528 | */ | ||
529 | uint64_t pend_grp:4; | ||
530 | /* This is the wqp when pend_nosched_clr is set. */ | ||
531 | uint64_t pend_wqp:36; | ||
532 | } s_sstatus1; | ||
533 | |||
534 | /** | ||
535 | * Result for a POW Status Load (when get_cur==1, get_wqp==0, and | ||
536 | * get_rev==0) | ||
537 | */ | ||
538 | struct { | ||
539 | uint64_t reserved_62_63:2; | ||
540 | /* | ||
541 | * Points to the next POW entry in the tag list when | ||
542 | * tail == 0 (and tag_type is not NULL or NULL_NULL). | ||
543 | */ | ||
544 | uint64_t link_index:11; | ||
545 | /* The POW entry attached to the core. */ | ||
546 | uint64_t index:11; | ||
547 | /* | ||
548 | * The group attached to the core (updated when new | ||
549 | * tag list entered on SWTAG_FULL). | ||
550 | */ | ||
551 | uint64_t grp:4; | ||
552 | /* | ||
553 | * Set when this POW entry is at the head of its tag | ||
554 | * list (also set when in the NULL or NULL_NULL | ||
555 | * state). | ||
556 | */ | ||
557 | uint64_t head:1; | ||
558 | /* | ||
559 | * Set when this POW entry is at the tail of its tag | ||
560 | * list (also set when in the NULL or NULL_NULL | ||
561 | * state). | ||
562 | */ | ||
563 | uint64_t tail:1; | ||
564 | /* | ||
565 | * The tag type attached to the core (updated when new | ||
566 | * tag list entered on SWTAG, SWTAG_FULL, or | ||
567 | * SWTAG_DESCHED). | ||
568 | */ | ||
569 | uint64_t tag_type:2; | ||
570 | /* | ||
571 | * The tag attached to the core (updated when new tag | ||
572 | * list entered on SWTAG, SWTAG_FULL, or | ||
573 | * SWTAG_DESCHED). | ||
574 | */ | ||
575 | uint64_t tag:32; | ||
576 | } s_sstatus2; | ||
577 | |||
578 | /** | ||
579 | * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1) | ||
580 | */ | ||
581 | struct { | ||
582 | uint64_t reserved_62_63:2; | ||
583 | /* | ||
584 | * Points to the prior POW entry in the tag list when | ||
585 | * head == 0 (and tag_type is not NULL or | ||
586 | * NULL_NULL). This field is unpredictable when the | ||
587 | * core's state is NULL or NULL_NULL. | ||
588 | */ | ||
589 | uint64_t revlink_index:11; | ||
590 | /* The POW entry attached to the core. */ | ||
591 | uint64_t index:11; | ||
592 | /* | ||
593 | * The group attached to the core (updated when new | ||
594 | * tag list entered on SWTAG_FULL). | ||
595 | */ | ||
596 | uint64_t grp:4; | ||
597 | /* Set when this POW entry is at the head of its tag | ||
598 | * list (also set when in the NULL or NULL_NULL | ||
599 | * state). | ||
600 | */ | ||
601 | uint64_t head:1; | ||
602 | /* | ||
603 | * Set when this POW entry is at the tail of its tag | ||
604 | * list (also set when in the NULL or NULL_NULL | ||
605 | * state). | ||
606 | */ | ||
607 | uint64_t tail:1; | ||
608 | /* | ||
609 | * The tag type attached to the core (updated when new | ||
610 | * tag list entered on SWTAG, SWTAG_FULL, or | ||
611 | * SWTAG_DESCHED). | ||
612 | */ | ||
613 | uint64_t tag_type:2; | ||
614 | /* | ||
615 | * The tag attached to the core (updated when new tag | ||
616 | * list entered on SWTAG, SWTAG_FULL, or | ||
617 | * SWTAG_DESCHED). | ||
618 | */ | ||
619 | uint64_t tag:32; | ||
620 | } s_sstatus3; | ||
621 | |||
622 | /** | ||
623 | * Result for a POW Status Load (when get_cur==1, get_wqp==1, and | ||
624 | * get_rev==0) | ||
625 | */ | ||
626 | struct { | ||
627 | uint64_t reserved_62_63:2; | ||
628 | /* | ||
629 | * Points to the next POW entry in the tag list when | ||
630 | * tail == 0 (and tag_type is not NULL or NULL_NULL). | ||
631 | */ | ||
632 | uint64_t link_index:11; | ||
633 | /* The POW entry attached to the core. */ | ||
634 | uint64_t index:11; | ||
635 | /* | ||
636 | * The group attached to the core (updated when new | ||
637 | * tag list entered on SWTAG_FULL). | ||
638 | */ | ||
639 | uint64_t grp:4; | ||
640 | /* | ||
641 | * The wqp attached to the core (updated when new tag | ||
642 | * list entered on SWTAG_FULL). | ||
643 | */ | ||
644 | uint64_t wqp:36; | ||
645 | } s_sstatus4; | ||
646 | |||
647 | /** | ||
648 | * Result for a POW Status Load (when get_cur==1, get_wqp==1, and | ||
649 | * get_rev==1) | ||
650 | */ | ||
651 | struct { | ||
652 | uint64_t reserved_62_63:2; | ||
653 | /* | ||
654 | * Points to the prior POW entry in the tag list when | ||
655 | * head == 0 (and tag_type is not NULL or | ||
656 | * NULL_NULL). This field is unpredictable when the | ||
657 | * core's state is NULL or NULL_NULL. | ||
658 | */ | ||
659 | uint64_t revlink_index:11; | ||
660 | /* The POW entry attached to the core. */ | ||
661 | uint64_t index:11; | ||
662 | /* | ||
663 | * The group attached to the core (updated when new | ||
664 | * tag list entered on SWTAG_FULL). | ||
665 | */ | ||
666 | uint64_t grp:4; | ||
667 | /* | ||
668 | * The wqp attached to the core (updated when new tag | ||
669 | * list entered on SWTAG_FULL). | ||
670 | */ | ||
671 | uint64_t wqp:36; | ||
672 | } s_sstatus5; | ||
673 | |||
674 | /** | ||
675 | * Result For POW Memory Load (get_des == 0 and get_wqp == 0) | ||
676 | */ | ||
677 | struct { | ||
678 | uint64_t reserved_51_63:13; | ||
679 | /* | ||
680 | * The next entry in the input, free, descheduled_head | ||
681 | * list (unpredictable if entry is the tail of the | ||
682 | * list). | ||
683 | */ | ||
684 | uint64_t next_index:11; | ||
685 | /* The group of the POW entry. */ | ||
686 | uint64_t grp:4; | ||
687 | uint64_t reserved_35:1; | ||
688 | /* | ||
689 | * Set when this POW entry is at the tail of its tag | ||
690 | * list (also set when in the NULL or NULL_NULL | ||
691 | * state). | ||
692 | */ | ||
693 | uint64_t tail:1; | ||
694 | /* The tag type of the POW entry. */ | ||
695 | uint64_t tag_type:2; | ||
696 | /* The tag of the POW entry. */ | ||
697 | uint64_t tag:32; | ||
698 | } s_smemload0; | ||
699 | |||
700 | /** | ||
701 | * Result For POW Memory Load (get_des == 0 and get_wqp == 1) | ||
702 | */ | ||
703 | struct { | ||
704 | uint64_t reserved_51_63:13; | ||
705 | /* | ||
706 | * The next entry in the input, free, descheduled_head | ||
707 | * list (unpredictable if entry is the tail of the | ||
708 | * list). | ||
709 | */ | ||
710 | uint64_t next_index:11; | ||
711 | /* The group of the POW entry. */ | ||
712 | uint64_t grp:4; | ||
713 | /* The WQP held in the POW entry. */ | ||
714 | uint64_t wqp:36; | ||
715 | } s_smemload1; | ||
716 | |||
717 | /** | ||
718 | * Result For POW Memory Load (get_des == 1) | ||
719 | */ | ||
720 | struct { | ||
721 | uint64_t reserved_51_63:13; | ||
722 | /* | ||
723 | * The next entry in the tag list connected to the | ||
724 | * descheduled head. | ||
725 | */ | ||
726 | uint64_t fwd_index:11; | ||
727 | /* The group of the POW entry. */ | ||
728 | uint64_t grp:4; | ||
729 | /* The nosched bit for the POW entry. */ | ||
730 | uint64_t nosched:1; | ||
731 | /* There is a pending tag switch */ | ||
732 | uint64_t pend_switch:1; | ||
733 | /* | ||
734 | * The next tag type for the new tag list when | ||
735 | * pend_switch is set. | ||
736 | */ | ||
737 | uint64_t pend_type:2; | ||
738 | /* | ||
739 | * The next tag for the new tag list when pend_switch | ||
740 | * is set. | ||
741 | */ | ||
742 | uint64_t pend_tag:32; | ||
743 | } s_smemload2; | ||
744 | |||
745 | /** | ||
746 | * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0) | ||
747 | */ | ||
748 | struct { | ||
749 | uint64_t reserved_52_63:12; | ||
750 | /* | ||
751 | * set when there is one or more POW entries on the | ||
752 | * free list. | ||
753 | */ | ||
754 | uint64_t free_val:1; | ||
755 | /* | ||
756 | * set when there is exactly one POW entry on the free | ||
757 | * list. | ||
758 | */ | ||
759 | uint64_t free_one:1; | ||
760 | uint64_t reserved_49:1; | ||
761 | /* | ||
762 | * when free_val is set, indicates the first entry on | ||
763 | * the free list. | ||
764 | */ | ||
765 | uint64_t free_head:11; | ||
766 | uint64_t reserved_37:1; | ||
767 | /* | ||
768 | * when free_val is set, indicates the last entry on | ||
769 | * the free list. | ||
770 | */ | ||
771 | uint64_t free_tail:11; | ||
772 | /* | ||
773 | * set when there is one or more POW entries on the | ||
774 | * input Q list selected by qosgrp. | ||
775 | */ | ||
776 | uint64_t loc_val:1; | ||
777 | /* | ||
778 | * set when there is exactly one POW entry on the | ||
779 | * input Q list selected by qosgrp. | ||
780 | */ | ||
781 | uint64_t loc_one:1; | ||
782 | uint64_t reserved_23:1; | ||
783 | /* | ||
784 | * when loc_val is set, indicates the first entry on | ||
785 | * the input Q list selected by qosgrp. | ||
786 | */ | ||
787 | uint64_t loc_head:11; | ||
788 | uint64_t reserved_11:1; | ||
789 | /* | ||
790 | * when loc_val is set, indicates the last entry on | ||
791 | * the input Q list selected by qosgrp. | ||
792 | */ | ||
793 | uint64_t loc_tail:11; | ||
794 | } sindexload0; | ||
795 | |||
796 | /** | ||
797 | * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1) | ||
798 | */ | ||
799 | struct { | ||
800 | uint64_t reserved_52_63:12; | ||
801 | /* | ||
802 | * set when there is one or more POW entries on the | ||
803 | * nosched list. | ||
804 | */ | ||
805 | uint64_t nosched_val:1; | ||
806 | /* | ||
807 | * set when there is exactly one POW entry on the | ||
808 | * nosched list. | ||
809 | */ | ||
810 | uint64_t nosched_one:1; | ||
811 | uint64_t reserved_49:1; | ||
812 | /* | ||
813 | * when nosched_val is set, indicates the first entry | ||
814 | * on the nosched list. | ||
815 | */ | ||
816 | uint64_t nosched_head:11; | ||
817 | uint64_t reserved_37:1; | ||
818 | /* | ||
819 | * when nosched_val is set, indicates the last entry | ||
820 | * on the nosched list. | ||
821 | */ | ||
822 | uint64_t nosched_tail:11; | ||
823 | /* | ||
824 | * set when there is one or more descheduled heads on | ||
825 | * the descheduled list selected by qosgrp. | ||
826 | */ | ||
827 | uint64_t des_val:1; | ||
828 | /* | ||
829 | * set when there is exactly one descheduled head on | ||
830 | * the descheduled list selected by qosgrp. | ||
831 | */ | ||
832 | uint64_t des_one:1; | ||
833 | uint64_t reserved_23:1; | ||
834 | /* | ||
835 | * when des_val is set, indicates the first | ||
836 | * descheduled head on the descheduled list selected | ||
837 | * by qosgrp. | ||
838 | */ | ||
839 | uint64_t des_head:11; | ||
840 | uint64_t reserved_11:1; | ||
841 | /* | ||
842 | * when des_val is set, indicates the last descheduled | ||
843 | * head on the descheduled list selected by qosgrp. | ||
844 | */ | ||
845 | uint64_t des_tail:11; | ||
846 | } sindexload1; | ||
847 | |||
848 | /** | ||
849 | * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0) | ||
850 | */ | ||
851 | struct { | ||
852 | uint64_t reserved_39_63:25; | ||
853 | /* | ||
854 | * Set when this DRAM list is the current head | ||
855 | * (i.e. is the next to be reloaded when the POW | ||
856 | * hardware reloads a POW entry from DRAM). The POW | ||
857 | * hardware alternates between the two DRAM lists | ||
858 | * associated with a QOS level when it reloads work | ||
859 | * from DRAM into the POW unit. | ||
860 | */ | ||
861 | uint64_t rmt_is_head:1; | ||
862 | /* | ||
863 | * Set when the DRAM portion of the input Q list | ||
864 | * selected by qosgrp contains one or more pieces of | ||
865 | * work. | ||
866 | */ | ||
867 | uint64_t rmt_val:1; | ||
868 | /* | ||
869 | * Set when the DRAM portion of the input Q list | ||
870 | * selected by qosgrp contains exactly one piece of | ||
871 | * work. | ||
872 | */ | ||
873 | uint64_t rmt_one:1; | ||
874 | /* | ||
875 | * When rmt_val is set, indicates the first piece of | ||
876 | * work on the DRAM input Q list selected by | ||
877 | * qosgrp. | ||
878 | */ | ||
879 | uint64_t rmt_head:36; | ||
880 | } sindexload2; | ||
881 | |||
882 | /** | ||
883 | * Result For POW Index/Pointer Load (get_rmt == | ||
884 | * 1/get_des_get_tail == 1) | ||
885 | */ | ||
886 | struct { | ||
887 | uint64_t reserved_39_63:25; | ||
888 | /* | ||
889 | * set when this DRAM list is the current head | ||
890 | * (i.e. is the next to be reloaded when the POW | ||
891 | * hardware reloads a POW entry from DRAM). The POW | ||
892 | * hardware alternates between the two DRAM lists | ||
893 | * associated with a QOS level when it reloads work | ||
894 | * from DRAM into the POW unit. | ||
895 | */ | ||
896 | uint64_t rmt_is_head:1; | ||
897 | /* | ||
898 | * set when the DRAM portion of the input Q list | ||
899 | * selected by qosgrp contains one or more pieces of | ||
900 | * work. | ||
901 | */ | ||
902 | uint64_t rmt_val:1; | ||
903 | /* | ||
904 | * set when the DRAM portion of the input Q list | ||
905 | * selected by qosgrp contains exactly one piece of | ||
906 | * work. | ||
907 | */ | ||
908 | uint64_t rmt_one:1; | ||
909 | /* | ||
910 | * when rmt_val is set, indicates the last piece of | ||
911 | * work on the DRAM input Q list selected by | ||
912 | * qosgrp. | ||
913 | */ | ||
914 | uint64_t rmt_tail:36; | ||
915 | } sindexload3; | ||
916 | |||
917 | /** | ||
918 | * Response to NULL_RD request loads | ||
919 | */ | ||
920 | struct { | ||
921 | uint64_t unused:62; | ||
922 | /* of type cvmx_pow_tag_type_t. state is one of the | ||
923 | * following: | ||
924 | * | ||
925 | * - CVMX_POW_TAG_TYPE_ORDERED | ||
926 | * - CVMX_POW_TAG_TYPE_ATOMIC | ||
927 | * - CVMX_POW_TAG_TYPE_NULL | ||
928 | * - CVMX_POW_TAG_TYPE_NULL_NULL | ||
929 | */ | ||
930 | uint64_t state:2; | ||
931 | } s_null_rd; | ||
932 | |||
933 | } cvmx_pow_tag_load_resp_t; | ||
934 | |||
935 | /** | ||
936 | * This structure describes the address used for stores to the POW. | ||
937 | * The store address is meaningful on stores to the POW. The | ||
938 | * hardware assumes that an aligned 64-bit store was used for all | ||
939 | * these stores. Note the assumption that the work queue entry is | ||
940 | * aligned on an 8-byte boundary (since the low-order 3 address bits | ||
941 | * must be zero). Note that not all fields are used by all | ||
942 | * operations. | ||
943 | * | ||
944 | * NOTE: The following is the behavior of the pending switch bit at the PP | ||
945 | * for POW stores (i.e. when did<7:3> == 0xc) | ||
946 | * - did<2:0> == 0 => pending switch bit is set | ||
947 | * - did<2:0> == 1 => no affect on the pending switch bit | ||
948 | * - did<2:0> == 3 => pending switch bit is cleared | ||
949 | * - did<2:0> == 7 => no affect on the pending switch bit | ||
950 | * - did<2:0> == others => must not be used | ||
951 | * - No other loads/stores have an affect on the pending switch bit | ||
952 | * - The switch bus from POW can clear the pending switch bit | ||
953 | * | ||
954 | * NOTE: did<2:0> == 2 is used by the HW for a special single-cycle | ||
955 | * ADDWQ command that only contains the pointer). SW must never use | ||
956 | * did<2:0> == 2. | ||
957 | */ | ||
958 | typedef union { | ||
959 | /** | ||
960 | * Unsigned 64 bit integer representation of store address | ||
961 | */ | ||
962 | uint64_t u64; | ||
963 | |||
964 | struct { | ||
965 | /* Memory region. Should be CVMX_IO_SEG in most cases */ | ||
966 | uint64_t mem_reg:2; | ||
967 | uint64_t reserved_49_61:13; /* Must be zero */ | ||
968 | uint64_t is_io:1; /* Must be one */ | ||
969 | /* Device ID of POW. Note that different sub-dids are used. */ | ||
970 | uint64_t did:8; | ||
971 | uint64_t reserved_36_39:4; /* Must be zero */ | ||
972 | /* Address field. addr<2:0> must be zero */ | ||
973 | uint64_t addr:36; | ||
974 | } stag; | ||
975 | } cvmx_pow_tag_store_addr_t; | ||
976 | |||
977 | /** | ||
978 | * decode of the store data when an IOBDMA SENDSINGLE is sent to POW | ||
979 | */ | ||
980 | typedef union { | ||
981 | uint64_t u64; | ||
982 | |||
983 | struct { | ||
984 | /* | ||
985 | * the (64-bit word) location in scratchpad to write | ||
986 | * to (if len != 0) | ||
987 | */ | ||
988 | uint64_t scraddr:8; | ||
989 | /* the number of words in the response (0 => no response) */ | ||
990 | uint64_t len:8; | ||
991 | /* the ID of the device on the non-coherent bus */ | ||
992 | uint64_t did:8; | ||
993 | uint64_t unused:36; | ||
994 | /* if set, don't return load response until work is available */ | ||
995 | uint64_t wait:1; | ||
996 | uint64_t unused2:3; | ||
997 | } s; | ||
998 | |||
999 | } cvmx_pow_iobdma_store_t; | ||
1000 | |||
1001 | /* CSR typedefs have been moved to cvmx-csr-*.h */ | ||
1002 | |||
1003 | /** | ||
1004 | * Get the POW tag for this core. This returns the current | ||
1005 | * tag type, tag, group, and POW entry index associated with | ||
1006 | * this core. Index is only valid if the tag type isn't NULL_NULL. | ||
1007 | * If a tag switch is pending this routine returns the tag before | ||
1008 | * the tag switch, not after. | ||
1009 | * | ||
1010 | * Returns Current tag | ||
1011 | */ | ||
1012 | static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void) | ||
1013 | { | ||
1014 | cvmx_pow_load_addr_t load_addr; | ||
1015 | cvmx_pow_tag_load_resp_t load_resp; | ||
1016 | cvmx_pow_tag_req_t result; | ||
1017 | |||
1018 | load_addr.u64 = 0; | ||
1019 | load_addr.sstatus.mem_region = CVMX_IO_SEG; | ||
1020 | load_addr.sstatus.is_io = 1; | ||
1021 | load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1; | ||
1022 | load_addr.sstatus.coreid = cvmx_get_core_num(); | ||
1023 | load_addr.sstatus.get_cur = 1; | ||
1024 | load_resp.u64 = cvmx_read_csr(load_addr.u64); | ||
1025 | result.u64 = 0; | ||
1026 | result.s.grp = load_resp.s_sstatus2.grp; | ||
1027 | result.s.index = load_resp.s_sstatus2.index; | ||
1028 | result.s.type = load_resp.s_sstatus2.tag_type; | ||
1029 | result.s.tag = load_resp.s_sstatus2.tag; | ||
1030 | return result; | ||
1031 | } | ||
1032 | |||
1033 | /** | ||
1034 | * Get the POW WQE for this core. This returns the work queue | ||
1035 | * entry currently associated with this core. | ||
1036 | * | ||
1037 | * Returns WQE pointer | ||
1038 | */ | ||
1039 | static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void) | ||
1040 | { | ||
1041 | cvmx_pow_load_addr_t load_addr; | ||
1042 | cvmx_pow_tag_load_resp_t load_resp; | ||
1043 | |||
1044 | load_addr.u64 = 0; | ||
1045 | load_addr.sstatus.mem_region = CVMX_IO_SEG; | ||
1046 | load_addr.sstatus.is_io = 1; | ||
1047 | load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1; | ||
1048 | load_addr.sstatus.coreid = cvmx_get_core_num(); | ||
1049 | load_addr.sstatus.get_cur = 1; | ||
1050 | load_addr.sstatus.get_wqp = 1; | ||
1051 | load_resp.u64 = cvmx_read_csr(load_addr.u64); | ||
1052 | return (cvmx_wqe_t *) cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp); | ||
1053 | } | ||
1054 | |||
1055 | #ifndef CVMX_MF_CHORD | ||
1056 | #define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) | ||
1057 | #endif | ||
1058 | |||
1059 | /** | ||
1060 | * Print a warning if a tag switch is pending for this core | ||
1061 | * | ||
1062 | * @function: Function name checking for a pending tag switch | ||
1063 | */ | ||
1064 | static inline void __cvmx_pow_warn_if_pending_switch(const char *function) | ||
1065 | { | ||
1066 | uint64_t switch_complete; | ||
1067 | CVMX_MF_CHORD(switch_complete); | ||
1068 | if (!switch_complete) | ||
1069 | pr_warning("%s called with tag switch in progress\n", function); | ||
1070 | } | ||
1071 | |||
1072 | /** | ||
1073 | * Waits for a tag switch to complete by polling the completion bit. | ||
1074 | * Note that switches to NULL complete immediately and do not need | ||
1075 | * to be waited for. | ||
1076 | */ | ||
1077 | static inline void cvmx_pow_tag_sw_wait(void) | ||
1078 | { | ||
1079 | const uint64_t MAX_CYCLES = 1ull << 31; | ||
1080 | uint64_t switch_complete; | ||
1081 | uint64_t start_cycle = cvmx_get_cycle(); | ||
1082 | while (1) { | ||
1083 | CVMX_MF_CHORD(switch_complete); | ||
1084 | if (unlikely(switch_complete)) | ||
1085 | break; | ||
1086 | if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) { | ||
1087 | pr_warning("Tag switch is taking a long time, " | ||
1088 | "possible deadlock\n"); | ||
1089 | start_cycle = -MAX_CYCLES - 1; | ||
1090 | } | ||
1091 | } | ||
1092 | } | ||
1093 | |||
1094 | /** | ||
1095 | * Synchronous work request. Requests work from the POW. | ||
1096 | * This function does NOT wait for previous tag switches to complete, | ||
1097 | * so the caller must ensure that there is not a pending tag switch. | ||
1098 | * | ||
1099 | * @wait: When set, call stalls until work becomes avaiable, or times out. | ||
1100 | * If not set, returns immediately. | ||
1101 | * | ||
1102 | * Returns Returns the WQE pointer from POW. Returns NULL if no work | ||
1103 | * was available. | ||
1104 | */ | ||
1105 | static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t | ||
1106 | wait) | ||
1107 | { | ||
1108 | cvmx_pow_load_addr_t ptr; | ||
1109 | cvmx_pow_tag_load_resp_t result; | ||
1110 | |||
1111 | if (CVMX_ENABLE_POW_CHECKS) | ||
1112 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1113 | |||
1114 | ptr.u64 = 0; | ||
1115 | ptr.swork.mem_region = CVMX_IO_SEG; | ||
1116 | ptr.swork.is_io = 1; | ||
1117 | ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG; | ||
1118 | ptr.swork.wait = wait; | ||
1119 | |||
1120 | result.u64 = cvmx_read_csr(ptr.u64); | ||
1121 | |||
1122 | if (result.s_work.no_work) | ||
1123 | return NULL; | ||
1124 | else | ||
1125 | return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr); | ||
1126 | } | ||
1127 | |||
1128 | /** | ||
1129 | * Synchronous work request. Requests work from the POW. | ||
1130 | * This function waits for any previous tag switch to complete before | ||
1131 | * requesting the new work. | ||
1132 | * | ||
1133 | * @wait: When set, call stalls until work becomes avaiable, or times out. | ||
1134 | * If not set, returns immediately. | ||
1135 | * | ||
1136 | * Returns Returns the WQE pointer from POW. Returns NULL if no work | ||
1137 | * was available. | ||
1138 | */ | ||
1139 | static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait) | ||
1140 | { | ||
1141 | if (CVMX_ENABLE_POW_CHECKS) | ||
1142 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1143 | |||
1144 | /* Must not have a switch pending when requesting work */ | ||
1145 | cvmx_pow_tag_sw_wait(); | ||
1146 | return cvmx_pow_work_request_sync_nocheck(wait); | ||
1147 | |||
1148 | } | ||
1149 | |||
1150 | /** | ||
1151 | * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state. | ||
1152 | * This function waits for any previous tag switch to complete before | ||
1153 | * requesting the null_rd. | ||
1154 | * | ||
1155 | * Returns Returns the POW state of type cvmx_pow_tag_type_t. | ||
1156 | */ | ||
1157 | static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void) | ||
1158 | { | ||
1159 | cvmx_pow_load_addr_t ptr; | ||
1160 | cvmx_pow_tag_load_resp_t result; | ||
1161 | |||
1162 | if (CVMX_ENABLE_POW_CHECKS) | ||
1163 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1164 | |||
1165 | /* Must not have a switch pending when requesting work */ | ||
1166 | cvmx_pow_tag_sw_wait(); | ||
1167 | |||
1168 | ptr.u64 = 0; | ||
1169 | ptr.snull_rd.mem_region = CVMX_IO_SEG; | ||
1170 | ptr.snull_rd.is_io = 1; | ||
1171 | ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD; | ||
1172 | |||
1173 | result.u64 = cvmx_read_csr(ptr.u64); | ||
1174 | |||
1175 | return (enum cvmx_pow_tag_type) result.s_null_rd.state; | ||
1176 | } | ||
1177 | |||
1178 | /** | ||
1179 | * Asynchronous work request. Work is requested from the POW unit, | ||
1180 | * and should later be checked with function | ||
1181 | * cvmx_pow_work_response_async. This function does NOT wait for | ||
1182 | * previous tag switches to complete, so the caller must ensure that | ||
1183 | * there is not a pending tag switch. | ||
1184 | * | ||
1185 | * @scr_addr: Scratch memory address that response will be returned | ||
1186 | * to, which is either a valid WQE, or a response with the | ||
1187 | * invalid bit set. Byte address, must be 8 byte aligned. | ||
1188 | * | ||
1189 | * @wait: 1 to cause response to wait for work to become available (or | ||
1190 | * timeout), 0 to cause response to return immediately | ||
1191 | */ | ||
1192 | static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, | ||
1193 | cvmx_pow_wait_t wait) | ||
1194 | { | ||
1195 | cvmx_pow_iobdma_store_t data; | ||
1196 | |||
1197 | if (CVMX_ENABLE_POW_CHECKS) | ||
1198 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1199 | |||
1200 | /* scr_addr must be 8 byte aligned */ | ||
1201 | data.s.scraddr = scr_addr >> 3; | ||
1202 | data.s.len = 1; | ||
1203 | data.s.did = CVMX_OCT_DID_TAG_SWTAG; | ||
1204 | data.s.wait = wait; | ||
1205 | cvmx_send_single(data.u64); | ||
1206 | } | ||
1207 | |||
1208 | /** | ||
1209 | * Asynchronous work request. Work is requested from the POW unit, | ||
1210 | * and should later be checked with function | ||
1211 | * cvmx_pow_work_response_async. This function waits for any previous | ||
1212 | * tag switch to complete before requesting the new work. | ||
1213 | * | ||
1214 | * @scr_addr: Scratch memory address that response will be returned | ||
1215 | * to, which is either a valid WQE, or a response with the | ||
1216 | * invalid bit set. Byte address, must be 8 byte aligned. | ||
1217 | * | ||
1218 | * @wait: 1 to cause response to wait for work to become available (or | ||
1219 | * timeout), 0 to cause response to return immediately | ||
1220 | */ | ||
1221 | static inline void cvmx_pow_work_request_async(int scr_addr, | ||
1222 | cvmx_pow_wait_t wait) | ||
1223 | { | ||
1224 | if (CVMX_ENABLE_POW_CHECKS) | ||
1225 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1226 | |||
1227 | /* Must not have a switch pending when requesting work */ | ||
1228 | cvmx_pow_tag_sw_wait(); | ||
1229 | cvmx_pow_work_request_async_nocheck(scr_addr, wait); | ||
1230 | } | ||
1231 | |||
1232 | /** | ||
1233 | * Gets result of asynchronous work request. Performs a IOBDMA sync | ||
1234 | * to wait for the response. | ||
1235 | * | ||
1236 | * @scr_addr: Scratch memory address to get result from Byte address, | ||
1237 | * must be 8 byte aligned. | ||
1238 | * | ||
1239 | * Returns Returns the WQE from the scratch register, or NULL if no | ||
1240 | * work was available. | ||
1241 | */ | ||
1242 | static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr) | ||
1243 | { | ||
1244 | cvmx_pow_tag_load_resp_t result; | ||
1245 | |||
1246 | CVMX_SYNCIOBDMA; | ||
1247 | result.u64 = cvmx_scratch_read64(scr_addr); | ||
1248 | |||
1249 | if (result.s_work.no_work) | ||
1250 | return NULL; | ||
1251 | else | ||
1252 | return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr); | ||
1253 | } | ||
1254 | |||
1255 | /** | ||
1256 | * Checks if a work queue entry pointer returned by a work | ||
1257 | * request is valid. It may be invalid due to no work | ||
1258 | * being available or due to a timeout. | ||
1259 | * | ||
1260 | * @wqe_ptr: pointer to a work queue entry returned by the POW | ||
1261 | * | ||
1262 | * Returns 0 if pointer is valid | ||
1263 | * 1 if invalid (no work was returned) | ||
1264 | */ | ||
1265 | static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr) | ||
1266 | { | ||
1267 | return wqe_ptr == NULL; | ||
1268 | } | ||
1269 | |||
1270 | /** | ||
1271 | * Starts a tag switch to the provided tag value and tag type. | ||
1272 | * Completion for the tag switch must be checked for separately. This | ||
1273 | * function does NOT update the work queue entry in dram to match tag | ||
1274 | * value and type, so the application must keep track of these if they | ||
1275 | * are important to the application. This tag switch command must not | ||
1276 | * be used for switches to NULL, as the tag switch pending bit will be | ||
1277 | * set by the switch request, but never cleared by the hardware. | ||
1278 | * | ||
1279 | * NOTE: This should not be used when switching from a NULL tag. Use | ||
1280 | * cvmx_pow_tag_sw_full() instead. | ||
1281 | * | ||
1282 | * This function does no checks, so the caller must ensure that any | ||
1283 | * previous tag switch has completed. | ||
1284 | * | ||
1285 | * @tag: new tag value | ||
1286 | * @tag_type: new tag type (ordered or atomic) | ||
1287 | */ | ||
1288 | static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag, | ||
1289 | enum cvmx_pow_tag_type tag_type) | ||
1290 | { | ||
1291 | cvmx_addr_t ptr; | ||
1292 | cvmx_pow_tag_req_t tag_req; | ||
1293 | |||
1294 | if (CVMX_ENABLE_POW_CHECKS) { | ||
1295 | cvmx_pow_tag_req_t current_tag; | ||
1296 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1297 | current_tag = cvmx_pow_get_current_tag(); | ||
1298 | if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) | ||
1299 | pr_warning("%s called with NULL_NULL tag\n", | ||
1300 | __func__); | ||
1301 | if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) | ||
1302 | pr_warning("%s called with NULL tag\n", __func__); | ||
1303 | if ((current_tag.s.type == tag_type) | ||
1304 | && (current_tag.s.tag == tag)) | ||
1305 | pr_warning("%s called to perform a tag switch to the " | ||
1306 | "same tag\n", | ||
1307 | __func__); | ||
1308 | if (tag_type == CVMX_POW_TAG_TYPE_NULL) | ||
1309 | pr_warning("%s called to perform a tag switch to " | ||
1310 | "NULL. Use cvmx_pow_tag_sw_null() instead\n", | ||
1311 | __func__); | ||
1312 | } | ||
1313 | |||
1314 | /* | ||
1315 | * Note that WQE in DRAM is not updated here, as the POW does | ||
1316 | * not read from DRAM once the WQE is in flight. See hardware | ||
1317 | * manual for complete details. It is the application's | ||
1318 | * responsibility to keep track of the current tag value if | ||
1319 | * that is important. | ||
1320 | */ | ||
1321 | |||
1322 | tag_req.u64 = 0; | ||
1323 | tag_req.s.op = CVMX_POW_TAG_OP_SWTAG; | ||
1324 | tag_req.s.tag = tag; | ||
1325 | tag_req.s.type = tag_type; | ||
1326 | |||
1327 | ptr.u64 = 0; | ||
1328 | ptr.sio.mem_region = CVMX_IO_SEG; | ||
1329 | ptr.sio.is_io = 1; | ||
1330 | ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; | ||
1331 | |||
1332 | /* once this store arrives at POW, it will attempt the switch | ||
1333 | software must wait for the switch to complete separately */ | ||
1334 | cvmx_write_io(ptr.u64, tag_req.u64); | ||
1335 | } | ||
1336 | |||
1337 | /** | ||
1338 | * Starts a tag switch to the provided tag value and tag type. | ||
1339 | * Completion for the tag switch must be checked for separately. This | ||
1340 | * function does NOT update the work queue entry in dram to match tag | ||
1341 | * value and type, so the application must keep track of these if they | ||
1342 | * are important to the application. This tag switch command must not | ||
1343 | * be used for switches to NULL, as the tag switch pending bit will be | ||
1344 | * set by the switch request, but never cleared by the hardware. | ||
1345 | * | ||
1346 | * NOTE: This should not be used when switching from a NULL tag. Use | ||
1347 | * cvmx_pow_tag_sw_full() instead. | ||
1348 | * | ||
1349 | * This function waits for any previous tag switch to complete, and also | ||
1350 | * displays an error on tag switches to NULL. | ||
1351 | * | ||
1352 | * @tag: new tag value | ||
1353 | * @tag_type: new tag type (ordered or atomic) | ||
1354 | */ | ||
1355 | static inline void cvmx_pow_tag_sw(uint32_t tag, | ||
1356 | enum cvmx_pow_tag_type tag_type) | ||
1357 | { | ||
1358 | if (CVMX_ENABLE_POW_CHECKS) | ||
1359 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1360 | |||
1361 | /* | ||
1362 | * Note that WQE in DRAM is not updated here, as the POW does | ||
1363 | * not read from DRAM once the WQE is in flight. See hardware | ||
1364 | * manual for complete details. It is the application's | ||
1365 | * responsibility to keep track of the current tag value if | ||
1366 | * that is important. | ||
1367 | */ | ||
1368 | |||
1369 | /* | ||
1370 | * Ensure that there is not a pending tag switch, as a tag | ||
1371 | * switch cannot be started if a previous switch is still | ||
1372 | * pending. | ||
1373 | */ | ||
1374 | cvmx_pow_tag_sw_wait(); | ||
1375 | cvmx_pow_tag_sw_nocheck(tag, tag_type); | ||
1376 | } | ||
1377 | |||
1378 | /** | ||
1379 | * Starts a tag switch to the provided tag value and tag type. | ||
1380 | * Completion for the tag switch must be checked for separately. This | ||
1381 | * function does NOT update the work queue entry in dram to match tag | ||
1382 | * value and type, so the application must keep track of these if they | ||
1383 | * are important to the application. This tag switch command must not | ||
1384 | * be used for switches to NULL, as the tag switch pending bit will be | ||
1385 | * set by the switch request, but never cleared by the hardware. | ||
1386 | * | ||
1387 | * This function must be used for tag switches from NULL. | ||
1388 | * | ||
1389 | * This function does no checks, so the caller must ensure that any | ||
1390 | * previous tag switch has completed. | ||
1391 | * | ||
1392 | * @wqp: pointer to work queue entry to submit. This entry is | ||
1393 | * updated to match the other parameters | ||
1394 | * @tag: tag value to be assigned to work queue entry | ||
1395 | * @tag_type: type of tag | ||
1396 | * @group: group value for the work queue entry. | ||
1397 | */ | ||
1398 | static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, | ||
1399 | enum cvmx_pow_tag_type tag_type, | ||
1400 | uint64_t group) | ||
1401 | { | ||
1402 | cvmx_addr_t ptr; | ||
1403 | cvmx_pow_tag_req_t tag_req; | ||
1404 | |||
1405 | if (CVMX_ENABLE_POW_CHECKS) { | ||
1406 | cvmx_pow_tag_req_t current_tag; | ||
1407 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1408 | current_tag = cvmx_pow_get_current_tag(); | ||
1409 | if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) | ||
1410 | pr_warning("%s called with NULL_NULL tag\n", | ||
1411 | __func__); | ||
1412 | if ((current_tag.s.type == tag_type) | ||
1413 | && (current_tag.s.tag == tag)) | ||
1414 | pr_warning("%s called to perform a tag switch to " | ||
1415 | "the same tag\n", | ||
1416 | __func__); | ||
1417 | if (tag_type == CVMX_POW_TAG_TYPE_NULL) | ||
1418 | pr_warning("%s called to perform a tag switch to " | ||
1419 | "NULL. Use cvmx_pow_tag_sw_null() instead\n", | ||
1420 | __func__); | ||
1421 | if (wqp != cvmx_phys_to_ptr(0x80)) | ||
1422 | if (wqp != cvmx_pow_get_current_wqp()) | ||
1423 | pr_warning("%s passed WQE(%p) doesn't match " | ||
1424 | "the address in the POW(%p)\n", | ||
1425 | __func__, wqp, | ||
1426 | cvmx_pow_get_current_wqp()); | ||
1427 | } | ||
1428 | |||
1429 | /* | ||
1430 | * Note that WQE in DRAM is not updated here, as the POW does | ||
1431 | * not read from DRAM once the WQE is in flight. See hardware | ||
1432 | * manual for complete details. It is the application's | ||
1433 | * responsibility to keep track of the current tag value if | ||
1434 | * that is important. | ||
1435 | */ | ||
1436 | |||
1437 | tag_req.u64 = 0; | ||
1438 | tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL; | ||
1439 | tag_req.s.tag = tag; | ||
1440 | tag_req.s.type = tag_type; | ||
1441 | tag_req.s.grp = group; | ||
1442 | |||
1443 | ptr.u64 = 0; | ||
1444 | ptr.sio.mem_region = CVMX_IO_SEG; | ||
1445 | ptr.sio.is_io = 1; | ||
1446 | ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; | ||
1447 | ptr.sio.offset = CAST64(wqp); | ||
1448 | |||
1449 | /* | ||
1450 | * once this store arrives at POW, it will attempt the switch | ||
1451 | * software must wait for the switch to complete separately. | ||
1452 | */ | ||
1453 | cvmx_write_io(ptr.u64, tag_req.u64); | ||
1454 | } | ||
1455 | |||
1456 | /** | ||
1457 | * Starts a tag switch to the provided tag value and tag type. | ||
1458 | * Completion for the tag switch must be checked for separately. This | ||
1459 | * function does NOT update the work queue entry in dram to match tag | ||
1460 | * value and type, so the application must keep track of these if they | ||
1461 | * are important to the application. This tag switch command must not | ||
1462 | * be used for switches to NULL, as the tag switch pending bit will be | ||
1463 | * set by the switch request, but never cleared by the hardware. | ||
1464 | * | ||
1465 | * This function must be used for tag switches from NULL. | ||
1466 | * | ||
1467 | * This function waits for any pending tag switches to complete | ||
1468 | * before requesting the tag switch. | ||
1469 | * | ||
1470 | * @wqp: pointer to work queue entry to submit. This entry is updated | ||
1471 | * to match the other parameters | ||
1472 | * @tag: tag value to be assigned to work queue entry | ||
1473 | * @tag_type: type of tag | ||
1474 | * @group: group value for the work queue entry. | ||
1475 | */ | ||
1476 | static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag, | ||
1477 | enum cvmx_pow_tag_type tag_type, | ||
1478 | uint64_t group) | ||
1479 | { | ||
1480 | if (CVMX_ENABLE_POW_CHECKS) | ||
1481 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1482 | |||
1483 | /* | ||
1484 | * Ensure that there is not a pending tag switch, as a tag | ||
1485 | * switch cannot be started if a previous switch is still | ||
1486 | * pending. | ||
1487 | */ | ||
1488 | cvmx_pow_tag_sw_wait(); | ||
1489 | cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group); | ||
1490 | } | ||
1491 | |||
1492 | /** | ||
1493 | * Switch to a NULL tag, which ends any ordering or | ||
1494 | * synchronization provided by the POW for the current | ||
1495 | * work queue entry. This operation completes immediatly, | ||
1496 | * so completetion should not be waited for. | ||
1497 | * This function does NOT wait for previous tag switches to complete, | ||
1498 | * so the caller must ensure that any previous tag switches have completed. | ||
1499 | */ | ||
1500 | static inline void cvmx_pow_tag_sw_null_nocheck(void) | ||
1501 | { | ||
1502 | cvmx_addr_t ptr; | ||
1503 | cvmx_pow_tag_req_t tag_req; | ||
1504 | |||
1505 | if (CVMX_ENABLE_POW_CHECKS) { | ||
1506 | cvmx_pow_tag_req_t current_tag; | ||
1507 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1508 | current_tag = cvmx_pow_get_current_tag(); | ||
1509 | if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) | ||
1510 | pr_warning("%s called with NULL_NULL tag\n", | ||
1511 | __func__); | ||
1512 | if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) | ||
1513 | pr_warning("%s called when we already have a " | ||
1514 | "NULL tag\n", | ||
1515 | __func__); | ||
1516 | } | ||
1517 | |||
1518 | tag_req.u64 = 0; | ||
1519 | tag_req.s.op = CVMX_POW_TAG_OP_SWTAG; | ||
1520 | tag_req.s.type = CVMX_POW_TAG_TYPE_NULL; | ||
1521 | |||
1522 | ptr.u64 = 0; | ||
1523 | ptr.sio.mem_region = CVMX_IO_SEG; | ||
1524 | ptr.sio.is_io = 1; | ||
1525 | ptr.sio.did = CVMX_OCT_DID_TAG_TAG1; | ||
1526 | |||
1527 | cvmx_write_io(ptr.u64, tag_req.u64); | ||
1528 | |||
1529 | /* switch to NULL completes immediately */ | ||
1530 | } | ||
1531 | |||
1532 | /** | ||
1533 | * Switch to a NULL tag, which ends any ordering or | ||
1534 | * synchronization provided by the POW for the current | ||
1535 | * work queue entry. This operation completes immediatly, | ||
1536 | * so completetion should not be waited for. | ||
1537 | * This function waits for any pending tag switches to complete | ||
1538 | * before requesting the switch to NULL. | ||
1539 | */ | ||
1540 | static inline void cvmx_pow_tag_sw_null(void) | ||
1541 | { | ||
1542 | if (CVMX_ENABLE_POW_CHECKS) | ||
1543 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1544 | |||
1545 | /* | ||
1546 | * Ensure that there is not a pending tag switch, as a tag | ||
1547 | * switch cannot be started if a previous switch is still | ||
1548 | * pending. | ||
1549 | */ | ||
1550 | cvmx_pow_tag_sw_wait(); | ||
1551 | cvmx_pow_tag_sw_null_nocheck(); | ||
1552 | |||
1553 | /* switch to NULL completes immediately */ | ||
1554 | } | ||
1555 | |||
1556 | /** | ||
1557 | * Submits work to an input queue. This function updates the work | ||
1558 | * queue entry in DRAM to match the arguments given. Note that the | ||
1559 | * tag provided is for the work queue entry submitted, and is | ||
1560 | * unrelated to the tag that the core currently holds. | ||
1561 | * | ||
1562 | * @wqp: pointer to work queue entry to submit. This entry is | ||
1563 | * updated to match the other parameters | ||
1564 | * @tag: tag value to be assigned to work queue entry | ||
1565 | * @tag_type: type of tag | ||
1566 | * @qos: Input queue to add to. | ||
1567 | * @grp: group value for the work queue entry. | ||
1568 | */ | ||
1569 | static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, | ||
1570 | enum cvmx_pow_tag_type tag_type, | ||
1571 | uint64_t qos, uint64_t grp) | ||
1572 | { | ||
1573 | cvmx_addr_t ptr; | ||
1574 | cvmx_pow_tag_req_t tag_req; | ||
1575 | |||
1576 | wqp->qos = qos; | ||
1577 | wqp->tag = tag; | ||
1578 | wqp->tag_type = tag_type; | ||
1579 | wqp->grp = grp; | ||
1580 | |||
1581 | tag_req.u64 = 0; | ||
1582 | tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ; | ||
1583 | tag_req.s.type = tag_type; | ||
1584 | tag_req.s.tag = tag; | ||
1585 | tag_req.s.qos = qos; | ||
1586 | tag_req.s.grp = grp; | ||
1587 | |||
1588 | ptr.u64 = 0; | ||
1589 | ptr.sio.mem_region = CVMX_IO_SEG; | ||
1590 | ptr.sio.is_io = 1; | ||
1591 | ptr.sio.did = CVMX_OCT_DID_TAG_TAG1; | ||
1592 | ptr.sio.offset = cvmx_ptr_to_phys(wqp); | ||
1593 | |||
1594 | /* | ||
1595 | * SYNC write to memory before the work submit. This is | ||
1596 | * necessary as POW may read values from DRAM at this time. | ||
1597 | */ | ||
1598 | CVMX_SYNCWS; | ||
1599 | cvmx_write_io(ptr.u64, tag_req.u64); | ||
1600 | } | ||
1601 | |||
1602 | /** | ||
1603 | * This function sets the group mask for a core. The group mask | ||
1604 | * indicates which groups each core will accept work from. There are | ||
1605 | * 16 groups. | ||
1606 | * | ||
1607 | * @core_num: core to apply mask to | ||
1608 | * @mask: Group mask. There are 16 groups, so only bits 0-15 are valid, | ||
1609 | * representing groups 0-15. | ||
1610 | * Each 1 bit in the mask enables the core to accept work from | ||
1611 | * the corresponding group. | ||
1612 | */ | ||
1613 | static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask) | ||
1614 | { | ||
1615 | union cvmx_pow_pp_grp_mskx grp_msk; | ||
1616 | |||
1617 | grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); | ||
1618 | grp_msk.s.grp_msk = mask; | ||
1619 | cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); | ||
1620 | } | ||
1621 | |||
1622 | /** | ||
1623 | * This function sets POW static priorities for a core. Each input queue has | ||
1624 | * an associated priority value. | ||
1625 | * | ||
1626 | * @core_num: core to apply priorities to | ||
1627 | * @priority: Vector of 8 priorities, one per POW Input Queue (0-7). | ||
1628 | * Highest priority is 0 and lowest is 7. A priority value | ||
1629 | * of 0xF instructs POW to skip the Input Queue when | ||
1630 | * scheduling to this specific core. | ||
1631 | * NOTE: priorities should not have gaps in values, meaning | ||
1632 | * {0,1,1,1,1,1,1,1} is a valid configuration while | ||
1633 | * {0,2,2,2,2,2,2,2} is not. | ||
1634 | */ | ||
1635 | static inline void cvmx_pow_set_priority(uint64_t core_num, | ||
1636 | const uint8_t priority[]) | ||
1637 | { | ||
1638 | /* POW priorities are supported on CN5xxx and later */ | ||
1639 | if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { | ||
1640 | union cvmx_pow_pp_grp_mskx grp_msk; | ||
1641 | |||
1642 | grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); | ||
1643 | grp_msk.s.qos0_pri = priority[0]; | ||
1644 | grp_msk.s.qos1_pri = priority[1]; | ||
1645 | grp_msk.s.qos2_pri = priority[2]; | ||
1646 | grp_msk.s.qos3_pri = priority[3]; | ||
1647 | grp_msk.s.qos4_pri = priority[4]; | ||
1648 | grp_msk.s.qos5_pri = priority[5]; | ||
1649 | grp_msk.s.qos6_pri = priority[6]; | ||
1650 | grp_msk.s.qos7_pri = priority[7]; | ||
1651 | |||
1652 | /* Detect gaps between priorities and flag error */ | ||
1653 | { | ||
1654 | int i; | ||
1655 | uint32_t prio_mask = 0; | ||
1656 | |||
1657 | for (i = 0; i < 8; i++) | ||
1658 | if (priority[i] != 0xF) | ||
1659 | prio_mask |= 1 << priority[i]; | ||
1660 | |||
1661 | if (prio_mask ^ ((1 << cvmx_pop(prio_mask)) - 1)) { | ||
1662 | pr_err("POW static priorities should be " | ||
1663 | "contiguous (0x%llx)\n", | ||
1664 | (unsigned long long)prio_mask); | ||
1665 | return; | ||
1666 | } | ||
1667 | } | ||
1668 | |||
1669 | cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); | ||
1670 | } | ||
1671 | } | ||
1672 | |||
1673 | /** | ||
1674 | * Performs a tag switch and then an immediate deschedule. This completes | ||
1675 | * immediatly, so completion must not be waited for. This function does NOT | ||
1676 | * update the wqe in DRAM to match arguments. | ||
1677 | * | ||
1678 | * This function does NOT wait for any prior tag switches to complete, so the | ||
1679 | * calling code must do this. | ||
1680 | * | ||
1681 | * Note the following CAVEAT of the Octeon HW behavior when | ||
1682 | * re-scheduling DE-SCHEDULEd items whose (next) state is | ||
1683 | * ORDERED: | ||
1684 | * - If there are no switches pending at the time that the | ||
1685 | * HW executes the de-schedule, the HW will only re-schedule | ||
1686 | * the head of the FIFO associated with the given tag. This | ||
1687 | * means that in many respects, the HW treats this ORDERED | ||
1688 | * tag as an ATOMIC tag. Note that in the SWTAG_DESCH | ||
1689 | * case (to an ORDERED tag), the HW will do the switch | ||
1690 | * before the deschedule whenever it is possible to do | ||
1691 | * the switch immediately, so it may often look like | ||
1692 | * this case. | ||
1693 | * - If there is a pending switch to ORDERED at the time | ||
1694 | * the HW executes the de-schedule, the HW will perform | ||
1695 | * the switch at the time it re-schedules, and will be | ||
1696 | * able to reschedule any/all of the entries with the | ||
1697 | * same tag. | ||
1698 | * Due to this behavior, the RECOMMENDATION to software is | ||
1699 | * that they have a (next) state of ATOMIC when they | ||
1700 | * DE-SCHEDULE. If an ORDERED tag is what was really desired, | ||
1701 | * SW can choose to immediately switch to an ORDERED tag | ||
1702 | * after the work (that has an ATOMIC tag) is re-scheduled. | ||
1703 | * Note that since there are never any tag switches pending | ||
1704 | * when the HW re-schedules, this switch can be IMMEDIATE upon | ||
1705 | * the reception of the pointer during the re-schedule. | ||
1706 | * | ||
1707 | * @tag: New tag value | ||
1708 | * @tag_type: New tag type | ||
1709 | * @group: New group value | ||
1710 | * @no_sched: Control whether this work queue entry will be rescheduled. | ||
1711 | * - 1 : don't schedule this work | ||
1712 | * - 0 : allow this work to be scheduled. | ||
1713 | */ | ||
1714 | static inline void cvmx_pow_tag_sw_desched_nocheck( | ||
1715 | uint32_t tag, | ||
1716 | enum cvmx_pow_tag_type tag_type, | ||
1717 | uint64_t group, | ||
1718 | uint64_t no_sched) | ||
1719 | { | ||
1720 | cvmx_addr_t ptr; | ||
1721 | cvmx_pow_tag_req_t tag_req; | ||
1722 | |||
1723 | if (CVMX_ENABLE_POW_CHECKS) { | ||
1724 | cvmx_pow_tag_req_t current_tag; | ||
1725 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1726 | current_tag = cvmx_pow_get_current_tag(); | ||
1727 | if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) | ||
1728 | pr_warning("%s called with NULL_NULL tag\n", | ||
1729 | __func__); | ||
1730 | if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) | ||
1731 | pr_warning("%s called with NULL tag. Deschedule not " | ||
1732 | "allowed from NULL state\n", | ||
1733 | __func__); | ||
1734 | if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC) | ||
1735 | && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC)) | ||
1736 | pr_warning("%s called where neither the before or " | ||
1737 | "after tag is ATOMIC\n", | ||
1738 | __func__); | ||
1739 | } | ||
1740 | |||
1741 | tag_req.u64 = 0; | ||
1742 | tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH; | ||
1743 | tag_req.s.tag = tag; | ||
1744 | tag_req.s.type = tag_type; | ||
1745 | tag_req.s.grp = group; | ||
1746 | tag_req.s.no_sched = no_sched; | ||
1747 | |||
1748 | ptr.u64 = 0; | ||
1749 | ptr.sio.mem_region = CVMX_IO_SEG; | ||
1750 | ptr.sio.is_io = 1; | ||
1751 | ptr.sio.did = CVMX_OCT_DID_TAG_TAG3; | ||
1752 | /* | ||
1753 | * since TAG3 is used, this store will clear the local pending | ||
1754 | * switch bit. | ||
1755 | */ | ||
1756 | cvmx_write_io(ptr.u64, tag_req.u64); | ||
1757 | } | ||
1758 | |||
1759 | /** | ||
1760 | * Performs a tag switch and then an immediate deschedule. This completes | ||
1761 | * immediatly, so completion must not be waited for. This function does NOT | ||
1762 | * update the wqe in DRAM to match arguments. | ||
1763 | * | ||
1764 | * This function waits for any prior tag switches to complete, so the | ||
1765 | * calling code may call this function with a pending tag switch. | ||
1766 | * | ||
1767 | * Note the following CAVEAT of the Octeon HW behavior when | ||
1768 | * re-scheduling DE-SCHEDULEd items whose (next) state is | ||
1769 | * ORDERED: | ||
1770 | * - If there are no switches pending at the time that the | ||
1771 | * HW executes the de-schedule, the HW will only re-schedule | ||
1772 | * the head of the FIFO associated with the given tag. This | ||
1773 | * means that in many respects, the HW treats this ORDERED | ||
1774 | * tag as an ATOMIC tag. Note that in the SWTAG_DESCH | ||
1775 | * case (to an ORDERED tag), the HW will do the switch | ||
1776 | * before the deschedule whenever it is possible to do | ||
1777 | * the switch immediately, so it may often look like | ||
1778 | * this case. | ||
1779 | * - If there is a pending switch to ORDERED at the time | ||
1780 | * the HW executes the de-schedule, the HW will perform | ||
1781 | * the switch at the time it re-schedules, and will be | ||
1782 | * able to reschedule any/all of the entries with the | ||
1783 | * same tag. | ||
1784 | * Due to this behavior, the RECOMMENDATION to software is | ||
1785 | * that they have a (next) state of ATOMIC when they | ||
1786 | * DE-SCHEDULE. If an ORDERED tag is what was really desired, | ||
1787 | * SW can choose to immediately switch to an ORDERED tag | ||
1788 | * after the work (that has an ATOMIC tag) is re-scheduled. | ||
1789 | * Note that since there are never any tag switches pending | ||
1790 | * when the HW re-schedules, this switch can be IMMEDIATE upon | ||
1791 | * the reception of the pointer during the re-schedule. | ||
1792 | * | ||
1793 | * @tag: New tag value | ||
1794 | * @tag_type: New tag type | ||
1795 | * @group: New group value | ||
1796 | * @no_sched: Control whether this work queue entry will be rescheduled. | ||
1797 | * - 1 : don't schedule this work | ||
1798 | * - 0 : allow this work to be scheduled. | ||
1799 | */ | ||
1800 | static inline void cvmx_pow_tag_sw_desched(uint32_t tag, | ||
1801 | enum cvmx_pow_tag_type tag_type, | ||
1802 | uint64_t group, uint64_t no_sched) | ||
1803 | { | ||
1804 | if (CVMX_ENABLE_POW_CHECKS) | ||
1805 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1806 | |||
1807 | /* Need to make sure any writes to the work queue entry are complete */ | ||
1808 | CVMX_SYNCWS; | ||
1809 | /* | ||
1810 | * Ensure that there is not a pending tag switch, as a tag | ||
1811 | * switch cannot be started if a previous switch is still | ||
1812 | * pending. | ||
1813 | */ | ||
1814 | cvmx_pow_tag_sw_wait(); | ||
1815 | cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched); | ||
1816 | } | ||
1817 | |||
1818 | /** | ||
1819 | * Descchedules the current work queue entry. | ||
1820 | * | ||
1821 | * @no_sched: no schedule flag value to be set on the work queue | ||
1822 | * entry. If this is set the entry will not be | ||
1823 | * rescheduled. | ||
1824 | */ | ||
1825 | static inline void cvmx_pow_desched(uint64_t no_sched) | ||
1826 | { | ||
1827 | cvmx_addr_t ptr; | ||
1828 | cvmx_pow_tag_req_t tag_req; | ||
1829 | |||
1830 | if (CVMX_ENABLE_POW_CHECKS) { | ||
1831 | cvmx_pow_tag_req_t current_tag; | ||
1832 | __cvmx_pow_warn_if_pending_switch(__func__); | ||
1833 | current_tag = cvmx_pow_get_current_tag(); | ||
1834 | if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) | ||
1835 | pr_warning("%s called with NULL_NULL tag\n", | ||
1836 | __func__); | ||
1837 | if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) | ||
1838 | pr_warning("%s called with NULL tag. Deschedule not " | ||
1839 | "expected from NULL state\n", | ||
1840 | __func__); | ||
1841 | } | ||
1842 | |||
1843 | /* Need to make sure any writes to the work queue entry are complete */ | ||
1844 | CVMX_SYNCWS; | ||
1845 | |||
1846 | tag_req.u64 = 0; | ||
1847 | tag_req.s.op = CVMX_POW_TAG_OP_DESCH; | ||
1848 | tag_req.s.no_sched = no_sched; | ||
1849 | |||
1850 | ptr.u64 = 0; | ||
1851 | ptr.sio.mem_region = CVMX_IO_SEG; | ||
1852 | ptr.sio.is_io = 1; | ||
1853 | ptr.sio.did = CVMX_OCT_DID_TAG_TAG3; | ||
1854 | /* | ||
1855 | * since TAG3 is used, this store will clear the local pending | ||
1856 | * switch bit. | ||
1857 | */ | ||
1858 | cvmx_write_io(ptr.u64, tag_req.u64); | ||
1859 | } | ||
1860 | |||
1861 | /**************************************************** | ||
1862 | * Define usage of bits within the 32 bit tag values. | ||
1863 | *****************************************************/ | ||
1864 | |||
1865 | /* | ||
1866 | * Number of bits of the tag used by software. The SW bits are always | ||
1867 | * a contiguous block of the high starting at bit 31. The hardware | ||
1868 | * bits are always the low bits. By default, the top 8 bits of the | ||
1869 | * tag are reserved for software, and the low 24 are set by the IPD | ||
1870 | * unit. | ||
1871 | */ | ||
1872 | #define CVMX_TAG_SW_BITS (8) | ||
1873 | #define CVMX_TAG_SW_SHIFT (32 - CVMX_TAG_SW_BITS) | ||
1874 | |||
1875 | /* Below is the list of values for the top 8 bits of the tag. */ | ||
1876 | /* | ||
1877 | * Tag values with top byte of this value are reserved for internal | ||
1878 | * executive uses. | ||
1879 | */ | ||
1880 | #define CVMX_TAG_SW_BITS_INTERNAL 0x1 | ||
1881 | /* The executive divides the remaining 24 bits as follows: | ||
1882 | * - the upper 8 bits (bits 23 - 16 of the tag) define a subgroup | ||
1883 | * | ||
1884 | * - the lower 16 bits (bits 15 - 0 of the tag) define are the value | ||
1885 | * with the subgroup | ||
1886 | * | ||
1887 | * Note that this section describes the format of tags generated by | ||
1888 | * software - refer to the hardware documentation for a description of | ||
1889 | * the tags values generated by the packet input hardware. Subgroups | ||
1890 | * are defined here. | ||
1891 | */ | ||
1892 | /* Mask for the value portion of the tag */ | ||
1893 | #define CVMX_TAG_SUBGROUP_MASK 0xFFFF | ||
1894 | #define CVMX_TAG_SUBGROUP_SHIFT 16 | ||
1895 | #define CVMX_TAG_SUBGROUP_PKO 0x1 | ||
1896 | |||
1897 | /* End of executive tag subgroup definitions */ | ||
1898 | |||
1899 | /* | ||
1900 | * The remaining values software bit values 0x2 - 0xff are available | ||
1901 | * for application use. | ||
1902 | */ | ||
1903 | |||
1904 | /** | ||
1905 | * This function creates a 32 bit tag value from the two values provided. | ||
1906 | * | ||
1907 | * @sw_bits: The upper bits (number depends on configuration) are set | ||
1908 | * to this value. The remainder of bits are set by the | ||
1909 | * hw_bits parameter. | ||
1910 | * | ||
1911 | * @hw_bits: The lower bits (number depends on configuration) are set | ||
1912 | * to this value. The remainder of bits are set by the | ||
1913 | * sw_bits parameter. | ||
1914 | * | ||
1915 | * Returns 32 bit value of the combined hw and sw bits. | ||
1916 | */ | ||
1917 | static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits) | ||
1918 | { | ||
1919 | return ((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) << | ||
1920 | CVMX_TAG_SW_SHIFT) | | ||
1921 | (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS)); | ||
1922 | } | ||
1923 | |||
1924 | /** | ||
1925 | * Extracts the bits allocated for software use from the tag | ||
1926 | * | ||
1927 | * @tag: 32 bit tag value | ||
1928 | * | ||
1929 | * Returns N bit software tag value, where N is configurable with the | ||
1930 | * CVMX_TAG_SW_BITS define | ||
1931 | */ | ||
1932 | static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag) | ||
1933 | { | ||
1934 | return (tag >> (32 - CVMX_TAG_SW_BITS)) & | ||
1935 | cvmx_build_mask(CVMX_TAG_SW_BITS); | ||
1936 | } | ||
1937 | |||
1938 | /** | ||
1939 | * | ||
1940 | * Extracts the bits allocated for hardware use from the tag | ||
1941 | * | ||
1942 | * @tag: 32 bit tag value | ||
1943 | * | ||
1944 | * Returns (32 - N) bit software tag value, where N is configurable | ||
1945 | * with the CVMX_TAG_SW_BITS define | ||
1946 | */ | ||
1947 | static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag) | ||
1948 | { | ||
1949 | return tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS); | ||
1950 | } | ||
1951 | |||
1952 | /** | ||
1953 | * Store the current POW internal state into the supplied | ||
1954 | * buffer. It is recommended that you pass a buffer of at least | ||
1955 | * 128KB. The format of the capture may change based on SDK | ||
1956 | * version and Octeon chip. | ||
1957 | * | ||
1958 | * @buffer: Buffer to store capture into | ||
1959 | * @buffer_size: | ||
1960 | * The size of the supplied buffer | ||
1961 | * | ||
1962 | * Returns Zero on sucess, negative on failure | ||
1963 | */ | ||
1964 | extern int cvmx_pow_capture(void *buffer, int buffer_size); | ||
1965 | |||
1966 | /** | ||
1967 | * Dump a POW capture to the console in a human readable format. | ||
1968 | * | ||
1969 | * @buffer: POW capture from cvmx_pow_capture() | ||
1970 | * @buffer_size: | ||
1971 | * Size of the buffer | ||
1972 | */ | ||
1973 | extern void cvmx_pow_display(void *buffer, int buffer_size); | ||
1974 | |||
1975 | /** | ||
1976 | * Return the number of POW entries supported by this chip | ||
1977 | * | ||
1978 | * Returns Number of POW entries | ||
1979 | */ | ||
1980 | extern int cvmx_pow_get_num_entries(void); | ||
1981 | |||
1982 | #endif /* __CVMX_POW_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-scratch.h b/drivers/staging/octeon/cvmx-scratch.h new file mode 100644 index 000000000000..96b70cfd6245 --- /dev/null +++ b/drivers/staging/octeon/cvmx-scratch.h | |||
@@ -0,0 +1,139 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * | ||
30 | * This file provides support for the processor local scratch memory. | ||
31 | * Scratch memory is byte addressable - all addresses are byte addresses. | ||
32 | * | ||
33 | */ | ||
34 | |||
35 | #ifndef __CVMX_SCRATCH_H__ | ||
36 | #define __CVMX_SCRATCH_H__ | ||
37 | |||
38 | /* | ||
39 | * Note: This define must be a long, not a long long in order to | ||
40 | * compile without warnings for both 32bit and 64bit. | ||
41 | */ | ||
42 | #define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */ | ||
43 | |||
44 | /** | ||
45 | * Reads an 8 bit value from the processor local scratchpad memory. | ||
46 | * | ||
47 | * @address: byte address to read from | ||
48 | * | ||
49 | * Returns value read | ||
50 | */ | ||
51 | static inline uint8_t cvmx_scratch_read8(uint64_t address) | ||
52 | { | ||
53 | return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address); | ||
54 | } | ||
55 | |||
56 | /** | ||
57 | * Reads a 16 bit value from the processor local scratchpad memory. | ||
58 | * | ||
59 | * @address: byte address to read from | ||
60 | * | ||
61 | * Returns value read | ||
62 | */ | ||
63 | static inline uint16_t cvmx_scratch_read16(uint64_t address) | ||
64 | { | ||
65 | return *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address); | ||
66 | } | ||
67 | |||
68 | /** | ||
69 | * Reads a 32 bit value from the processor local scratchpad memory. | ||
70 | * | ||
71 | * @address: byte address to read from | ||
72 | * | ||
73 | * Returns value read | ||
74 | */ | ||
75 | static inline uint32_t cvmx_scratch_read32(uint64_t address) | ||
76 | { | ||
77 | return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address); | ||
78 | } | ||
79 | |||
80 | /** | ||
81 | * Reads a 64 bit value from the processor local scratchpad memory. | ||
82 | * | ||
83 | * @address: byte address to read from | ||
84 | * | ||
85 | * Returns value read | ||
86 | */ | ||
87 | static inline uint64_t cvmx_scratch_read64(uint64_t address) | ||
88 | { | ||
89 | return *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address); | ||
90 | } | ||
91 | |||
92 | /** | ||
93 | * Writes an 8 bit value to the processor local scratchpad memory. | ||
94 | * | ||
95 | * @address: byte address to write to | ||
96 | * @value: value to write | ||
97 | */ | ||
98 | static inline void cvmx_scratch_write8(uint64_t address, uint64_t value) | ||
99 | { | ||
100 | *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) = | ||
101 | (uint8_t) value; | ||
102 | } | ||
103 | |||
104 | /** | ||
105 | * Writes a 32 bit value to the processor local scratchpad memory. | ||
106 | * | ||
107 | * @address: byte address to write to | ||
108 | * @value: value to write | ||
109 | */ | ||
110 | static inline void cvmx_scratch_write16(uint64_t address, uint64_t value) | ||
111 | { | ||
112 | *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address) = | ||
113 | (uint16_t) value; | ||
114 | } | ||
115 | |||
116 | /** | ||
117 | * Writes a 16 bit value to the processor local scratchpad memory. | ||
118 | * | ||
119 | * @address: byte address to write to | ||
120 | * @value: value to write | ||
121 | */ | ||
122 | static inline void cvmx_scratch_write32(uint64_t address, uint64_t value) | ||
123 | { | ||
124 | *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) = | ||
125 | (uint32_t) value; | ||
126 | } | ||
127 | |||
128 | /** | ||
129 | * Writes a 64 bit value to the processor local scratchpad memory. | ||
130 | * | ||
131 | * @address: byte address to write to | ||
132 | * @value: value to write | ||
133 | */ | ||
134 | static inline void cvmx_scratch_write64(uint64_t address, uint64_t value) | ||
135 | { | ||
136 | *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address) = value; | ||
137 | } | ||
138 | |||
139 | #endif /* __CVMX_SCRATCH_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-smix-defs.h b/drivers/staging/octeon/cvmx-smix-defs.h new file mode 100644 index 000000000000..9ae45fcbe3e3 --- /dev/null +++ b/drivers/staging/octeon/cvmx-smix-defs.h | |||
@@ -0,0 +1,178 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_SMIX_DEFS_H__ | ||
29 | #define __CVMX_SMIX_DEFS_H__ | ||
30 | |||
31 | #define CVMX_SMIX_CLK(offset) \ | ||
32 | CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256)) | ||
33 | #define CVMX_SMIX_CMD(offset) \ | ||
34 | CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256)) | ||
35 | #define CVMX_SMIX_EN(offset) \ | ||
36 | CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256)) | ||
37 | #define CVMX_SMIX_RD_DAT(offset) \ | ||
38 | CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256)) | ||
39 | #define CVMX_SMIX_WR_DAT(offset) \ | ||
40 | CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256)) | ||
41 | |||
42 | union cvmx_smix_clk { | ||
43 | uint64_t u64; | ||
44 | struct cvmx_smix_clk_s { | ||
45 | uint64_t reserved_25_63:39; | ||
46 | uint64_t mode:1; | ||
47 | uint64_t reserved_21_23:3; | ||
48 | uint64_t sample_hi:5; | ||
49 | uint64_t sample_mode:1; | ||
50 | uint64_t reserved_14_14:1; | ||
51 | uint64_t clk_idle:1; | ||
52 | uint64_t preamble:1; | ||
53 | uint64_t sample:4; | ||
54 | uint64_t phase:8; | ||
55 | } s; | ||
56 | struct cvmx_smix_clk_cn30xx { | ||
57 | uint64_t reserved_21_63:43; | ||
58 | uint64_t sample_hi:5; | ||
59 | uint64_t reserved_14_15:2; | ||
60 | uint64_t clk_idle:1; | ||
61 | uint64_t preamble:1; | ||
62 | uint64_t sample:4; | ||
63 | uint64_t phase:8; | ||
64 | } cn30xx; | ||
65 | struct cvmx_smix_clk_cn30xx cn31xx; | ||
66 | struct cvmx_smix_clk_cn30xx cn38xx; | ||
67 | struct cvmx_smix_clk_cn30xx cn38xxp2; | ||
68 | struct cvmx_smix_clk_cn50xx { | ||
69 | uint64_t reserved_25_63:39; | ||
70 | uint64_t mode:1; | ||
71 | uint64_t reserved_21_23:3; | ||
72 | uint64_t sample_hi:5; | ||
73 | uint64_t reserved_14_15:2; | ||
74 | uint64_t clk_idle:1; | ||
75 | uint64_t preamble:1; | ||
76 | uint64_t sample:4; | ||
77 | uint64_t phase:8; | ||
78 | } cn50xx; | ||
79 | struct cvmx_smix_clk_s cn52xx; | ||
80 | struct cvmx_smix_clk_cn50xx cn52xxp1; | ||
81 | struct cvmx_smix_clk_s cn56xx; | ||
82 | struct cvmx_smix_clk_cn50xx cn56xxp1; | ||
83 | struct cvmx_smix_clk_cn30xx cn58xx; | ||
84 | struct cvmx_smix_clk_cn30xx cn58xxp1; | ||
85 | }; | ||
86 | |||
87 | union cvmx_smix_cmd { | ||
88 | uint64_t u64; | ||
89 | struct cvmx_smix_cmd_s { | ||
90 | uint64_t reserved_18_63:46; | ||
91 | uint64_t phy_op:2; | ||
92 | uint64_t reserved_13_15:3; | ||
93 | uint64_t phy_adr:5; | ||
94 | uint64_t reserved_5_7:3; | ||
95 | uint64_t reg_adr:5; | ||
96 | } s; | ||
97 | struct cvmx_smix_cmd_cn30xx { | ||
98 | uint64_t reserved_17_63:47; | ||
99 | uint64_t phy_op:1; | ||
100 | uint64_t reserved_13_15:3; | ||
101 | uint64_t phy_adr:5; | ||
102 | uint64_t reserved_5_7:3; | ||
103 | uint64_t reg_adr:5; | ||
104 | } cn30xx; | ||
105 | struct cvmx_smix_cmd_cn30xx cn31xx; | ||
106 | struct cvmx_smix_cmd_cn30xx cn38xx; | ||
107 | struct cvmx_smix_cmd_cn30xx cn38xxp2; | ||
108 | struct cvmx_smix_cmd_s cn50xx; | ||
109 | struct cvmx_smix_cmd_s cn52xx; | ||
110 | struct cvmx_smix_cmd_s cn52xxp1; | ||
111 | struct cvmx_smix_cmd_s cn56xx; | ||
112 | struct cvmx_smix_cmd_s cn56xxp1; | ||
113 | struct cvmx_smix_cmd_cn30xx cn58xx; | ||
114 | struct cvmx_smix_cmd_cn30xx cn58xxp1; | ||
115 | }; | ||
116 | |||
117 | union cvmx_smix_en { | ||
118 | uint64_t u64; | ||
119 | struct cvmx_smix_en_s { | ||
120 | uint64_t reserved_1_63:63; | ||
121 | uint64_t en:1; | ||
122 | } s; | ||
123 | struct cvmx_smix_en_s cn30xx; | ||
124 | struct cvmx_smix_en_s cn31xx; | ||
125 | struct cvmx_smix_en_s cn38xx; | ||
126 | struct cvmx_smix_en_s cn38xxp2; | ||
127 | struct cvmx_smix_en_s cn50xx; | ||
128 | struct cvmx_smix_en_s cn52xx; | ||
129 | struct cvmx_smix_en_s cn52xxp1; | ||
130 | struct cvmx_smix_en_s cn56xx; | ||
131 | struct cvmx_smix_en_s cn56xxp1; | ||
132 | struct cvmx_smix_en_s cn58xx; | ||
133 | struct cvmx_smix_en_s cn58xxp1; | ||
134 | }; | ||
135 | |||
136 | union cvmx_smix_rd_dat { | ||
137 | uint64_t u64; | ||
138 | struct cvmx_smix_rd_dat_s { | ||
139 | uint64_t reserved_18_63:46; | ||
140 | uint64_t pending:1; | ||
141 | uint64_t val:1; | ||
142 | uint64_t dat:16; | ||
143 | } s; | ||
144 | struct cvmx_smix_rd_dat_s cn30xx; | ||
145 | struct cvmx_smix_rd_dat_s cn31xx; | ||
146 | struct cvmx_smix_rd_dat_s cn38xx; | ||
147 | struct cvmx_smix_rd_dat_s cn38xxp2; | ||
148 | struct cvmx_smix_rd_dat_s cn50xx; | ||
149 | struct cvmx_smix_rd_dat_s cn52xx; | ||
150 | struct cvmx_smix_rd_dat_s cn52xxp1; | ||
151 | struct cvmx_smix_rd_dat_s cn56xx; | ||
152 | struct cvmx_smix_rd_dat_s cn56xxp1; | ||
153 | struct cvmx_smix_rd_dat_s cn58xx; | ||
154 | struct cvmx_smix_rd_dat_s cn58xxp1; | ||
155 | }; | ||
156 | |||
157 | union cvmx_smix_wr_dat { | ||
158 | uint64_t u64; | ||
159 | struct cvmx_smix_wr_dat_s { | ||
160 | uint64_t reserved_18_63:46; | ||
161 | uint64_t pending:1; | ||
162 | uint64_t val:1; | ||
163 | uint64_t dat:16; | ||
164 | } s; | ||
165 | struct cvmx_smix_wr_dat_s cn30xx; | ||
166 | struct cvmx_smix_wr_dat_s cn31xx; | ||
167 | struct cvmx_smix_wr_dat_s cn38xx; | ||
168 | struct cvmx_smix_wr_dat_s cn38xxp2; | ||
169 | struct cvmx_smix_wr_dat_s cn50xx; | ||
170 | struct cvmx_smix_wr_dat_s cn52xx; | ||
171 | struct cvmx_smix_wr_dat_s cn52xxp1; | ||
172 | struct cvmx_smix_wr_dat_s cn56xx; | ||
173 | struct cvmx_smix_wr_dat_s cn56xxp1; | ||
174 | struct cvmx_smix_wr_dat_s cn58xx; | ||
175 | struct cvmx_smix_wr_dat_s cn58xxp1; | ||
176 | }; | ||
177 | |||
178 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-spi.c b/drivers/staging/octeon/cvmx-spi.c new file mode 100644 index 000000000000..82794d920cec --- /dev/null +++ b/drivers/staging/octeon/cvmx-spi.c | |||
@@ -0,0 +1,667 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * | ||
30 | * Support library for the SPI | ||
31 | */ | ||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "cvmx-config.h" | ||
35 | |||
36 | #include "cvmx-pko.h" | ||
37 | #include "cvmx-spi.h" | ||
38 | |||
39 | #include "cvmx-spxx-defs.h" | ||
40 | #include "cvmx-stxx-defs.h" | ||
41 | #include "cvmx-srxx-defs.h" | ||
42 | |||
43 | #define INVOKE_CB(function_p, args...) \ | ||
44 | do { \ | ||
45 | if (function_p) { \ | ||
46 | res = function_p(args); \ | ||
47 | if (res) \ | ||
48 | return res; \ | ||
49 | } \ | ||
50 | } while (0) | ||
51 | |||
52 | #if CVMX_ENABLE_DEBUG_PRINTS | ||
53 | static const char *modes[] = | ||
54 | { "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" }; | ||
55 | #endif | ||
56 | |||
57 | /* Default callbacks, can be overridden | ||
58 | * using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks | ||
59 | */ | ||
60 | static cvmx_spi_callbacks_t cvmx_spi_callbacks = { | ||
61 | .reset_cb = cvmx_spi_reset_cb, | ||
62 | .calendar_setup_cb = cvmx_spi_calendar_setup_cb, | ||
63 | .clock_detect_cb = cvmx_spi_clock_detect_cb, | ||
64 | .training_cb = cvmx_spi_training_cb, | ||
65 | .calendar_sync_cb = cvmx_spi_calendar_sync_cb, | ||
66 | .interface_up_cb = cvmx_spi_interface_up_cb | ||
67 | }; | ||
68 | |||
69 | /** | ||
70 | * Get current SPI4 initialization callbacks | ||
71 | * | ||
72 | * @callbacks: Pointer to the callbacks structure.to fill | ||
73 | * | ||
74 | * Returns Pointer to cvmx_spi_callbacks_t structure. | ||
75 | */ | ||
76 | void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks) | ||
77 | { | ||
78 | memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks)); | ||
79 | } | ||
80 | |||
81 | /** | ||
82 | * Set new SPI4 initialization callbacks | ||
83 | * | ||
84 | * @new_callbacks: Pointer to an updated callbacks structure. | ||
85 | */ | ||
86 | void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks) | ||
87 | { | ||
88 | memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks)); | ||
89 | } | ||
90 | |||
91 | /** | ||
92 | * Initialize and start the SPI interface. | ||
93 | * | ||
94 | * @interface: The identifier of the packet interface to configure and | ||
95 | * use as a SPI interface. | ||
96 | * @mode: The operating mode for the SPI interface. The interface | ||
97 | * can operate as a full duplex (both Tx and Rx data paths | ||
98 | * active) or as a halfplex (either the Tx data path is | ||
99 | * active or the Rx data path is active, but not both). | ||
100 | * @timeout: Timeout to wait for clock synchronization in seconds | ||
101 | * @num_ports: Number of SPI ports to configure | ||
102 | * | ||
103 | * Returns Zero on success, negative of failure. | ||
104 | */ | ||
105 | int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout, | ||
106 | int num_ports) | ||
107 | { | ||
108 | int res = -1; | ||
109 | |||
110 | if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) | ||
111 | return res; | ||
112 | |||
113 | /* Callback to perform SPI4 reset */ | ||
114 | INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); | ||
115 | |||
116 | /* Callback to perform calendar setup */ | ||
117 | INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode, | ||
118 | num_ports); | ||
119 | |||
120 | /* Callback to perform clock detection */ | ||
121 | INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); | ||
122 | |||
123 | /* Callback to perform SPI4 link training */ | ||
124 | INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); | ||
125 | |||
126 | /* Callback to perform calendar sync */ | ||
127 | INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, | ||
128 | timeout); | ||
129 | |||
130 | /* Callback to handle interface coming up */ | ||
131 | INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); | ||
132 | |||
133 | return res; | ||
134 | } | ||
135 | |||
136 | /** | ||
137 | * This routine restarts the SPI interface after it has lost synchronization | ||
138 | * with its correspondent system. | ||
139 | * | ||
140 | * @interface: The identifier of the packet interface to configure and | ||
141 | * use as a SPI interface. | ||
142 | * @mode: The operating mode for the SPI interface. The interface | ||
143 | * can operate as a full duplex (both Tx and Rx data paths | ||
144 | * active) or as a halfplex (either the Tx data path is | ||
145 | * active or the Rx data path is active, but not both). | ||
146 | * @timeout: Timeout to wait for clock synchronization in seconds | ||
147 | * | ||
148 | * Returns Zero on success, negative of failure. | ||
149 | */ | ||
150 | int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout) | ||
151 | { | ||
152 | int res = -1; | ||
153 | |||
154 | if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) | ||
155 | return res; | ||
156 | |||
157 | cvmx_dprintf("SPI%d: Restart %s\n", interface, modes[mode]); | ||
158 | |||
159 | /* Callback to perform SPI4 reset */ | ||
160 | INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); | ||
161 | |||
162 | /* NOTE: Calendar setup is not performed during restart */ | ||
163 | /* Refer to cvmx_spi_start_interface() for the full sequence */ | ||
164 | |||
165 | /* Callback to perform clock detection */ | ||
166 | INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); | ||
167 | |||
168 | /* Callback to perform SPI4 link training */ | ||
169 | INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); | ||
170 | |||
171 | /* Callback to perform calendar sync */ | ||
172 | INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, | ||
173 | timeout); | ||
174 | |||
175 | /* Callback to handle interface coming up */ | ||
176 | INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); | ||
177 | |||
178 | return res; | ||
179 | } | ||
180 | |||
181 | /** | ||
182 | * Callback to perform SPI4 reset | ||
183 | * | ||
184 | * @interface: The identifier of the packet interface to configure and | ||
185 | * use as a SPI interface. | ||
186 | * @mode: The operating mode for the SPI interface. The interface | ||
187 | * can operate as a full duplex (both Tx and Rx data paths | ||
188 | * active) or as a halfplex (either the Tx data path is | ||
189 | * active or the Rx data path is active, but not both). | ||
190 | * | ||
191 | * Returns Zero on success, non-zero error code on failure (will cause | ||
192 | * SPI initialization to abort) | ||
193 | */ | ||
194 | int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) | ||
195 | { | ||
196 | union cvmx_spxx_dbg_deskew_ctl spxx_dbg_deskew_ctl; | ||
197 | union cvmx_spxx_clk_ctl spxx_clk_ctl; | ||
198 | union cvmx_spxx_bist_stat spxx_bist_stat; | ||
199 | union cvmx_spxx_int_msk spxx_int_msk; | ||
200 | union cvmx_stxx_int_msk stxx_int_msk; | ||
201 | union cvmx_spxx_trn4_ctl spxx_trn4_ctl; | ||
202 | int index; | ||
203 | uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; | ||
204 | |||
205 | /* Disable SPI error events while we run BIST */ | ||
206 | spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); | ||
207 | cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); | ||
208 | stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface)); | ||
209 | cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); | ||
210 | |||
211 | /* Run BIST in the SPI interface */ | ||
212 | cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); | ||
213 | cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); | ||
214 | spxx_clk_ctl.u64 = 0; | ||
215 | spxx_clk_ctl.s.runbist = 1; | ||
216 | cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); | ||
217 | cvmx_wait(10 * MS); | ||
218 | spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface)); | ||
219 | if (spxx_bist_stat.s.stat0) | ||
220 | cvmx_dprintf | ||
221 | ("ERROR SPI%d: BIST failed on receive datapath FIFO\n", | ||
222 | interface); | ||
223 | if (spxx_bist_stat.s.stat1) | ||
224 | cvmx_dprintf("ERROR SPI%d: BIST failed on RX calendar table\n", | ||
225 | interface); | ||
226 | if (spxx_bist_stat.s.stat2) | ||
227 | cvmx_dprintf("ERROR SPI%d: BIST failed on TX calendar table\n", | ||
228 | interface); | ||
229 | |||
230 | /* Clear the calendar table after BIST to fix parity errors */ | ||
231 | for (index = 0; index < 32; index++) { | ||
232 | union cvmx_srxx_spi4_calx srxx_spi4_calx; | ||
233 | union cvmx_stxx_spi4_calx stxx_spi4_calx; | ||
234 | |||
235 | srxx_spi4_calx.u64 = 0; | ||
236 | srxx_spi4_calx.s.oddpar = 1; | ||
237 | cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), | ||
238 | srxx_spi4_calx.u64); | ||
239 | |||
240 | stxx_spi4_calx.u64 = 0; | ||
241 | stxx_spi4_calx.s.oddpar = 1; | ||
242 | cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), | ||
243 | stxx_spi4_calx.u64); | ||
244 | } | ||
245 | |||
246 | /* Re enable reporting of error interrupts */ | ||
247 | cvmx_write_csr(CVMX_SPXX_INT_REG(interface), | ||
248 | cvmx_read_csr(CVMX_SPXX_INT_REG(interface))); | ||
249 | cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); | ||
250 | cvmx_write_csr(CVMX_STXX_INT_REG(interface), | ||
251 | cvmx_read_csr(CVMX_STXX_INT_REG(interface))); | ||
252 | cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64); | ||
253 | |||
254 | /* Setup the CLKDLY right in the middle */ | ||
255 | spxx_clk_ctl.u64 = 0; | ||
256 | spxx_clk_ctl.s.seetrn = 0; | ||
257 | spxx_clk_ctl.s.clkdly = 0x10; | ||
258 | spxx_clk_ctl.s.runbist = 0; | ||
259 | spxx_clk_ctl.s.statdrv = 0; | ||
260 | /* This should always be on the opposite edge as statdrv */ | ||
261 | spxx_clk_ctl.s.statrcv = 1; | ||
262 | spxx_clk_ctl.s.sndtrn = 0; | ||
263 | spxx_clk_ctl.s.drptrn = 0; | ||
264 | spxx_clk_ctl.s.rcvtrn = 0; | ||
265 | spxx_clk_ctl.s.srxdlck = 0; | ||
266 | cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); | ||
267 | cvmx_wait(100 * MS); | ||
268 | |||
269 | /* Reset SRX0 DLL */ | ||
270 | spxx_clk_ctl.s.srxdlck = 1; | ||
271 | cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); | ||
272 | |||
273 | /* Waiting for Inf0 Spi4 RX DLL to lock */ | ||
274 | cvmx_wait(100 * MS); | ||
275 | |||
276 | /* Enable dynamic alignment */ | ||
277 | spxx_trn4_ctl.s.trntest = 0; | ||
278 | spxx_trn4_ctl.s.jitter = 1; | ||
279 | spxx_trn4_ctl.s.clr_boot = 1; | ||
280 | spxx_trn4_ctl.s.set_boot = 0; | ||
281 | if (OCTEON_IS_MODEL(OCTEON_CN58XX)) | ||
282 | spxx_trn4_ctl.s.maxdist = 3; | ||
283 | else | ||
284 | spxx_trn4_ctl.s.maxdist = 8; | ||
285 | spxx_trn4_ctl.s.macro_en = 1; | ||
286 | spxx_trn4_ctl.s.mux_en = 1; | ||
287 | cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); | ||
288 | |||
289 | spxx_dbg_deskew_ctl.u64 = 0; | ||
290 | cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface), | ||
291 | spxx_dbg_deskew_ctl.u64); | ||
292 | |||
293 | return 0; | ||
294 | } | ||
295 | |||
296 | /** | ||
297 | * Callback to setup calendar and miscellaneous settings before clock detection | ||
298 | * | ||
299 | * @interface: The identifier of the packet interface to configure and | ||
300 | * use as a SPI interface. | ||
301 | * @mode: The operating mode for the SPI interface. The interface | ||
302 | * can operate as a full duplex (both Tx and Rx data paths | ||
303 | * active) or as a halfplex (either the Tx data path is | ||
304 | * active or the Rx data path is active, but not both). | ||
305 | * @num_ports: Number of ports to configure on SPI | ||
306 | * | ||
307 | * Returns Zero on success, non-zero error code on failure (will cause | ||
308 | * SPI initialization to abort) | ||
309 | */ | ||
310 | int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, | ||
311 | int num_ports) | ||
312 | { | ||
313 | int port; | ||
314 | int index; | ||
315 | if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { | ||
316 | union cvmx_srxx_com_ctl srxx_com_ctl; | ||
317 | union cvmx_srxx_spi4_stat srxx_spi4_stat; | ||
318 | |||
319 | /* SRX0 number of Ports */ | ||
320 | srxx_com_ctl.u64 = 0; | ||
321 | srxx_com_ctl.s.prts = num_ports - 1; | ||
322 | srxx_com_ctl.s.st_en = 0; | ||
323 | srxx_com_ctl.s.inf_en = 0; | ||
324 | cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); | ||
325 | |||
326 | /* SRX0 Calendar Table. This round robbins through all ports */ | ||
327 | port = 0; | ||
328 | index = 0; | ||
329 | while (port < num_ports) { | ||
330 | union cvmx_srxx_spi4_calx srxx_spi4_calx; | ||
331 | srxx_spi4_calx.u64 = 0; | ||
332 | srxx_spi4_calx.s.prt0 = port++; | ||
333 | srxx_spi4_calx.s.prt1 = port++; | ||
334 | srxx_spi4_calx.s.prt2 = port++; | ||
335 | srxx_spi4_calx.s.prt3 = port++; | ||
336 | srxx_spi4_calx.s.oddpar = | ||
337 | ~(cvmx_dpop(srxx_spi4_calx.u64) & 1); | ||
338 | cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), | ||
339 | srxx_spi4_calx.u64); | ||
340 | index++; | ||
341 | } | ||
342 | srxx_spi4_stat.u64 = 0; | ||
343 | srxx_spi4_stat.s.len = num_ports; | ||
344 | srxx_spi4_stat.s.m = 1; | ||
345 | cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface), | ||
346 | srxx_spi4_stat.u64); | ||
347 | } | ||
348 | |||
349 | if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { | ||
350 | union cvmx_stxx_arb_ctl stxx_arb_ctl; | ||
351 | union cvmx_gmxx_tx_spi_max gmxx_tx_spi_max; | ||
352 | union cvmx_gmxx_tx_spi_thresh gmxx_tx_spi_thresh; | ||
353 | union cvmx_gmxx_tx_spi_ctl gmxx_tx_spi_ctl; | ||
354 | union cvmx_stxx_spi4_stat stxx_spi4_stat; | ||
355 | union cvmx_stxx_spi4_dat stxx_spi4_dat; | ||
356 | |||
357 | /* STX0 Config */ | ||
358 | stxx_arb_ctl.u64 = 0; | ||
359 | stxx_arb_ctl.s.igntpa = 0; | ||
360 | stxx_arb_ctl.s.mintrn = 0; | ||
361 | cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64); | ||
362 | |||
363 | gmxx_tx_spi_max.u64 = 0; | ||
364 | gmxx_tx_spi_max.s.max1 = 8; | ||
365 | gmxx_tx_spi_max.s.max2 = 4; | ||
366 | gmxx_tx_spi_max.s.slice = 0; | ||
367 | cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface), | ||
368 | gmxx_tx_spi_max.u64); | ||
369 | |||
370 | gmxx_tx_spi_thresh.u64 = 0; | ||
371 | gmxx_tx_spi_thresh.s.thresh = 4; | ||
372 | cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface), | ||
373 | gmxx_tx_spi_thresh.u64); | ||
374 | |||
375 | gmxx_tx_spi_ctl.u64 = 0; | ||
376 | gmxx_tx_spi_ctl.s.tpa_clr = 0; | ||
377 | gmxx_tx_spi_ctl.s.cont_pkt = 0; | ||
378 | cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface), | ||
379 | gmxx_tx_spi_ctl.u64); | ||
380 | |||
381 | /* STX0 Training Control */ | ||
382 | stxx_spi4_dat.u64 = 0; | ||
383 | /*Minimum needed by dynamic alignment */ | ||
384 | stxx_spi4_dat.s.alpha = 32; | ||
385 | stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */ | ||
386 | cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface), | ||
387 | stxx_spi4_dat.u64); | ||
388 | |||
389 | /* STX0 Calendar Table. This round robbins through all ports */ | ||
390 | port = 0; | ||
391 | index = 0; | ||
392 | while (port < num_ports) { | ||
393 | union cvmx_stxx_spi4_calx stxx_spi4_calx; | ||
394 | stxx_spi4_calx.u64 = 0; | ||
395 | stxx_spi4_calx.s.prt0 = port++; | ||
396 | stxx_spi4_calx.s.prt1 = port++; | ||
397 | stxx_spi4_calx.s.prt2 = port++; | ||
398 | stxx_spi4_calx.s.prt3 = port++; | ||
399 | stxx_spi4_calx.s.oddpar = | ||
400 | ~(cvmx_dpop(stxx_spi4_calx.u64) & 1); | ||
401 | cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), | ||
402 | stxx_spi4_calx.u64); | ||
403 | index++; | ||
404 | } | ||
405 | stxx_spi4_stat.u64 = 0; | ||
406 | stxx_spi4_stat.s.len = num_ports; | ||
407 | stxx_spi4_stat.s.m = 1; | ||
408 | cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface), | ||
409 | stxx_spi4_stat.u64); | ||
410 | } | ||
411 | |||
412 | return 0; | ||
413 | } | ||
414 | |||
415 | /** | ||
416 | * Callback to perform clock detection | ||
417 | * | ||
418 | * @interface: The identifier of the packet interface to configure and | ||
419 | * use as a SPI interface. | ||
420 | * @mode: The operating mode for the SPI interface. The interface | ||
421 | * can operate as a full duplex (both Tx and Rx data paths | ||
422 | * active) or as a halfplex (either the Tx data path is | ||
423 | * active or the Rx data path is active, but not both). | ||
424 | * @timeout: Timeout to wait for clock synchronization in seconds | ||
425 | * | ||
426 | * Returns Zero on success, non-zero error code on failure (will cause | ||
427 | * SPI initialization to abort) | ||
428 | */ | ||
429 | int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout) | ||
430 | { | ||
431 | int clock_transitions; | ||
432 | union cvmx_spxx_clk_stat stat; | ||
433 | uint64_t timeout_time; | ||
434 | uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; | ||
435 | |||
436 | /* | ||
437 | * Regardless of operating mode, both Tx and Rx clocks must be | ||
438 | * present for the SPI interface to operate. | ||
439 | */ | ||
440 | cvmx_dprintf("SPI%d: Waiting to see TsClk...\n", interface); | ||
441 | timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; | ||
442 | /* | ||
443 | * Require 100 clock transitions in order to avoid any noise | ||
444 | * in the beginning. | ||
445 | */ | ||
446 | clock_transitions = 100; | ||
447 | do { | ||
448 | stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); | ||
449 | if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) { | ||
450 | /* | ||
451 | * We've seen a clock transition, so decrement | ||
452 | * the number we still need. | ||
453 | */ | ||
454 | clock_transitions--; | ||
455 | cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); | ||
456 | stat.s.s4clk0 = 0; | ||
457 | stat.s.s4clk1 = 0; | ||
458 | } | ||
459 | if (cvmx_get_cycle() > timeout_time) { | ||
460 | cvmx_dprintf("SPI%d: Timeout\n", interface); | ||
461 | return -1; | ||
462 | } | ||
463 | } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0); | ||
464 | |||
465 | cvmx_dprintf("SPI%d: Waiting to see RsClk...\n", interface); | ||
466 | timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; | ||
467 | /* | ||
468 | * Require 100 clock transitions in order to avoid any noise in the | ||
469 | * beginning. | ||
470 | */ | ||
471 | clock_transitions = 100; | ||
472 | do { | ||
473 | stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); | ||
474 | if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) { | ||
475 | /* | ||
476 | * We've seen a clock transition, so decrement | ||
477 | * the number we still need | ||
478 | */ | ||
479 | clock_transitions--; | ||
480 | cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); | ||
481 | stat.s.d4clk0 = 0; | ||
482 | stat.s.d4clk1 = 0; | ||
483 | } | ||
484 | if (cvmx_get_cycle() > timeout_time) { | ||
485 | cvmx_dprintf("SPI%d: Timeout\n", interface); | ||
486 | return -1; | ||
487 | } | ||
488 | } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0); | ||
489 | |||
490 | return 0; | ||
491 | } | ||
492 | |||
493 | /** | ||
494 | * Callback to perform link training | ||
495 | * | ||
496 | * @interface: The identifier of the packet interface to configure and | ||
497 | * use as a SPI interface. | ||
498 | * @mode: The operating mode for the SPI interface. The interface | ||
499 | * can operate as a full duplex (both Tx and Rx data paths | ||
500 | * active) or as a halfplex (either the Tx data path is | ||
501 | * active or the Rx data path is active, but not both). | ||
502 | * @timeout: Timeout to wait for link to be trained (in seconds) | ||
503 | * | ||
504 | * Returns Zero on success, non-zero error code on failure (will cause | ||
505 | * SPI initialization to abort) | ||
506 | */ | ||
507 | int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout) | ||
508 | { | ||
509 | union cvmx_spxx_trn4_ctl spxx_trn4_ctl; | ||
510 | union cvmx_spxx_clk_stat stat; | ||
511 | uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; | ||
512 | uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; | ||
513 | int rx_training_needed; | ||
514 | |||
515 | /* SRX0 & STX0 Inf0 Links are configured - begin training */ | ||
516 | union cvmx_spxx_clk_ctl spxx_clk_ctl; | ||
517 | spxx_clk_ctl.u64 = 0; | ||
518 | spxx_clk_ctl.s.seetrn = 0; | ||
519 | spxx_clk_ctl.s.clkdly = 0x10; | ||
520 | spxx_clk_ctl.s.runbist = 0; | ||
521 | spxx_clk_ctl.s.statdrv = 0; | ||
522 | /* This should always be on the opposite edge as statdrv */ | ||
523 | spxx_clk_ctl.s.statrcv = 1; | ||
524 | spxx_clk_ctl.s.sndtrn = 1; | ||
525 | spxx_clk_ctl.s.drptrn = 1; | ||
526 | spxx_clk_ctl.s.rcvtrn = 1; | ||
527 | spxx_clk_ctl.s.srxdlck = 1; | ||
528 | cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); | ||
529 | cvmx_wait(1000 * MS); | ||
530 | |||
531 | /* SRX0 clear the boot bit */ | ||
532 | spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface)); | ||
533 | spxx_trn4_ctl.s.clr_boot = 1; | ||
534 | cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); | ||
535 | |||
536 | /* Wait for the training sequence to complete */ | ||
537 | cvmx_dprintf("SPI%d: Waiting for training\n", interface); | ||
538 | cvmx_wait(1000 * MS); | ||
539 | /* Wait a really long time here */ | ||
540 | timeout_time = cvmx_get_cycle() + 1000ull * MS * 600; | ||
541 | /* | ||
542 | * The HRM says we must wait for 34 + 16 * MAXDIST training sequences. | ||
543 | * We'll be pessimistic and wait for a lot more. | ||
544 | */ | ||
545 | rx_training_needed = 500; | ||
546 | do { | ||
547 | stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); | ||
548 | if (stat.s.srxtrn && rx_training_needed) { | ||
549 | rx_training_needed--; | ||
550 | cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); | ||
551 | stat.s.srxtrn = 0; | ||
552 | } | ||
553 | if (cvmx_get_cycle() > timeout_time) { | ||
554 | cvmx_dprintf("SPI%d: Timeout\n", interface); | ||
555 | return -1; | ||
556 | } | ||
557 | } while (stat.s.srxtrn == 0); | ||
558 | |||
559 | return 0; | ||
560 | } | ||
561 | |||
562 | /** | ||
563 | * Callback to perform calendar data synchronization | ||
564 | * | ||
565 | * @interface: The identifier of the packet interface to configure and | ||
566 | * use as a SPI interface. | ||
567 | * @mode: The operating mode for the SPI interface. The interface | ||
568 | * can operate as a full duplex (both Tx and Rx data paths | ||
569 | * active) or as a halfplex (either the Tx data path is | ||
570 | * active or the Rx data path is active, but not both). | ||
571 | * @timeout: Timeout to wait for calendar data in seconds | ||
572 | * | ||
573 | * Returns Zero on success, non-zero error code on failure (will cause | ||
574 | * SPI initialization to abort) | ||
575 | */ | ||
576 | int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout) | ||
577 | { | ||
578 | uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; | ||
579 | if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { | ||
580 | /* SRX0 interface should be good, send calendar data */ | ||
581 | union cvmx_srxx_com_ctl srxx_com_ctl; | ||
582 | cvmx_dprintf | ||
583 | ("SPI%d: Rx is synchronized, start sending calendar data\n", | ||
584 | interface); | ||
585 | srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); | ||
586 | srxx_com_ctl.s.inf_en = 1; | ||
587 | srxx_com_ctl.s.st_en = 1; | ||
588 | cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); | ||
589 | } | ||
590 | |||
591 | if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { | ||
592 | /* STX0 has achieved sync */ | ||
593 | /* The corespondant board should be sending calendar data */ | ||
594 | /* Enable the STX0 STAT receiver. */ | ||
595 | union cvmx_spxx_clk_stat stat; | ||
596 | uint64_t timeout_time; | ||
597 | union cvmx_stxx_com_ctl stxx_com_ctl; | ||
598 | stxx_com_ctl.u64 = 0; | ||
599 | stxx_com_ctl.s.st_en = 1; | ||
600 | cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); | ||
601 | |||
602 | /* Waiting for calendar sync on STX0 STAT */ | ||
603 | cvmx_dprintf("SPI%d: Waiting to sync on STX[%d] STAT\n", | ||
604 | interface, interface); | ||
605 | timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; | ||
606 | /* SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10) */ | ||
607 | do { | ||
608 | stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); | ||
609 | if (cvmx_get_cycle() > timeout_time) { | ||
610 | cvmx_dprintf("SPI%d: Timeout\n", interface); | ||
611 | return -1; | ||
612 | } | ||
613 | } while (stat.s.stxcal == 0); | ||
614 | } | ||
615 | |||
616 | return 0; | ||
617 | } | ||
618 | |||
619 | /** | ||
620 | * Callback to handle interface up | ||
621 | * | ||
622 | * @interface: The identifier of the packet interface to configure and | ||
623 | * use as a SPI interface. | ||
624 | * @mode: The operating mode for the SPI interface. The interface | ||
625 | * can operate as a full duplex (both Tx and Rx data paths | ||
626 | * active) or as a halfplex (either the Tx data path is | ||
627 | * active or the Rx data path is active, but not both). | ||
628 | * | ||
629 | * Returns Zero on success, non-zero error code on failure (will cause | ||
630 | * SPI initialization to abort) | ||
631 | */ | ||
632 | int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode) | ||
633 | { | ||
634 | union cvmx_gmxx_rxx_frm_min gmxx_rxx_frm_min; | ||
635 | union cvmx_gmxx_rxx_frm_max gmxx_rxx_frm_max; | ||
636 | union cvmx_gmxx_rxx_jabber gmxx_rxx_jabber; | ||
637 | |||
638 | if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { | ||
639 | union cvmx_srxx_com_ctl srxx_com_ctl; | ||
640 | srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); | ||
641 | srxx_com_ctl.s.inf_en = 1; | ||
642 | cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); | ||
643 | cvmx_dprintf("SPI%d: Rx is now up\n", interface); | ||
644 | } | ||
645 | |||
646 | if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { | ||
647 | union cvmx_stxx_com_ctl stxx_com_ctl; | ||
648 | stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface)); | ||
649 | stxx_com_ctl.s.inf_en = 1; | ||
650 | cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); | ||
651 | cvmx_dprintf("SPI%d: Tx is now up\n", interface); | ||
652 | } | ||
653 | |||
654 | gmxx_rxx_frm_min.u64 = 0; | ||
655 | gmxx_rxx_frm_min.s.len = 64; | ||
656 | cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface), | ||
657 | gmxx_rxx_frm_min.u64); | ||
658 | gmxx_rxx_frm_max.u64 = 0; | ||
659 | gmxx_rxx_frm_max.s.len = 64 * 1024 - 4; | ||
660 | cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface), | ||
661 | gmxx_rxx_frm_max.u64); | ||
662 | gmxx_rxx_jabber.u64 = 0; | ||
663 | gmxx_rxx_jabber.s.cnt = 64 * 1024 - 4; | ||
664 | cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64); | ||
665 | |||
666 | return 0; | ||
667 | } | ||
diff --git a/drivers/staging/octeon/cvmx-spi.h b/drivers/staging/octeon/cvmx-spi.h new file mode 100644 index 000000000000..e814648953a5 --- /dev/null +++ b/drivers/staging/octeon/cvmx-spi.h | |||
@@ -0,0 +1,269 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /* | ||
29 | * | ||
30 | * This file contains defines for the SPI interface | ||
31 | */ | ||
32 | #ifndef __CVMX_SPI_H__ | ||
33 | #define __CVMX_SPI_H__ | ||
34 | |||
35 | #include "cvmx-gmxx-defs.h" | ||
36 | |||
37 | /* CSR typedefs have been moved to cvmx-csr-*.h */ | ||
38 | |||
39 | typedef enum { | ||
40 | CVMX_SPI_MODE_UNKNOWN = 0, | ||
41 | CVMX_SPI_MODE_TX_HALFPLEX = 1, | ||
42 | CVMX_SPI_MODE_RX_HALFPLEX = 2, | ||
43 | CVMX_SPI_MODE_DUPLEX = 3 | ||
44 | } cvmx_spi_mode_t; | ||
45 | |||
46 | /** Callbacks structure to customize SPI4 initialization sequence */ | ||
47 | typedef struct { | ||
48 | /** Called to reset SPI4 DLL */ | ||
49 | int (*reset_cb) (int interface, cvmx_spi_mode_t mode); | ||
50 | |||
51 | /** Called to setup calendar */ | ||
52 | int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode, | ||
53 | int num_ports); | ||
54 | |||
55 | /** Called for Tx and Rx clock detection */ | ||
56 | int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode, | ||
57 | int timeout); | ||
58 | |||
59 | /** Called to perform link training */ | ||
60 | int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout); | ||
61 | |||
62 | /** Called for calendar data synchronization */ | ||
63 | int (*calendar_sync_cb) (int interface, cvmx_spi_mode_t mode, | ||
64 | int timeout); | ||
65 | |||
66 | /** Called when interface is up */ | ||
67 | int (*interface_up_cb) (int interface, cvmx_spi_mode_t mode); | ||
68 | |||
69 | } cvmx_spi_callbacks_t; | ||
70 | |||
71 | /** | ||
72 | * Return true if the supplied interface is configured for SPI | ||
73 | * | ||
74 | * @interface: Interface to check | ||
75 | * Returns True if interface is SPI | ||
76 | */ | ||
77 | static inline int cvmx_spi_is_spi_interface(int interface) | ||
78 | { | ||
79 | uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); | ||
80 | return (gmxState & 0x2) && (gmxState & 0x1); | ||
81 | } | ||
82 | |||
83 | /** | ||
84 | * Initialize and start the SPI interface. | ||
85 | * | ||
86 | * @interface: The identifier of the packet interface to configure and | ||
87 | * use as a SPI interface. | ||
88 | * @mode: The operating mode for the SPI interface. The interface | ||
89 | * can operate as a full duplex (both Tx and Rx data paths | ||
90 | * active) or as a halfplex (either the Tx data path is | ||
91 | * active or the Rx data path is active, but not both). | ||
92 | * @timeout: Timeout to wait for clock synchronization in seconds | ||
93 | * @num_ports: Number of SPI ports to configure | ||
94 | * | ||
95 | * Returns Zero on success, negative of failure. | ||
96 | */ | ||
97 | extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, | ||
98 | int timeout, int num_ports); | ||
99 | |||
100 | /** | ||
101 | * This routine restarts the SPI interface after it has lost synchronization | ||
102 | * with its corespondant system. | ||
103 | * | ||
104 | * @interface: The identifier of the packet interface to configure and | ||
105 | * use as a SPI interface. | ||
106 | * @mode: The operating mode for the SPI interface. The interface | ||
107 | * can operate as a full duplex (both Tx and Rx data paths | ||
108 | * active) or as a halfplex (either the Tx data path is | ||
109 | * active or the Rx data path is active, but not both). | ||
110 | * @timeout: Timeout to wait for clock synchronization in seconds | ||
111 | * Returns Zero on success, negative of failure. | ||
112 | */ | ||
113 | extern int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, | ||
114 | int timeout); | ||
115 | |||
116 | /** | ||
117 | * Return non-zero if the SPI interface has a SPI4000 attached | ||
118 | * | ||
119 | * @interface: SPI interface the SPI4000 is connected to | ||
120 | * | ||
121 | * Returns | ||
122 | */ | ||
123 | static inline int cvmx_spi4000_is_present(int interface) | ||
124 | { | ||
125 | return 0; | ||
126 | } | ||
127 | |||
128 | /** | ||
129 | * Initialize the SPI4000 for use | ||
130 | * | ||
131 | * @interface: SPI interface the SPI4000 is connected to | ||
132 | */ | ||
133 | static inline int cvmx_spi4000_initialize(int interface) | ||
134 | { | ||
135 | return 0; | ||
136 | } | ||
137 | |||
138 | /** | ||
139 | * Poll all the SPI4000 port and check its speed | ||
140 | * | ||
141 | * @interface: Interface the SPI4000 is on | ||
142 | * @port: Port to poll (0-9) | ||
143 | * Returns Status of the port. 0=down. All other values the port is up. | ||
144 | */ | ||
145 | static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed( | ||
146 | int interface, | ||
147 | int port) | ||
148 | { | ||
149 | union cvmx_gmxx_rxx_rx_inbnd r; | ||
150 | r.u64 = 0; | ||
151 | return r; | ||
152 | } | ||
153 | |||
154 | /** | ||
155 | * Get current SPI4 initialization callbacks | ||
156 | * | ||
157 | * @callbacks: Pointer to the callbacks structure.to fill | ||
158 | * | ||
159 | * Returns Pointer to cvmx_spi_callbacks_t structure. | ||
160 | */ | ||
161 | extern void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks); | ||
162 | |||
163 | /** | ||
164 | * Set new SPI4 initialization callbacks | ||
165 | * | ||
166 | * @new_callbacks: Pointer to an updated callbacks structure. | ||
167 | */ | ||
168 | extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks); | ||
169 | |||
170 | /** | ||
171 | * Callback to perform SPI4 reset | ||
172 | * | ||
173 | * @interface: The identifier of the packet interface to configure and | ||
174 | * use as a SPI interface. | ||
175 | * @mode: The operating mode for the SPI interface. The interface | ||
176 | * can operate as a full duplex (both Tx and Rx data paths | ||
177 | * active) or as a halfplex (either the Tx data path is | ||
178 | * active or the Rx data path is active, but not both). | ||
179 | * | ||
180 | * Returns Zero on success, non-zero error code on failure (will cause | ||
181 | * SPI initialization to abort) | ||
182 | */ | ||
183 | extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode); | ||
184 | |||
185 | /** | ||
186 | * Callback to setup calendar and miscellaneous settings before clock | ||
187 | * detection | ||
188 | * | ||
189 | * @interface: The identifier of the packet interface to configure and | ||
190 | * use as a SPI interface. | ||
191 | * @mode: The operating mode for the SPI interface. The interface | ||
192 | * can operate as a full duplex (both Tx and Rx data paths | ||
193 | * active) or as a halfplex (either the Tx data path is | ||
194 | * active or the Rx data path is active, but not both). | ||
195 | * @num_ports: Number of ports to configure on SPI | ||
196 | * | ||
197 | * Returns Zero on success, non-zero error code on failure (will cause | ||
198 | * SPI initialization to abort) | ||
199 | */ | ||
200 | extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, | ||
201 | int num_ports); | ||
202 | |||
203 | /** | ||
204 | * Callback to perform clock detection | ||
205 | * | ||
206 | * @interface: The identifier of the packet interface to configure and | ||
207 | * use as a SPI interface. | ||
208 | * @mode: The operating mode for the SPI interface. The interface | ||
209 | * can operate as a full duplex (both Tx and Rx data paths | ||
210 | * active) or as a halfplex (either the Tx data path is | ||
211 | * active or the Rx data path is active, but not both). | ||
212 | * @timeout: Timeout to wait for clock synchronization in seconds | ||
213 | * | ||
214 | * Returns Zero on success, non-zero error code on failure (will cause | ||
215 | * SPI initialization to abort) | ||
216 | */ | ||
217 | extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, | ||
218 | int timeout); | ||
219 | |||
220 | /** | ||
221 | * Callback to perform link training | ||
222 | * | ||
223 | * @interface: The identifier of the packet interface to configure and | ||
224 | * use as a SPI interface. | ||
225 | * @mode: The operating mode for the SPI interface. The interface | ||
226 | * can operate as a full duplex (both Tx and Rx data paths | ||
227 | * active) or as a halfplex (either the Tx data path is | ||
228 | * active or the Rx data path is active, but not both). | ||
229 | * @timeout: Timeout to wait for link to be trained (in seconds) | ||
230 | * | ||
231 | * Returns Zero on success, non-zero error code on failure (will cause | ||
232 | * SPI initialization to abort) | ||
233 | */ | ||
234 | extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, | ||
235 | int timeout); | ||
236 | |||
237 | /** | ||
238 | * Callback to perform calendar data synchronization | ||
239 | * | ||
240 | * @interface: The identifier of the packet interface to configure and | ||
241 | * use as a SPI interface. | ||
242 | * @mode: The operating mode for the SPI interface. The interface | ||
243 | * can operate as a full duplex (both Tx and Rx data paths | ||
244 | * active) or as a halfplex (either the Tx data path is | ||
245 | * active or the Rx data path is active, but not both). | ||
246 | * @timeout: Timeout to wait for calendar data in seconds | ||
247 | * | ||
248 | * Returns Zero on success, non-zero error code on failure (will cause | ||
249 | * SPI initialization to abort) | ||
250 | */ | ||
251 | extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, | ||
252 | int timeout); | ||
253 | |||
254 | /** | ||
255 | * Callback to handle interface up | ||
256 | * | ||
257 | * @interface: The identifier of the packet interface to configure and | ||
258 | * use as a SPI interface. | ||
259 | * @mode: The operating mode for the SPI interface. The interface | ||
260 | * can operate as a full duplex (both Tx and Rx data paths | ||
261 | * active) or as a halfplex (either the Tx data path is | ||
262 | * active or the Rx data path is active, but not both). | ||
263 | * | ||
264 | * Returns Zero on success, non-zero error code on failure (will cause | ||
265 | * SPI initialization to abort) | ||
266 | */ | ||
267 | extern int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode); | ||
268 | |||
269 | #endif /* __CVMX_SPI_H__ */ | ||
diff --git a/drivers/staging/octeon/cvmx-spxx-defs.h b/drivers/staging/octeon/cvmx-spxx-defs.h new file mode 100644 index 000000000000..b16940e32c83 --- /dev/null +++ b/drivers/staging/octeon/cvmx-spxx-defs.h | |||
@@ -0,0 +1,347 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_SPXX_DEFS_H__ | ||
29 | #define __CVMX_SPXX_DEFS_H__ | ||
30 | |||
31 | #define CVMX_SPXX_BCKPRS_CNT(block_id) \ | ||
32 | CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull)) | ||
33 | #define CVMX_SPXX_BIST_STAT(block_id) \ | ||
34 | CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull)) | ||
35 | #define CVMX_SPXX_CLK_CTL(block_id) \ | ||
36 | CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull)) | ||
37 | #define CVMX_SPXX_CLK_STAT(block_id) \ | ||
38 | CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull)) | ||
39 | #define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \ | ||
40 | CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull)) | ||
41 | #define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \ | ||
42 | CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull)) | ||
43 | #define CVMX_SPXX_DRV_CTL(block_id) \ | ||
44 | CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull)) | ||
45 | #define CVMX_SPXX_ERR_CTL(block_id) \ | ||
46 | CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull)) | ||
47 | #define CVMX_SPXX_INT_DAT(block_id) \ | ||
48 | CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull)) | ||
49 | #define CVMX_SPXX_INT_MSK(block_id) \ | ||
50 | CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull)) | ||
51 | #define CVMX_SPXX_INT_REG(block_id) \ | ||
52 | CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull)) | ||
53 | #define CVMX_SPXX_INT_SYNC(block_id) \ | ||
54 | CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull)) | ||
55 | #define CVMX_SPXX_TPA_ACC(block_id) \ | ||
56 | CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull)) | ||
57 | #define CVMX_SPXX_TPA_MAX(block_id) \ | ||
58 | CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull)) | ||
59 | #define CVMX_SPXX_TPA_SEL(block_id) \ | ||
60 | CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull)) | ||
61 | #define CVMX_SPXX_TRN4_CTL(block_id) \ | ||
62 | CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull)) | ||
63 | |||
64 | union cvmx_spxx_bckprs_cnt { | ||
65 | uint64_t u64; | ||
66 | struct cvmx_spxx_bckprs_cnt_s { | ||
67 | uint64_t reserved_32_63:32; | ||
68 | uint64_t cnt:32; | ||
69 | } s; | ||
70 | struct cvmx_spxx_bckprs_cnt_s cn38xx; | ||
71 | struct cvmx_spxx_bckprs_cnt_s cn38xxp2; | ||
72 | struct cvmx_spxx_bckprs_cnt_s cn58xx; | ||
73 | struct cvmx_spxx_bckprs_cnt_s cn58xxp1; | ||
74 | }; | ||
75 | |||
76 | union cvmx_spxx_bist_stat { | ||
77 | uint64_t u64; | ||
78 | struct cvmx_spxx_bist_stat_s { | ||
79 | uint64_t reserved_3_63:61; | ||
80 | uint64_t stat2:1; | ||
81 | uint64_t stat1:1; | ||
82 | uint64_t stat0:1; | ||
83 | } s; | ||
84 | struct cvmx_spxx_bist_stat_s cn38xx; | ||
85 | struct cvmx_spxx_bist_stat_s cn38xxp2; | ||
86 | struct cvmx_spxx_bist_stat_s cn58xx; | ||
87 | struct cvmx_spxx_bist_stat_s cn58xxp1; | ||
88 | }; | ||
89 | |||
90 | union cvmx_spxx_clk_ctl { | ||
91 | uint64_t u64; | ||
92 | struct cvmx_spxx_clk_ctl_s { | ||
93 | uint64_t reserved_17_63:47; | ||
94 | uint64_t seetrn:1; | ||
95 | uint64_t reserved_12_15:4; | ||
96 | uint64_t clkdly:5; | ||
97 | uint64_t runbist:1; | ||
98 | uint64_t statdrv:1; | ||
99 | uint64_t statrcv:1; | ||
100 | uint64_t sndtrn:1; | ||
101 | uint64_t drptrn:1; | ||
102 | uint64_t rcvtrn:1; | ||
103 | uint64_t srxdlck:1; | ||
104 | } s; | ||
105 | struct cvmx_spxx_clk_ctl_s cn38xx; | ||
106 | struct cvmx_spxx_clk_ctl_s cn38xxp2; | ||
107 | struct cvmx_spxx_clk_ctl_s cn58xx; | ||
108 | struct cvmx_spxx_clk_ctl_s cn58xxp1; | ||
109 | }; | ||
110 | |||
111 | union cvmx_spxx_clk_stat { | ||
112 | uint64_t u64; | ||
113 | struct cvmx_spxx_clk_stat_s { | ||
114 | uint64_t reserved_11_63:53; | ||
115 | uint64_t stxcal:1; | ||
116 | uint64_t reserved_9_9:1; | ||
117 | uint64_t srxtrn:1; | ||
118 | uint64_t s4clk1:1; | ||
119 | uint64_t s4clk0:1; | ||
120 | uint64_t d4clk1:1; | ||
121 | uint64_t d4clk0:1; | ||
122 | uint64_t reserved_0_3:4; | ||
123 | } s; | ||
124 | struct cvmx_spxx_clk_stat_s cn38xx; | ||
125 | struct cvmx_spxx_clk_stat_s cn38xxp2; | ||
126 | struct cvmx_spxx_clk_stat_s cn58xx; | ||
127 | struct cvmx_spxx_clk_stat_s cn58xxp1; | ||
128 | }; | ||
129 | |||
130 | union cvmx_spxx_dbg_deskew_ctl { | ||
131 | uint64_t u64; | ||
132 | struct cvmx_spxx_dbg_deskew_ctl_s { | ||
133 | uint64_t reserved_30_63:34; | ||
134 | uint64_t fallnop:1; | ||
135 | uint64_t fall8:1; | ||
136 | uint64_t reserved_26_27:2; | ||
137 | uint64_t sstep_go:1; | ||
138 | uint64_t sstep:1; | ||
139 | uint64_t reserved_22_23:2; | ||
140 | uint64_t clrdly:1; | ||
141 | uint64_t dec:1; | ||
142 | uint64_t inc:1; | ||
143 | uint64_t mux:1; | ||
144 | uint64_t offset:5; | ||
145 | uint64_t bitsel:5; | ||
146 | uint64_t offdly:6; | ||
147 | uint64_t dllfrc:1; | ||
148 | uint64_t dlldis:1; | ||
149 | } s; | ||
150 | struct cvmx_spxx_dbg_deskew_ctl_s cn38xx; | ||
151 | struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2; | ||
152 | struct cvmx_spxx_dbg_deskew_ctl_s cn58xx; | ||
153 | struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1; | ||
154 | }; | ||
155 | |||
156 | union cvmx_spxx_dbg_deskew_state { | ||
157 | uint64_t u64; | ||
158 | struct cvmx_spxx_dbg_deskew_state_s { | ||
159 | uint64_t reserved_9_63:55; | ||
160 | uint64_t testres:1; | ||
161 | uint64_t unxterm:1; | ||
162 | uint64_t muxsel:2; | ||
163 | uint64_t offset:5; | ||
164 | } s; | ||
165 | struct cvmx_spxx_dbg_deskew_state_s cn38xx; | ||
166 | struct cvmx_spxx_dbg_deskew_state_s cn38xxp2; | ||
167 | struct cvmx_spxx_dbg_deskew_state_s cn58xx; | ||
168 | struct cvmx_spxx_dbg_deskew_state_s cn58xxp1; | ||
169 | }; | ||
170 | |||
171 | union cvmx_spxx_drv_ctl { | ||
172 | uint64_t u64; | ||
173 | struct cvmx_spxx_drv_ctl_s { | ||
174 | uint64_t reserved_0_63:64; | ||
175 | } s; | ||
176 | struct cvmx_spxx_drv_ctl_cn38xx { | ||
177 | uint64_t reserved_16_63:48; | ||
178 | uint64_t stx4ncmp:4; | ||
179 | uint64_t stx4pcmp:4; | ||
180 | uint64_t srx4cmp:8; | ||
181 | } cn38xx; | ||
182 | struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2; | ||
183 | struct cvmx_spxx_drv_ctl_cn58xx { | ||
184 | uint64_t reserved_24_63:40; | ||
185 | uint64_t stx4ncmp:4; | ||
186 | uint64_t stx4pcmp:4; | ||
187 | uint64_t reserved_10_15:6; | ||
188 | uint64_t srx4cmp:10; | ||
189 | } cn58xx; | ||
190 | struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1; | ||
191 | }; | ||
192 | |||
193 | union cvmx_spxx_err_ctl { | ||
194 | uint64_t u64; | ||
195 | struct cvmx_spxx_err_ctl_s { | ||
196 | uint64_t reserved_9_63:55; | ||
197 | uint64_t prtnxa:1; | ||
198 | uint64_t dipcls:1; | ||
199 | uint64_t dippay:1; | ||
200 | uint64_t reserved_4_5:2; | ||
201 | uint64_t errcnt:4; | ||
202 | } s; | ||
203 | struct cvmx_spxx_err_ctl_s cn38xx; | ||
204 | struct cvmx_spxx_err_ctl_s cn38xxp2; | ||
205 | struct cvmx_spxx_err_ctl_s cn58xx; | ||
206 | struct cvmx_spxx_err_ctl_s cn58xxp1; | ||
207 | }; | ||
208 | |||
209 | union cvmx_spxx_int_dat { | ||
210 | uint64_t u64; | ||
211 | struct cvmx_spxx_int_dat_s { | ||
212 | uint64_t reserved_32_63:32; | ||
213 | uint64_t mul:1; | ||
214 | uint64_t reserved_14_30:17; | ||
215 | uint64_t calbnk:2; | ||
216 | uint64_t rsvop:4; | ||
217 | uint64_t prt:8; | ||
218 | } s; | ||
219 | struct cvmx_spxx_int_dat_s cn38xx; | ||
220 | struct cvmx_spxx_int_dat_s cn38xxp2; | ||
221 | struct cvmx_spxx_int_dat_s cn58xx; | ||
222 | struct cvmx_spxx_int_dat_s cn58xxp1; | ||
223 | }; | ||
224 | |||
225 | union cvmx_spxx_int_msk { | ||
226 | uint64_t u64; | ||
227 | struct cvmx_spxx_int_msk_s { | ||
228 | uint64_t reserved_12_63:52; | ||
229 | uint64_t calerr:1; | ||
230 | uint64_t syncerr:1; | ||
231 | uint64_t diperr:1; | ||
232 | uint64_t tpaovr:1; | ||
233 | uint64_t rsverr:1; | ||
234 | uint64_t drwnng:1; | ||
235 | uint64_t clserr:1; | ||
236 | uint64_t spiovr:1; | ||
237 | uint64_t reserved_2_3:2; | ||
238 | uint64_t abnorm:1; | ||
239 | uint64_t prtnxa:1; | ||
240 | } s; | ||
241 | struct cvmx_spxx_int_msk_s cn38xx; | ||
242 | struct cvmx_spxx_int_msk_s cn38xxp2; | ||
243 | struct cvmx_spxx_int_msk_s cn58xx; | ||
244 | struct cvmx_spxx_int_msk_s cn58xxp1; | ||
245 | }; | ||
246 | |||
247 | union cvmx_spxx_int_reg { | ||
248 | uint64_t u64; | ||
249 | struct cvmx_spxx_int_reg_s { | ||
250 | uint64_t reserved_32_63:32; | ||
251 | uint64_t spf:1; | ||
252 | uint64_t reserved_12_30:19; | ||
253 | uint64_t calerr:1; | ||
254 | uint64_t syncerr:1; | ||
255 | uint64_t diperr:1; | ||
256 | uint64_t tpaovr:1; | ||
257 | uint64_t rsverr:1; | ||
258 | uint64_t drwnng:1; | ||
259 | uint64_t clserr:1; | ||
260 | uint64_t spiovr:1; | ||
261 | uint64_t reserved_2_3:2; | ||
262 | uint64_t abnorm:1; | ||
263 | uint64_t prtnxa:1; | ||
264 | } s; | ||
265 | struct cvmx_spxx_int_reg_s cn38xx; | ||
266 | struct cvmx_spxx_int_reg_s cn38xxp2; | ||
267 | struct cvmx_spxx_int_reg_s cn58xx; | ||
268 | struct cvmx_spxx_int_reg_s cn58xxp1; | ||
269 | }; | ||
270 | |||
271 | union cvmx_spxx_int_sync { | ||
272 | uint64_t u64; | ||
273 | struct cvmx_spxx_int_sync_s { | ||
274 | uint64_t reserved_12_63:52; | ||
275 | uint64_t calerr:1; | ||
276 | uint64_t syncerr:1; | ||
277 | uint64_t diperr:1; | ||
278 | uint64_t tpaovr:1; | ||
279 | uint64_t rsverr:1; | ||
280 | uint64_t drwnng:1; | ||
281 | uint64_t clserr:1; | ||
282 | uint64_t spiovr:1; | ||
283 | uint64_t reserved_2_3:2; | ||
284 | uint64_t abnorm:1; | ||
285 | uint64_t prtnxa:1; | ||
286 | } s; | ||
287 | struct cvmx_spxx_int_sync_s cn38xx; | ||
288 | struct cvmx_spxx_int_sync_s cn38xxp2; | ||
289 | struct cvmx_spxx_int_sync_s cn58xx; | ||
290 | struct cvmx_spxx_int_sync_s cn58xxp1; | ||
291 | }; | ||
292 | |||
293 | union cvmx_spxx_tpa_acc { | ||
294 | uint64_t u64; | ||
295 | struct cvmx_spxx_tpa_acc_s { | ||
296 | uint64_t reserved_32_63:32; | ||
297 | uint64_t cnt:32; | ||
298 | } s; | ||
299 | struct cvmx_spxx_tpa_acc_s cn38xx; | ||
300 | struct cvmx_spxx_tpa_acc_s cn38xxp2; | ||
301 | struct cvmx_spxx_tpa_acc_s cn58xx; | ||
302 | struct cvmx_spxx_tpa_acc_s cn58xxp1; | ||
303 | }; | ||
304 | |||
305 | union cvmx_spxx_tpa_max { | ||
306 | uint64_t u64; | ||
307 | struct cvmx_spxx_tpa_max_s { | ||
308 | uint64_t reserved_32_63:32; | ||
309 | uint64_t max:32; | ||
310 | } s; | ||
311 | struct cvmx_spxx_tpa_max_s cn38xx; | ||
312 | struct cvmx_spxx_tpa_max_s cn38xxp2; | ||
313 | struct cvmx_spxx_tpa_max_s cn58xx; | ||
314 | struct cvmx_spxx_tpa_max_s cn58xxp1; | ||
315 | }; | ||
316 | |||
317 | union cvmx_spxx_tpa_sel { | ||
318 | uint64_t u64; | ||
319 | struct cvmx_spxx_tpa_sel_s { | ||
320 | uint64_t reserved_4_63:60; | ||
321 | uint64_t prtsel:4; | ||
322 | } s; | ||
323 | struct cvmx_spxx_tpa_sel_s cn38xx; | ||
324 | struct cvmx_spxx_tpa_sel_s cn38xxp2; | ||
325 | struct cvmx_spxx_tpa_sel_s cn58xx; | ||
326 | struct cvmx_spxx_tpa_sel_s cn58xxp1; | ||
327 | }; | ||
328 | |||
329 | union cvmx_spxx_trn4_ctl { | ||
330 | uint64_t u64; | ||
331 | struct cvmx_spxx_trn4_ctl_s { | ||
332 | uint64_t reserved_13_63:51; | ||
333 | uint64_t trntest:1; | ||
334 | uint64_t jitter:3; | ||
335 | uint64_t clr_boot:1; | ||
336 | uint64_t set_boot:1; | ||
337 | uint64_t maxdist:5; | ||
338 | uint64_t macro_en:1; | ||
339 | uint64_t mux_en:1; | ||
340 | } s; | ||
341 | struct cvmx_spxx_trn4_ctl_s cn38xx; | ||
342 | struct cvmx_spxx_trn4_ctl_s cn38xxp2; | ||
343 | struct cvmx_spxx_trn4_ctl_s cn58xx; | ||
344 | struct cvmx_spxx_trn4_ctl_s cn58xxp1; | ||
345 | }; | ||
346 | |||
347 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-srxx-defs.h b/drivers/staging/octeon/cvmx-srxx-defs.h new file mode 100644 index 000000000000..d82b366c279f --- /dev/null +++ b/drivers/staging/octeon/cvmx-srxx-defs.h | |||
@@ -0,0 +1,126 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_SRXX_DEFS_H__ | ||
29 | #define __CVMX_SRXX_DEFS_H__ | ||
30 | |||
31 | #define CVMX_SRXX_COM_CTL(block_id) \ | ||
32 | CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull)) | ||
33 | #define CVMX_SRXX_IGN_RX_FULL(block_id) \ | ||
34 | CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull)) | ||
35 | #define CVMX_SRXX_SPI4_CALX(offset, block_id) \ | ||
36 | CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
37 | #define CVMX_SRXX_SPI4_STAT(block_id) \ | ||
38 | CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull)) | ||
39 | #define CVMX_SRXX_SW_TICK_CTL(block_id) \ | ||
40 | CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull)) | ||
41 | #define CVMX_SRXX_SW_TICK_DAT(block_id) \ | ||
42 | CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull)) | ||
43 | |||
44 | union cvmx_srxx_com_ctl { | ||
45 | uint64_t u64; | ||
46 | struct cvmx_srxx_com_ctl_s { | ||
47 | uint64_t reserved_8_63:56; | ||
48 | uint64_t prts:4; | ||
49 | uint64_t st_en:1; | ||
50 | uint64_t reserved_1_2:2; | ||
51 | uint64_t inf_en:1; | ||
52 | } s; | ||
53 | struct cvmx_srxx_com_ctl_s cn38xx; | ||
54 | struct cvmx_srxx_com_ctl_s cn38xxp2; | ||
55 | struct cvmx_srxx_com_ctl_s cn58xx; | ||
56 | struct cvmx_srxx_com_ctl_s cn58xxp1; | ||
57 | }; | ||
58 | |||
59 | union cvmx_srxx_ign_rx_full { | ||
60 | uint64_t u64; | ||
61 | struct cvmx_srxx_ign_rx_full_s { | ||
62 | uint64_t reserved_16_63:48; | ||
63 | uint64_t ignore:16; | ||
64 | } s; | ||
65 | struct cvmx_srxx_ign_rx_full_s cn38xx; | ||
66 | struct cvmx_srxx_ign_rx_full_s cn38xxp2; | ||
67 | struct cvmx_srxx_ign_rx_full_s cn58xx; | ||
68 | struct cvmx_srxx_ign_rx_full_s cn58xxp1; | ||
69 | }; | ||
70 | |||
71 | union cvmx_srxx_spi4_calx { | ||
72 | uint64_t u64; | ||
73 | struct cvmx_srxx_spi4_calx_s { | ||
74 | uint64_t reserved_17_63:47; | ||
75 | uint64_t oddpar:1; | ||
76 | uint64_t prt3:4; | ||
77 | uint64_t prt2:4; | ||
78 | uint64_t prt1:4; | ||
79 | uint64_t prt0:4; | ||
80 | } s; | ||
81 | struct cvmx_srxx_spi4_calx_s cn38xx; | ||
82 | struct cvmx_srxx_spi4_calx_s cn38xxp2; | ||
83 | struct cvmx_srxx_spi4_calx_s cn58xx; | ||
84 | struct cvmx_srxx_spi4_calx_s cn58xxp1; | ||
85 | }; | ||
86 | |||
87 | union cvmx_srxx_spi4_stat { | ||
88 | uint64_t u64; | ||
89 | struct cvmx_srxx_spi4_stat_s { | ||
90 | uint64_t reserved_16_63:48; | ||
91 | uint64_t m:8; | ||
92 | uint64_t reserved_7_7:1; | ||
93 | uint64_t len:7; | ||
94 | } s; | ||
95 | struct cvmx_srxx_spi4_stat_s cn38xx; | ||
96 | struct cvmx_srxx_spi4_stat_s cn38xxp2; | ||
97 | struct cvmx_srxx_spi4_stat_s cn58xx; | ||
98 | struct cvmx_srxx_spi4_stat_s cn58xxp1; | ||
99 | }; | ||
100 | |||
101 | union cvmx_srxx_sw_tick_ctl { | ||
102 | uint64_t u64; | ||
103 | struct cvmx_srxx_sw_tick_ctl_s { | ||
104 | uint64_t reserved_14_63:50; | ||
105 | uint64_t eop:1; | ||
106 | uint64_t sop:1; | ||
107 | uint64_t mod:4; | ||
108 | uint64_t opc:4; | ||
109 | uint64_t adr:4; | ||
110 | } s; | ||
111 | struct cvmx_srxx_sw_tick_ctl_s cn38xx; | ||
112 | struct cvmx_srxx_sw_tick_ctl_s cn58xx; | ||
113 | struct cvmx_srxx_sw_tick_ctl_s cn58xxp1; | ||
114 | }; | ||
115 | |||
116 | union cvmx_srxx_sw_tick_dat { | ||
117 | uint64_t u64; | ||
118 | struct cvmx_srxx_sw_tick_dat_s { | ||
119 | uint64_t dat:64; | ||
120 | } s; | ||
121 | struct cvmx_srxx_sw_tick_dat_s cn38xx; | ||
122 | struct cvmx_srxx_sw_tick_dat_s cn58xx; | ||
123 | struct cvmx_srxx_sw_tick_dat_s cn58xxp1; | ||
124 | }; | ||
125 | |||
126 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-stxx-defs.h b/drivers/staging/octeon/cvmx-stxx-defs.h new file mode 100644 index 000000000000..4f209b62cae1 --- /dev/null +++ b/drivers/staging/octeon/cvmx-stxx-defs.h | |||
@@ -0,0 +1,292 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_STXX_DEFS_H__ | ||
29 | #define __CVMX_STXX_DEFS_H__ | ||
30 | |||
31 | #define CVMX_STXX_ARB_CTL(block_id) \ | ||
32 | CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull)) | ||
33 | #define CVMX_STXX_BCKPRS_CNT(block_id) \ | ||
34 | CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull)) | ||
35 | #define CVMX_STXX_COM_CTL(block_id) \ | ||
36 | CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull)) | ||
37 | #define CVMX_STXX_DIP_CNT(block_id) \ | ||
38 | CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull)) | ||
39 | #define CVMX_STXX_IGN_CAL(block_id) \ | ||
40 | CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull)) | ||
41 | #define CVMX_STXX_INT_MSK(block_id) \ | ||
42 | CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull)) | ||
43 | #define CVMX_STXX_INT_REG(block_id) \ | ||
44 | CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull)) | ||
45 | #define CVMX_STXX_INT_SYNC(block_id) \ | ||
46 | CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull)) | ||
47 | #define CVMX_STXX_MIN_BST(block_id) \ | ||
48 | CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull)) | ||
49 | #define CVMX_STXX_SPI4_CALX(offset, block_id) \ | ||
50 | CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) | ||
51 | #define CVMX_STXX_SPI4_DAT(block_id) \ | ||
52 | CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull)) | ||
53 | #define CVMX_STXX_SPI4_STAT(block_id) \ | ||
54 | CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull)) | ||
55 | #define CVMX_STXX_STAT_BYTES_HI(block_id) \ | ||
56 | CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull)) | ||
57 | #define CVMX_STXX_STAT_BYTES_LO(block_id) \ | ||
58 | CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull)) | ||
59 | #define CVMX_STXX_STAT_CTL(block_id) \ | ||
60 | CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull)) | ||
61 | #define CVMX_STXX_STAT_PKT_XMT(block_id) \ | ||
62 | CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull)) | ||
63 | |||
64 | union cvmx_stxx_arb_ctl { | ||
65 | uint64_t u64; | ||
66 | struct cvmx_stxx_arb_ctl_s { | ||
67 | uint64_t reserved_6_63:58; | ||
68 | uint64_t mintrn:1; | ||
69 | uint64_t reserved_4_4:1; | ||
70 | uint64_t igntpa:1; | ||
71 | uint64_t reserved_0_2:3; | ||
72 | } s; | ||
73 | struct cvmx_stxx_arb_ctl_s cn38xx; | ||
74 | struct cvmx_stxx_arb_ctl_s cn38xxp2; | ||
75 | struct cvmx_stxx_arb_ctl_s cn58xx; | ||
76 | struct cvmx_stxx_arb_ctl_s cn58xxp1; | ||
77 | }; | ||
78 | |||
79 | union cvmx_stxx_bckprs_cnt { | ||
80 | uint64_t u64; | ||
81 | struct cvmx_stxx_bckprs_cnt_s { | ||
82 | uint64_t reserved_32_63:32; | ||
83 | uint64_t cnt:32; | ||
84 | } s; | ||
85 | struct cvmx_stxx_bckprs_cnt_s cn38xx; | ||
86 | struct cvmx_stxx_bckprs_cnt_s cn38xxp2; | ||
87 | struct cvmx_stxx_bckprs_cnt_s cn58xx; | ||
88 | struct cvmx_stxx_bckprs_cnt_s cn58xxp1; | ||
89 | }; | ||
90 | |||
91 | union cvmx_stxx_com_ctl { | ||
92 | uint64_t u64; | ||
93 | struct cvmx_stxx_com_ctl_s { | ||
94 | uint64_t reserved_4_63:60; | ||
95 | uint64_t st_en:1; | ||
96 | uint64_t reserved_1_2:2; | ||
97 | uint64_t inf_en:1; | ||
98 | } s; | ||
99 | struct cvmx_stxx_com_ctl_s cn38xx; | ||
100 | struct cvmx_stxx_com_ctl_s cn38xxp2; | ||
101 | struct cvmx_stxx_com_ctl_s cn58xx; | ||
102 | struct cvmx_stxx_com_ctl_s cn58xxp1; | ||
103 | }; | ||
104 | |||
105 | union cvmx_stxx_dip_cnt { | ||
106 | uint64_t u64; | ||
107 | struct cvmx_stxx_dip_cnt_s { | ||
108 | uint64_t reserved_8_63:56; | ||
109 | uint64_t frmmax:4; | ||
110 | uint64_t dipmax:4; | ||
111 | } s; | ||
112 | struct cvmx_stxx_dip_cnt_s cn38xx; | ||
113 | struct cvmx_stxx_dip_cnt_s cn38xxp2; | ||
114 | struct cvmx_stxx_dip_cnt_s cn58xx; | ||
115 | struct cvmx_stxx_dip_cnt_s cn58xxp1; | ||
116 | }; | ||
117 | |||
118 | union cvmx_stxx_ign_cal { | ||
119 | uint64_t u64; | ||
120 | struct cvmx_stxx_ign_cal_s { | ||
121 | uint64_t reserved_16_63:48; | ||
122 | uint64_t igntpa:16; | ||
123 | } s; | ||
124 | struct cvmx_stxx_ign_cal_s cn38xx; | ||
125 | struct cvmx_stxx_ign_cal_s cn38xxp2; | ||
126 | struct cvmx_stxx_ign_cal_s cn58xx; | ||
127 | struct cvmx_stxx_ign_cal_s cn58xxp1; | ||
128 | }; | ||
129 | |||
130 | union cvmx_stxx_int_msk { | ||
131 | uint64_t u64; | ||
132 | struct cvmx_stxx_int_msk_s { | ||
133 | uint64_t reserved_8_63:56; | ||
134 | uint64_t frmerr:1; | ||
135 | uint64_t unxfrm:1; | ||
136 | uint64_t nosync:1; | ||
137 | uint64_t diperr:1; | ||
138 | uint64_t datovr:1; | ||
139 | uint64_t ovrbst:1; | ||
140 | uint64_t calpar1:1; | ||
141 | uint64_t calpar0:1; | ||
142 | } s; | ||
143 | struct cvmx_stxx_int_msk_s cn38xx; | ||
144 | struct cvmx_stxx_int_msk_s cn38xxp2; | ||
145 | struct cvmx_stxx_int_msk_s cn58xx; | ||
146 | struct cvmx_stxx_int_msk_s cn58xxp1; | ||
147 | }; | ||
148 | |||
149 | union cvmx_stxx_int_reg { | ||
150 | uint64_t u64; | ||
151 | struct cvmx_stxx_int_reg_s { | ||
152 | uint64_t reserved_9_63:55; | ||
153 | uint64_t syncerr:1; | ||
154 | uint64_t frmerr:1; | ||
155 | uint64_t unxfrm:1; | ||
156 | uint64_t nosync:1; | ||
157 | uint64_t diperr:1; | ||
158 | uint64_t datovr:1; | ||
159 | uint64_t ovrbst:1; | ||
160 | uint64_t calpar1:1; | ||
161 | uint64_t calpar0:1; | ||
162 | } s; | ||
163 | struct cvmx_stxx_int_reg_s cn38xx; | ||
164 | struct cvmx_stxx_int_reg_s cn38xxp2; | ||
165 | struct cvmx_stxx_int_reg_s cn58xx; | ||
166 | struct cvmx_stxx_int_reg_s cn58xxp1; | ||
167 | }; | ||
168 | |||
169 | union cvmx_stxx_int_sync { | ||
170 | uint64_t u64; | ||
171 | struct cvmx_stxx_int_sync_s { | ||
172 | uint64_t reserved_8_63:56; | ||
173 | uint64_t frmerr:1; | ||
174 | uint64_t unxfrm:1; | ||
175 | uint64_t nosync:1; | ||
176 | uint64_t diperr:1; | ||
177 | uint64_t datovr:1; | ||
178 | uint64_t ovrbst:1; | ||
179 | uint64_t calpar1:1; | ||
180 | uint64_t calpar0:1; | ||
181 | } s; | ||
182 | struct cvmx_stxx_int_sync_s cn38xx; | ||
183 | struct cvmx_stxx_int_sync_s cn38xxp2; | ||
184 | struct cvmx_stxx_int_sync_s cn58xx; | ||
185 | struct cvmx_stxx_int_sync_s cn58xxp1; | ||
186 | }; | ||
187 | |||
188 | union cvmx_stxx_min_bst { | ||
189 | uint64_t u64; | ||
190 | struct cvmx_stxx_min_bst_s { | ||
191 | uint64_t reserved_9_63:55; | ||
192 | uint64_t minb:9; | ||
193 | } s; | ||
194 | struct cvmx_stxx_min_bst_s cn38xx; | ||
195 | struct cvmx_stxx_min_bst_s cn38xxp2; | ||
196 | struct cvmx_stxx_min_bst_s cn58xx; | ||
197 | struct cvmx_stxx_min_bst_s cn58xxp1; | ||
198 | }; | ||
199 | |||
200 | union cvmx_stxx_spi4_calx { | ||
201 | uint64_t u64; | ||
202 | struct cvmx_stxx_spi4_calx_s { | ||
203 | uint64_t reserved_17_63:47; | ||
204 | uint64_t oddpar:1; | ||
205 | uint64_t prt3:4; | ||
206 | uint64_t prt2:4; | ||
207 | uint64_t prt1:4; | ||
208 | uint64_t prt0:4; | ||
209 | } s; | ||
210 | struct cvmx_stxx_spi4_calx_s cn38xx; | ||
211 | struct cvmx_stxx_spi4_calx_s cn38xxp2; | ||
212 | struct cvmx_stxx_spi4_calx_s cn58xx; | ||
213 | struct cvmx_stxx_spi4_calx_s cn58xxp1; | ||
214 | }; | ||
215 | |||
216 | union cvmx_stxx_spi4_dat { | ||
217 | uint64_t u64; | ||
218 | struct cvmx_stxx_spi4_dat_s { | ||
219 | uint64_t reserved_32_63:32; | ||
220 | uint64_t alpha:16; | ||
221 | uint64_t max_t:16; | ||
222 | } s; | ||
223 | struct cvmx_stxx_spi4_dat_s cn38xx; | ||
224 | struct cvmx_stxx_spi4_dat_s cn38xxp2; | ||
225 | struct cvmx_stxx_spi4_dat_s cn58xx; | ||
226 | struct cvmx_stxx_spi4_dat_s cn58xxp1; | ||
227 | }; | ||
228 | |||
229 | union cvmx_stxx_spi4_stat { | ||
230 | uint64_t u64; | ||
231 | struct cvmx_stxx_spi4_stat_s { | ||
232 | uint64_t reserved_16_63:48; | ||
233 | uint64_t m:8; | ||
234 | uint64_t reserved_7_7:1; | ||
235 | uint64_t len:7; | ||
236 | } s; | ||
237 | struct cvmx_stxx_spi4_stat_s cn38xx; | ||
238 | struct cvmx_stxx_spi4_stat_s cn38xxp2; | ||
239 | struct cvmx_stxx_spi4_stat_s cn58xx; | ||
240 | struct cvmx_stxx_spi4_stat_s cn58xxp1; | ||
241 | }; | ||
242 | |||
243 | union cvmx_stxx_stat_bytes_hi { | ||
244 | uint64_t u64; | ||
245 | struct cvmx_stxx_stat_bytes_hi_s { | ||
246 | uint64_t reserved_32_63:32; | ||
247 | uint64_t cnt:32; | ||
248 | } s; | ||
249 | struct cvmx_stxx_stat_bytes_hi_s cn38xx; | ||
250 | struct cvmx_stxx_stat_bytes_hi_s cn38xxp2; | ||
251 | struct cvmx_stxx_stat_bytes_hi_s cn58xx; | ||
252 | struct cvmx_stxx_stat_bytes_hi_s cn58xxp1; | ||
253 | }; | ||
254 | |||
255 | union cvmx_stxx_stat_bytes_lo { | ||
256 | uint64_t u64; | ||
257 | struct cvmx_stxx_stat_bytes_lo_s { | ||
258 | uint64_t reserved_32_63:32; | ||
259 | uint64_t cnt:32; | ||
260 | } s; | ||
261 | struct cvmx_stxx_stat_bytes_lo_s cn38xx; | ||
262 | struct cvmx_stxx_stat_bytes_lo_s cn38xxp2; | ||
263 | struct cvmx_stxx_stat_bytes_lo_s cn58xx; | ||
264 | struct cvmx_stxx_stat_bytes_lo_s cn58xxp1; | ||
265 | }; | ||
266 | |||
267 | union cvmx_stxx_stat_ctl { | ||
268 | uint64_t u64; | ||
269 | struct cvmx_stxx_stat_ctl_s { | ||
270 | uint64_t reserved_5_63:59; | ||
271 | uint64_t clr:1; | ||
272 | uint64_t bckprs:4; | ||
273 | } s; | ||
274 | struct cvmx_stxx_stat_ctl_s cn38xx; | ||
275 | struct cvmx_stxx_stat_ctl_s cn38xxp2; | ||
276 | struct cvmx_stxx_stat_ctl_s cn58xx; | ||
277 | struct cvmx_stxx_stat_ctl_s cn58xxp1; | ||
278 | }; | ||
279 | |||
280 | union cvmx_stxx_stat_pkt_xmt { | ||
281 | uint64_t u64; | ||
282 | struct cvmx_stxx_stat_pkt_xmt_s { | ||
283 | uint64_t reserved_32_63:32; | ||
284 | uint64_t cnt:32; | ||
285 | } s; | ||
286 | struct cvmx_stxx_stat_pkt_xmt_s cn38xx; | ||
287 | struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2; | ||
288 | struct cvmx_stxx_stat_pkt_xmt_s cn58xx; | ||
289 | struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1; | ||
290 | }; | ||
291 | |||
292 | #endif | ||
diff --git a/drivers/staging/octeon/cvmx-wqe.h b/drivers/staging/octeon/cvmx-wqe.h new file mode 100644 index 000000000000..653610953d28 --- /dev/null +++ b/drivers/staging/octeon/cvmx-wqe.h | |||
@@ -0,0 +1,397 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * | ||
30 | * This header file defines the work queue entry (wqe) data structure. | ||
31 | * Since this is a commonly used structure that depends on structures | ||
32 | * from several hardware blocks, those definitions have been placed | ||
33 | * in this file to create a single point of definition of the wqe | ||
34 | * format. | ||
35 | * Data structures are still named according to the block that they | ||
36 | * relate to. | ||
37 | * | ||
38 | */ | ||
39 | |||
40 | #ifndef __CVMX_WQE_H__ | ||
41 | #define __CVMX_WQE_H__ | ||
42 | |||
43 | #include "cvmx-packet.h" | ||
44 | |||
45 | |||
46 | #define OCT_TAG_TYPE_STRING(x) \ | ||
47 | (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \ | ||
48 | (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \ | ||
49 | (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \ | ||
50 | "NULL_NULL"))) | ||
51 | |||
52 | /** | ||
53 | * HW decode / err_code in work queue entry | ||
54 | */ | ||
55 | typedef union { | ||
56 | uint64_t u64; | ||
57 | |||
58 | /* Use this struct if the hardware determines that the packet is IP */ | ||
59 | struct { | ||
60 | /* HW sets this to the number of buffers used by this packet */ | ||
61 | uint64_t bufs:8; | ||
62 | /* HW sets to the number of L2 bytes prior to the IP */ | ||
63 | uint64_t ip_offset:8; | ||
64 | /* set to 1 if we found DSA/VLAN in the L2 */ | ||
65 | uint64_t vlan_valid:1; | ||
66 | /* Set to 1 if the DSA/VLAN tag is stacked */ | ||
67 | uint64_t vlan_stacked:1; | ||
68 | uint64_t unassigned:1; | ||
69 | /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */ | ||
70 | uint64_t vlan_cfi:1; | ||
71 | /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */ | ||
72 | uint64_t vlan_id:12; | ||
73 | /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */ | ||
74 | uint64_t pr:4; | ||
75 | uint64_t unassigned2:8; | ||
76 | /* the packet needs to be decompressed */ | ||
77 | uint64_t dec_ipcomp:1; | ||
78 | /* the packet is either TCP or UDP */ | ||
79 | uint64_t tcp_or_udp:1; | ||
80 | /* the packet needs to be decrypted (ESP or AH) */ | ||
81 | uint64_t dec_ipsec:1; | ||
82 | /* the packet is IPv6 */ | ||
83 | uint64_t is_v6:1; | ||
84 | |||
85 | /* | ||
86 | * (rcv_error, not_IP, IP_exc, is_frag, L4_error, | ||
87 | * software, etc.). | ||
88 | */ | ||
89 | |||
90 | /* | ||
91 | * reserved for software use, hardware will clear on | ||
92 | * packet creation. | ||
93 | */ | ||
94 | uint64_t software:1; | ||
95 | /* exceptional conditions below */ | ||
96 | /* the receive interface hardware detected an L4 error | ||
97 | * (only applies if !is_frag) (only applies if | ||
98 | * !rcv_error && !not_IP && !IP_exc && !is_frag) | ||
99 | * failure indicated in err_code below, decode: | ||
100 | * | ||
101 | * - 1 = Malformed L4 | ||
102 | * - 2 = L4 Checksum Error: the L4 checksum value is | ||
103 | * - 3 = UDP Length Error: The UDP length field would | ||
104 | * make the UDP data longer than what remains in | ||
105 | * the IP packet (as defined by the IP header | ||
106 | * length field). | ||
107 | * - 4 = Bad L4 Port: either the source or destination | ||
108 | * TCP/UDP port is 0. | ||
109 | * - 8 = TCP FIN Only: the packet is TCP and only the | ||
110 | * FIN flag set. | ||
111 | * - 9 = TCP No Flags: the packet is TCP and no flags | ||
112 | * are set. | ||
113 | * - 10 = TCP FIN RST: the packet is TCP and both FIN | ||
114 | * and RST are set. | ||
115 | * - 11 = TCP SYN URG: the packet is TCP and both SYN | ||
116 | * and URG are set. | ||
117 | * - 12 = TCP SYN RST: the packet is TCP and both SYN | ||
118 | * and RST are set. | ||
119 | * - 13 = TCP SYN FIN: the packet is TCP and both SYN | ||
120 | * and FIN are set. | ||
121 | */ | ||
122 | uint64_t L4_error:1; | ||
123 | /* set if the packet is a fragment */ | ||
124 | uint64_t is_frag:1; | ||
125 | /* the receive interface hardware detected an IP error | ||
126 | * / exception (only applies if !rcv_error && !not_IP) | ||
127 | * failure indicated in err_code below, decode: | ||
128 | * | ||
129 | * - 1 = Not IP: the IP version field is neither 4 nor | ||
130 | * 6. | ||
131 | * - 2 = IPv4 Header Checksum Error: the IPv4 header | ||
132 | * has a checksum violation. | ||
133 | * - 3 = IP Malformed Header: the packet is not long | ||
134 | * enough to contain the IP header. | ||
135 | * - 4 = IP Malformed: the packet is not long enough | ||
136 | * to contain the bytes indicated by the IP | ||
137 | * header. Pad is allowed. | ||
138 | * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 | ||
139 | * Hop Count field are zero. | ||
140 | * - 6 = IP Options | ||
141 | */ | ||
142 | uint64_t IP_exc:1; | ||
143 | /* | ||
144 | * Set if the hardware determined that the packet is a | ||
145 | * broadcast. | ||
146 | */ | ||
147 | uint64_t is_bcast:1; | ||
148 | /* | ||
149 | * St if the hardware determined that the packet is a | ||
150 | * multi-cast. | ||
151 | */ | ||
152 | uint64_t is_mcast:1; | ||
153 | /* | ||
154 | * Set if the packet may not be IP (must be zero in | ||
155 | * this case). | ||
156 | */ | ||
157 | uint64_t not_IP:1; | ||
158 | /* | ||
159 | * The receive interface hardware detected a receive | ||
160 | * error (must be zero in this case). | ||
161 | */ | ||
162 | uint64_t rcv_error:1; | ||
163 | /* lower err_code = first-level descriptor of the | ||
164 | * work */ | ||
165 | /* zero for packet submitted by hardware that isn't on | ||
166 | * the slow path */ | ||
167 | /* type is cvmx_pip_err_t */ | ||
168 | uint64_t err_code:8; | ||
169 | } s; | ||
170 | |||
171 | /* use this to get at the 16 vlan bits */ | ||
172 | struct { | ||
173 | uint64_t unused1:16; | ||
174 | uint64_t vlan:16; | ||
175 | uint64_t unused2:32; | ||
176 | } svlan; | ||
177 | |||
178 | /* | ||
179 | * use this struct if the hardware could not determine that | ||
180 | * the packet is ip. | ||
181 | */ | ||
182 | struct { | ||
183 | /* | ||
184 | * HW sets this to the number of buffers used by this | ||
185 | * packet. | ||
186 | */ | ||
187 | uint64_t bufs:8; | ||
188 | uint64_t unused:8; | ||
189 | /* set to 1 if we found DSA/VLAN in the L2 */ | ||
190 | uint64_t vlan_valid:1; | ||
191 | /* Set to 1 if the DSA/VLAN tag is stacked */ | ||
192 | uint64_t vlan_stacked:1; | ||
193 | uint64_t unassigned:1; | ||
194 | /* | ||
195 | * HW sets to the DSA/VLAN CFI flag (valid when | ||
196 | * vlan_valid) | ||
197 | */ | ||
198 | uint64_t vlan_cfi:1; | ||
199 | /* | ||
200 | * HW sets to the DSA/VLAN_ID field (valid when | ||
201 | * vlan_valid). | ||
202 | */ | ||
203 | uint64_t vlan_id:12; | ||
204 | /* | ||
205 | * Ring Identifier (if PCIe). Requires | ||
206 | * PIP_GBL_CTL[RING_EN]=1 | ||
207 | */ | ||
208 | uint64_t pr:4; | ||
209 | uint64_t unassigned2:12; | ||
210 | /* | ||
211 | * reserved for software use, hardware will clear on | ||
212 | * packet creation. | ||
213 | */ | ||
214 | uint64_t software:1; | ||
215 | uint64_t unassigned3:1; | ||
216 | /* | ||
217 | * set if the hardware determined that the packet is | ||
218 | * rarp. | ||
219 | */ | ||
220 | uint64_t is_rarp:1; | ||
221 | /* | ||
222 | * set if the hardware determined that the packet is | ||
223 | * arp | ||
224 | */ | ||
225 | uint64_t is_arp:1; | ||
226 | /* | ||
227 | * set if the hardware determined that the packet is a | ||
228 | * broadcast. | ||
229 | */ | ||
230 | uint64_t is_bcast:1; | ||
231 | /* | ||
232 | * set if the hardware determined that the packet is a | ||
233 | * multi-cast | ||
234 | */ | ||
235 | uint64_t is_mcast:1; | ||
236 | /* | ||
237 | * set if the packet may not be IP (must be one in | ||
238 | * this case) | ||
239 | */ | ||
240 | uint64_t not_IP:1; | ||
241 | /* The receive interface hardware detected a receive | ||
242 | * error. Failure indicated in err_code below, | ||
243 | * decode: | ||
244 | * | ||
245 | * - 1 = partial error: a packet was partially | ||
246 | * received, but internal buffering / bandwidth | ||
247 | * was not adequate to receive the entire | ||
248 | * packet. | ||
249 | * - 2 = jabber error: the RGMII packet was too large | ||
250 | * and is truncated. | ||
251 | * - 3 = overrun error: the RGMII packet is longer | ||
252 | * than allowed and had an FCS error. | ||
253 | * - 4 = oversize error: the RGMII packet is longer | ||
254 | * than allowed. | ||
255 | * - 5 = alignment error: the RGMII packet is not an | ||
256 | * integer number of bytes | ||
257 | * and had an FCS error (100M and 10M only). | ||
258 | * - 6 = fragment error: the RGMII packet is shorter | ||
259 | * than allowed and had an FCS error. | ||
260 | * - 7 = GMX FCS error: the RGMII packet had an FCS | ||
261 | * error. | ||
262 | * - 8 = undersize error: the RGMII packet is shorter | ||
263 | * than allowed. | ||
264 | * - 9 = extend error: the RGMII packet had an extend | ||
265 | * error. | ||
266 | * - 10 = length mismatch error: the RGMII packet had | ||
267 | * a length that did not match the length field | ||
268 | * in the L2 HDR. | ||
269 | * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII | ||
270 | * packet had one or more data reception errors | ||
271 | * (RXERR) or the SPI4 packet had one or more | ||
272 | * DIP4 errors. | ||
273 | * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII | ||
274 | * packet was not large enough to cover the | ||
275 | * skipped bytes or the SPI4 packet was | ||
276 | * terminated with an About EOPS. | ||
277 | * - 13 = RGMII nibble error/SPI4 Port NXA Error: the | ||
278 | * RGMII packet had a studder error (data not | ||
279 | * repeated - 10/100M only) or the SPI4 packet | ||
280 | * was sent to an NXA. | ||
281 | * - 16 = FCS error: a SPI4.2 packet had an FCS error. | ||
282 | * - 17 = Skip error: a packet was not large enough to | ||
283 | * cover the skipped bytes. | ||
284 | * - 18 = L2 header malformed: the packet is not long | ||
285 | * enough to contain the L2. | ||
286 | */ | ||
287 | |||
288 | uint64_t rcv_error:1; | ||
289 | /* | ||
290 | * lower err_code = first-level descriptor of the | ||
291 | * work | ||
292 | */ | ||
293 | /* | ||
294 | * zero for packet submitted by hardware that isn't on | ||
295 | * the slow path | ||
296 | */ | ||
297 | /* type is cvmx_pip_err_t (union, so can't use directly */ | ||
298 | uint64_t err_code:8; | ||
299 | } snoip; | ||
300 | |||
301 | } cvmx_pip_wqe_word2; | ||
302 | |||
303 | /** | ||
304 | * Work queue entry format | ||
305 | * | ||
306 | * must be 8-byte aligned | ||
307 | */ | ||
308 | typedef struct { | ||
309 | |||
310 | /***************************************************************** | ||
311 | * WORD 0 | ||
312 | * HW WRITE: the following 64 bits are filled by HW when a packet arrives | ||
313 | */ | ||
314 | |||
315 | /** | ||
316 | * raw chksum result generated by the HW | ||
317 | */ | ||
318 | uint16_t hw_chksum; | ||
319 | /** | ||
320 | * Field unused by hardware - available for software | ||
321 | */ | ||
322 | uint8_t unused; | ||
323 | /** | ||
324 | * Next pointer used by hardware for list maintenance. | ||
325 | * May be written/read by HW before the work queue | ||
326 | * entry is scheduled to a PP | ||
327 | * (Only 36 bits used in Octeon 1) | ||
328 | */ | ||
329 | uint64_t next_ptr:40; | ||
330 | |||
331 | /***************************************************************** | ||
332 | * WORD 1 | ||
333 | * HW WRITE: the following 64 bits are filled by HW when a packet arrives | ||
334 | */ | ||
335 | |||
336 | /** | ||
337 | * HW sets to the total number of bytes in the packet | ||
338 | */ | ||
339 | uint64_t len:16; | ||
340 | /** | ||
341 | * HW sets this to input physical port | ||
342 | */ | ||
343 | uint64_t ipprt:6; | ||
344 | |||
345 | /** | ||
346 | * HW sets this to what it thought the priority of the input packet was | ||
347 | */ | ||
348 | uint64_t qos:3; | ||
349 | |||
350 | /** | ||
351 | * the group that the work queue entry will be scheduled to | ||
352 | */ | ||
353 | uint64_t grp:4; | ||
354 | /** | ||
355 | * the type of the tag (ORDERED, ATOMIC, NULL) | ||
356 | */ | ||
357 | uint64_t tag_type:3; | ||
358 | /** | ||
359 | * the synchronization/ordering tag | ||
360 | */ | ||
361 | uint64_t tag:32; | ||
362 | |||
363 | /** | ||
364 | * WORD 2 HW WRITE: the following 64-bits are filled in by | ||
365 | * hardware when a packet arrives This indicates a variety of | ||
366 | * status and error conditions. | ||
367 | */ | ||
368 | cvmx_pip_wqe_word2 word2; | ||
369 | |||
370 | /** | ||
371 | * Pointer to the first segment of the packet. | ||
372 | */ | ||
373 | union cvmx_buf_ptr packet_ptr; | ||
374 | |||
375 | /** | ||
376 | * HW WRITE: octeon will fill in a programmable amount from the | ||
377 | * packet, up to (at most, but perhaps less) the amount | ||
378 | * needed to fill the work queue entry to 128 bytes | ||
379 | * | ||
380 | * If the packet is recognized to be IP, the hardware starts | ||
381 | * (except that the IPv4 header is padded for appropriate | ||
382 | * alignment) writing here where the IP header starts. If the | ||
383 | * packet is not recognized to be IP, the hardware starts | ||
384 | * writing the beginning of the packet here. | ||
385 | */ | ||
386 | uint8_t packet_data[96]; | ||
387 | |||
388 | /** | ||
389 | * If desired, SW can make the work Q entry any length. For the | ||
390 | * purposes of discussion here, Assume 128B always, as this is all that | ||
391 | * the hardware deals with. | ||
392 | * | ||
393 | */ | ||
394 | |||
395 | } CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t; | ||
396 | |||
397 | #endif /* __CVMX_WQE_H__ */ | ||
diff --git a/drivers/staging/octeon/ethernet-common.c b/drivers/staging/octeon/ethernet-common.c new file mode 100644 index 000000000000..3e6f5b8cc63d --- /dev/null +++ b/drivers/staging/octeon/ethernet-common.c | |||
@@ -0,0 +1,328 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/mii.h> | ||
29 | #include <net/dst.h> | ||
30 | |||
31 | #include <asm/atomic.h> | ||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "ethernet-defines.h" | ||
35 | #include "ethernet-tx.h" | ||
36 | #include "ethernet-mdio.h" | ||
37 | #include "ethernet-util.h" | ||
38 | #include "octeon-ethernet.h" | ||
39 | #include "ethernet-common.h" | ||
40 | |||
41 | #include "cvmx-pip.h" | ||
42 | #include "cvmx-pko.h" | ||
43 | #include "cvmx-fau.h" | ||
44 | #include "cvmx-helper.h" | ||
45 | |||
46 | #include "cvmx-gmxx-defs.h" | ||
47 | |||
48 | /** | ||
49 | * Get the low level ethernet statistics | ||
50 | * | ||
51 | * @dev: Device to get the statistics from | ||
52 | * Returns Pointer to the statistics | ||
53 | */ | ||
54 | static struct net_device_stats *cvm_oct_common_get_stats(struct net_device *dev) | ||
55 | { | ||
56 | cvmx_pip_port_status_t rx_status; | ||
57 | cvmx_pko_port_status_t tx_status; | ||
58 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
59 | |||
60 | if (priv->port < CVMX_PIP_NUM_INPUT_PORTS) { | ||
61 | if (octeon_is_simulation()) { | ||
62 | /* The simulator doesn't support statistics */ | ||
63 | memset(&rx_status, 0, sizeof(rx_status)); | ||
64 | memset(&tx_status, 0, sizeof(tx_status)); | ||
65 | } else { | ||
66 | cvmx_pip_get_port_status(priv->port, 1, &rx_status); | ||
67 | cvmx_pko_get_port_status(priv->port, 1, &tx_status); | ||
68 | } | ||
69 | |||
70 | priv->stats.rx_packets += rx_status.inb_packets; | ||
71 | priv->stats.tx_packets += tx_status.packets; | ||
72 | priv->stats.rx_bytes += rx_status.inb_octets; | ||
73 | priv->stats.tx_bytes += tx_status.octets; | ||
74 | priv->stats.multicast += rx_status.multicast_packets; | ||
75 | priv->stats.rx_crc_errors += rx_status.inb_errors; | ||
76 | priv->stats.rx_frame_errors += rx_status.fcs_align_err_packets; | ||
77 | |||
78 | /* | ||
79 | * The drop counter must be incremented atomically | ||
80 | * since the RX tasklet also increments it. | ||
81 | */ | ||
82 | #ifdef CONFIG_64BIT | ||
83 | atomic64_add(rx_status.dropped_packets, | ||
84 | (atomic64_t *)&priv->stats.rx_dropped); | ||
85 | #else | ||
86 | atomic_add(rx_status.dropped_packets, | ||
87 | (atomic_t *)&priv->stats.rx_dropped); | ||
88 | #endif | ||
89 | } | ||
90 | |||
91 | return &priv->stats; | ||
92 | } | ||
93 | |||
94 | /** | ||
95 | * Set the multicast list. Currently unimplemented. | ||
96 | * | ||
97 | * @dev: Device to work on | ||
98 | */ | ||
99 | static void cvm_oct_common_set_multicast_list(struct net_device *dev) | ||
100 | { | ||
101 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
102 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
103 | int interface = INTERFACE(priv->port); | ||
104 | int index = INDEX(priv->port); | ||
105 | |||
106 | if ((interface < 2) | ||
107 | && (cvmx_helper_interface_get_mode(interface) != | ||
108 | CVMX_HELPER_INTERFACE_MODE_SPI)) { | ||
109 | union cvmx_gmxx_rxx_adr_ctl control; | ||
110 | control.u64 = 0; | ||
111 | control.s.bcst = 1; /* Allow broadcast MAC addresses */ | ||
112 | |||
113 | if (dev->mc_list || (dev->flags & IFF_ALLMULTI) || | ||
114 | (dev->flags & IFF_PROMISC)) | ||
115 | /* Force accept multicast packets */ | ||
116 | control.s.mcst = 2; | ||
117 | else | ||
118 | /* Force reject multicat packets */ | ||
119 | control.s.mcst = 1; | ||
120 | |||
121 | if (dev->flags & IFF_PROMISC) | ||
122 | /* | ||
123 | * Reject matches if promisc. Since CAM is | ||
124 | * shut off, should accept everything. | ||
125 | */ | ||
126 | control.s.cam_mode = 0; | ||
127 | else | ||
128 | /* Filter packets based on the CAM */ | ||
129 | control.s.cam_mode = 1; | ||
130 | |||
131 | gmx_cfg.u64 = | ||
132 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
133 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), | ||
134 | gmx_cfg.u64 & ~1ull); | ||
135 | |||
136 | cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface), | ||
137 | control.u64); | ||
138 | if (dev->flags & IFF_PROMISC) | ||
139 | cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN | ||
140 | (index, interface), 0); | ||
141 | else | ||
142 | cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN | ||
143 | (index, interface), 1); | ||
144 | |||
145 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), | ||
146 | gmx_cfg.u64); | ||
147 | } | ||
148 | } | ||
149 | |||
150 | /** | ||
151 | * Set the hardware MAC address for a device | ||
152 | * | ||
153 | * @dev: Device to change the MAC address for | ||
154 | * @addr: Address structure to change it too. MAC address is addr + 2. | ||
155 | * Returns Zero on success | ||
156 | */ | ||
157 | static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) | ||
158 | { | ||
159 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
160 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
161 | int interface = INTERFACE(priv->port); | ||
162 | int index = INDEX(priv->port); | ||
163 | |||
164 | memcpy(dev->dev_addr, addr + 2, 6); | ||
165 | |||
166 | if ((interface < 2) | ||
167 | && (cvmx_helper_interface_get_mode(interface) != | ||
168 | CVMX_HELPER_INTERFACE_MODE_SPI)) { | ||
169 | int i; | ||
170 | uint8_t *ptr = addr; | ||
171 | uint64_t mac = 0; | ||
172 | for (i = 0; i < 6; i++) | ||
173 | mac = (mac << 8) | (uint64_t) (ptr[i + 2]); | ||
174 | |||
175 | gmx_cfg.u64 = | ||
176 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
177 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), | ||
178 | gmx_cfg.u64 & ~1ull); | ||
179 | |||
180 | cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac); | ||
181 | cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface), | ||
182 | ptr[2]); | ||
183 | cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface), | ||
184 | ptr[3]); | ||
185 | cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface), | ||
186 | ptr[4]); | ||
187 | cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface), | ||
188 | ptr[5]); | ||
189 | cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface), | ||
190 | ptr[6]); | ||
191 | cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface), | ||
192 | ptr[7]); | ||
193 | cvm_oct_common_set_multicast_list(dev); | ||
194 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), | ||
195 | gmx_cfg.u64); | ||
196 | } | ||
197 | return 0; | ||
198 | } | ||
199 | |||
200 | /** | ||
201 | * Change the link MTU. Unimplemented | ||
202 | * | ||
203 | * @dev: Device to change | ||
204 | * @new_mtu: The new MTU | ||
205 | * | ||
206 | * Returns Zero on success | ||
207 | */ | ||
208 | static int cvm_oct_common_change_mtu(struct net_device *dev, int new_mtu) | ||
209 | { | ||
210 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
211 | int interface = INTERFACE(priv->port); | ||
212 | int index = INDEX(priv->port); | ||
213 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | ||
214 | int vlan_bytes = 4; | ||
215 | #else | ||
216 | int vlan_bytes = 0; | ||
217 | #endif | ||
218 | |||
219 | /* | ||
220 | * Limit the MTU to make sure the ethernet packets are between | ||
221 | * 64 bytes and 65535 bytes. | ||
222 | */ | ||
223 | if ((new_mtu + 14 + 4 + vlan_bytes < 64) | ||
224 | || (new_mtu + 14 + 4 + vlan_bytes > 65392)) { | ||
225 | pr_err("MTU must be between %d and %d.\n", | ||
226 | 64 - 14 - 4 - vlan_bytes, 65392 - 14 - 4 - vlan_bytes); | ||
227 | return -EINVAL; | ||
228 | } | ||
229 | dev->mtu = new_mtu; | ||
230 | |||
231 | if ((interface < 2) | ||
232 | && (cvmx_helper_interface_get_mode(interface) != | ||
233 | CVMX_HELPER_INTERFACE_MODE_SPI)) { | ||
234 | /* Add ethernet header and FCS, and VLAN if configured. */ | ||
235 | int max_packet = new_mtu + 14 + 4 + vlan_bytes; | ||
236 | |||
237 | if (OCTEON_IS_MODEL(OCTEON_CN3XXX) | ||
238 | || OCTEON_IS_MODEL(OCTEON_CN58XX)) { | ||
239 | /* Signal errors on packets larger than the MTU */ | ||
240 | cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(index, interface), | ||
241 | max_packet); | ||
242 | } else { | ||
243 | /* | ||
244 | * Set the hardware to truncate packets larger | ||
245 | * than the MTU and smaller the 64 bytes. | ||
246 | */ | ||
247 | union cvmx_pip_frm_len_chkx frm_len_chk; | ||
248 | frm_len_chk.u64 = 0; | ||
249 | frm_len_chk.s.minlen = 64; | ||
250 | frm_len_chk.s.maxlen = max_packet; | ||
251 | cvmx_write_csr(CVMX_PIP_FRM_LEN_CHKX(interface), | ||
252 | frm_len_chk.u64); | ||
253 | } | ||
254 | /* | ||
255 | * Set the hardware to truncate packets larger than | ||
256 | * the MTU. The jabber register must be set to a | ||
257 | * multiple of 8 bytes, so round up. | ||
258 | */ | ||
259 | cvmx_write_csr(CVMX_GMXX_RXX_JABBER(index, interface), | ||
260 | (max_packet + 7) & ~7u); | ||
261 | } | ||
262 | return 0; | ||
263 | } | ||
264 | |||
265 | /** | ||
266 | * Per network device initialization | ||
267 | * | ||
268 | * @dev: Device to initialize | ||
269 | * Returns Zero on success | ||
270 | */ | ||
271 | int cvm_oct_common_init(struct net_device *dev) | ||
272 | { | ||
273 | static int count; | ||
274 | char mac[8] = { 0x00, 0x00, | ||
275 | octeon_bootinfo->mac_addr_base[0], | ||
276 | octeon_bootinfo->mac_addr_base[1], | ||
277 | octeon_bootinfo->mac_addr_base[2], | ||
278 | octeon_bootinfo->mac_addr_base[3], | ||
279 | octeon_bootinfo->mac_addr_base[4], | ||
280 | octeon_bootinfo->mac_addr_base[5] + count | ||
281 | }; | ||
282 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
283 | |||
284 | /* | ||
285 | * Force the interface to use the POW send if always_use_pow | ||
286 | * was specified or it is in the pow send list. | ||
287 | */ | ||
288 | if ((pow_send_group != -1) | ||
289 | && (always_use_pow || strstr(pow_send_list, dev->name))) | ||
290 | priv->queue = -1; | ||
291 | |||
292 | if (priv->queue != -1) { | ||
293 | dev->hard_start_xmit = cvm_oct_xmit; | ||
294 | if (USE_HW_TCPUDP_CHECKSUM) | ||
295 | dev->features |= NETIF_F_IP_CSUM; | ||
296 | } else | ||
297 | dev->hard_start_xmit = cvm_oct_xmit_pow; | ||
298 | count++; | ||
299 | |||
300 | dev->get_stats = cvm_oct_common_get_stats; | ||
301 | dev->set_mac_address = cvm_oct_common_set_mac_address; | ||
302 | dev->set_multicast_list = cvm_oct_common_set_multicast_list; | ||
303 | dev->change_mtu = cvm_oct_common_change_mtu; | ||
304 | dev->do_ioctl = cvm_oct_ioctl; | ||
305 | /* We do our own locking, Linux doesn't need to */ | ||
306 | dev->features |= NETIF_F_LLTX; | ||
307 | SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops); | ||
308 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
309 | dev->poll_controller = cvm_oct_poll_controller; | ||
310 | #endif | ||
311 | |||
312 | cvm_oct_mdio_setup_device(dev); | ||
313 | dev->set_mac_address(dev, mac); | ||
314 | dev->change_mtu(dev, dev->mtu); | ||
315 | |||
316 | /* | ||
317 | * Zero out stats for port so we won't mistakenly show | ||
318 | * counters from the bootloader. | ||
319 | */ | ||
320 | memset(dev->get_stats(dev), 0, sizeof(struct net_device_stats)); | ||
321 | |||
322 | return 0; | ||
323 | } | ||
324 | |||
325 | void cvm_oct_common_uninit(struct net_device *dev) | ||
326 | { | ||
327 | /* Currently nothing to do */ | ||
328 | } | ||
diff --git a/drivers/staging/octeon/ethernet-common.h b/drivers/staging/octeon/ethernet-common.h new file mode 100644 index 000000000000..2bd9cd76a398 --- /dev/null +++ b/drivers/staging/octeon/ethernet-common.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /********************************************************************* | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | *********************************************************************/ | ||
27 | |||
28 | int cvm_oct_common_init(struct net_device *dev); | ||
29 | void cvm_oct_common_uninit(struct net_device *dev); | ||
diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h new file mode 100644 index 000000000000..8f7374e7664c --- /dev/null +++ b/drivers/staging/octeon/ethernet-defines.h | |||
@@ -0,0 +1,134 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | |||
28 | /* | ||
29 | * A few defines are used to control the operation of this driver: | ||
30 | * CONFIG_CAVIUM_RESERVE32 | ||
31 | * This kernel config options controls the amount of memory configured | ||
32 | * in a wired TLB entry for all processes to share. If this is set, the | ||
33 | * driver will use this memory instead of kernel memory for pools. This | ||
34 | * allows 32bit userspace application to access the buffers, but also | ||
35 | * requires all received packets to be copied. | ||
36 | * CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS | ||
37 | * This kernel config option allows the user to control the number of | ||
38 | * packet and work queue buffers allocated by the driver. If this is zero, | ||
39 | * the driver uses the default from below. | ||
40 | * USE_SKBUFFS_IN_HW | ||
41 | * Tells the driver to populate the packet buffers with kernel skbuffs. | ||
42 | * This allows the driver to receive packets without copying them. It also | ||
43 | * means that 32bit userspace can't access the packet buffers. | ||
44 | * USE_32BIT_SHARED | ||
45 | * This define tells the driver to allocate memory for buffers from the | ||
46 | * 32bit sahred region instead of the kernel memory space. | ||
47 | * USE_HW_TCPUDP_CHECKSUM | ||
48 | * Controls if the Octeon TCP/UDP checksum engine is used for packet | ||
49 | * output. If this is zero, the kernel will perform the checksum in | ||
50 | * software. | ||
51 | * USE_MULTICORE_RECEIVE | ||
52 | * Process receive interrupts on multiple cores. This spreads the network | ||
53 | * load across the first 8 processors. If ths is zero, only one core | ||
54 | * processes incomming packets. | ||
55 | * USE_ASYNC_IOBDMA | ||
56 | * Use asynchronous IO access to hardware. This uses Octeon's asynchronous | ||
57 | * IOBDMAs to issue IO accesses without stalling. Set this to zero | ||
58 | * to disable this. Note that IOBDMAs require CVMSEG. | ||
59 | * REUSE_SKBUFFS_WITHOUT_FREE | ||
60 | * Allows the TX path to free an skbuff into the FPA hardware pool. This | ||
61 | * can significantly improve performance for forwarding and bridging, but | ||
62 | * may be somewhat dangerous. Checks are made, but if any buffer is reused | ||
63 | * without the proper Linux cleanup, the networking stack may have very | ||
64 | * bizarre bugs. | ||
65 | */ | ||
66 | #ifndef __ETHERNET_DEFINES_H__ | ||
67 | #define __ETHERNET_DEFINES_H__ | ||
68 | |||
69 | #include "cvmx-config.h" | ||
70 | |||
71 | |||
72 | #define OCTEON_ETHERNET_VERSION "1.9" | ||
73 | |||
74 | #ifndef CONFIG_CAVIUM_RESERVE32 | ||
75 | #define CONFIG_CAVIUM_RESERVE32 0 | ||
76 | #endif | ||
77 | |||
78 | #if CONFIG_CAVIUM_RESERVE32 | ||
79 | #define USE_32BIT_SHARED 1 | ||
80 | #define USE_SKBUFFS_IN_HW 0 | ||
81 | #define REUSE_SKBUFFS_WITHOUT_FREE 0 | ||
82 | #else | ||
83 | #define USE_32BIT_SHARED 0 | ||
84 | #define USE_SKBUFFS_IN_HW 1 | ||
85 | #ifdef CONFIG_NETFILTER | ||
86 | #define REUSE_SKBUFFS_WITHOUT_FREE 0 | ||
87 | #else | ||
88 | #define REUSE_SKBUFFS_WITHOUT_FREE 1 | ||
89 | #endif | ||
90 | #endif | ||
91 | |||
92 | /* Max interrupts per second per core */ | ||
93 | #define INTERRUPT_LIMIT 10000 | ||
94 | |||
95 | /* Don't limit the number of interrupts */ | ||
96 | /*#define INTERRUPT_LIMIT 0 */ | ||
97 | #define USE_HW_TCPUDP_CHECKSUM 1 | ||
98 | |||
99 | #define USE_MULTICORE_RECEIVE 1 | ||
100 | |||
101 | /* Enable Random Early Dropping under load */ | ||
102 | #define USE_RED 1 | ||
103 | #define USE_ASYNC_IOBDMA (CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0) | ||
104 | |||
105 | /* | ||
106 | * Allow SW based preamble removal at 10Mbps to workaround PHYs giving | ||
107 | * us bad preambles. | ||
108 | */ | ||
109 | #define USE_10MBPS_PREAMBLE_WORKAROUND 1 | ||
110 | /* | ||
111 | * Use this to have all FPA frees also tell the L2 not to write data | ||
112 | * to memory. | ||
113 | */ | ||
114 | #define DONT_WRITEBACK(x) (x) | ||
115 | /* Use this to not have FPA frees control L2 */ | ||
116 | /*#define DONT_WRITEBACK(x) 0 */ | ||
117 | |||
118 | /* Maximum number of packets to process per interrupt. */ | ||
119 | #define MAX_RX_PACKETS 120 | ||
120 | #define MAX_OUT_QUEUE_DEPTH 1000 | ||
121 | |||
122 | #ifndef CONFIG_SMP | ||
123 | #undef USE_MULTICORE_RECEIVE | ||
124 | #define USE_MULTICORE_RECEIVE 0 | ||
125 | #endif | ||
126 | |||
127 | #define IP_PROTOCOL_TCP 6 | ||
128 | #define IP_PROTOCOL_UDP 0x11 | ||
129 | |||
130 | #define FAU_NUM_PACKET_BUFFERS_TO_FREE (CVMX_FAU_REG_END - sizeof(uint32_t)) | ||
131 | #define TOTAL_NUMBER_OF_PORTS (CVMX_PIP_NUM_INPUT_PORTS+1) | ||
132 | |||
133 | |||
134 | #endif /* __ETHERNET_DEFINES_H__ */ | ||
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c new file mode 100644 index 000000000000..93cab0a48925 --- /dev/null +++ b/drivers/staging/octeon/ethernet-mdio.c | |||
@@ -0,0 +1,231 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/ethtool.h> | ||
29 | #include <linux/mii.h> | ||
30 | #include <net/dst.h> | ||
31 | |||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "ethernet-defines.h" | ||
35 | #include "octeon-ethernet.h" | ||
36 | #include "ethernet-mdio.h" | ||
37 | |||
38 | #include "cvmx-helper-board.h" | ||
39 | |||
40 | #include "cvmx-smix-defs.h" | ||
41 | |||
42 | DECLARE_MUTEX(mdio_sem); | ||
43 | |||
44 | /** | ||
45 | * Perform an MII read. Called by the generic MII routines | ||
46 | * | ||
47 | * @dev: Device to perform read for | ||
48 | * @phy_id: The MII phy id | ||
49 | * @location: Register location to read | ||
50 | * Returns Result from the read or zero on failure | ||
51 | */ | ||
52 | static int cvm_oct_mdio_read(struct net_device *dev, int phy_id, int location) | ||
53 | { | ||
54 | union cvmx_smix_cmd smi_cmd; | ||
55 | union cvmx_smix_rd_dat smi_rd; | ||
56 | |||
57 | smi_cmd.u64 = 0; | ||
58 | smi_cmd.s.phy_op = 1; | ||
59 | smi_cmd.s.phy_adr = phy_id; | ||
60 | smi_cmd.s.reg_adr = location; | ||
61 | cvmx_write_csr(CVMX_SMIX_CMD(0), smi_cmd.u64); | ||
62 | |||
63 | do { | ||
64 | if (!in_interrupt()) | ||
65 | yield(); | ||
66 | smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(0)); | ||
67 | } while (smi_rd.s.pending); | ||
68 | |||
69 | if (smi_rd.s.val) | ||
70 | return smi_rd.s.dat; | ||
71 | else | ||
72 | return 0; | ||
73 | } | ||
74 | |||
75 | static int cvm_oct_mdio_dummy_read(struct net_device *dev, int phy_id, | ||
76 | int location) | ||
77 | { | ||
78 | return 0xffff; | ||
79 | } | ||
80 | |||
81 | /** | ||
82 | * Perform an MII write. Called by the generic MII routines | ||
83 | * | ||
84 | * @dev: Device to perform write for | ||
85 | * @phy_id: The MII phy id | ||
86 | * @location: Register location to write | ||
87 | * @val: Value to write | ||
88 | */ | ||
89 | static void cvm_oct_mdio_write(struct net_device *dev, int phy_id, int location, | ||
90 | int val) | ||
91 | { | ||
92 | union cvmx_smix_cmd smi_cmd; | ||
93 | union cvmx_smix_wr_dat smi_wr; | ||
94 | |||
95 | smi_wr.u64 = 0; | ||
96 | smi_wr.s.dat = val; | ||
97 | cvmx_write_csr(CVMX_SMIX_WR_DAT(0), smi_wr.u64); | ||
98 | |||
99 | smi_cmd.u64 = 0; | ||
100 | smi_cmd.s.phy_op = 0; | ||
101 | smi_cmd.s.phy_adr = phy_id; | ||
102 | smi_cmd.s.reg_adr = location; | ||
103 | cvmx_write_csr(CVMX_SMIX_CMD(0), smi_cmd.u64); | ||
104 | |||
105 | do { | ||
106 | if (!in_interrupt()) | ||
107 | yield(); | ||
108 | smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(0)); | ||
109 | } while (smi_wr.s.pending); | ||
110 | } | ||
111 | |||
112 | static void cvm_oct_mdio_dummy_write(struct net_device *dev, int phy_id, | ||
113 | int location, int val) | ||
114 | { | ||
115 | } | ||
116 | |||
117 | static void cvm_oct_get_drvinfo(struct net_device *dev, | ||
118 | struct ethtool_drvinfo *info) | ||
119 | { | ||
120 | strcpy(info->driver, "cavium-ethernet"); | ||
121 | strcpy(info->version, OCTEON_ETHERNET_VERSION); | ||
122 | strcpy(info->bus_info, "Builtin"); | ||
123 | } | ||
124 | |||
125 | static int cvm_oct_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
126 | { | ||
127 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
128 | int ret; | ||
129 | |||
130 | down(&mdio_sem); | ||
131 | ret = mii_ethtool_gset(&priv->mii_info, cmd); | ||
132 | up(&mdio_sem); | ||
133 | |||
134 | return ret; | ||
135 | } | ||
136 | |||
137 | static int cvm_oct_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
138 | { | ||
139 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
140 | int ret; | ||
141 | |||
142 | down(&mdio_sem); | ||
143 | ret = mii_ethtool_sset(&priv->mii_info, cmd); | ||
144 | up(&mdio_sem); | ||
145 | |||
146 | return ret; | ||
147 | } | ||
148 | |||
149 | static int cvm_oct_nway_reset(struct net_device *dev) | ||
150 | { | ||
151 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
152 | int ret; | ||
153 | |||
154 | down(&mdio_sem); | ||
155 | ret = mii_nway_restart(&priv->mii_info); | ||
156 | up(&mdio_sem); | ||
157 | |||
158 | return ret; | ||
159 | } | ||
160 | |||
161 | static u32 cvm_oct_get_link(struct net_device *dev) | ||
162 | { | ||
163 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
164 | u32 ret; | ||
165 | |||
166 | down(&mdio_sem); | ||
167 | ret = mii_link_ok(&priv->mii_info); | ||
168 | up(&mdio_sem); | ||
169 | |||
170 | return ret; | ||
171 | } | ||
172 | |||
173 | struct ethtool_ops cvm_oct_ethtool_ops = { | ||
174 | .get_drvinfo = cvm_oct_get_drvinfo, | ||
175 | .get_settings = cvm_oct_get_settings, | ||
176 | .set_settings = cvm_oct_set_settings, | ||
177 | .nway_reset = cvm_oct_nway_reset, | ||
178 | .get_link = cvm_oct_get_link, | ||
179 | .get_sg = ethtool_op_get_sg, | ||
180 | .get_tx_csum = ethtool_op_get_tx_csum, | ||
181 | }; | ||
182 | |||
183 | /** | ||
184 | * IOCTL support for PHY control | ||
185 | * | ||
186 | * @dev: Device to change | ||
187 | * @rq: the request | ||
188 | * @cmd: the command | ||
189 | * Returns Zero on success | ||
190 | */ | ||
191 | int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | ||
192 | { | ||
193 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
194 | struct mii_ioctl_data *data = if_mii(rq); | ||
195 | unsigned int duplex_chg; | ||
196 | int ret; | ||
197 | |||
198 | down(&mdio_sem); | ||
199 | ret = generic_mii_ioctl(&priv->mii_info, data, cmd, &duplex_chg); | ||
200 | up(&mdio_sem); | ||
201 | |||
202 | return ret; | ||
203 | } | ||
204 | |||
205 | /** | ||
206 | * Setup the MDIO device structures | ||
207 | * | ||
208 | * @dev: Device to setup | ||
209 | * | ||
210 | * Returns Zero on success, negative on failure | ||
211 | */ | ||
212 | int cvm_oct_mdio_setup_device(struct net_device *dev) | ||
213 | { | ||
214 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
215 | int phy_id = cvmx_helper_board_get_mii_address(priv->port); | ||
216 | if (phy_id != -1) { | ||
217 | priv->mii_info.dev = dev; | ||
218 | priv->mii_info.phy_id = phy_id; | ||
219 | priv->mii_info.phy_id_mask = 0xff; | ||
220 | priv->mii_info.supports_gmii = 1; | ||
221 | priv->mii_info.reg_num_mask = 0x1f; | ||
222 | priv->mii_info.mdio_read = cvm_oct_mdio_read; | ||
223 | priv->mii_info.mdio_write = cvm_oct_mdio_write; | ||
224 | } else { | ||
225 | /* Supply dummy MDIO routines so the kernel won't crash | ||
226 | if the user tries to read them */ | ||
227 | priv->mii_info.mdio_read = cvm_oct_mdio_dummy_read; | ||
228 | priv->mii_info.mdio_write = cvm_oct_mdio_dummy_write; | ||
229 | } | ||
230 | return 0; | ||
231 | } | ||
diff --git a/drivers/staging/octeon/ethernet-mdio.h b/drivers/staging/octeon/ethernet-mdio.h new file mode 100644 index 000000000000..6314141e5ef2 --- /dev/null +++ b/drivers/staging/octeon/ethernet-mdio.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /********************************************************************* | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | *********************************************************************/ | ||
27 | #include <linux/module.h> | ||
28 | #include <linux/kernel.h> | ||
29 | #include <linux/netdevice.h> | ||
30 | #include <linux/init.h> | ||
31 | #include <linux/etherdevice.h> | ||
32 | #include <linux/ip.h> | ||
33 | #include <linux/string.h> | ||
34 | #include <linux/ethtool.h> | ||
35 | #include <linux/mii.h> | ||
36 | #include <linux/seq_file.h> | ||
37 | #include <linux/proc_fs.h> | ||
38 | #include <net/dst.h> | ||
39 | #ifdef CONFIG_XFRM | ||
40 | #include <linux/xfrm.h> | ||
41 | #include <net/xfrm.h> | ||
42 | #endif /* CONFIG_XFRM */ | ||
43 | |||
44 | extern struct ethtool_ops cvm_oct_ethtool_ops; | ||
45 | int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | ||
46 | int cvm_oct_mdio_setup_device(struct net_device *dev); | ||
diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c new file mode 100644 index 000000000000..b595903e2af1 --- /dev/null +++ b/drivers/staging/octeon/ethernet-mem.c | |||
@@ -0,0 +1,198 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/netdevice.h> | ||
29 | #include <linux/mii.h> | ||
30 | #include <net/dst.h> | ||
31 | |||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "ethernet-defines.h" | ||
35 | |||
36 | #include "cvmx-fpa.h" | ||
37 | |||
38 | /** | ||
39 | * Fill the supplied hardware pool with skbuffs | ||
40 | * | ||
41 | * @pool: Pool to allocate an skbuff for | ||
42 | * @size: Size of the buffer needed for the pool | ||
43 | * @elements: Number of buffers to allocate | ||
44 | */ | ||
45 | static int cvm_oct_fill_hw_skbuff(int pool, int size, int elements) | ||
46 | { | ||
47 | int freed = elements; | ||
48 | while (freed) { | ||
49 | |||
50 | struct sk_buff *skb = dev_alloc_skb(size + 128); | ||
51 | if (unlikely(skb == NULL)) { | ||
52 | pr_warning | ||
53 | ("Failed to allocate skb for hardware pool %d\n", | ||
54 | pool); | ||
55 | break; | ||
56 | } | ||
57 | |||
58 | skb_reserve(skb, 128 - (((unsigned long)skb->data) & 0x7f)); | ||
59 | *(struct sk_buff **)(skb->data - sizeof(void *)) = skb; | ||
60 | cvmx_fpa_free(skb->data, pool, DONT_WRITEBACK(size / 128)); | ||
61 | freed--; | ||
62 | } | ||
63 | return elements - freed; | ||
64 | } | ||
65 | |||
66 | /** | ||
67 | * Free the supplied hardware pool of skbuffs | ||
68 | * | ||
69 | * @pool: Pool to allocate an skbuff for | ||
70 | * @size: Size of the buffer needed for the pool | ||
71 | * @elements: Number of buffers to allocate | ||
72 | */ | ||
73 | static void cvm_oct_free_hw_skbuff(int pool, int size, int elements) | ||
74 | { | ||
75 | char *memory; | ||
76 | |||
77 | do { | ||
78 | memory = cvmx_fpa_alloc(pool); | ||
79 | if (memory) { | ||
80 | struct sk_buff *skb = | ||
81 | *(struct sk_buff **)(memory - sizeof(void *)); | ||
82 | elements--; | ||
83 | dev_kfree_skb(skb); | ||
84 | } | ||
85 | } while (memory); | ||
86 | |||
87 | if (elements < 0) | ||
88 | pr_warning("Freeing of pool %u had too many skbuffs (%d)\n", | ||
89 | pool, elements); | ||
90 | else if (elements > 0) | ||
91 | pr_warning("Freeing of pool %u is missing %d skbuffs\n", | ||
92 | pool, elements); | ||
93 | } | ||
94 | |||
95 | /** | ||
96 | * This function fills a hardware pool with memory. Depending | ||
97 | * on the config defines, this memory might come from the | ||
98 | * kernel or global 32bit memory allocated with | ||
99 | * cvmx_bootmem_alloc. | ||
100 | * | ||
101 | * @pool: Pool to populate | ||
102 | * @size: Size of each buffer in the pool | ||
103 | * @elements: Number of buffers to allocate | ||
104 | */ | ||
105 | static int cvm_oct_fill_hw_memory(int pool, int size, int elements) | ||
106 | { | ||
107 | char *memory; | ||
108 | int freed = elements; | ||
109 | |||
110 | if (USE_32BIT_SHARED) { | ||
111 | extern uint64_t octeon_reserve32_memory; | ||
112 | |||
113 | memory = | ||
114 | cvmx_bootmem_alloc_range(elements * size, 128, | ||
115 | octeon_reserve32_memory, | ||
116 | octeon_reserve32_memory + | ||
117 | (CONFIG_CAVIUM_RESERVE32 << 20) - | ||
118 | 1); | ||
119 | if (memory == NULL) | ||
120 | panic("Unable to allocate %u bytes for FPA pool %d\n", | ||
121 | elements * size, pool); | ||
122 | |||
123 | pr_notice("Memory range %p - %p reserved for " | ||
124 | "hardware\n", memory, | ||
125 | memory + elements * size - 1); | ||
126 | |||
127 | while (freed) { | ||
128 | cvmx_fpa_free(memory, pool, 0); | ||
129 | memory += size; | ||
130 | freed--; | ||
131 | } | ||
132 | } else { | ||
133 | while (freed) { | ||
134 | /* We need to force alignment to 128 bytes here */ | ||
135 | memory = kmalloc(size + 127, GFP_ATOMIC); | ||
136 | if (unlikely(memory == NULL)) { | ||
137 | pr_warning("Unable to allocate %u bytes for " | ||
138 | "FPA pool %d\n", | ||
139 | elements * size, pool); | ||
140 | break; | ||
141 | } | ||
142 | memory = (char *)(((unsigned long)memory + 127) & -128); | ||
143 | cvmx_fpa_free(memory, pool, 0); | ||
144 | freed--; | ||
145 | } | ||
146 | } | ||
147 | return elements - freed; | ||
148 | } | ||
149 | |||
150 | /** | ||
151 | * Free memory previously allocated with cvm_oct_fill_hw_memory | ||
152 | * | ||
153 | * @pool: FPA pool to free | ||
154 | * @size: Size of each buffer in the pool | ||
155 | * @elements: Number of buffers that should be in the pool | ||
156 | */ | ||
157 | static void cvm_oct_free_hw_memory(int pool, int size, int elements) | ||
158 | { | ||
159 | if (USE_32BIT_SHARED) { | ||
160 | pr_warning("Warning: 32 shared memory is not freeable\n"); | ||
161 | } else { | ||
162 | char *memory; | ||
163 | do { | ||
164 | memory = cvmx_fpa_alloc(pool); | ||
165 | if (memory) { | ||
166 | elements--; | ||
167 | kfree(phys_to_virt(cvmx_ptr_to_phys(memory))); | ||
168 | } | ||
169 | } while (memory); | ||
170 | |||
171 | if (elements < 0) | ||
172 | pr_warning("Freeing of pool %u had too many " | ||
173 | "buffers (%d)\n", | ||
174 | pool, elements); | ||
175 | else if (elements > 0) | ||
176 | pr_warning("Warning: Freeing of pool %u is " | ||
177 | "missing %d buffers\n", | ||
178 | pool, elements); | ||
179 | } | ||
180 | } | ||
181 | |||
182 | int cvm_oct_mem_fill_fpa(int pool, int size, int elements) | ||
183 | { | ||
184 | int freed; | ||
185 | if (USE_SKBUFFS_IN_HW) | ||
186 | freed = cvm_oct_fill_hw_skbuff(pool, size, elements); | ||
187 | else | ||
188 | freed = cvm_oct_fill_hw_memory(pool, size, elements); | ||
189 | return freed; | ||
190 | } | ||
191 | |||
192 | void cvm_oct_mem_empty_fpa(int pool, int size, int elements) | ||
193 | { | ||
194 | if (USE_SKBUFFS_IN_HW) | ||
195 | cvm_oct_free_hw_skbuff(pool, size, elements); | ||
196 | else | ||
197 | cvm_oct_free_hw_memory(pool, size, elements); | ||
198 | } | ||
diff --git a/drivers/staging/octeon/ethernet-mem.h b/drivers/staging/octeon/ethernet-mem.h new file mode 100644 index 000000000000..713f2edc8b4f --- /dev/null +++ b/drivers/staging/octeon/ethernet-mem.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /********************************************************************* | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ********************************************************************/ | ||
27 | |||
28 | int cvm_oct_mem_fill_fpa(int pool, int size, int elements); | ||
29 | void cvm_oct_mem_empty_fpa(int pool, int size, int elements); | ||
diff --git a/drivers/staging/octeon/ethernet-proc.c b/drivers/staging/octeon/ethernet-proc.c new file mode 100644 index 000000000000..8fa88fc419b7 --- /dev/null +++ b/drivers/staging/octeon/ethernet-proc.c | |||
@@ -0,0 +1,256 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/mii.h> | ||
29 | #include <linux/seq_file.h> | ||
30 | #include <linux/proc_fs.h> | ||
31 | #include <net/dst.h> | ||
32 | |||
33 | #include <asm/octeon/octeon.h> | ||
34 | |||
35 | #include "octeon-ethernet.h" | ||
36 | #include "ethernet-defines.h" | ||
37 | |||
38 | #include "cvmx-helper.h" | ||
39 | #include "cvmx-pip.h" | ||
40 | |||
41 | static unsigned long long cvm_oct_stats_read_switch(struct net_device *dev, | ||
42 | int phy_id, int offset) | ||
43 | { | ||
44 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
45 | |||
46 | priv->mii_info.mdio_write(dev, phy_id, 0x1d, 0xcc00 | offset); | ||
47 | return ((uint64_t) priv->mii_info. | ||
48 | mdio_read(dev, phy_id, | ||
49 | 0x1e) << 16) | (uint64_t) priv->mii_info. | ||
50 | mdio_read(dev, phy_id, 0x1f); | ||
51 | } | ||
52 | |||
53 | static int cvm_oct_stats_switch_show(struct seq_file *m, void *v) | ||
54 | { | ||
55 | static const int ports[] = { 0, 1, 2, 3, 9, -1 }; | ||
56 | struct net_device *dev = cvm_oct_device[0]; | ||
57 | int index = 0; | ||
58 | |||
59 | while (ports[index] != -1) { | ||
60 | |||
61 | /* Latch port */ | ||
62 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
63 | |||
64 | priv->mii_info.mdio_write(dev, 0x1b, 0x1d, | ||
65 | 0xdc00 | ports[index]); | ||
66 | seq_printf(m, "\nSwitch Port %d\n", ports[index]); | ||
67 | seq_printf(m, "InGoodOctets: %12llu\t" | ||
68 | "OutOctets: %12llu\t" | ||
69 | "64 Octets: %12llu\n", | ||
70 | cvm_oct_stats_read_switch(dev, 0x1b, | ||
71 | 0x00) | | ||
72 | (cvm_oct_stats_read_switch(dev, 0x1b, 0x01) << 32), | ||
73 | cvm_oct_stats_read_switch(dev, 0x1b, | ||
74 | 0x0E) | | ||
75 | (cvm_oct_stats_read_switch(dev, 0x1b, 0x0F) << 32), | ||
76 | cvm_oct_stats_read_switch(dev, 0x1b, 0x08)); | ||
77 | |||
78 | seq_printf(m, "InBadOctets: %12llu\t" | ||
79 | "OutUnicast: %12llu\t" | ||
80 | "65-127 Octets: %12llu\n", | ||
81 | cvm_oct_stats_read_switch(dev, 0x1b, 0x02), | ||
82 | cvm_oct_stats_read_switch(dev, 0x1b, 0x10), | ||
83 | cvm_oct_stats_read_switch(dev, 0x1b, 0x09)); | ||
84 | |||
85 | seq_printf(m, "InUnicast: %12llu\t" | ||
86 | "OutBroadcasts: %12llu\t" | ||
87 | "128-255 Octets: %12llu\n", | ||
88 | cvm_oct_stats_read_switch(dev, 0x1b, 0x04), | ||
89 | cvm_oct_stats_read_switch(dev, 0x1b, 0x13), | ||
90 | cvm_oct_stats_read_switch(dev, 0x1b, 0x0A)); | ||
91 | |||
92 | seq_printf(m, "InBroadcasts: %12llu\t" | ||
93 | "OutMulticasts: %12llu\t" | ||
94 | "256-511 Octets: %12llu\n", | ||
95 | cvm_oct_stats_read_switch(dev, 0x1b, 0x06), | ||
96 | cvm_oct_stats_read_switch(dev, 0x1b, 0x12), | ||
97 | cvm_oct_stats_read_switch(dev, 0x1b, 0x0B)); | ||
98 | |||
99 | seq_printf(m, "InMulticasts: %12llu\t" | ||
100 | "OutPause: %12llu\t" | ||
101 | "512-1023 Octets:%12llu\n", | ||
102 | cvm_oct_stats_read_switch(dev, 0x1b, 0x07), | ||
103 | cvm_oct_stats_read_switch(dev, 0x1b, 0x15), | ||
104 | cvm_oct_stats_read_switch(dev, 0x1b, 0x0C)); | ||
105 | |||
106 | seq_printf(m, "InPause: %12llu\t" | ||
107 | "Excessive: %12llu\t" | ||
108 | "1024-Max Octets:%12llu\n", | ||
109 | cvm_oct_stats_read_switch(dev, 0x1b, 0x16), | ||
110 | cvm_oct_stats_read_switch(dev, 0x1b, 0x11), | ||
111 | cvm_oct_stats_read_switch(dev, 0x1b, 0x0D)); | ||
112 | |||
113 | seq_printf(m, "InUndersize: %12llu\t" | ||
114 | "Collisions: %12llu\n", | ||
115 | cvm_oct_stats_read_switch(dev, 0x1b, 0x18), | ||
116 | cvm_oct_stats_read_switch(dev, 0x1b, 0x1E)); | ||
117 | |||
118 | seq_printf(m, "InFragments: %12llu\t" | ||
119 | "Deferred: %12llu\n", | ||
120 | cvm_oct_stats_read_switch(dev, 0x1b, 0x19), | ||
121 | cvm_oct_stats_read_switch(dev, 0x1b, 0x05)); | ||
122 | |||
123 | seq_printf(m, "InOversize: %12llu\t" | ||
124 | "Single: %12llu\n", | ||
125 | cvm_oct_stats_read_switch(dev, 0x1b, 0x1A), | ||
126 | cvm_oct_stats_read_switch(dev, 0x1b, 0x14)); | ||
127 | |||
128 | seq_printf(m, "InJabber: %12llu\t" | ||
129 | "Multiple: %12llu\n", | ||
130 | cvm_oct_stats_read_switch(dev, 0x1b, 0x1B), | ||
131 | cvm_oct_stats_read_switch(dev, 0x1b, 0x17)); | ||
132 | |||
133 | seq_printf(m, "In RxErr: %12llu\t" | ||
134 | "OutFCSErr: %12llu\n", | ||
135 | cvm_oct_stats_read_switch(dev, 0x1b, 0x1C), | ||
136 | cvm_oct_stats_read_switch(dev, 0x1b, 0x03)); | ||
137 | |||
138 | seq_printf(m, "InFCSErr: %12llu\t" | ||
139 | "Late: %12llu\n", | ||
140 | cvm_oct_stats_read_switch(dev, 0x1b, 0x1D), | ||
141 | cvm_oct_stats_read_switch(dev, 0x1b, 0x1F)); | ||
142 | index++; | ||
143 | } | ||
144 | return 0; | ||
145 | } | ||
146 | |||
147 | /** | ||
148 | * User is reading /proc/octeon_ethernet_stats | ||
149 | * | ||
150 | * @m: | ||
151 | * @v: | ||
152 | * Returns | ||
153 | */ | ||
154 | static int cvm_oct_stats_show(struct seq_file *m, void *v) | ||
155 | { | ||
156 | struct octeon_ethernet *priv; | ||
157 | int port; | ||
158 | |||
159 | for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) { | ||
160 | |||
161 | if (cvm_oct_device[port]) { | ||
162 | priv = netdev_priv(cvm_oct_device[port]); | ||
163 | |||
164 | seq_printf(m, "\nOcteon Port %d (%s)\n", port, | ||
165 | cvm_oct_device[port]->name); | ||
166 | seq_printf(m, | ||
167 | "rx_packets: %12lu\t" | ||
168 | "tx_packets: %12lu\n", | ||
169 | priv->stats.rx_packets, | ||
170 | priv->stats.tx_packets); | ||
171 | seq_printf(m, | ||
172 | "rx_bytes: %12lu\t" | ||
173 | "tx_bytes: %12lu\n", | ||
174 | priv->stats.rx_bytes, priv->stats.tx_bytes); | ||
175 | seq_printf(m, | ||
176 | "rx_errors: %12lu\t" | ||
177 | "tx_errors: %12lu\n", | ||
178 | priv->stats.rx_errors, | ||
179 | priv->stats.tx_errors); | ||
180 | seq_printf(m, | ||
181 | "rx_dropped: %12lu\t" | ||
182 | "tx_dropped: %12lu\n", | ||
183 | priv->stats.rx_dropped, | ||
184 | priv->stats.tx_dropped); | ||
185 | seq_printf(m, | ||
186 | "rx_length_errors: %12lu\t" | ||
187 | "tx_aborted_errors: %12lu\n", | ||
188 | priv->stats.rx_length_errors, | ||
189 | priv->stats.tx_aborted_errors); | ||
190 | seq_printf(m, | ||
191 | "rx_over_errors: %12lu\t" | ||
192 | "tx_carrier_errors: %12lu\n", | ||
193 | priv->stats.rx_over_errors, | ||
194 | priv->stats.tx_carrier_errors); | ||
195 | seq_printf(m, | ||
196 | "rx_crc_errors: %12lu\t" | ||
197 | "tx_fifo_errors: %12lu\n", | ||
198 | priv->stats.rx_crc_errors, | ||
199 | priv->stats.tx_fifo_errors); | ||
200 | seq_printf(m, | ||
201 | "rx_frame_errors: %12lu\t" | ||
202 | "tx_heartbeat_errors: %12lu\n", | ||
203 | priv->stats.rx_frame_errors, | ||
204 | priv->stats.tx_heartbeat_errors); | ||
205 | seq_printf(m, | ||
206 | "rx_fifo_errors: %12lu\t" | ||
207 | "tx_window_errors: %12lu\n", | ||
208 | priv->stats.rx_fifo_errors, | ||
209 | priv->stats.tx_window_errors); | ||
210 | seq_printf(m, | ||
211 | "rx_missed_errors: %12lu\t" | ||
212 | "multicast: %12lu\n", | ||
213 | priv->stats.rx_missed_errors, | ||
214 | priv->stats.multicast); | ||
215 | } | ||
216 | } | ||
217 | |||
218 | if (cvm_oct_device[0]) { | ||
219 | priv = netdev_priv(cvm_oct_device[0]); | ||
220 | if (priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII) | ||
221 | cvm_oct_stats_switch_show(m, v); | ||
222 | } | ||
223 | return 0; | ||
224 | } | ||
225 | |||
226 | /** | ||
227 | * /proc/octeon_ethernet_stats was openned. Use the single_open iterator | ||
228 | * | ||
229 | * @inode: | ||
230 | * @file: | ||
231 | * Returns | ||
232 | */ | ||
233 | static int cvm_oct_stats_open(struct inode *inode, struct file *file) | ||
234 | { | ||
235 | return single_open(file, cvm_oct_stats_show, NULL); | ||
236 | } | ||
237 | |||
238 | static const struct file_operations cvm_oct_stats_operations = { | ||
239 | .open = cvm_oct_stats_open, | ||
240 | .read = seq_read, | ||
241 | .llseek = seq_lseek, | ||
242 | .release = single_release, | ||
243 | }; | ||
244 | |||
245 | void cvm_oct_proc_initialize(void) | ||
246 | { | ||
247 | struct proc_dir_entry *entry = | ||
248 | create_proc_entry("octeon_ethernet_stats", 0, NULL); | ||
249 | if (entry) | ||
250 | entry->proc_fops = &cvm_oct_stats_operations; | ||
251 | } | ||
252 | |||
253 | void cvm_oct_proc_shutdown(void) | ||
254 | { | ||
255 | remove_proc_entry("octeon_ethernet_stats", NULL); | ||
256 | } | ||
diff --git a/drivers/staging/octeon/ethernet-proc.h b/drivers/staging/octeon/ethernet-proc.h new file mode 100644 index 000000000000..82c7d9f78bc4 --- /dev/null +++ b/drivers/staging/octeon/ethernet-proc.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /********************************************************************* | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | *********************************************************************/ | ||
27 | |||
28 | void cvm_oct_proc_initialize(void); | ||
29 | void cvm_oct_proc_shutdown(void); | ||
diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c new file mode 100644 index 000000000000..8579f1670d1e --- /dev/null +++ b/drivers/staging/octeon/ethernet-rgmii.c | |||
@@ -0,0 +1,397 @@ | |||
1 | /********************************************************************* | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/netdevice.h> | ||
29 | #include <linux/mii.h> | ||
30 | #include <net/dst.h> | ||
31 | |||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "ethernet-defines.h" | ||
35 | #include "octeon-ethernet.h" | ||
36 | #include "ethernet-common.h" | ||
37 | #include "ethernet-util.h" | ||
38 | |||
39 | #include "cvmx-helper.h" | ||
40 | |||
41 | #include <asm/octeon/cvmx-ipd-defs.h> | ||
42 | #include <asm/octeon/cvmx-npi-defs.h> | ||
43 | #include "cvmx-gmxx-defs.h" | ||
44 | |||
45 | DEFINE_SPINLOCK(global_register_lock); | ||
46 | |||
47 | static int number_rgmii_ports; | ||
48 | |||
49 | static void cvm_oct_rgmii_poll(struct net_device *dev) | ||
50 | { | ||
51 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
52 | unsigned long flags; | ||
53 | cvmx_helper_link_info_t link_info; | ||
54 | |||
55 | /* | ||
56 | * Take the global register lock since we are going to touch | ||
57 | * registers that affect more than one port. | ||
58 | */ | ||
59 | spin_lock_irqsave(&global_register_lock, flags); | ||
60 | |||
61 | link_info = cvmx_helper_link_get(priv->port); | ||
62 | if (link_info.u64 == priv->link_info) { | ||
63 | |||
64 | /* | ||
65 | * If the 10Mbps preamble workaround is supported and we're | ||
66 | * at 10Mbps we may need to do some special checking. | ||
67 | */ | ||
68 | if (USE_10MBPS_PREAMBLE_WORKAROUND && (link_info.s.speed == 10)) { | ||
69 | |||
70 | /* | ||
71 | * Read the GMXX_RXX_INT_REG[PCTERR] bit and | ||
72 | * see if we are getting preamble errors. | ||
73 | */ | ||
74 | int interface = INTERFACE(priv->port); | ||
75 | int index = INDEX(priv->port); | ||
76 | union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg; | ||
77 | gmxx_rxx_int_reg.u64 = | ||
78 | cvmx_read_csr(CVMX_GMXX_RXX_INT_REG | ||
79 | (index, interface)); | ||
80 | if (gmxx_rxx_int_reg.s.pcterr) { | ||
81 | |||
82 | /* | ||
83 | * We are getting preamble errors at | ||
84 | * 10Mbps. Most likely the PHY is | ||
85 | * giving us packets with mis aligned | ||
86 | * preambles. In order to get these | ||
87 | * packets we need to disable preamble | ||
88 | * checking and do it in software. | ||
89 | */ | ||
90 | union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl; | ||
91 | union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs; | ||
92 | |||
93 | /* Disable preamble checking */ | ||
94 | gmxx_rxx_frm_ctl.u64 = | ||
95 | cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL | ||
96 | (index, interface)); | ||
97 | gmxx_rxx_frm_ctl.s.pre_chk = 0; | ||
98 | cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL | ||
99 | (index, interface), | ||
100 | gmxx_rxx_frm_ctl.u64); | ||
101 | |||
102 | /* Disable FCS stripping */ | ||
103 | ipd_sub_port_fcs.u64 = | ||
104 | cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); | ||
105 | ipd_sub_port_fcs.s.port_bit &= | ||
106 | 0xffffffffull ^ (1ull << priv->port); | ||
107 | cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, | ||
108 | ipd_sub_port_fcs.u64); | ||
109 | |||
110 | /* Clear any error bits */ | ||
111 | cvmx_write_csr(CVMX_GMXX_RXX_INT_REG | ||
112 | (index, interface), | ||
113 | gmxx_rxx_int_reg.u64); | ||
114 | DEBUGPRINT("%s: Using 10Mbps with software " | ||
115 | "preamble removal\n", | ||
116 | dev->name); | ||
117 | } | ||
118 | } | ||
119 | spin_unlock_irqrestore(&global_register_lock, flags); | ||
120 | return; | ||
121 | } | ||
122 | |||
123 | /* If the 10Mbps preamble workaround is allowed we need to on | ||
124 | preamble checking, FCS stripping, and clear error bits on | ||
125 | every speed change. If errors occur during 10Mbps operation | ||
126 | the above code will change this stuff */ | ||
127 | if (USE_10MBPS_PREAMBLE_WORKAROUND) { | ||
128 | |||
129 | union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl; | ||
130 | union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs; | ||
131 | union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg; | ||
132 | int interface = INTERFACE(priv->port); | ||
133 | int index = INDEX(priv->port); | ||
134 | |||
135 | /* Enable preamble checking */ | ||
136 | gmxx_rxx_frm_ctl.u64 = | ||
137 | cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface)); | ||
138 | gmxx_rxx_frm_ctl.s.pre_chk = 1; | ||
139 | cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), | ||
140 | gmxx_rxx_frm_ctl.u64); | ||
141 | /* Enable FCS stripping */ | ||
142 | ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); | ||
143 | ipd_sub_port_fcs.s.port_bit |= 1ull << priv->port; | ||
144 | cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); | ||
145 | /* Clear any error bits */ | ||
146 | gmxx_rxx_int_reg.u64 = | ||
147 | cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface)); | ||
148 | cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), | ||
149 | gmxx_rxx_int_reg.u64); | ||
150 | } | ||
151 | |||
152 | link_info = cvmx_helper_link_autoconf(priv->port); | ||
153 | priv->link_info = link_info.u64; | ||
154 | spin_unlock_irqrestore(&global_register_lock, flags); | ||
155 | |||
156 | /* Tell Linux */ | ||
157 | if (link_info.s.link_up) { | ||
158 | |||
159 | if (!netif_carrier_ok(dev)) | ||
160 | netif_carrier_on(dev); | ||
161 | if (priv->queue != -1) | ||
162 | DEBUGPRINT | ||
163 | ("%s: %u Mbps %s duplex, port %2d, queue %2d\n", | ||
164 | dev->name, link_info.s.speed, | ||
165 | (link_info.s.full_duplex) ? "Full" : "Half", | ||
166 | priv->port, priv->queue); | ||
167 | else | ||
168 | DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, POW\n", | ||
169 | dev->name, link_info.s.speed, | ||
170 | (link_info.s.full_duplex) ? "Full" : "Half", | ||
171 | priv->port); | ||
172 | } else { | ||
173 | |||
174 | if (netif_carrier_ok(dev)) | ||
175 | netif_carrier_off(dev); | ||
176 | DEBUGPRINT("%s: Link down\n", dev->name); | ||
177 | } | ||
178 | } | ||
179 | |||
180 | static irqreturn_t cvm_oct_rgmii_rml_interrupt(int cpl, void *dev_id) | ||
181 | { | ||
182 | union cvmx_npi_rsl_int_blocks rsl_int_blocks; | ||
183 | int index; | ||
184 | irqreturn_t return_status = IRQ_NONE; | ||
185 | |||
186 | rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS); | ||
187 | |||
188 | /* Check and see if this interrupt was caused by the GMX0 block */ | ||
189 | if (rsl_int_blocks.s.gmx0) { | ||
190 | |||
191 | int interface = 0; | ||
192 | /* Loop through every port of this interface */ | ||
193 | for (index = 0; | ||
194 | index < cvmx_helper_ports_on_interface(interface); | ||
195 | index++) { | ||
196 | |||
197 | /* Read the GMX interrupt status bits */ | ||
198 | union cvmx_gmxx_rxx_int_reg gmx_rx_int_reg; | ||
199 | gmx_rx_int_reg.u64 = | ||
200 | cvmx_read_csr(CVMX_GMXX_RXX_INT_REG | ||
201 | (index, interface)); | ||
202 | gmx_rx_int_reg.u64 &= | ||
203 | cvmx_read_csr(CVMX_GMXX_RXX_INT_EN | ||
204 | (index, interface)); | ||
205 | /* Poll the port if inband status changed */ | ||
206 | if (gmx_rx_int_reg.s.phy_dupx | ||
207 | || gmx_rx_int_reg.s.phy_link | ||
208 | || gmx_rx_int_reg.s.phy_spd) { | ||
209 | |||
210 | struct net_device *dev = | ||
211 | cvm_oct_device[cvmx_helper_get_ipd_port | ||
212 | (interface, index)]; | ||
213 | if (dev) | ||
214 | cvm_oct_rgmii_poll(dev); | ||
215 | gmx_rx_int_reg.u64 = 0; | ||
216 | gmx_rx_int_reg.s.phy_dupx = 1; | ||
217 | gmx_rx_int_reg.s.phy_link = 1; | ||
218 | gmx_rx_int_reg.s.phy_spd = 1; | ||
219 | cvmx_write_csr(CVMX_GMXX_RXX_INT_REG | ||
220 | (index, interface), | ||
221 | gmx_rx_int_reg.u64); | ||
222 | return_status = IRQ_HANDLED; | ||
223 | } | ||
224 | } | ||
225 | } | ||
226 | |||
227 | /* Check and see if this interrupt was caused by the GMX1 block */ | ||
228 | if (rsl_int_blocks.s.gmx1) { | ||
229 | |||
230 | int interface = 1; | ||
231 | /* Loop through every port of this interface */ | ||
232 | for (index = 0; | ||
233 | index < cvmx_helper_ports_on_interface(interface); | ||
234 | index++) { | ||
235 | |||
236 | /* Read the GMX interrupt status bits */ | ||
237 | union cvmx_gmxx_rxx_int_reg gmx_rx_int_reg; | ||
238 | gmx_rx_int_reg.u64 = | ||
239 | cvmx_read_csr(CVMX_GMXX_RXX_INT_REG | ||
240 | (index, interface)); | ||
241 | gmx_rx_int_reg.u64 &= | ||
242 | cvmx_read_csr(CVMX_GMXX_RXX_INT_EN | ||
243 | (index, interface)); | ||
244 | /* Poll the port if inband status changed */ | ||
245 | if (gmx_rx_int_reg.s.phy_dupx | ||
246 | || gmx_rx_int_reg.s.phy_link | ||
247 | || gmx_rx_int_reg.s.phy_spd) { | ||
248 | |||
249 | struct net_device *dev = | ||
250 | cvm_oct_device[cvmx_helper_get_ipd_port | ||
251 | (interface, index)]; | ||
252 | if (dev) | ||
253 | cvm_oct_rgmii_poll(dev); | ||
254 | gmx_rx_int_reg.u64 = 0; | ||
255 | gmx_rx_int_reg.s.phy_dupx = 1; | ||
256 | gmx_rx_int_reg.s.phy_link = 1; | ||
257 | gmx_rx_int_reg.s.phy_spd = 1; | ||
258 | cvmx_write_csr(CVMX_GMXX_RXX_INT_REG | ||
259 | (index, interface), | ||
260 | gmx_rx_int_reg.u64); | ||
261 | return_status = IRQ_HANDLED; | ||
262 | } | ||
263 | } | ||
264 | } | ||
265 | return return_status; | ||
266 | } | ||
267 | |||
268 | static int cvm_oct_rgmii_open(struct net_device *dev) | ||
269 | { | ||
270 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
271 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
272 | int interface = INTERFACE(priv->port); | ||
273 | int index = INDEX(priv->port); | ||
274 | cvmx_helper_link_info_t link_info; | ||
275 | |||
276 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
277 | gmx_cfg.s.en = 1; | ||
278 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
279 | |||
280 | if (!octeon_is_simulation()) { | ||
281 | link_info = cvmx_helper_link_get(priv->port); | ||
282 | if (!link_info.s.link_up) | ||
283 | netif_carrier_off(dev); | ||
284 | } | ||
285 | |||
286 | return 0; | ||
287 | } | ||
288 | |||
289 | static int cvm_oct_rgmii_stop(struct net_device *dev) | ||
290 | { | ||
291 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
292 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
293 | int interface = INTERFACE(priv->port); | ||
294 | int index = INDEX(priv->port); | ||
295 | |||
296 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
297 | gmx_cfg.s.en = 0; | ||
298 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
299 | return 0; | ||
300 | } | ||
301 | |||
302 | int cvm_oct_rgmii_init(struct net_device *dev) | ||
303 | { | ||
304 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
305 | int r; | ||
306 | |||
307 | cvm_oct_common_init(dev); | ||
308 | dev->open = cvm_oct_rgmii_open; | ||
309 | dev->stop = cvm_oct_rgmii_stop; | ||
310 | dev->stop(dev); | ||
311 | |||
312 | /* | ||
313 | * Due to GMX errata in CN3XXX series chips, it is necessary | ||
314 | * to take the link down immediately whne the PHY changes | ||
315 | * state. In order to do this we call the poll function every | ||
316 | * time the RGMII inband status changes. This may cause | ||
317 | * problems if the PHY doesn't implement inband status | ||
318 | * properly. | ||
319 | */ | ||
320 | if (number_rgmii_ports == 0) { | ||
321 | r = request_irq(OCTEON_IRQ_RML, cvm_oct_rgmii_rml_interrupt, | ||
322 | IRQF_SHARED, "RGMII", &number_rgmii_ports); | ||
323 | } | ||
324 | number_rgmii_ports++; | ||
325 | |||
326 | /* | ||
327 | * Only true RGMII ports need to be polled. In GMII mode, port | ||
328 | * 0 is really a RGMII port. | ||
329 | */ | ||
330 | if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII) | ||
331 | && (priv->port == 0)) | ||
332 | || (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) { | ||
333 | |||
334 | if (!octeon_is_simulation()) { | ||
335 | |||
336 | union cvmx_gmxx_rxx_int_en gmx_rx_int_en; | ||
337 | int interface = INTERFACE(priv->port); | ||
338 | int index = INDEX(priv->port); | ||
339 | |||
340 | /* | ||
341 | * Enable interrupts on inband status changes | ||
342 | * for this port. | ||
343 | */ | ||
344 | gmx_rx_int_en.u64 = | ||
345 | cvmx_read_csr(CVMX_GMXX_RXX_INT_EN | ||
346 | (index, interface)); | ||
347 | gmx_rx_int_en.s.phy_dupx = 1; | ||
348 | gmx_rx_int_en.s.phy_link = 1; | ||
349 | gmx_rx_int_en.s.phy_spd = 1; | ||
350 | cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface), | ||
351 | gmx_rx_int_en.u64); | ||
352 | priv->poll = cvm_oct_rgmii_poll; | ||
353 | } | ||
354 | } | ||
355 | |||
356 | return 0; | ||
357 | } | ||
358 | |||
359 | void cvm_oct_rgmii_uninit(struct net_device *dev) | ||
360 | { | ||
361 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
362 | cvm_oct_common_uninit(dev); | ||
363 | |||
364 | /* | ||
365 | * Only true RGMII ports need to be polled. In GMII mode, port | ||
366 | * 0 is really a RGMII port. | ||
367 | */ | ||
368 | if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII) | ||
369 | && (priv->port == 0)) | ||
370 | || (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) { | ||
371 | |||
372 | if (!octeon_is_simulation()) { | ||
373 | |||
374 | union cvmx_gmxx_rxx_int_en gmx_rx_int_en; | ||
375 | int interface = INTERFACE(priv->port); | ||
376 | int index = INDEX(priv->port); | ||
377 | |||
378 | /* | ||
379 | * Disable interrupts on inband status changes | ||
380 | * for this port. | ||
381 | */ | ||
382 | gmx_rx_int_en.u64 = | ||
383 | cvmx_read_csr(CVMX_GMXX_RXX_INT_EN | ||
384 | (index, interface)); | ||
385 | gmx_rx_int_en.s.phy_dupx = 0; | ||
386 | gmx_rx_int_en.s.phy_link = 0; | ||
387 | gmx_rx_int_en.s.phy_spd = 0; | ||
388 | cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface), | ||
389 | gmx_rx_int_en.u64); | ||
390 | } | ||
391 | } | ||
392 | |||
393 | /* Remove the interrupt handler when the last port is removed. */ | ||
394 | number_rgmii_ports--; | ||
395 | if (number_rgmii_ports == 0) | ||
396 | free_irq(OCTEON_IRQ_RML, &number_rgmii_ports); | ||
397 | } | ||
diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c new file mode 100644 index 000000000000..1b237b7e689d --- /dev/null +++ b/drivers/staging/octeon/ethernet-rx.c | |||
@@ -0,0 +1,505 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/module.h> | ||
28 | #include <linux/kernel.h> | ||
29 | #include <linux/cache.h> | ||
30 | #include <linux/netdevice.h> | ||
31 | #include <linux/init.h> | ||
32 | #include <linux/etherdevice.h> | ||
33 | #include <linux/ip.h> | ||
34 | #include <linux/string.h> | ||
35 | #include <linux/prefetch.h> | ||
36 | #include <linux/ethtool.h> | ||
37 | #include <linux/mii.h> | ||
38 | #include <linux/seq_file.h> | ||
39 | #include <linux/proc_fs.h> | ||
40 | #include <net/dst.h> | ||
41 | #ifdef CONFIG_XFRM | ||
42 | #include <linux/xfrm.h> | ||
43 | #include <net/xfrm.h> | ||
44 | #endif /* CONFIG_XFRM */ | ||
45 | |||
46 | #include <asm/atomic.h> | ||
47 | |||
48 | #include <asm/octeon/octeon.h> | ||
49 | |||
50 | #include "ethernet-defines.h" | ||
51 | #include "octeon-ethernet.h" | ||
52 | #include "ethernet-mem.h" | ||
53 | #include "ethernet-util.h" | ||
54 | |||
55 | #include "cvmx-helper.h" | ||
56 | #include "cvmx-wqe.h" | ||
57 | #include "cvmx-fau.h" | ||
58 | #include "cvmx-pow.h" | ||
59 | #include "cvmx-pip.h" | ||
60 | #include "cvmx-scratch.h" | ||
61 | |||
62 | #include "cvmx-gmxx-defs.h" | ||
63 | |||
64 | struct cvm_tasklet_wrapper { | ||
65 | struct tasklet_struct t; | ||
66 | }; | ||
67 | |||
68 | /* | ||
69 | * Aligning the tasklet_struct on cachline boundries seems to decrease | ||
70 | * throughput even though in theory it would reduce contantion on the | ||
71 | * cache lines containing the locks. | ||
72 | */ | ||
73 | |||
74 | static struct cvm_tasklet_wrapper cvm_oct_tasklet[NR_CPUS]; | ||
75 | |||
76 | /** | ||
77 | * Interrupt handler. The interrupt occurs whenever the POW | ||
78 | * transitions from 0->1 packets in our group. | ||
79 | * | ||
80 | * @cpl: | ||
81 | * @dev_id: | ||
82 | * @regs: | ||
83 | * Returns | ||
84 | */ | ||
85 | irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id) | ||
86 | { | ||
87 | /* Acknowledge the interrupt */ | ||
88 | if (INTERRUPT_LIMIT) | ||
89 | cvmx_write_csr(CVMX_POW_WQ_INT, 1 << pow_receive_group); | ||
90 | else | ||
91 | cvmx_write_csr(CVMX_POW_WQ_INT, 0x10001 << pow_receive_group); | ||
92 | preempt_disable(); | ||
93 | tasklet_schedule(&cvm_oct_tasklet[smp_processor_id()].t); | ||
94 | preempt_enable(); | ||
95 | return IRQ_HANDLED; | ||
96 | } | ||
97 | |||
98 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
99 | /** | ||
100 | * This is called when the kernel needs to manually poll the | ||
101 | * device. For Octeon, this is simply calling the interrupt | ||
102 | * handler. We actually poll all the devices, not just the | ||
103 | * one supplied. | ||
104 | * | ||
105 | * @dev: Device to poll. Unused | ||
106 | */ | ||
107 | void cvm_oct_poll_controller(struct net_device *dev) | ||
108 | { | ||
109 | preempt_disable(); | ||
110 | tasklet_schedule(&cvm_oct_tasklet[smp_processor_id()].t); | ||
111 | preempt_enable(); | ||
112 | } | ||
113 | #endif | ||
114 | |||
115 | /** | ||
116 | * This is called on receive errors, and determines if the packet | ||
117 | * can be dropped early-on in cvm_oct_tasklet_rx(). | ||
118 | * | ||
119 | * @work: Work queue entry pointing to the packet. | ||
120 | * Returns Non-zero if the packet can be dropped, zero otherwise. | ||
121 | */ | ||
122 | static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work) | ||
123 | { | ||
124 | if ((work->word2.snoip.err_code == 10) && (work->len <= 64)) { | ||
125 | /* | ||
126 | * Ignore length errors on min size packets. Some | ||
127 | * equipment incorrectly pads packets to 64+4FCS | ||
128 | * instead of 60+4FCS. Note these packets still get | ||
129 | * counted as frame errors. | ||
130 | */ | ||
131 | } else | ||
132 | if (USE_10MBPS_PREAMBLE_WORKAROUND | ||
133 | && ((work->word2.snoip.err_code == 5) | ||
134 | || (work->word2.snoip.err_code == 7))) { | ||
135 | |||
136 | /* | ||
137 | * We received a packet with either an alignment error | ||
138 | * or a FCS error. This may be signalling that we are | ||
139 | * running 10Mbps with GMXX_RXX_FRM_CTL[PRE_CHK} | ||
140 | * off. If this is the case we need to parse the | ||
141 | * packet to determine if we can remove a non spec | ||
142 | * preamble and generate a correct packet. | ||
143 | */ | ||
144 | int interface = cvmx_helper_get_interface_num(work->ipprt); | ||
145 | int index = cvmx_helper_get_interface_index_num(work->ipprt); | ||
146 | union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl; | ||
147 | gmxx_rxx_frm_ctl.u64 = | ||
148 | cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface)); | ||
149 | if (gmxx_rxx_frm_ctl.s.pre_chk == 0) { | ||
150 | |||
151 | uint8_t *ptr = | ||
152 | cvmx_phys_to_ptr(work->packet_ptr.s.addr); | ||
153 | int i = 0; | ||
154 | |||
155 | while (i < work->len - 1) { | ||
156 | if (*ptr != 0x55) | ||
157 | break; | ||
158 | ptr++; | ||
159 | i++; | ||
160 | } | ||
161 | |||
162 | if (*ptr == 0xd5) { | ||
163 | /* | ||
164 | DEBUGPRINT("Port %d received 0xd5 preamble\n", work->ipprt); | ||
165 | */ | ||
166 | work->packet_ptr.s.addr += i + 1; | ||
167 | work->len -= i + 5; | ||
168 | } else if ((*ptr & 0xf) == 0xd) { | ||
169 | /* | ||
170 | DEBUGPRINT("Port %d received 0x?d preamble\n", work->ipprt); | ||
171 | */ | ||
172 | work->packet_ptr.s.addr += i; | ||
173 | work->len -= i + 4; | ||
174 | for (i = 0; i < work->len; i++) { | ||
175 | *ptr = | ||
176 | ((*ptr & 0xf0) >> 4) | | ||
177 | ((*(ptr + 1) & 0xf) << 4); | ||
178 | ptr++; | ||
179 | } | ||
180 | } else { | ||
181 | DEBUGPRINT("Port %d unknown preamble, packet " | ||
182 | "dropped\n", | ||
183 | work->ipprt); | ||
184 | /* | ||
185 | cvmx_helper_dump_packet(work); | ||
186 | */ | ||
187 | cvm_oct_free_work(work); | ||
188 | return 1; | ||
189 | } | ||
190 | } | ||
191 | } else { | ||
192 | DEBUGPRINT("Port %d receive error code %d, packet dropped\n", | ||
193 | work->ipprt, work->word2.snoip.err_code); | ||
194 | cvm_oct_free_work(work); | ||
195 | return 1; | ||
196 | } | ||
197 | |||
198 | return 0; | ||
199 | } | ||
200 | |||
201 | /** | ||
202 | * Tasklet function that is scheduled on a core when an interrupt occurs. | ||
203 | * | ||
204 | * @unused: | ||
205 | */ | ||
206 | void cvm_oct_tasklet_rx(unsigned long unused) | ||
207 | { | ||
208 | const int coreid = cvmx_get_core_num(); | ||
209 | uint64_t old_group_mask; | ||
210 | uint64_t old_scratch; | ||
211 | int rx_count = 0; | ||
212 | int number_to_free; | ||
213 | int num_freed; | ||
214 | int packet_not_copied; | ||
215 | |||
216 | /* Prefetch cvm_oct_device since we know we need it soon */ | ||
217 | prefetch(cvm_oct_device); | ||
218 | |||
219 | if (USE_ASYNC_IOBDMA) { | ||
220 | /* Save scratch in case userspace is using it */ | ||
221 | CVMX_SYNCIOBDMA; | ||
222 | old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH); | ||
223 | } | ||
224 | |||
225 | /* Only allow work for our group (and preserve priorities) */ | ||
226 | old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid)); | ||
227 | cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), | ||
228 | (old_group_mask & ~0xFFFFull) | 1 << pow_receive_group); | ||
229 | |||
230 | if (USE_ASYNC_IOBDMA) | ||
231 | cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT); | ||
232 | |||
233 | while (1) { | ||
234 | struct sk_buff *skb = NULL; | ||
235 | int skb_in_hw; | ||
236 | cvmx_wqe_t *work; | ||
237 | |||
238 | if (USE_ASYNC_IOBDMA) { | ||
239 | work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH); | ||
240 | } else { | ||
241 | if ((INTERRUPT_LIMIT == 0) | ||
242 | || likely(rx_count < MAX_RX_PACKETS)) | ||
243 | work = | ||
244 | cvmx_pow_work_request_sync | ||
245 | (CVMX_POW_NO_WAIT); | ||
246 | else | ||
247 | work = NULL; | ||
248 | } | ||
249 | prefetch(work); | ||
250 | if (work == NULL) | ||
251 | break; | ||
252 | |||
253 | /* | ||
254 | * Limit each core to processing MAX_RX_PACKETS | ||
255 | * packets without a break. This way the RX can't | ||
256 | * starve the TX task. | ||
257 | */ | ||
258 | if (USE_ASYNC_IOBDMA) { | ||
259 | |||
260 | if ((INTERRUPT_LIMIT == 0) | ||
261 | || likely(rx_count < MAX_RX_PACKETS)) | ||
262 | cvmx_pow_work_request_async_nocheck | ||
263 | (CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT); | ||
264 | else { | ||
265 | cvmx_scratch_write64(CVMX_SCR_SCRATCH, | ||
266 | 0x8000000000000000ull); | ||
267 | cvmx_pow_tag_sw_null_nocheck(); | ||
268 | } | ||
269 | } | ||
270 | |||
271 | skb_in_hw = USE_SKBUFFS_IN_HW && work->word2.s.bufs == 1; | ||
272 | if (likely(skb_in_hw)) { | ||
273 | skb = | ||
274 | *(struct sk_buff | ||
275 | **)(cvm_oct_get_buffer_ptr(work->packet_ptr) - | ||
276 | sizeof(void *)); | ||
277 | prefetch(&skb->head); | ||
278 | prefetch(&skb->len); | ||
279 | } | ||
280 | prefetch(cvm_oct_device[work->ipprt]); | ||
281 | |||
282 | rx_count++; | ||
283 | /* Immediately throw away all packets with receive errors */ | ||
284 | if (unlikely(work->word2.snoip.rcv_error)) { | ||
285 | if (cvm_oct_check_rcv_error(work)) | ||
286 | continue; | ||
287 | } | ||
288 | |||
289 | /* | ||
290 | * We can only use the zero copy path if skbuffs are | ||
291 | * in the FPA pool and the packet fits in a single | ||
292 | * buffer. | ||
293 | */ | ||
294 | if (likely(skb_in_hw)) { | ||
295 | /* | ||
296 | * This calculation was changed in case the | ||
297 | * skb header is using a different address | ||
298 | * aliasing type than the buffer. It doesn't | ||
299 | * make any differnece now, but the new one is | ||
300 | * more correct. | ||
301 | */ | ||
302 | skb->data = | ||
303 | skb->head + work->packet_ptr.s.addr - | ||
304 | cvmx_ptr_to_phys(skb->head); | ||
305 | prefetch(skb->data); | ||
306 | skb->len = work->len; | ||
307 | skb_set_tail_pointer(skb, skb->len); | ||
308 | packet_not_copied = 1; | ||
309 | } else { | ||
310 | |||
311 | /* | ||
312 | * We have to copy the packet. First allocate | ||
313 | * an skbuff for it. | ||
314 | */ | ||
315 | skb = dev_alloc_skb(work->len); | ||
316 | if (!skb) { | ||
317 | DEBUGPRINT("Port %d failed to allocate " | ||
318 | "skbuff, packet dropped\n", | ||
319 | work->ipprt); | ||
320 | cvm_oct_free_work(work); | ||
321 | continue; | ||
322 | } | ||
323 | |||
324 | /* | ||
325 | * Check if we've received a packet that was | ||
326 | * entirely stored in the work entry. This is | ||
327 | * untested. | ||
328 | */ | ||
329 | if (unlikely(work->word2.s.bufs == 0)) { | ||
330 | uint8_t *ptr = work->packet_data; | ||
331 | |||
332 | if (likely(!work->word2.s.not_IP)) { | ||
333 | /* | ||
334 | * The beginning of the packet | ||
335 | * moves for IP packets. | ||
336 | */ | ||
337 | if (work->word2.s.is_v6) | ||
338 | ptr += 2; | ||
339 | else | ||
340 | ptr += 6; | ||
341 | } | ||
342 | memcpy(skb_put(skb, work->len), ptr, work->len); | ||
343 | /* No packet buffers to free */ | ||
344 | } else { | ||
345 | int segments = work->word2.s.bufs; | ||
346 | union cvmx_buf_ptr segment_ptr = | ||
347 | work->packet_ptr; | ||
348 | int len = work->len; | ||
349 | |||
350 | while (segments--) { | ||
351 | union cvmx_buf_ptr next_ptr = | ||
352 | *(union cvmx_buf_ptr *) | ||
353 | cvmx_phys_to_ptr(segment_ptr.s. | ||
354 | addr - 8); | ||
355 | /* | ||
356 | * Octeon Errata PKI-100: The segment size is | ||
357 | * wrong. Until it is fixed, calculate the | ||
358 | * segment size based on the packet pool | ||
359 | * buffer size. When it is fixed, the | ||
360 | * following line should be replaced with this | ||
361 | * one: int segment_size = | ||
362 | * segment_ptr.s.size; | ||
363 | */ | ||
364 | int segment_size = | ||
365 | CVMX_FPA_PACKET_POOL_SIZE - | ||
366 | (segment_ptr.s.addr - | ||
367 | (((segment_ptr.s.addr >> 7) - | ||
368 | segment_ptr.s.back) << 7)); | ||
369 | /* Don't copy more than what is left | ||
370 | in the packet */ | ||
371 | if (segment_size > len) | ||
372 | segment_size = len; | ||
373 | /* Copy the data into the packet */ | ||
374 | memcpy(skb_put(skb, segment_size), | ||
375 | cvmx_phys_to_ptr(segment_ptr.s. | ||
376 | addr), | ||
377 | segment_size); | ||
378 | /* Reduce the amount of bytes left | ||
379 | to copy */ | ||
380 | len -= segment_size; | ||
381 | segment_ptr = next_ptr; | ||
382 | } | ||
383 | } | ||
384 | packet_not_copied = 0; | ||
385 | } | ||
386 | |||
387 | if (likely((work->ipprt < TOTAL_NUMBER_OF_PORTS) && | ||
388 | cvm_oct_device[work->ipprt])) { | ||
389 | struct net_device *dev = cvm_oct_device[work->ipprt]; | ||
390 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
391 | |||
392 | /* Only accept packets for devices | ||
393 | that are currently up */ | ||
394 | if (likely(dev->flags & IFF_UP)) { | ||
395 | skb->protocol = eth_type_trans(skb, dev); | ||
396 | skb->dev = dev; | ||
397 | |||
398 | if (unlikely | ||
399 | (work->word2.s.not_IP | ||
400 | || work->word2.s.IP_exc | ||
401 | || work->word2.s.L4_error)) | ||
402 | skb->ip_summed = CHECKSUM_NONE; | ||
403 | else | ||
404 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
405 | |||
406 | /* Increment RX stats for virtual ports */ | ||
407 | if (work->ipprt >= CVMX_PIP_NUM_INPUT_PORTS) { | ||
408 | #ifdef CONFIG_64BIT | ||
409 | atomic64_add(1, (atomic64_t *)&priv->stats.rx_packets); | ||
410 | atomic64_add(skb->len, (atomic64_t *)&priv->stats.rx_bytes); | ||
411 | #else | ||
412 | atomic_add(1, (atomic_t *)&priv->stats.rx_packets); | ||
413 | atomic_add(skb->len, (atomic_t *)&priv->stats.rx_bytes); | ||
414 | #endif | ||
415 | } | ||
416 | netif_receive_skb(skb); | ||
417 | } else { | ||
418 | /* | ||
419 | * Drop any packet received for a | ||
420 | * device that isn't up. | ||
421 | */ | ||
422 | /* | ||
423 | DEBUGPRINT("%s: Device not up, packet dropped\n", | ||
424 | dev->name); | ||
425 | */ | ||
426 | #ifdef CONFIG_64BIT | ||
427 | atomic64_add(1, (atomic64_t *)&priv->stats.rx_dropped); | ||
428 | #else | ||
429 | atomic_add(1, (atomic_t *)&priv->stats.rx_dropped); | ||
430 | #endif | ||
431 | dev_kfree_skb_irq(skb); | ||
432 | } | ||
433 | } else { | ||
434 | /* | ||
435 | * Drop any packet received for a device that | ||
436 | * doesn't exist. | ||
437 | */ | ||
438 | DEBUGPRINT("Port %d not controlled by Linux, packet " | ||
439 | "dropped\n", | ||
440 | work->ipprt); | ||
441 | dev_kfree_skb_irq(skb); | ||
442 | } | ||
443 | /* | ||
444 | * Check to see if the skbuff and work share the same | ||
445 | * packet buffer. | ||
446 | */ | ||
447 | if (USE_SKBUFFS_IN_HW && likely(packet_not_copied)) { | ||
448 | /* | ||
449 | * This buffer needs to be replaced, increment | ||
450 | * the number of buffers we need to free by | ||
451 | * one. | ||
452 | */ | ||
453 | cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE, | ||
454 | 1); | ||
455 | |||
456 | cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, | ||
457 | DONT_WRITEBACK(1)); | ||
458 | } else { | ||
459 | cvm_oct_free_work(work); | ||
460 | } | ||
461 | } | ||
462 | |||
463 | /* Restore the original POW group mask */ | ||
464 | cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask); | ||
465 | if (USE_ASYNC_IOBDMA) { | ||
466 | /* Restore the scratch area */ | ||
467 | cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch); | ||
468 | } | ||
469 | |||
470 | if (USE_SKBUFFS_IN_HW) { | ||
471 | /* Refill the packet buffer pool */ | ||
472 | number_to_free = | ||
473 | cvmx_fau_fetch_and_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0); | ||
474 | |||
475 | if (number_to_free > 0) { | ||
476 | cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE, | ||
477 | -number_to_free); | ||
478 | num_freed = | ||
479 | cvm_oct_mem_fill_fpa(CVMX_FPA_PACKET_POOL, | ||
480 | CVMX_FPA_PACKET_POOL_SIZE, | ||
481 | number_to_free); | ||
482 | if (num_freed != number_to_free) { | ||
483 | cvmx_fau_atomic_add32 | ||
484 | (FAU_NUM_PACKET_BUFFERS_TO_FREE, | ||
485 | number_to_free - num_freed); | ||
486 | } | ||
487 | } | ||
488 | } | ||
489 | } | ||
490 | |||
491 | void cvm_oct_rx_initialize(void) | ||
492 | { | ||
493 | int i; | ||
494 | /* Initialize all of the tasklets */ | ||
495 | for (i = 0; i < NR_CPUS; i++) | ||
496 | tasklet_init(&cvm_oct_tasklet[i].t, cvm_oct_tasklet_rx, 0); | ||
497 | } | ||
498 | |||
499 | void cvm_oct_rx_shutdown(void) | ||
500 | { | ||
501 | int i; | ||
502 | /* Shutdown all of the tasklets */ | ||
503 | for (i = 0; i < NR_CPUS; i++) | ||
504 | tasklet_kill(&cvm_oct_tasklet[i].t); | ||
505 | } | ||
diff --git a/drivers/staging/octeon/ethernet-rx.h b/drivers/staging/octeon/ethernet-rx.h new file mode 100644 index 000000000000..a9b72b87a7a6 --- /dev/null +++ b/drivers/staging/octeon/ethernet-rx.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /********************************************************************* | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | *********************************************************************/ | ||
27 | |||
28 | irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id); | ||
29 | void cvm_oct_poll_controller(struct net_device *dev); | ||
30 | void cvm_oct_tasklet_rx(unsigned long unused); | ||
31 | |||
32 | void cvm_oct_rx_initialize(void); | ||
33 | void cvm_oct_rx_shutdown(void); | ||
diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c new file mode 100644 index 000000000000..58fa39c1d675 --- /dev/null +++ b/drivers/staging/octeon/ethernet-sgmii.c | |||
@@ -0,0 +1,129 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/netdevice.h> | ||
29 | #include <linux/mii.h> | ||
30 | #include <net/dst.h> | ||
31 | |||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "ethernet-defines.h" | ||
35 | #include "octeon-ethernet.h" | ||
36 | #include "ethernet-util.h" | ||
37 | #include "ethernet-common.h" | ||
38 | |||
39 | #include "cvmx-helper.h" | ||
40 | |||
41 | #include "cvmx-gmxx-defs.h" | ||
42 | |||
43 | static int cvm_oct_sgmii_open(struct net_device *dev) | ||
44 | { | ||
45 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
46 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
47 | int interface = INTERFACE(priv->port); | ||
48 | int index = INDEX(priv->port); | ||
49 | cvmx_helper_link_info_t link_info; | ||
50 | |||
51 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
52 | gmx_cfg.s.en = 1; | ||
53 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
54 | |||
55 | if (!octeon_is_simulation()) { | ||
56 | link_info = cvmx_helper_link_get(priv->port); | ||
57 | if (!link_info.s.link_up) | ||
58 | netif_carrier_off(dev); | ||
59 | } | ||
60 | |||
61 | return 0; | ||
62 | } | ||
63 | |||
64 | static int cvm_oct_sgmii_stop(struct net_device *dev) | ||
65 | { | ||
66 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
67 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
68 | int interface = INTERFACE(priv->port); | ||
69 | int index = INDEX(priv->port); | ||
70 | |||
71 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
72 | gmx_cfg.s.en = 0; | ||
73 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
74 | return 0; | ||
75 | } | ||
76 | |||
77 | static void cvm_oct_sgmii_poll(struct net_device *dev) | ||
78 | { | ||
79 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
80 | cvmx_helper_link_info_t link_info; | ||
81 | |||
82 | link_info = cvmx_helper_link_get(priv->port); | ||
83 | if (link_info.u64 == priv->link_info) | ||
84 | return; | ||
85 | |||
86 | link_info = cvmx_helper_link_autoconf(priv->port); | ||
87 | priv->link_info = link_info.u64; | ||
88 | |||
89 | /* Tell Linux */ | ||
90 | if (link_info.s.link_up) { | ||
91 | |||
92 | if (!netif_carrier_ok(dev)) | ||
93 | netif_carrier_on(dev); | ||
94 | if (priv->queue != -1) | ||
95 | DEBUGPRINT | ||
96 | ("%s: %u Mbps %s duplex, port %2d, queue %2d\n", | ||
97 | dev->name, link_info.s.speed, | ||
98 | (link_info.s.full_duplex) ? "Full" : "Half", | ||
99 | priv->port, priv->queue); | ||
100 | else | ||
101 | DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, POW\n", | ||
102 | dev->name, link_info.s.speed, | ||
103 | (link_info.s.full_duplex) ? "Full" : "Half", | ||
104 | priv->port); | ||
105 | } else { | ||
106 | if (netif_carrier_ok(dev)) | ||
107 | netif_carrier_off(dev); | ||
108 | DEBUGPRINT("%s: Link down\n", dev->name); | ||
109 | } | ||
110 | } | ||
111 | |||
112 | int cvm_oct_sgmii_init(struct net_device *dev) | ||
113 | { | ||
114 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
115 | cvm_oct_common_init(dev); | ||
116 | dev->open = cvm_oct_sgmii_open; | ||
117 | dev->stop = cvm_oct_sgmii_stop; | ||
118 | dev->stop(dev); | ||
119 | if (!octeon_is_simulation()) | ||
120 | priv->poll = cvm_oct_sgmii_poll; | ||
121 | |||
122 | /* FIXME: Need autoneg logic */ | ||
123 | return 0; | ||
124 | } | ||
125 | |||
126 | void cvm_oct_sgmii_uninit(struct net_device *dev) | ||
127 | { | ||
128 | cvm_oct_common_uninit(dev); | ||
129 | } | ||
diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c new file mode 100644 index 000000000000..e0971bbe4ddc --- /dev/null +++ b/drivers/staging/octeon/ethernet-spi.c | |||
@@ -0,0 +1,323 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/netdevice.h> | ||
29 | #include <linux/mii.h> | ||
30 | #include <net/dst.h> | ||
31 | |||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "ethernet-defines.h" | ||
35 | #include "octeon-ethernet.h" | ||
36 | #include "ethernet-common.h" | ||
37 | #include "ethernet-util.h" | ||
38 | |||
39 | #include "cvmx-spi.h" | ||
40 | |||
41 | #include <asm/octeon/cvmx-npi-defs.h> | ||
42 | #include "cvmx-spxx-defs.h" | ||
43 | #include "cvmx-stxx-defs.h" | ||
44 | |||
45 | static int number_spi_ports; | ||
46 | static int need_retrain[2] = { 0, 0 }; | ||
47 | |||
48 | static irqreturn_t cvm_oct_spi_rml_interrupt(int cpl, void *dev_id) | ||
49 | { | ||
50 | irqreturn_t return_status = IRQ_NONE; | ||
51 | union cvmx_npi_rsl_int_blocks rsl_int_blocks; | ||
52 | |||
53 | /* Check and see if this interrupt was caused by the GMX block */ | ||
54 | rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS); | ||
55 | if (rsl_int_blocks.s.spx1) { /* 19 - SPX1_INT_REG & STX1_INT_REG */ | ||
56 | |||
57 | union cvmx_spxx_int_reg spx_int_reg; | ||
58 | union cvmx_stxx_int_reg stx_int_reg; | ||
59 | |||
60 | spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(1)); | ||
61 | cvmx_write_csr(CVMX_SPXX_INT_REG(1), spx_int_reg.u64); | ||
62 | if (!need_retrain[1]) { | ||
63 | |||
64 | spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(1)); | ||
65 | if (spx_int_reg.s.spf) | ||
66 | pr_err("SPI1: SRX Spi4 interface down\n"); | ||
67 | if (spx_int_reg.s.calerr) | ||
68 | pr_err("SPI1: SRX Spi4 Calendar table " | ||
69 | "parity error\n"); | ||
70 | if (spx_int_reg.s.syncerr) | ||
71 | pr_err("SPI1: SRX Consecutive Spi4 DIP4 " | ||
72 | "errors have exceeded " | ||
73 | "SPX_ERR_CTL[ERRCNT]\n"); | ||
74 | if (spx_int_reg.s.diperr) | ||
75 | pr_err("SPI1: SRX Spi4 DIP4 error\n"); | ||
76 | if (spx_int_reg.s.tpaovr) | ||
77 | pr_err("SPI1: SRX Selected port has hit " | ||
78 | "TPA overflow\n"); | ||
79 | if (spx_int_reg.s.rsverr) | ||
80 | pr_err("SPI1: SRX Spi4 reserved control " | ||
81 | "word detected\n"); | ||
82 | if (spx_int_reg.s.drwnng) | ||
83 | pr_err("SPI1: SRX Spi4 receive FIFO " | ||
84 | "drowning/overflow\n"); | ||
85 | if (spx_int_reg.s.clserr) | ||
86 | pr_err("SPI1: SRX Spi4 packet closed on " | ||
87 | "non-16B alignment without EOP\n"); | ||
88 | if (spx_int_reg.s.spiovr) | ||
89 | pr_err("SPI1: SRX Spi4 async FIFO overflow\n"); | ||
90 | if (spx_int_reg.s.abnorm) | ||
91 | pr_err("SPI1: SRX Abnormal packet " | ||
92 | "termination (ERR bit)\n"); | ||
93 | if (spx_int_reg.s.prtnxa) | ||
94 | pr_err("SPI1: SRX Port out of range\n"); | ||
95 | } | ||
96 | |||
97 | stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(1)); | ||
98 | cvmx_write_csr(CVMX_STXX_INT_REG(1), stx_int_reg.u64); | ||
99 | if (!need_retrain[1]) { | ||
100 | |||
101 | stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(1)); | ||
102 | if (stx_int_reg.s.syncerr) | ||
103 | pr_err("SPI1: STX Interface encountered a " | ||
104 | "fatal error\n"); | ||
105 | if (stx_int_reg.s.frmerr) | ||
106 | pr_err("SPI1: STX FRMCNT has exceeded " | ||
107 | "STX_DIP_CNT[MAXFRM]\n"); | ||
108 | if (stx_int_reg.s.unxfrm) | ||
109 | pr_err("SPI1: STX Unexpected framing " | ||
110 | "sequence\n"); | ||
111 | if (stx_int_reg.s.nosync) | ||
112 | pr_err("SPI1: STX ERRCNT has exceeded " | ||
113 | "STX_DIP_CNT[MAXDIP]\n"); | ||
114 | if (stx_int_reg.s.diperr) | ||
115 | pr_err("SPI1: STX DIP2 error on the Spi4 " | ||
116 | "Status channel\n"); | ||
117 | if (stx_int_reg.s.datovr) | ||
118 | pr_err("SPI1: STX Spi4 FIFO overflow error\n"); | ||
119 | if (stx_int_reg.s.ovrbst) | ||
120 | pr_err("SPI1: STX Transmit packet burst " | ||
121 | "too big\n"); | ||
122 | if (stx_int_reg.s.calpar1) | ||
123 | pr_err("SPI1: STX Calendar Table Parity " | ||
124 | "Error Bank1\n"); | ||
125 | if (stx_int_reg.s.calpar0) | ||
126 | pr_err("SPI1: STX Calendar Table Parity " | ||
127 | "Error Bank0\n"); | ||
128 | } | ||
129 | |||
130 | cvmx_write_csr(CVMX_SPXX_INT_MSK(1), 0); | ||
131 | cvmx_write_csr(CVMX_STXX_INT_MSK(1), 0); | ||
132 | need_retrain[1] = 1; | ||
133 | return_status = IRQ_HANDLED; | ||
134 | } | ||
135 | |||
136 | if (rsl_int_blocks.s.spx0) { /* 18 - SPX0_INT_REG & STX0_INT_REG */ | ||
137 | union cvmx_spxx_int_reg spx_int_reg; | ||
138 | union cvmx_stxx_int_reg stx_int_reg; | ||
139 | |||
140 | spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(0)); | ||
141 | cvmx_write_csr(CVMX_SPXX_INT_REG(0), spx_int_reg.u64); | ||
142 | if (!need_retrain[0]) { | ||
143 | |||
144 | spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(0)); | ||
145 | if (spx_int_reg.s.spf) | ||
146 | pr_err("SPI0: SRX Spi4 interface down\n"); | ||
147 | if (spx_int_reg.s.calerr) | ||
148 | pr_err("SPI0: SRX Spi4 Calendar table " | ||
149 | "parity error\n"); | ||
150 | if (spx_int_reg.s.syncerr) | ||
151 | pr_err("SPI0: SRX Consecutive Spi4 DIP4 " | ||
152 | "errors have exceeded " | ||
153 | "SPX_ERR_CTL[ERRCNT]\n"); | ||
154 | if (spx_int_reg.s.diperr) | ||
155 | pr_err("SPI0: SRX Spi4 DIP4 error\n"); | ||
156 | if (spx_int_reg.s.tpaovr) | ||
157 | pr_err("SPI0: SRX Selected port has hit " | ||
158 | "TPA overflow\n"); | ||
159 | if (spx_int_reg.s.rsverr) | ||
160 | pr_err("SPI0: SRX Spi4 reserved control " | ||
161 | "word detected\n"); | ||
162 | if (spx_int_reg.s.drwnng) | ||
163 | pr_err("SPI0: SRX Spi4 receive FIFO " | ||
164 | "drowning/overflow\n"); | ||
165 | if (spx_int_reg.s.clserr) | ||
166 | pr_err("SPI0: SRX Spi4 packet closed on " | ||
167 | "non-16B alignment without EOP\n"); | ||
168 | if (spx_int_reg.s.spiovr) | ||
169 | pr_err("SPI0: SRX Spi4 async FIFO overflow\n"); | ||
170 | if (spx_int_reg.s.abnorm) | ||
171 | pr_err("SPI0: SRX Abnormal packet " | ||
172 | "termination (ERR bit)\n"); | ||
173 | if (spx_int_reg.s.prtnxa) | ||
174 | pr_err("SPI0: SRX Port out of range\n"); | ||
175 | } | ||
176 | |||
177 | stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(0)); | ||
178 | cvmx_write_csr(CVMX_STXX_INT_REG(0), stx_int_reg.u64); | ||
179 | if (!need_retrain[0]) { | ||
180 | |||
181 | stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(0)); | ||
182 | if (stx_int_reg.s.syncerr) | ||
183 | pr_err("SPI0: STX Interface encountered a " | ||
184 | "fatal error\n"); | ||
185 | if (stx_int_reg.s.frmerr) | ||
186 | pr_err("SPI0: STX FRMCNT has exceeded " | ||
187 | "STX_DIP_CNT[MAXFRM]\n"); | ||
188 | if (stx_int_reg.s.unxfrm) | ||
189 | pr_err("SPI0: STX Unexpected framing " | ||
190 | "sequence\n"); | ||
191 | if (stx_int_reg.s.nosync) | ||
192 | pr_err("SPI0: STX ERRCNT has exceeded " | ||
193 | "STX_DIP_CNT[MAXDIP]\n"); | ||
194 | if (stx_int_reg.s.diperr) | ||
195 | pr_err("SPI0: STX DIP2 error on the Spi4 " | ||
196 | "Status channel\n"); | ||
197 | if (stx_int_reg.s.datovr) | ||
198 | pr_err("SPI0: STX Spi4 FIFO overflow error\n"); | ||
199 | if (stx_int_reg.s.ovrbst) | ||
200 | pr_err("SPI0: STX Transmit packet burst " | ||
201 | "too big\n"); | ||
202 | if (stx_int_reg.s.calpar1) | ||
203 | pr_err("SPI0: STX Calendar Table Parity " | ||
204 | "Error Bank1\n"); | ||
205 | if (stx_int_reg.s.calpar0) | ||
206 | pr_err("SPI0: STX Calendar Table Parity " | ||
207 | "Error Bank0\n"); | ||
208 | } | ||
209 | |||
210 | cvmx_write_csr(CVMX_SPXX_INT_MSK(0), 0); | ||
211 | cvmx_write_csr(CVMX_STXX_INT_MSK(0), 0); | ||
212 | need_retrain[0] = 1; | ||
213 | return_status = IRQ_HANDLED; | ||
214 | } | ||
215 | |||
216 | return return_status; | ||
217 | } | ||
218 | |||
219 | static void cvm_oct_spi_enable_error_reporting(int interface) | ||
220 | { | ||
221 | union cvmx_spxx_int_msk spxx_int_msk; | ||
222 | union cvmx_stxx_int_msk stxx_int_msk; | ||
223 | |||
224 | spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); | ||
225 | spxx_int_msk.s.calerr = 1; | ||
226 | spxx_int_msk.s.syncerr = 1; | ||
227 | spxx_int_msk.s.diperr = 1; | ||
228 | spxx_int_msk.s.tpaovr = 1; | ||
229 | spxx_int_msk.s.rsverr = 1; | ||
230 | spxx_int_msk.s.drwnng = 1; | ||
231 | spxx_int_msk.s.clserr = 1; | ||
232 | spxx_int_msk.s.spiovr = 1; | ||
233 | spxx_int_msk.s.abnorm = 1; | ||
234 | spxx_int_msk.s.prtnxa = 1; | ||
235 | cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); | ||
236 | |||
237 | stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface)); | ||
238 | stxx_int_msk.s.frmerr = 1; | ||
239 | stxx_int_msk.s.unxfrm = 1; | ||
240 | stxx_int_msk.s.nosync = 1; | ||
241 | stxx_int_msk.s.diperr = 1; | ||
242 | stxx_int_msk.s.datovr = 1; | ||
243 | stxx_int_msk.s.ovrbst = 1; | ||
244 | stxx_int_msk.s.calpar1 = 1; | ||
245 | stxx_int_msk.s.calpar0 = 1; | ||
246 | cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64); | ||
247 | } | ||
248 | |||
249 | static void cvm_oct_spi_poll(struct net_device *dev) | ||
250 | { | ||
251 | static int spi4000_port; | ||
252 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
253 | int interface; | ||
254 | |||
255 | for (interface = 0; interface < 2; interface++) { | ||
256 | |||
257 | if ((priv->port == interface * 16) && need_retrain[interface]) { | ||
258 | |||
259 | if (cvmx_spi_restart_interface | ||
260 | (interface, CVMX_SPI_MODE_DUPLEX, 10) == 0) { | ||
261 | need_retrain[interface] = 0; | ||
262 | cvm_oct_spi_enable_error_reporting(interface); | ||
263 | } | ||
264 | } | ||
265 | |||
266 | /* | ||
267 | * The SPI4000 TWSI interface is very slow. In order | ||
268 | * not to bring the system to a crawl, we only poll a | ||
269 | * single port every second. This means negotiation | ||
270 | * speed changes take up to 10 seconds, but at least | ||
271 | * we don't waste absurd amounts of time waiting for | ||
272 | * TWSI. | ||
273 | */ | ||
274 | if (priv->port == spi4000_port) { | ||
275 | /* | ||
276 | * This function does nothing if it is called on an | ||
277 | * interface without a SPI4000. | ||
278 | */ | ||
279 | cvmx_spi4000_check_speed(interface, priv->port); | ||
280 | /* | ||
281 | * Normal ordering increments. By decrementing | ||
282 | * we only match once per iteration. | ||
283 | */ | ||
284 | spi4000_port--; | ||
285 | if (spi4000_port < 0) | ||
286 | spi4000_port = 10; | ||
287 | } | ||
288 | } | ||
289 | } | ||
290 | |||
291 | int cvm_oct_spi_init(struct net_device *dev) | ||
292 | { | ||
293 | int r; | ||
294 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
295 | |||
296 | if (number_spi_ports == 0) { | ||
297 | r = request_irq(OCTEON_IRQ_RML, cvm_oct_spi_rml_interrupt, | ||
298 | IRQF_SHARED, "SPI", &number_spi_ports); | ||
299 | } | ||
300 | number_spi_ports++; | ||
301 | |||
302 | if ((priv->port == 0) || (priv->port == 16)) { | ||
303 | cvm_oct_spi_enable_error_reporting(INTERFACE(priv->port)); | ||
304 | priv->poll = cvm_oct_spi_poll; | ||
305 | } | ||
306 | cvm_oct_common_init(dev); | ||
307 | return 0; | ||
308 | } | ||
309 | |||
310 | void cvm_oct_spi_uninit(struct net_device *dev) | ||
311 | { | ||
312 | int interface; | ||
313 | |||
314 | cvm_oct_common_uninit(dev); | ||
315 | number_spi_ports--; | ||
316 | if (number_spi_ports == 0) { | ||
317 | for (interface = 0; interface < 2; interface++) { | ||
318 | cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); | ||
319 | cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); | ||
320 | } | ||
321 | free_irq(8 + 46, &number_spi_ports); | ||
322 | } | ||
323 | } | ||
diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c new file mode 100644 index 000000000000..77b7122c8fdb --- /dev/null +++ b/drivers/staging/octeon/ethernet-tx.c | |||
@@ -0,0 +1,634 @@ | |||
1 | /********************************************************************* | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | *********************************************************************/ | ||
27 | #include <linux/module.h> | ||
28 | #include <linux/kernel.h> | ||
29 | #include <linux/netdevice.h> | ||
30 | #include <linux/init.h> | ||
31 | #include <linux/etherdevice.h> | ||
32 | #include <linux/ip.h> | ||
33 | #include <linux/string.h> | ||
34 | #include <linux/ethtool.h> | ||
35 | #include <linux/mii.h> | ||
36 | #include <linux/seq_file.h> | ||
37 | #include <linux/proc_fs.h> | ||
38 | #include <net/dst.h> | ||
39 | #ifdef CONFIG_XFRM | ||
40 | #include <linux/xfrm.h> | ||
41 | #include <net/xfrm.h> | ||
42 | #endif /* CONFIG_XFRM */ | ||
43 | |||
44 | #include <asm/atomic.h> | ||
45 | |||
46 | #include <asm/octeon/octeon.h> | ||
47 | |||
48 | #include "ethernet-defines.h" | ||
49 | #include "octeon-ethernet.h" | ||
50 | #include "ethernet-util.h" | ||
51 | |||
52 | #include "cvmx-wqe.h" | ||
53 | #include "cvmx-fau.h" | ||
54 | #include "cvmx-pko.h" | ||
55 | #include "cvmx-helper.h" | ||
56 | |||
57 | #include "cvmx-gmxx-defs.h" | ||
58 | |||
59 | /* | ||
60 | * You can define GET_SKBUFF_QOS() to override how the skbuff output | ||
61 | * function determines which output queue is used. The default | ||
62 | * implementation always uses the base queue for the port. If, for | ||
63 | * example, you wanted to use the skb->priority fieid, define | ||
64 | * GET_SKBUFF_QOS as: #define GET_SKBUFF_QOS(skb) ((skb)->priority) | ||
65 | */ | ||
66 | #ifndef GET_SKBUFF_QOS | ||
67 | #define GET_SKBUFF_QOS(skb) 0 | ||
68 | #endif | ||
69 | |||
70 | /** | ||
71 | * Packet transmit | ||
72 | * | ||
73 | * @skb: Packet to send | ||
74 | * @dev: Device info structure | ||
75 | * Returns Always returns zero | ||
76 | */ | ||
77 | int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) | ||
78 | { | ||
79 | cvmx_pko_command_word0_t pko_command; | ||
80 | union cvmx_buf_ptr hw_buffer; | ||
81 | uint64_t old_scratch; | ||
82 | uint64_t old_scratch2; | ||
83 | int dropped; | ||
84 | int qos; | ||
85 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
86 | int32_t in_use; | ||
87 | int32_t buffers_to_free; | ||
88 | #if REUSE_SKBUFFS_WITHOUT_FREE | ||
89 | unsigned char *fpa_head; | ||
90 | #endif | ||
91 | |||
92 | /* | ||
93 | * Prefetch the private data structure. It is larger that one | ||
94 | * cache line. | ||
95 | */ | ||
96 | prefetch(priv); | ||
97 | |||
98 | /* Start off assuming no drop */ | ||
99 | dropped = 0; | ||
100 | |||
101 | /* | ||
102 | * The check on CVMX_PKO_QUEUES_PER_PORT_* is designed to | ||
103 | * completely remove "qos" in the event neither interface | ||
104 | * supports multiple queues per port. | ||
105 | */ | ||
106 | if ((CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 > 1) || | ||
107 | (CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 > 1)) { | ||
108 | qos = GET_SKBUFF_QOS(skb); | ||
109 | if (qos <= 0) | ||
110 | qos = 0; | ||
111 | else if (qos >= cvmx_pko_get_num_queues(priv->port)) | ||
112 | qos = 0; | ||
113 | } else | ||
114 | qos = 0; | ||
115 | |||
116 | if (USE_ASYNC_IOBDMA) { | ||
117 | /* Save scratch in case userspace is using it */ | ||
118 | CVMX_SYNCIOBDMA; | ||
119 | old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH); | ||
120 | old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8); | ||
121 | |||
122 | /* | ||
123 | * Assume we're going to be able t osend this | ||
124 | * packet. Fetch and increment the number of pending | ||
125 | * packets for output. | ||
126 | */ | ||
127 | cvmx_fau_async_fetch_and_add32(CVMX_SCR_SCRATCH + 8, | ||
128 | FAU_NUM_PACKET_BUFFERS_TO_FREE, | ||
129 | 0); | ||
130 | cvmx_fau_async_fetch_and_add32(CVMX_SCR_SCRATCH, | ||
131 | priv->fau + qos * 4, 1); | ||
132 | } | ||
133 | |||
134 | /* | ||
135 | * The CN3XXX series of parts has an errata (GMX-401) which | ||
136 | * causes the GMX block to hang if a collision occurs towards | ||
137 | * the end of a <68 byte packet. As a workaround for this, we | ||
138 | * pad packets to be 68 bytes whenever we are in half duplex | ||
139 | * mode. We don't handle the case of having a small packet but | ||
140 | * no room to add the padding. The kernel should always give | ||
141 | * us at least a cache line | ||
142 | */ | ||
143 | if ((skb->len < 64) && OCTEON_IS_MODEL(OCTEON_CN3XXX)) { | ||
144 | union cvmx_gmxx_prtx_cfg gmx_prt_cfg; | ||
145 | int interface = INTERFACE(priv->port); | ||
146 | int index = INDEX(priv->port); | ||
147 | |||
148 | if (interface < 2) { | ||
149 | /* We only need to pad packet in half duplex mode */ | ||
150 | gmx_prt_cfg.u64 = | ||
151 | cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
152 | if (gmx_prt_cfg.s.duplex == 0) { | ||
153 | int add_bytes = 64 - skb->len; | ||
154 | if ((skb_tail_pointer(skb) + add_bytes) <= | ||
155 | skb_end_pointer(skb)) | ||
156 | memset(__skb_put(skb, add_bytes), 0, | ||
157 | add_bytes); | ||
158 | } | ||
159 | } | ||
160 | } | ||
161 | |||
162 | /* Build the PKO buffer pointer */ | ||
163 | hw_buffer.u64 = 0; | ||
164 | hw_buffer.s.addr = cvmx_ptr_to_phys(skb->data); | ||
165 | hw_buffer.s.pool = 0; | ||
166 | hw_buffer.s.size = | ||
167 | (unsigned long)skb_end_pointer(skb) - (unsigned long)skb->head; | ||
168 | |||
169 | /* Build the PKO command */ | ||
170 | pko_command.u64 = 0; | ||
171 | pko_command.s.n2 = 1; /* Don't pollute L2 with the outgoing packet */ | ||
172 | pko_command.s.segs = 1; | ||
173 | pko_command.s.total_bytes = skb->len; | ||
174 | pko_command.s.size0 = CVMX_FAU_OP_SIZE_32; | ||
175 | pko_command.s.subone0 = 1; | ||
176 | |||
177 | pko_command.s.dontfree = 1; | ||
178 | pko_command.s.reg0 = priv->fau + qos * 4; | ||
179 | /* | ||
180 | * See if we can put this skb in the FPA pool. Any strange | ||
181 | * behavior from the Linux networking stack will most likely | ||
182 | * be caused by a bug in the following code. If some field is | ||
183 | * in use by the network stack and get carried over when a | ||
184 | * buffer is reused, bad thing may happen. If in doubt and | ||
185 | * you dont need the absolute best performance, disable the | ||
186 | * define REUSE_SKBUFFS_WITHOUT_FREE. The reuse of buffers has | ||
187 | * shown a 25% increase in performance under some loads. | ||
188 | */ | ||
189 | #if REUSE_SKBUFFS_WITHOUT_FREE | ||
190 | fpa_head = skb->head + 128 - ((unsigned long)skb->head & 0x7f); | ||
191 | if (unlikely(skb->data < fpa_head)) { | ||
192 | /* | ||
193 | * printk("TX buffer beginning can't meet FPA | ||
194 | * alignment constraints\n"); | ||
195 | */ | ||
196 | goto dont_put_skbuff_in_hw; | ||
197 | } | ||
198 | if (unlikely | ||
199 | ((skb_end_pointer(skb) - fpa_head) < CVMX_FPA_PACKET_POOL_SIZE)) { | ||
200 | /* | ||
201 | printk("TX buffer isn't large enough for the FPA\n"); | ||
202 | */ | ||
203 | goto dont_put_skbuff_in_hw; | ||
204 | } | ||
205 | if (unlikely(skb_shared(skb))) { | ||
206 | /* | ||
207 | printk("TX buffer sharing data with someone else\n"); | ||
208 | */ | ||
209 | goto dont_put_skbuff_in_hw; | ||
210 | } | ||
211 | if (unlikely(skb_cloned(skb))) { | ||
212 | /* | ||
213 | printk("TX buffer has been cloned\n"); | ||
214 | */ | ||
215 | goto dont_put_skbuff_in_hw; | ||
216 | } | ||
217 | if (unlikely(skb_header_cloned(skb))) { | ||
218 | /* | ||
219 | printk("TX buffer header has been cloned\n"); | ||
220 | */ | ||
221 | goto dont_put_skbuff_in_hw; | ||
222 | } | ||
223 | if (unlikely(skb->destructor)) { | ||
224 | /* | ||
225 | printk("TX buffer has a destructor\n"); | ||
226 | */ | ||
227 | goto dont_put_skbuff_in_hw; | ||
228 | } | ||
229 | if (unlikely(skb_shinfo(skb)->nr_frags)) { | ||
230 | /* | ||
231 | printk("TX buffer has fragments\n"); | ||
232 | */ | ||
233 | goto dont_put_skbuff_in_hw; | ||
234 | } | ||
235 | if (unlikely | ||
236 | (skb->truesize != | ||
237 | sizeof(*skb) + skb_end_pointer(skb) - skb->head)) { | ||
238 | /* | ||
239 | printk("TX buffer truesize has been changed\n"); | ||
240 | */ | ||
241 | goto dont_put_skbuff_in_hw; | ||
242 | } | ||
243 | |||
244 | /* | ||
245 | * We can use this buffer in the FPA. We don't need the FAU | ||
246 | * update anymore | ||
247 | */ | ||
248 | pko_command.s.reg0 = 0; | ||
249 | pko_command.s.dontfree = 0; | ||
250 | |||
251 | hw_buffer.s.back = (skb->data - fpa_head) >> 7; | ||
252 | *(struct sk_buff **)(fpa_head - sizeof(void *)) = skb; | ||
253 | |||
254 | /* | ||
255 | * The skbuff will be reused without ever being freed. We must | ||
256 | * cleanup a bunch of Linux stuff. | ||
257 | */ | ||
258 | dst_release(skb->dst); | ||
259 | skb->dst = NULL; | ||
260 | #ifdef CONFIG_XFRM | ||
261 | secpath_put(skb->sp); | ||
262 | skb->sp = NULL; | ||
263 | #endif | ||
264 | nf_reset(skb); | ||
265 | |||
266 | #ifdef CONFIG_NET_SCHED | ||
267 | skb->tc_index = 0; | ||
268 | #ifdef CONFIG_NET_CLS_ACT | ||
269 | skb->tc_verd = 0; | ||
270 | #endif /* CONFIG_NET_CLS_ACT */ | ||
271 | #endif /* CONFIG_NET_SCHED */ | ||
272 | |||
273 | dont_put_skbuff_in_hw: | ||
274 | #endif /* REUSE_SKBUFFS_WITHOUT_FREE */ | ||
275 | |||
276 | /* Check if we can use the hardware checksumming */ | ||
277 | if (USE_HW_TCPUDP_CHECKSUM && (skb->protocol == htons(ETH_P_IP)) && | ||
278 | (ip_hdr(skb)->version == 4) && (ip_hdr(skb)->ihl == 5) && | ||
279 | ((ip_hdr(skb)->frag_off == 0) || (ip_hdr(skb)->frag_off == 1 << 14)) | ||
280 | && ((ip_hdr(skb)->protocol == IP_PROTOCOL_TCP) | ||
281 | || (ip_hdr(skb)->protocol == IP_PROTOCOL_UDP))) { | ||
282 | /* Use hardware checksum calc */ | ||
283 | pko_command.s.ipoffp1 = sizeof(struct ethhdr) + 1; | ||
284 | } | ||
285 | |||
286 | if (USE_ASYNC_IOBDMA) { | ||
287 | /* Get the number of skbuffs in use by the hardware */ | ||
288 | CVMX_SYNCIOBDMA; | ||
289 | in_use = cvmx_scratch_read64(CVMX_SCR_SCRATCH); | ||
290 | buffers_to_free = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8); | ||
291 | } else { | ||
292 | /* Get the number of skbuffs in use by the hardware */ | ||
293 | in_use = cvmx_fau_fetch_and_add32(priv->fau + qos * 4, 1); | ||
294 | buffers_to_free = | ||
295 | cvmx_fau_fetch_and_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0); | ||
296 | } | ||
297 | |||
298 | /* | ||
299 | * If we're sending faster than the receive can free them then | ||
300 | * don't do the HW free. | ||
301 | */ | ||
302 | if ((buffers_to_free < -100) && !pko_command.s.dontfree) { | ||
303 | pko_command.s.dontfree = 1; | ||
304 | pko_command.s.reg0 = priv->fau + qos * 4; | ||
305 | } | ||
306 | |||
307 | cvmx_pko_send_packet_prepare(priv->port, priv->queue + qos, | ||
308 | CVMX_PKO_LOCK_CMD_QUEUE); | ||
309 | |||
310 | /* Drop this packet if we have too many already queued to the HW */ | ||
311 | if (unlikely | ||
312 | (skb_queue_len(&priv->tx_free_list[qos]) >= MAX_OUT_QUEUE_DEPTH)) { | ||
313 | /* | ||
314 | DEBUGPRINT("%s: Tx dropped. Too many queued\n", dev->name); | ||
315 | */ | ||
316 | dropped = 1; | ||
317 | } | ||
318 | /* Send the packet to the output queue */ | ||
319 | else if (unlikely | ||
320 | (cvmx_pko_send_packet_finish | ||
321 | (priv->port, priv->queue + qos, pko_command, hw_buffer, | ||
322 | CVMX_PKO_LOCK_CMD_QUEUE))) { | ||
323 | DEBUGPRINT("%s: Failed to send the packet\n", dev->name); | ||
324 | dropped = 1; | ||
325 | } | ||
326 | |||
327 | if (USE_ASYNC_IOBDMA) { | ||
328 | /* Restore the scratch area */ | ||
329 | cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch); | ||
330 | cvmx_scratch_write64(CVMX_SCR_SCRATCH + 8, old_scratch2); | ||
331 | } | ||
332 | |||
333 | if (unlikely(dropped)) { | ||
334 | dev_kfree_skb_any(skb); | ||
335 | cvmx_fau_atomic_add32(priv->fau + qos * 4, -1); | ||
336 | priv->stats.tx_dropped++; | ||
337 | } else { | ||
338 | if (USE_SKBUFFS_IN_HW) { | ||
339 | /* Put this packet on the queue to be freed later */ | ||
340 | if (pko_command.s.dontfree) | ||
341 | skb_queue_tail(&priv->tx_free_list[qos], skb); | ||
342 | else { | ||
343 | cvmx_fau_atomic_add32 | ||
344 | (FAU_NUM_PACKET_BUFFERS_TO_FREE, -1); | ||
345 | cvmx_fau_atomic_add32(priv->fau + qos * 4, -1); | ||
346 | } | ||
347 | } else { | ||
348 | /* Put this packet on the queue to be freed later */ | ||
349 | skb_queue_tail(&priv->tx_free_list[qos], skb); | ||
350 | } | ||
351 | } | ||
352 | |||
353 | /* Free skbuffs not in use by the hardware, possibly two at a time */ | ||
354 | if (skb_queue_len(&priv->tx_free_list[qos]) > in_use) { | ||
355 | spin_lock(&priv->tx_free_list[qos].lock); | ||
356 | /* | ||
357 | * Check again now that we have the lock. It might | ||
358 | * have changed. | ||
359 | */ | ||
360 | if (skb_queue_len(&priv->tx_free_list[qos]) > in_use) | ||
361 | dev_kfree_skb(__skb_dequeue(&priv->tx_free_list[qos])); | ||
362 | if (skb_queue_len(&priv->tx_free_list[qos]) > in_use) | ||
363 | dev_kfree_skb(__skb_dequeue(&priv->tx_free_list[qos])); | ||
364 | spin_unlock(&priv->tx_free_list[qos].lock); | ||
365 | } | ||
366 | |||
367 | return 0; | ||
368 | } | ||
369 | |||
370 | /** | ||
371 | * Packet transmit to the POW | ||
372 | * | ||
373 | * @skb: Packet to send | ||
374 | * @dev: Device info structure | ||
375 | * Returns Always returns zero | ||
376 | */ | ||
377 | int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev) | ||
378 | { | ||
379 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
380 | void *packet_buffer; | ||
381 | void *copy_location; | ||
382 | |||
383 | /* Get a work queue entry */ | ||
384 | cvmx_wqe_t *work = cvmx_fpa_alloc(CVMX_FPA_WQE_POOL); | ||
385 | if (unlikely(work == NULL)) { | ||
386 | DEBUGPRINT("%s: Failed to allocate a work queue entry\n", | ||
387 | dev->name); | ||
388 | priv->stats.tx_dropped++; | ||
389 | dev_kfree_skb(skb); | ||
390 | return 0; | ||
391 | } | ||
392 | |||
393 | /* Get a packet buffer */ | ||
394 | packet_buffer = cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL); | ||
395 | if (unlikely(packet_buffer == NULL)) { | ||
396 | DEBUGPRINT("%s: Failed to allocate a packet buffer\n", | ||
397 | dev->name); | ||
398 | cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, DONT_WRITEBACK(1)); | ||
399 | priv->stats.tx_dropped++; | ||
400 | dev_kfree_skb(skb); | ||
401 | return 0; | ||
402 | } | ||
403 | |||
404 | /* | ||
405 | * Calculate where we need to copy the data to. We need to | ||
406 | * leave 8 bytes for a next pointer (unused). We also need to | ||
407 | * include any configure skip. Then we need to align the IP | ||
408 | * packet src and dest into the same 64bit word. The below | ||
409 | * calculation may add a little extra, but that doesn't | ||
410 | * hurt. | ||
411 | */ | ||
412 | copy_location = packet_buffer + sizeof(uint64_t); | ||
413 | copy_location += ((CVMX_HELPER_FIRST_MBUFF_SKIP + 7) & 0xfff8) + 6; | ||
414 | |||
415 | /* | ||
416 | * We have to copy the packet since whoever processes this | ||
417 | * packet will free it to a hardware pool. We can't use the | ||
418 | * trick of counting outstanding packets like in | ||
419 | * cvm_oct_xmit. | ||
420 | */ | ||
421 | memcpy(copy_location, skb->data, skb->len); | ||
422 | |||
423 | /* | ||
424 | * Fill in some of the work queue fields. We may need to add | ||
425 | * more if the software at the other end needs them. | ||
426 | */ | ||
427 | work->hw_chksum = skb->csum; | ||
428 | work->len = skb->len; | ||
429 | work->ipprt = priv->port; | ||
430 | work->qos = priv->port & 0x7; | ||
431 | work->grp = pow_send_group; | ||
432 | work->tag_type = CVMX_HELPER_INPUT_TAG_TYPE; | ||
433 | work->tag = pow_send_group; /* FIXME */ | ||
434 | /* Default to zero. Sets of zero later are commented out */ | ||
435 | work->word2.u64 = 0; | ||
436 | work->word2.s.bufs = 1; | ||
437 | work->packet_ptr.u64 = 0; | ||
438 | work->packet_ptr.s.addr = cvmx_ptr_to_phys(copy_location); | ||
439 | work->packet_ptr.s.pool = CVMX_FPA_PACKET_POOL; | ||
440 | work->packet_ptr.s.size = CVMX_FPA_PACKET_POOL_SIZE; | ||
441 | work->packet_ptr.s.back = (copy_location - packet_buffer) >> 7; | ||
442 | |||
443 | if (skb->protocol == htons(ETH_P_IP)) { | ||
444 | work->word2.s.ip_offset = 14; | ||
445 | #if 0 | ||
446 | work->word2.s.vlan_valid = 0; /* FIXME */ | ||
447 | work->word2.s.vlan_cfi = 0; /* FIXME */ | ||
448 | work->word2.s.vlan_id = 0; /* FIXME */ | ||
449 | work->word2.s.dec_ipcomp = 0; /* FIXME */ | ||
450 | #endif | ||
451 | work->word2.s.tcp_or_udp = | ||
452 | (ip_hdr(skb)->protocol == IP_PROTOCOL_TCP) | ||
453 | || (ip_hdr(skb)->protocol == IP_PROTOCOL_UDP); | ||
454 | #if 0 | ||
455 | /* FIXME */ | ||
456 | work->word2.s.dec_ipsec = 0; | ||
457 | /* We only support IPv4 right now */ | ||
458 | work->word2.s.is_v6 = 0; | ||
459 | /* Hardware would set to zero */ | ||
460 | work->word2.s.software = 0; | ||
461 | /* No error, packet is internal */ | ||
462 | work->word2.s.L4_error = 0; | ||
463 | #endif | ||
464 | work->word2.s.is_frag = !((ip_hdr(skb)->frag_off == 0) | ||
465 | || (ip_hdr(skb)->frag_off == | ||
466 | 1 << 14)); | ||
467 | #if 0 | ||
468 | /* Assume Linux is sending a good packet */ | ||
469 | work->word2.s.IP_exc = 0; | ||
470 | #endif | ||
471 | work->word2.s.is_bcast = (skb->pkt_type == PACKET_BROADCAST); | ||
472 | work->word2.s.is_mcast = (skb->pkt_type == PACKET_MULTICAST); | ||
473 | #if 0 | ||
474 | /* This is an IP packet */ | ||
475 | work->word2.s.not_IP = 0; | ||
476 | /* No error, packet is internal */ | ||
477 | work->word2.s.rcv_error = 0; | ||
478 | /* No error, packet is internal */ | ||
479 | work->word2.s.err_code = 0; | ||
480 | #endif | ||
481 | |||
482 | /* | ||
483 | * When copying the data, include 4 bytes of the | ||
484 | * ethernet header to align the same way hardware | ||
485 | * does. | ||
486 | */ | ||
487 | memcpy(work->packet_data, skb->data + 10, | ||
488 | sizeof(work->packet_data)); | ||
489 | } else { | ||
490 | #if 0 | ||
491 | work->word2.snoip.vlan_valid = 0; /* FIXME */ | ||
492 | work->word2.snoip.vlan_cfi = 0; /* FIXME */ | ||
493 | work->word2.snoip.vlan_id = 0; /* FIXME */ | ||
494 | work->word2.snoip.software = 0; /* Hardware would set to zero */ | ||
495 | #endif | ||
496 | work->word2.snoip.is_rarp = skb->protocol == htons(ETH_P_RARP); | ||
497 | work->word2.snoip.is_arp = skb->protocol == htons(ETH_P_ARP); | ||
498 | work->word2.snoip.is_bcast = | ||
499 | (skb->pkt_type == PACKET_BROADCAST); | ||
500 | work->word2.snoip.is_mcast = | ||
501 | (skb->pkt_type == PACKET_MULTICAST); | ||
502 | work->word2.snoip.not_IP = 1; /* IP was done up above */ | ||
503 | #if 0 | ||
504 | /* No error, packet is internal */ | ||
505 | work->word2.snoip.rcv_error = 0; | ||
506 | /* No error, packet is internal */ | ||
507 | work->word2.snoip.err_code = 0; | ||
508 | #endif | ||
509 | memcpy(work->packet_data, skb->data, sizeof(work->packet_data)); | ||
510 | } | ||
511 | |||
512 | /* Submit the packet to the POW */ | ||
513 | cvmx_pow_work_submit(work, work->tag, work->tag_type, work->qos, | ||
514 | work->grp); | ||
515 | priv->stats.tx_packets++; | ||
516 | priv->stats.tx_bytes += skb->len; | ||
517 | dev_kfree_skb(skb); | ||
518 | return 0; | ||
519 | } | ||
520 | |||
521 | /** | ||
522 | * Transmit a work queue entry out of the ethernet port. Both | ||
523 | * the work queue entry and the packet data can optionally be | ||
524 | * freed. The work will be freed on error as well. | ||
525 | * | ||
526 | * @dev: Device to transmit out. | ||
527 | * @work_queue_entry: | ||
528 | * Work queue entry to send | ||
529 | * @do_free: True if the work queue entry and packet data should be | ||
530 | * freed. If false, neither will be freed. | ||
531 | * @qos: Index into the queues for this port to transmit on. This | ||
532 | * is used to implement QoS if their are multiple queues per | ||
533 | * port. This parameter must be between 0 and the number of | ||
534 | * queues per port minus 1. Values outside of this range will | ||
535 | * be change to zero. | ||
536 | * | ||
537 | * Returns Zero on success, negative on failure. | ||
538 | */ | ||
539 | int cvm_oct_transmit_qos(struct net_device *dev, void *work_queue_entry, | ||
540 | int do_free, int qos) | ||
541 | { | ||
542 | unsigned long flags; | ||
543 | union cvmx_buf_ptr hw_buffer; | ||
544 | cvmx_pko_command_word0_t pko_command; | ||
545 | int dropped; | ||
546 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
547 | cvmx_wqe_t *work = work_queue_entry; | ||
548 | |||
549 | if (!(dev->flags & IFF_UP)) { | ||
550 | DEBUGPRINT("%s: Device not up\n", dev->name); | ||
551 | if (do_free) | ||
552 | cvm_oct_free_work(work); | ||
553 | return -1; | ||
554 | } | ||
555 | |||
556 | /* The check on CVMX_PKO_QUEUES_PER_PORT_* is designed to completely | ||
557 | remove "qos" in the event neither interface supports | ||
558 | multiple queues per port */ | ||
559 | if ((CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 > 1) || | ||
560 | (CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 > 1)) { | ||
561 | if (qos <= 0) | ||
562 | qos = 0; | ||
563 | else if (qos >= cvmx_pko_get_num_queues(priv->port)) | ||
564 | qos = 0; | ||
565 | } else | ||
566 | qos = 0; | ||
567 | |||
568 | /* Start off assuming no drop */ | ||
569 | dropped = 0; | ||
570 | |||
571 | local_irq_save(flags); | ||
572 | cvmx_pko_send_packet_prepare(priv->port, priv->queue + qos, | ||
573 | CVMX_PKO_LOCK_CMD_QUEUE); | ||
574 | |||
575 | /* Build the PKO buffer pointer */ | ||
576 | hw_buffer.u64 = 0; | ||
577 | hw_buffer.s.addr = work->packet_ptr.s.addr; | ||
578 | hw_buffer.s.pool = CVMX_FPA_PACKET_POOL; | ||
579 | hw_buffer.s.size = CVMX_FPA_PACKET_POOL_SIZE; | ||
580 | hw_buffer.s.back = work->packet_ptr.s.back; | ||
581 | |||
582 | /* Build the PKO command */ | ||
583 | pko_command.u64 = 0; | ||
584 | pko_command.s.n2 = 1; /* Don't pollute L2 with the outgoing packet */ | ||
585 | pko_command.s.dontfree = !do_free; | ||
586 | pko_command.s.segs = work->word2.s.bufs; | ||
587 | pko_command.s.total_bytes = work->len; | ||
588 | |||
589 | /* Check if we can use the hardware checksumming */ | ||
590 | if (unlikely(work->word2.s.not_IP || work->word2.s.IP_exc)) | ||
591 | pko_command.s.ipoffp1 = 0; | ||
592 | else | ||
593 | pko_command.s.ipoffp1 = sizeof(struct ethhdr) + 1; | ||
594 | |||
595 | /* Send the packet to the output queue */ | ||
596 | if (unlikely | ||
597 | (cvmx_pko_send_packet_finish | ||
598 | (priv->port, priv->queue + qos, pko_command, hw_buffer, | ||
599 | CVMX_PKO_LOCK_CMD_QUEUE))) { | ||
600 | DEBUGPRINT("%s: Failed to send the packet\n", dev->name); | ||
601 | dropped = -1; | ||
602 | } | ||
603 | local_irq_restore(flags); | ||
604 | |||
605 | if (unlikely(dropped)) { | ||
606 | if (do_free) | ||
607 | cvm_oct_free_work(work); | ||
608 | priv->stats.tx_dropped++; | ||
609 | } else if (do_free) | ||
610 | cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, DONT_WRITEBACK(1)); | ||
611 | |||
612 | return dropped; | ||
613 | } | ||
614 | EXPORT_SYMBOL(cvm_oct_transmit_qos); | ||
615 | |||
616 | /** | ||
617 | * This function frees all skb that are currenty queued for TX. | ||
618 | * | ||
619 | * @dev: Device being shutdown | ||
620 | */ | ||
621 | void cvm_oct_tx_shutdown(struct net_device *dev) | ||
622 | { | ||
623 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
624 | unsigned long flags; | ||
625 | int qos; | ||
626 | |||
627 | for (qos = 0; qos < 16; qos++) { | ||
628 | spin_lock_irqsave(&priv->tx_free_list[qos].lock, flags); | ||
629 | while (skb_queue_len(&priv->tx_free_list[qos])) | ||
630 | dev_kfree_skb_any(__skb_dequeue | ||
631 | (&priv->tx_free_list[qos])); | ||
632 | spin_unlock_irqrestore(&priv->tx_free_list[qos].lock, flags); | ||
633 | } | ||
634 | } | ||
diff --git a/drivers/staging/octeon/ethernet-tx.h b/drivers/staging/octeon/ethernet-tx.h new file mode 100644 index 000000000000..5106236fe981 --- /dev/null +++ b/drivers/staging/octeon/ethernet-tx.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /********************************************************************* | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | *********************************************************************/ | ||
27 | |||
28 | int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev); | ||
29 | int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev); | ||
30 | int cvm_oct_transmit_qos(struct net_device *dev, void *work_queue_entry, | ||
31 | int do_free, int qos); | ||
32 | void cvm_oct_tx_shutdown(struct net_device *dev); | ||
diff --git a/drivers/staging/octeon/ethernet-util.h b/drivers/staging/octeon/ethernet-util.h new file mode 100644 index 000000000000..37b665918000 --- /dev/null +++ b/drivers/staging/octeon/ethernet-util.h | |||
@@ -0,0 +1,81 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | *********************************************************************/ | ||
27 | |||
28 | #define DEBUGPRINT(format, ...) do { if (printk_ratelimit()) \ | ||
29 | printk(format, ##__VA_ARGS__); \ | ||
30 | } while (0) | ||
31 | |||
32 | /** | ||
33 | * Given a packet data address, return a pointer to the | ||
34 | * beginning of the packet buffer. | ||
35 | * | ||
36 | * @packet_ptr: Packet data hardware address | ||
37 | * Returns Packet buffer pointer | ||
38 | */ | ||
39 | static inline void *cvm_oct_get_buffer_ptr(union cvmx_buf_ptr packet_ptr) | ||
40 | { | ||
41 | return cvmx_phys_to_ptr(((packet_ptr.s.addr >> 7) - packet_ptr.s.back) | ||
42 | << 7); | ||
43 | } | ||
44 | |||
45 | /** | ||
46 | * Given an IPD/PKO port number, return the logical interface it is | ||
47 | * on. | ||
48 | * | ||
49 | * @ipd_port: Port to check | ||
50 | * | ||
51 | * Returns Logical interface | ||
52 | */ | ||
53 | static inline int INTERFACE(int ipd_port) | ||
54 | { | ||
55 | if (ipd_port < 32) /* Interface 0 or 1 for RGMII,GMII,SPI, etc */ | ||
56 | return ipd_port >> 4; | ||
57 | else if (ipd_port < 36) /* Interface 2 for NPI */ | ||
58 | return 2; | ||
59 | else if (ipd_port < 40) /* Interface 3 for loopback */ | ||
60 | return 3; | ||
61 | else if (ipd_port == 40) /* Non existant interface for POW0 */ | ||
62 | return 4; | ||
63 | else | ||
64 | panic("Illegal ipd_port %d passed to INTERFACE\n", ipd_port); | ||
65 | } | ||
66 | |||
67 | /** | ||
68 | * Given an IPD/PKO port number, return the port's index on a | ||
69 | * logical interface. | ||
70 | * | ||
71 | * @ipd_port: Port to check | ||
72 | * | ||
73 | * Returns Index into interface port list | ||
74 | */ | ||
75 | static inline int INDEX(int ipd_port) | ||
76 | { | ||
77 | if (ipd_port < 32) | ||
78 | return ipd_port & 15; | ||
79 | else | ||
80 | return ipd_port & 3; | ||
81 | } | ||
diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c new file mode 100644 index 000000000000..f08eb32e04fc --- /dev/null +++ b/drivers/staging/octeon/ethernet-xaui.c | |||
@@ -0,0 +1,127 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/netdevice.h> | ||
29 | #include <linux/mii.h> | ||
30 | #include <net/dst.h> | ||
31 | |||
32 | #include <asm/octeon/octeon.h> | ||
33 | |||
34 | #include "ethernet-defines.h" | ||
35 | #include "octeon-ethernet.h" | ||
36 | #include "ethernet-common.h" | ||
37 | #include "ethernet-util.h" | ||
38 | |||
39 | #include "cvmx-helper.h" | ||
40 | |||
41 | #include "cvmx-gmxx-defs.h" | ||
42 | |||
43 | static int cvm_oct_xaui_open(struct net_device *dev) | ||
44 | { | ||
45 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
46 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
47 | int interface = INTERFACE(priv->port); | ||
48 | int index = INDEX(priv->port); | ||
49 | cvmx_helper_link_info_t link_info; | ||
50 | |||
51 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
52 | gmx_cfg.s.en = 1; | ||
53 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
54 | |||
55 | if (!octeon_is_simulation()) { | ||
56 | link_info = cvmx_helper_link_get(priv->port); | ||
57 | if (!link_info.s.link_up) | ||
58 | netif_carrier_off(dev); | ||
59 | } | ||
60 | return 0; | ||
61 | } | ||
62 | |||
63 | static int cvm_oct_xaui_stop(struct net_device *dev) | ||
64 | { | ||
65 | union cvmx_gmxx_prtx_cfg gmx_cfg; | ||
66 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
67 | int interface = INTERFACE(priv->port); | ||
68 | int index = INDEX(priv->port); | ||
69 | |||
70 | gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); | ||
71 | gmx_cfg.s.en = 0; | ||
72 | cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); | ||
73 | return 0; | ||
74 | } | ||
75 | |||
76 | static void cvm_oct_xaui_poll(struct net_device *dev) | ||
77 | { | ||
78 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
79 | cvmx_helper_link_info_t link_info; | ||
80 | |||
81 | link_info = cvmx_helper_link_get(priv->port); | ||
82 | if (link_info.u64 == priv->link_info) | ||
83 | return; | ||
84 | |||
85 | link_info = cvmx_helper_link_autoconf(priv->port); | ||
86 | priv->link_info = link_info.u64; | ||
87 | |||
88 | /* Tell Linux */ | ||
89 | if (link_info.s.link_up) { | ||
90 | |||
91 | if (!netif_carrier_ok(dev)) | ||
92 | netif_carrier_on(dev); | ||
93 | if (priv->queue != -1) | ||
94 | DEBUGPRINT | ||
95 | ("%s: %u Mbps %s duplex, port %2d, queue %2d\n", | ||
96 | dev->name, link_info.s.speed, | ||
97 | (link_info.s.full_duplex) ? "Full" : "Half", | ||
98 | priv->port, priv->queue); | ||
99 | else | ||
100 | DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, POW\n", | ||
101 | dev->name, link_info.s.speed, | ||
102 | (link_info.s.full_duplex) ? "Full" : "Half", | ||
103 | priv->port); | ||
104 | } else { | ||
105 | if (netif_carrier_ok(dev)) | ||
106 | netif_carrier_off(dev); | ||
107 | DEBUGPRINT("%s: Link down\n", dev->name); | ||
108 | } | ||
109 | } | ||
110 | |||
111 | int cvm_oct_xaui_init(struct net_device *dev) | ||
112 | { | ||
113 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
114 | cvm_oct_common_init(dev); | ||
115 | dev->open = cvm_oct_xaui_open; | ||
116 | dev->stop = cvm_oct_xaui_stop; | ||
117 | dev->stop(dev); | ||
118 | if (!octeon_is_simulation()) | ||
119 | priv->poll = cvm_oct_xaui_poll; | ||
120 | |||
121 | return 0; | ||
122 | } | ||
123 | |||
124 | void cvm_oct_xaui_uninit(struct net_device *dev) | ||
125 | { | ||
126 | cvm_oct_common_uninit(dev); | ||
127 | } | ||
diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c new file mode 100644 index 000000000000..e8ef9e0b791f --- /dev/null +++ b/drivers/staging/octeon/ethernet.c | |||
@@ -0,0 +1,507 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/init.h> | ||
29 | #include <linux/module.h> | ||
30 | #include <linux/netdevice.h> | ||
31 | #include <linux/etherdevice.h> | ||
32 | #include <linux/delay.h> | ||
33 | #include <linux/mii.h> | ||
34 | |||
35 | #include <net/dst.h> | ||
36 | |||
37 | #include <asm/octeon/octeon.h> | ||
38 | |||
39 | #include "ethernet-defines.h" | ||
40 | #include "ethernet-mem.h" | ||
41 | #include "ethernet-rx.h" | ||
42 | #include "ethernet-tx.h" | ||
43 | #include "ethernet-util.h" | ||
44 | #include "ethernet-proc.h" | ||
45 | #include "ethernet-common.h" | ||
46 | #include "octeon-ethernet.h" | ||
47 | |||
48 | #include "cvmx-pip.h" | ||
49 | #include "cvmx-pko.h" | ||
50 | #include "cvmx-fau.h" | ||
51 | #include "cvmx-ipd.h" | ||
52 | #include "cvmx-helper.h" | ||
53 | |||
54 | #include "cvmx-smix-defs.h" | ||
55 | |||
56 | #if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) \ | ||
57 | && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS | ||
58 | int num_packet_buffers = CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS; | ||
59 | #else | ||
60 | int num_packet_buffers = 1024; | ||
61 | #endif | ||
62 | module_param(num_packet_buffers, int, 0444); | ||
63 | MODULE_PARM_DESC(num_packet_buffers, "\n" | ||
64 | "\tNumber of packet buffers to allocate and store in the\n" | ||
65 | "\tFPA. By default, 1024 packet buffers are used unless\n" | ||
66 | "\tCONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS is defined."); | ||
67 | |||
68 | int pow_receive_group = 15; | ||
69 | module_param(pow_receive_group, int, 0444); | ||
70 | MODULE_PARM_DESC(pow_receive_group, "\n" | ||
71 | "\tPOW group to receive packets from. All ethernet hardware\n" | ||
72 | "\twill be configured to send incomming packets to this POW\n" | ||
73 | "\tgroup. Also any other software can submit packets to this\n" | ||
74 | "\tgroup for the kernel to process."); | ||
75 | |||
76 | int pow_send_group = -1; | ||
77 | module_param(pow_send_group, int, 0644); | ||
78 | MODULE_PARM_DESC(pow_send_group, "\n" | ||
79 | "\tPOW group to send packets to other software on. This\n" | ||
80 | "\tcontrols the creation of the virtual device pow0.\n" | ||
81 | "\talways_use_pow also depends on this value."); | ||
82 | |||
83 | int always_use_pow; | ||
84 | module_param(always_use_pow, int, 0444); | ||
85 | MODULE_PARM_DESC(always_use_pow, "\n" | ||
86 | "\tWhen set, always send to the pow group. This will cause\n" | ||
87 | "\tpackets sent to real ethernet devices to be sent to the\n" | ||
88 | "\tPOW group instead of the hardware. Unless some other\n" | ||
89 | "\tapplication changes the config, packets will still be\n" | ||
90 | "\treceived from the low level hardware. Use this option\n" | ||
91 | "\tto allow a CVMX app to intercept all packets from the\n" | ||
92 | "\tlinux kernel. You must specify pow_send_group along with\n" | ||
93 | "\tthis option."); | ||
94 | |||
95 | char pow_send_list[128] = ""; | ||
96 | module_param_string(pow_send_list, pow_send_list, sizeof(pow_send_list), 0444); | ||
97 | MODULE_PARM_DESC(pow_send_list, "\n" | ||
98 | "\tComma separated list of ethernet devices that should use the\n" | ||
99 | "\tPOW for transmit instead of the actual ethernet hardware. This\n" | ||
100 | "\tis a per port version of always_use_pow. always_use_pow takes\n" | ||
101 | "\tprecedence over this list. For example, setting this to\n" | ||
102 | "\t\"eth2,spi3,spi7\" would cause these three devices to transmit\n" | ||
103 | "\tusing the pow_send_group."); | ||
104 | |||
105 | static int disable_core_queueing = 1; | ||
106 | module_param(disable_core_queueing, int, 0444); | ||
107 | MODULE_PARM_DESC(disable_core_queueing, "\n" | ||
108 | "\tWhen set the networking core's tx_queue_len is set to zero. This\n" | ||
109 | "\tallows packets to be sent without lock contention in the packet\n" | ||
110 | "\tscheduler resulting in some cases in improved throughput.\n"); | ||
111 | |||
112 | /** | ||
113 | * Periodic timer to check auto negotiation | ||
114 | */ | ||
115 | static struct timer_list cvm_oct_poll_timer; | ||
116 | |||
117 | /** | ||
118 | * Array of every ethernet device owned by this driver indexed by | ||
119 | * the ipd input port number. | ||
120 | */ | ||
121 | struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS]; | ||
122 | |||
123 | extern struct semaphore mdio_sem; | ||
124 | |||
125 | /** | ||
126 | * Periodic timer tick for slow management operations | ||
127 | * | ||
128 | * @arg: Device to check | ||
129 | */ | ||
130 | static void cvm_do_timer(unsigned long arg) | ||
131 | { | ||
132 | static int port; | ||
133 | if (port < CVMX_PIP_NUM_INPUT_PORTS) { | ||
134 | if (cvm_oct_device[port]) { | ||
135 | int queues_per_port; | ||
136 | int qos; | ||
137 | struct octeon_ethernet *priv = | ||
138 | netdev_priv(cvm_oct_device[port]); | ||
139 | if (priv->poll) { | ||
140 | /* skip polling if we don't get the lock */ | ||
141 | if (!down_trylock(&mdio_sem)) { | ||
142 | priv->poll(cvm_oct_device[port]); | ||
143 | up(&mdio_sem); | ||
144 | } | ||
145 | } | ||
146 | |||
147 | queues_per_port = cvmx_pko_get_num_queues(port); | ||
148 | /* Drain any pending packets in the free list */ | ||
149 | for (qos = 0; qos < queues_per_port; qos++) { | ||
150 | if (skb_queue_len(&priv->tx_free_list[qos])) { | ||
151 | spin_lock(&priv->tx_free_list[qos]. | ||
152 | lock); | ||
153 | while (skb_queue_len | ||
154 | (&priv->tx_free_list[qos]) > | ||
155 | cvmx_fau_fetch_and_add32(priv-> | ||
156 | fau + | ||
157 | qos * 4, | ||
158 | 0)) | ||
159 | dev_kfree_skb(__skb_dequeue | ||
160 | (&priv-> | ||
161 | tx_free_list | ||
162 | [qos])); | ||
163 | spin_unlock(&priv->tx_free_list[qos]. | ||
164 | lock); | ||
165 | } | ||
166 | } | ||
167 | cvm_oct_device[port]->get_stats(cvm_oct_device[port]); | ||
168 | } | ||
169 | port++; | ||
170 | /* Poll the next port in a 50th of a second. | ||
171 | This spreads the polling of ports out a little bit */ | ||
172 | mod_timer(&cvm_oct_poll_timer, jiffies + HZ / 50); | ||
173 | } else { | ||
174 | port = 0; | ||
175 | /* All ports have been polled. Start the next iteration through | ||
176 | the ports in one second */ | ||
177 | mod_timer(&cvm_oct_poll_timer, jiffies + HZ); | ||
178 | } | ||
179 | } | ||
180 | |||
181 | /** | ||
182 | * Configure common hardware for all interfaces | ||
183 | */ | ||
184 | static __init void cvm_oct_configure_common_hw(void) | ||
185 | { | ||
186 | int r; | ||
187 | /* Setup the FPA */ | ||
188 | cvmx_fpa_enable(); | ||
189 | cvm_oct_mem_fill_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE, | ||
190 | num_packet_buffers); | ||
191 | cvm_oct_mem_fill_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE, | ||
192 | num_packet_buffers); | ||
193 | if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL) | ||
194 | cvm_oct_mem_fill_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL, | ||
195 | CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128); | ||
196 | |||
197 | if (USE_RED) | ||
198 | cvmx_helper_setup_red(num_packet_buffers / 4, | ||
199 | num_packet_buffers / 8); | ||
200 | |||
201 | /* Enable the MII interface */ | ||
202 | if (!octeon_is_simulation()) | ||
203 | cvmx_write_csr(CVMX_SMIX_EN(0), 1); | ||
204 | |||
205 | /* Register an IRQ hander for to receive POW interrupts */ | ||
206 | r = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, | ||
207 | cvm_oct_do_interrupt, IRQF_SHARED, "Ethernet", | ||
208 | cvm_oct_device); | ||
209 | |||
210 | #if defined(CONFIG_SMP) && 0 | ||
211 | if (USE_MULTICORE_RECEIVE) { | ||
212 | irq_set_affinity(OCTEON_IRQ_WORKQ0 + pow_receive_group, | ||
213 | cpu_online_mask); | ||
214 | } | ||
215 | #endif | ||
216 | } | ||
217 | |||
218 | /** | ||
219 | * Free a work queue entry received in a intercept callback. | ||
220 | * | ||
221 | * @work_queue_entry: | ||
222 | * Work queue entry to free | ||
223 | * Returns Zero on success, Negative on failure. | ||
224 | */ | ||
225 | int cvm_oct_free_work(void *work_queue_entry) | ||
226 | { | ||
227 | cvmx_wqe_t *work = work_queue_entry; | ||
228 | |||
229 | int segments = work->word2.s.bufs; | ||
230 | union cvmx_buf_ptr segment_ptr = work->packet_ptr; | ||
231 | |||
232 | while (segments--) { | ||
233 | union cvmx_buf_ptr next_ptr = *(union cvmx_buf_ptr *) | ||
234 | cvmx_phys_to_ptr(segment_ptr.s.addr - 8); | ||
235 | if (unlikely(!segment_ptr.s.i)) | ||
236 | cvmx_fpa_free(cvm_oct_get_buffer_ptr(segment_ptr), | ||
237 | segment_ptr.s.pool, | ||
238 | DONT_WRITEBACK(CVMX_FPA_PACKET_POOL_SIZE / | ||
239 | 128)); | ||
240 | segment_ptr = next_ptr; | ||
241 | } | ||
242 | cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, DONT_WRITEBACK(1)); | ||
243 | |||
244 | return 0; | ||
245 | } | ||
246 | EXPORT_SYMBOL(cvm_oct_free_work); | ||
247 | |||
248 | /** | ||
249 | * Module/ driver initialization. Creates the linux network | ||
250 | * devices. | ||
251 | * | ||
252 | * Returns Zero on success | ||
253 | */ | ||
254 | static int __init cvm_oct_init_module(void) | ||
255 | { | ||
256 | int num_interfaces; | ||
257 | int interface; | ||
258 | int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; | ||
259 | int qos; | ||
260 | |||
261 | pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); | ||
262 | |||
263 | cvm_oct_proc_initialize(); | ||
264 | cvm_oct_rx_initialize(); | ||
265 | cvm_oct_configure_common_hw(); | ||
266 | |||
267 | cvmx_helper_initialize_packet_io_global(); | ||
268 | |||
269 | /* Change the input group for all ports before input is enabled */ | ||
270 | num_interfaces = cvmx_helper_get_number_of_interfaces(); | ||
271 | for (interface = 0; interface < num_interfaces; interface++) { | ||
272 | int num_ports = cvmx_helper_ports_on_interface(interface); | ||
273 | int port; | ||
274 | |||
275 | for (port = cvmx_helper_get_ipd_port(interface, 0); | ||
276 | port < cvmx_helper_get_ipd_port(interface, num_ports); | ||
277 | port++) { | ||
278 | union cvmx_pip_prt_tagx pip_prt_tagx; | ||
279 | pip_prt_tagx.u64 = | ||
280 | cvmx_read_csr(CVMX_PIP_PRT_TAGX(port)); | ||
281 | pip_prt_tagx.s.grp = pow_receive_group; | ||
282 | cvmx_write_csr(CVMX_PIP_PRT_TAGX(port), | ||
283 | pip_prt_tagx.u64); | ||
284 | } | ||
285 | } | ||
286 | |||
287 | cvmx_helper_ipd_and_packet_input_enable(); | ||
288 | |||
289 | memset(cvm_oct_device, 0, sizeof(cvm_oct_device)); | ||
290 | |||
291 | /* | ||
292 | * Initialize the FAU used for counting packet buffers that | ||
293 | * need to be freed. | ||
294 | */ | ||
295 | cvmx_fau_atomic_write32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0); | ||
296 | |||
297 | if ((pow_send_group != -1)) { | ||
298 | struct net_device *dev; | ||
299 | pr_info("\tConfiguring device for POW only access\n"); | ||
300 | dev = alloc_etherdev(sizeof(struct octeon_ethernet)); | ||
301 | if (dev) { | ||
302 | /* Initialize the device private structure. */ | ||
303 | struct octeon_ethernet *priv = netdev_priv(dev); | ||
304 | memset(priv, 0, sizeof(struct octeon_ethernet)); | ||
305 | |||
306 | dev->init = cvm_oct_common_init; | ||
307 | priv->imode = CVMX_HELPER_INTERFACE_MODE_DISABLED; | ||
308 | priv->port = CVMX_PIP_NUM_INPUT_PORTS; | ||
309 | priv->queue = -1; | ||
310 | strcpy(dev->name, "pow%d"); | ||
311 | for (qos = 0; qos < 16; qos++) | ||
312 | skb_queue_head_init(&priv->tx_free_list[qos]); | ||
313 | |||
314 | if (register_netdev(dev) < 0) { | ||
315 | pr_err("Failed to register ethernet " | ||
316 | "device for POW\n"); | ||
317 | kfree(dev); | ||
318 | } else { | ||
319 | cvm_oct_device[CVMX_PIP_NUM_INPUT_PORTS] = dev; | ||
320 | pr_info("%s: POW send group %d, receive " | ||
321 | "group %d\n", | ||
322 | dev->name, pow_send_group, | ||
323 | pow_receive_group); | ||
324 | } | ||
325 | } else { | ||
326 | pr_err("Failed to allocate ethernet device " | ||
327 | "for POW\n"); | ||
328 | } | ||
329 | } | ||
330 | |||
331 | num_interfaces = cvmx_helper_get_number_of_interfaces(); | ||
332 | for (interface = 0; interface < num_interfaces; interface++) { | ||
333 | cvmx_helper_interface_mode_t imode = | ||
334 | cvmx_helper_interface_get_mode(interface); | ||
335 | int num_ports = cvmx_helper_ports_on_interface(interface); | ||
336 | int port; | ||
337 | |||
338 | for (port = cvmx_helper_get_ipd_port(interface, 0); | ||
339 | port < cvmx_helper_get_ipd_port(interface, num_ports); | ||
340 | port++) { | ||
341 | struct octeon_ethernet *priv; | ||
342 | struct net_device *dev = | ||
343 | alloc_etherdev(sizeof(struct octeon_ethernet)); | ||
344 | if (!dev) { | ||
345 | pr_err("Failed to allocate ethernet device " | ||
346 | "for port %d\n", port); | ||
347 | continue; | ||
348 | } | ||
349 | if (disable_core_queueing) | ||
350 | dev->tx_queue_len = 0; | ||
351 | |||
352 | /* Initialize the device private structure. */ | ||
353 | priv = netdev_priv(dev); | ||
354 | memset(priv, 0, sizeof(struct octeon_ethernet)); | ||
355 | |||
356 | priv->imode = imode; | ||
357 | priv->port = port; | ||
358 | priv->queue = cvmx_pko_get_base_queue(priv->port); | ||
359 | priv->fau = fau - cvmx_pko_get_num_queues(port) * 4; | ||
360 | for (qos = 0; qos < 16; qos++) | ||
361 | skb_queue_head_init(&priv->tx_free_list[qos]); | ||
362 | for (qos = 0; qos < cvmx_pko_get_num_queues(port); | ||
363 | qos++) | ||
364 | cvmx_fau_atomic_write32(priv->fau + qos * 4, 0); | ||
365 | |||
366 | switch (priv->imode) { | ||
367 | |||
368 | /* These types don't support ports to IPD/PKO */ | ||
369 | case CVMX_HELPER_INTERFACE_MODE_DISABLED: | ||
370 | case CVMX_HELPER_INTERFACE_MODE_PCIE: | ||
371 | case CVMX_HELPER_INTERFACE_MODE_PICMG: | ||
372 | break; | ||
373 | |||
374 | case CVMX_HELPER_INTERFACE_MODE_NPI: | ||
375 | dev->init = cvm_oct_common_init; | ||
376 | dev->uninit = cvm_oct_common_uninit; | ||
377 | strcpy(dev->name, "npi%d"); | ||
378 | break; | ||
379 | |||
380 | case CVMX_HELPER_INTERFACE_MODE_XAUI: | ||
381 | dev->init = cvm_oct_xaui_init; | ||
382 | dev->uninit = cvm_oct_xaui_uninit; | ||
383 | strcpy(dev->name, "xaui%d"); | ||
384 | break; | ||
385 | |||
386 | case CVMX_HELPER_INTERFACE_MODE_LOOP: | ||
387 | dev->init = cvm_oct_common_init; | ||
388 | dev->uninit = cvm_oct_common_uninit; | ||
389 | strcpy(dev->name, "loop%d"); | ||
390 | break; | ||
391 | |||
392 | case CVMX_HELPER_INTERFACE_MODE_SGMII: | ||
393 | dev->init = cvm_oct_sgmii_init; | ||
394 | dev->uninit = cvm_oct_sgmii_uninit; | ||
395 | strcpy(dev->name, "eth%d"); | ||
396 | break; | ||
397 | |||
398 | case CVMX_HELPER_INTERFACE_MODE_SPI: | ||
399 | dev->init = cvm_oct_spi_init; | ||
400 | dev->uninit = cvm_oct_spi_uninit; | ||
401 | strcpy(dev->name, "spi%d"); | ||
402 | break; | ||
403 | |||
404 | case CVMX_HELPER_INTERFACE_MODE_RGMII: | ||
405 | case CVMX_HELPER_INTERFACE_MODE_GMII: | ||
406 | dev->init = cvm_oct_rgmii_init; | ||
407 | dev->uninit = cvm_oct_rgmii_uninit; | ||
408 | strcpy(dev->name, "eth%d"); | ||
409 | break; | ||
410 | } | ||
411 | |||
412 | if (!dev->init) { | ||
413 | kfree(dev); | ||
414 | } else if (register_netdev(dev) < 0) { | ||
415 | pr_err("Failed to register ethernet device " | ||
416 | "for interface %d, port %d\n", | ||
417 | interface, priv->port); | ||
418 | kfree(dev); | ||
419 | } else { | ||
420 | cvm_oct_device[priv->port] = dev; | ||
421 | fau -= | ||
422 | cvmx_pko_get_num_queues(priv->port) * | ||
423 | sizeof(uint32_t); | ||
424 | } | ||
425 | } | ||
426 | } | ||
427 | |||
428 | if (INTERRUPT_LIMIT) { | ||
429 | /* | ||
430 | * Set the POW timer rate to give an interrupt at most | ||
431 | * INTERRUPT_LIMIT times per second. | ||
432 | */ | ||
433 | cvmx_write_csr(CVMX_POW_WQ_INT_PC, | ||
434 | octeon_bootinfo->eclock_hz / (INTERRUPT_LIMIT * | ||
435 | 16 * 256) << 8); | ||
436 | |||
437 | /* | ||
438 | * Enable POW timer interrupt. It will count when | ||
439 | * there are packets available. | ||
440 | */ | ||
441 | cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), | ||
442 | 0x1ful << 24); | ||
443 | } else { | ||
444 | /* Enable POW interrupt when our port has at least one packet */ | ||
445 | cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0x1001); | ||
446 | } | ||
447 | |||
448 | /* Enable the poll timer for checking RGMII status */ | ||
449 | init_timer(&cvm_oct_poll_timer); | ||
450 | cvm_oct_poll_timer.data = 0; | ||
451 | cvm_oct_poll_timer.function = cvm_do_timer; | ||
452 | mod_timer(&cvm_oct_poll_timer, jiffies + HZ); | ||
453 | |||
454 | return 0; | ||
455 | } | ||
456 | |||
457 | /** | ||
458 | * Module / driver shutdown | ||
459 | * | ||
460 | * Returns Zero on success | ||
461 | */ | ||
462 | static void __exit cvm_oct_cleanup_module(void) | ||
463 | { | ||
464 | int port; | ||
465 | |||
466 | /* Disable POW interrupt */ | ||
467 | cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0); | ||
468 | |||
469 | cvmx_ipd_disable(); | ||
470 | |||
471 | /* Free the interrupt handler */ | ||
472 | free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device); | ||
473 | |||
474 | del_timer(&cvm_oct_poll_timer); | ||
475 | cvm_oct_rx_shutdown(); | ||
476 | cvmx_pko_disable(); | ||
477 | |||
478 | /* Free the ethernet devices */ | ||
479 | for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) { | ||
480 | if (cvm_oct_device[port]) { | ||
481 | cvm_oct_tx_shutdown(cvm_oct_device[port]); | ||
482 | unregister_netdev(cvm_oct_device[port]); | ||
483 | kfree(cvm_oct_device[port]); | ||
484 | cvm_oct_device[port] = NULL; | ||
485 | } | ||
486 | } | ||
487 | |||
488 | cvmx_pko_shutdown(); | ||
489 | cvm_oct_proc_shutdown(); | ||
490 | |||
491 | cvmx_ipd_free_ptr(); | ||
492 | |||
493 | /* Free the HW pools */ | ||
494 | cvm_oct_mem_empty_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE, | ||
495 | num_packet_buffers); | ||
496 | cvm_oct_mem_empty_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE, | ||
497 | num_packet_buffers); | ||
498 | if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL) | ||
499 | cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL, | ||
500 | CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128); | ||
501 | } | ||
502 | |||
503 | MODULE_LICENSE("GPL"); | ||
504 | MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>"); | ||
505 | MODULE_DESCRIPTION("Cavium Networks Octeon ethernet driver."); | ||
506 | module_init(cvm_oct_init_module); | ||
507 | module_exit(cvm_oct_cleanup_module); | ||
diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h new file mode 100644 index 000000000000..b3199076ef5e --- /dev/null +++ b/drivers/staging/octeon/octeon-ethernet.h | |||
@@ -0,0 +1,127 @@ | |||
1 | /********************************************************************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2007 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | **********************************************************************/ | ||
27 | |||
28 | /* | ||
29 | * External interface for the Cavium Octeon ethernet driver. | ||
30 | */ | ||
31 | #ifndef OCTEON_ETHERNET_H | ||
32 | #define OCTEON_ETHERNET_H | ||
33 | |||
34 | /** | ||
35 | * This is the definition of the Ethernet driver's private | ||
36 | * driver state stored in netdev_priv(dev). | ||
37 | */ | ||
38 | struct octeon_ethernet { | ||
39 | /* PKO hardware output port */ | ||
40 | int port; | ||
41 | /* PKO hardware queue for the port */ | ||
42 | int queue; | ||
43 | /* Hardware fetch and add to count outstanding tx buffers */ | ||
44 | int fau; | ||
45 | /* | ||
46 | * Type of port. This is one of the enums in | ||
47 | * cvmx_helper_interface_mode_t | ||
48 | */ | ||
49 | int imode; | ||
50 | /* List of outstanding tx buffers per queue */ | ||
51 | struct sk_buff_head tx_free_list[16]; | ||
52 | /* Device statistics */ | ||
53 | struct net_device_stats stats | ||
54 | ; /* Generic MII info structure */ | ||
55 | struct mii_if_info mii_info; | ||
56 | /* Last negotiated link state */ | ||
57 | uint64_t link_info; | ||
58 | /* Called periodically to check link status */ | ||
59 | void (*poll) (struct net_device *dev); | ||
60 | }; | ||
61 | |||
62 | /** | ||
63 | * Free a work queue entry received in a intercept callback. | ||
64 | * | ||
65 | * @work_queue_entry: | ||
66 | * Work queue entry to free | ||
67 | * Returns Zero on success, Negative on failure. | ||
68 | */ | ||
69 | int cvm_oct_free_work(void *work_queue_entry); | ||
70 | |||
71 | /** | ||
72 | * Transmit a work queue entry out of the ethernet port. Both | ||
73 | * the work queue entry and the packet data can optionally be | ||
74 | * freed. The work will be freed on error as well. | ||
75 | * | ||
76 | * @dev: Device to transmit out. | ||
77 | * @work_queue_entry: | ||
78 | * Work queue entry to send | ||
79 | * @do_free: True if the work queue entry and packet data should be | ||
80 | * freed. If false, neither will be freed. | ||
81 | * @qos: Index into the queues for this port to transmit on. This | ||
82 | * is used to implement QoS if their are multiple queues per | ||
83 | * port. This parameter must be between 0 and the number of | ||
84 | * queues per port minus 1. Values outside of this range will | ||
85 | * be change to zero. | ||
86 | * | ||
87 | * Returns Zero on success, negative on failure. | ||
88 | */ | ||
89 | int cvm_oct_transmit_qos(struct net_device *dev, void *work_queue_entry, | ||
90 | int do_free, int qos); | ||
91 | |||
92 | /** | ||
93 | * Transmit a work queue entry out of the ethernet port. Both | ||
94 | * the work queue entry and the packet data can optionally be | ||
95 | * freed. The work will be freed on error as well. This simply | ||
96 | * wraps cvmx_oct_transmit_qos() for backwards compatability. | ||
97 | * | ||
98 | * @dev: Device to transmit out. | ||
99 | * @work_queue_entry: | ||
100 | * Work queue entry to send | ||
101 | * @do_free: True if the work queue entry and packet data should be | ||
102 | * freed. If false, neither will be freed. | ||
103 | * | ||
104 | * Returns Zero on success, negative on failure. | ||
105 | */ | ||
106 | static inline int cvm_oct_transmit(struct net_device *dev, | ||
107 | void *work_queue_entry, int do_free) | ||
108 | { | ||
109 | return cvm_oct_transmit_qos(dev, work_queue_entry, do_free, 0); | ||
110 | } | ||
111 | |||
112 | extern int cvm_oct_rgmii_init(struct net_device *dev); | ||
113 | extern void cvm_oct_rgmii_uninit(struct net_device *dev); | ||
114 | extern int cvm_oct_sgmii_init(struct net_device *dev); | ||
115 | extern void cvm_oct_sgmii_uninit(struct net_device *dev); | ||
116 | extern int cvm_oct_spi_init(struct net_device *dev); | ||
117 | extern void cvm_oct_spi_uninit(struct net_device *dev); | ||
118 | extern int cvm_oct_xaui_init(struct net_device *dev); | ||
119 | extern void cvm_oct_xaui_uninit(struct net_device *dev); | ||
120 | |||
121 | extern int always_use_pow; | ||
122 | extern int pow_send_group; | ||
123 | extern int pow_receive_group; | ||
124 | extern char pow_send_list[]; | ||
125 | extern struct net_device *cvm_oct_device[]; | ||
126 | |||
127 | #endif | ||