diff options
| author | Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> | 2010-06-17 07:37:13 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-08-05 08:26:04 -0400 |
| commit | 1f1f4e7dbc0c0312e9e7fe3cadd07340ea62070f (patch) | |
| tree | eb4beefbb99582df686f3db0bc2fb204d02620a2 | |
| parent | 4040703fffbb6b120253b2fe69f743466af69778 (diff) | |
MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n)
Don't duplicate worthless lines.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1390/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/include/asm/emma/markeins.h | 33 |
1 files changed, 1 insertions, 32 deletions
diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h index 507f125f98fd..bf2d229c2dae 100644 --- a/arch/mips/include/asm/emma/markeins.h +++ b/arch/mips/include/asm/emma/markeins.h | |||
| @@ -31,38 +31,7 @@ | |||
| 31 | #define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) | 31 | #define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) |
| 32 | #define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) | 32 | #define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) |
| 33 | 33 | ||
| 34 | #define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) | 34 | #define EMMA2RH_SW_IRQ_INT(n) (EMMA2RH_SW_IRQ_BASE + (n)) |
| 35 | #define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE) | ||
| 36 | #define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE) | ||
| 37 | #define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE) | ||
| 38 | #define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE) | ||
| 39 | #define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE) | ||
| 40 | #define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE) | ||
| 41 | #define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE) | ||
| 42 | #define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE) | ||
| 43 | #define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE) | ||
| 44 | #define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE) | ||
| 45 | #define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE) | ||
| 46 | #define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE) | ||
| 47 | #define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE) | ||
| 48 | #define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE) | ||
| 49 | #define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE) | ||
| 50 | #define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE) | ||
| 51 | #define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE) | ||
| 52 | #define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE) | ||
| 53 | #define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE) | ||
| 54 | #define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE) | ||
| 55 | #define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE) | ||
| 56 | #define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE) | ||
| 57 | #define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE) | ||
| 58 | #define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE) | ||
| 59 | #define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE) | ||
| 60 | #define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE) | ||
| 61 | #define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE) | ||
| 62 | #define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE) | ||
| 63 | #define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE) | ||
| 64 | #define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE) | ||
| 65 | #define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE) | ||
| 66 | 35 | ||
| 67 | #define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15 | 36 | #define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15 |
| 68 | #define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16 | 37 | #define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16 |