diff options
author | Michael Chan <mchan@broadcom.com> | 2010-06-08 03:21:30 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-06-11 21:37:07 -0400 |
commit | cbd6890c5987cd7115147e1dd2c10d729afabb08 (patch) | |
tree | 074d6e8fcb69fdc2d5a2d07d7a284c76f08b8771 | |
parent | fc0ba8e87189b02683177116932fa580ab97b7ff (diff) |
bnx2: Fix compiler warning in bnx2_disable_forced_2g5().
drivers/net/bnx2.c: In function 'bnx2_disable_forced_2g5':
drivers/net/bnx2.c:1489: warning: 'bmcr' may be used uninitialized in this function
We fix it by checking return values from all bnx2_read_phy() and proceeding
to do read-modify-write only if the read operation is successful.
The related bnx2_enable_forced_2g5() is also fixed the same way.
Reported-by: Prarit Bhargava <prarit@redhat.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/bnx2.c | 43 |
1 files changed, 28 insertions, 15 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 949d7a9dcf92..522de9f818be 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -1446,7 +1446,8 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp) | |||
1446 | static void | 1446 | static void |
1447 | bnx2_enable_forced_2g5(struct bnx2 *bp) | 1447 | bnx2_enable_forced_2g5(struct bnx2 *bp) |
1448 | { | 1448 | { |
1449 | u32 bmcr; | 1449 | u32 uninitialized_var(bmcr); |
1450 | int err; | ||
1450 | 1451 | ||
1451 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) | 1452 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
1452 | return; | 1453 | return; |
@@ -1456,22 +1457,28 @@ bnx2_enable_forced_2g5(struct bnx2 *bp) | |||
1456 | 1457 | ||
1457 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | 1458 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1458 | MII_BNX2_BLK_ADDR_SERDES_DIG); | 1459 | MII_BNX2_BLK_ADDR_SERDES_DIG); |
1459 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val); | 1460 | if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { |
1460 | val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; | 1461 | val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; |
1461 | val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G; | 1462 | val |= MII_BNX2_SD_MISC1_FORCE | |
1462 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | 1463 | MII_BNX2_SD_MISC1_FORCE_2_5G; |
1464 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | ||
1465 | } | ||
1463 | 1466 | ||
1464 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | 1467 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1465 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | 1468 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); |
1466 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | 1469 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1467 | 1470 | ||
1468 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { | 1471 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { |
1469 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | 1472 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1470 | bmcr |= BCM5708S_BMCR_FORCE_2500; | 1473 | if (!err) |
1474 | bmcr |= BCM5708S_BMCR_FORCE_2500; | ||
1471 | } else { | 1475 | } else { |
1472 | return; | 1476 | return; |
1473 | } | 1477 | } |
1474 | 1478 | ||
1479 | if (err) | ||
1480 | return; | ||
1481 | |||
1475 | if (bp->autoneg & AUTONEG_SPEED) { | 1482 | if (bp->autoneg & AUTONEG_SPEED) { |
1476 | bmcr &= ~BMCR_ANENABLE; | 1483 | bmcr &= ~BMCR_ANENABLE; |
1477 | if (bp->req_duplex == DUPLEX_FULL) | 1484 | if (bp->req_duplex == DUPLEX_FULL) |
@@ -1483,7 +1490,8 @@ bnx2_enable_forced_2g5(struct bnx2 *bp) | |||
1483 | static void | 1490 | static void |
1484 | bnx2_disable_forced_2g5(struct bnx2 *bp) | 1491 | bnx2_disable_forced_2g5(struct bnx2 *bp) |
1485 | { | 1492 | { |
1486 | u32 bmcr; | 1493 | u32 uninitialized_var(bmcr); |
1494 | int err; | ||
1487 | 1495 | ||
1488 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) | 1496 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
1489 | return; | 1497 | return; |
@@ -1493,21 +1501,26 @@ bnx2_disable_forced_2g5(struct bnx2 *bp) | |||
1493 | 1501 | ||
1494 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | 1502 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1495 | MII_BNX2_BLK_ADDR_SERDES_DIG); | 1503 | MII_BNX2_BLK_ADDR_SERDES_DIG); |
1496 | bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val); | 1504 | if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { |
1497 | val &= ~MII_BNX2_SD_MISC1_FORCE; | 1505 | val &= ~MII_BNX2_SD_MISC1_FORCE; |
1498 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); | 1506 | bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); |
1507 | } | ||
1499 | 1508 | ||
1500 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | 1509 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1501 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | 1510 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); |
1502 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | 1511 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1503 | 1512 | ||
1504 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { | 1513 | } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { |
1505 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | 1514 | err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1506 | bmcr &= ~BCM5708S_BMCR_FORCE_2500; | 1515 | if (!err) |
1516 | bmcr &= ~BCM5708S_BMCR_FORCE_2500; | ||
1507 | } else { | 1517 | } else { |
1508 | return; | 1518 | return; |
1509 | } | 1519 | } |
1510 | 1520 | ||
1521 | if (err) | ||
1522 | return; | ||
1523 | |||
1511 | if (bp->autoneg & AUTONEG_SPEED) | 1524 | if (bp->autoneg & AUTONEG_SPEED) |
1512 | bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; | 1525 | bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; |
1513 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | 1526 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |