ARM: OMAP: Fix DMA channel irq handling for omap24xx

- DMA CSR register is cleared by reading on omap1, but on
  omap2 it is cleard by writing to it.

- DMA TOUT interrupt does not exist on omap24xx, rename it

- Add SECURE and MISALIGNED errors by default for omap24xx

- Add defines for external DMA request lines

Signed-off-by: Tony Lindgren <tony@atomide.com>

4 files changed, 31 insertions, 21 deletions

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 8e7c33656b52..c5d0214ef191 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -43,6 +43,7 @@
 
 #define OMAP_DMA_ACTIVE         0x01
 #define OMAP_DMA_CCR_EN         (1 << 7)
+#define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
 
 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
 
@@ -409,8 +410,11 @@ static inline void omap_enable_channel_irq(int lch)
 {
         u32 status;
 
-        /* Read CSR to make sure it's cleared. */
-        status = OMAP_DMA_CSR_REG(lch);
+        /* Clear CSR */
+        if (cpu_class_is_omap1())
+                status = OMAP_DMA_CSR_REG(lch);
+        else if (cpu_is_omap24xx())
+                OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
 
         /* Enable some nice interrupts. */
         OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
@@ -509,11 +513,13 @@ int omap_request_dma(int dev_id, const char *dev_name,
         chan->dev_name = dev_name;
         chan->callback = callback;
         chan->data = data;
-        chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ |
-                                OMAP_DMA_BLOCK_IRQ;
+        chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 
-        if (cpu_is_omap24xx())
-                chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ;
+        if (cpu_class_is_omap1())
+                chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
+        else if (cpu_is_omap24xx())
+                chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
+                        OMAP2_DMA_TRANS_ERR_IRQ;
 
         if (cpu_is_omap16xx()) {
                 /* If the sync device is set, configure it dynamically. */
@@ -533,7 +539,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
 
                 omap_enable_channel_irq(free_ch);
                 /* Clear the CSR register and IRQ status register */
-                OMAP_DMA_CSR_REG(free_ch) = 0x0;
+                OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
                 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
         }
 
@@ -573,7 +579,7 @@ void omap_free_dma(int lch)
                 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
 
                 /* Clear the CSR register and IRQ status register */
-                OMAP_DMA_CSR_REG(lch) = 0x0;
+                OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
 
                 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
                 val |= 1 << lch;
@@ -837,7 +843,7 @@ static int omap1_dma_handle_ch(int ch)
                        "%d (CSR %04x)\n", ch, csr);
                 return 0;
         }
-        if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
+        if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
                 printk(KERN_WARNING "DMA timeout with device %d\n",
                        dma_chan[ch].dev_id);
         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
@@ -885,20 +891,21 @@ static int omap2_dma_handle_ch(int ch)
                 return 0;
         if (unlikely(dma_chan[ch].dev_id == -1))
                 return 0;
-        /* REVISIT: According to 24xx TRM, there's no TOUT_IE */
-        if (unlikely(status & OMAP_DMA_TOUT_IRQ))
-                printk(KERN_INFO "DMA timeout with device %d\n",
-                       dma_chan[ch].dev_id);
         if (unlikely(status & OMAP_DMA_DROP_IRQ))
                 printk(KERN_INFO
                        "DMA synchronization event drop occurred with device "
                        "%d\n", dma_chan[ch].dev_id);
-
         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
                 printk(KERN_INFO "DMA transaction error with device %d\n",
                        dma_chan[ch].dev_id);
+        if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
+                printk(KERN_INFO "DMA secure error with device %d\n",
+                       dma_chan[ch].dev_id);
+        if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
+                printk(KERN_INFO "DMA misaligned error with device %d\n",
+                       dma_chan[ch].dev_id);
 
-        OMAP_DMA_CSR_REG(ch) = 0x20;
+        OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
 
         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
         /* ch in this function is from 0-31 while in register it is 1-32 */
diff --git a/drivers/mmc/omap.c b/drivers/mmc/omap.c
index c25244b3657b..4aa1e56235c9 100644
--- a/drivers/mmc/omap.c
+++ b/drivers/mmc/omap.c
@@ -663,7 +663,7 @@ static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
                 return;
         }
         /* FIXME: We really should do something to _handle_ the errors */
-        if (ch_status & OMAP_DMA_TOUT_IRQ) {
+        if (ch_status & OMAP1_DMA_TOUT_IRQ) {
                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
                 return;
         }
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
index fbea51448909..36336486c883 100644
--- a/drivers/usb/gadget/omap_udc.c
+++ b/drivers/usb/gadget/omap_udc.c
@@ -773,7 +773,7 @@ static void dma_error(int lch, u16 ch_status, void *data)
         struct omap_ep  *ep = data;
 
         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
-        /* if ch_status & OMAP_DMA_TOUT_IRQ ... */
+        /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 
         /* complete current transfer ... */
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index e081400b658e..1b1b02307e77 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -185,8 +185,8 @@
 /* DMA channels for 24xx */
 #define OMAP24XX_DMA_NO_DEVICE          0
 #define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
-#define OMAP24XX_DMA_EXT_NDMA_REQ0      2       /* S_DMA_1 */
-#define OMAP24XX_DMA_EXT_NDMA_REQ1      3       /* S_DMA_2 */
+#define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
+#define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
 #define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
 #define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
 #define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
@@ -197,7 +197,9 @@
 #define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
 #define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
 #define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-
+#define OMAP24XX_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
+#define OMAP24XX_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
+#define OMAP24XX_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
 #define OMAP24XX_DMA_EAC_AC_RD          17      /* S_DMA_16 */
 #define OMAP24XX_DMA_EAC_AC_WR          18      /* S_DMA_17 */
 #define OMAP24XX_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
@@ -244,6 +246,7 @@
 #define OMAP24XX_DMA_MMC1_TX            61      /* SDMA_60 */
 #define OMAP24XX_DMA_MMC1_RX            62      /* SDMA_61 */
 #define OMAP24XX_DMA_MS                 63      /* SDMA_62 */
+#define OMAP24XX_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
 
 /*----------------------------------------------------------------------------*/
 
@@ -274,7 +277,7 @@
 #define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
 #define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
 
-#define OMAP_DMA_TOUT_IRQ               (1 << 0)        /* Only on omap1 */
+#define OMAP1_DMA_TOUT_IRQ              (1 << 0)
 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 #define OMAP_DMA_HALF_IRQ               (1 << 2)
 #define OMAP_DMA_FRAME_IRQ              (1 << 3)