diff options
author | Philipp Zabel <philipp.zabel@gmail.com> | 2008-07-09 20:16:27 -0400 |
---|---|---|
committer | Samuel Ortiz <samuel@sortiz.org> | 2008-07-20 13:56:24 -0400 |
commit | 279cac484e55317456900fe3567c7cb5bd46fd5f (patch) | |
tree | 2a2c04fca6970dee9831c60496615cb4f753d9c9 | |
parent | 4a67b528e0be5d855b1a7bb71ec769d954765f6c (diff) |
mfd: remove DS1WM register definitions from asic3.h
There is a dedicated ds1wm driver, no need to duplicate this
information here.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Samuel Ortiz <sameo@openedhand.com>
-rw-r--r-- | include/linux/mfd/asic3.h | 38 |
1 files changed, 3 insertions, 35 deletions
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h index 0eae3083da43..8f8c46c41f44 100644 --- a/include/linux/mfd/asic3.h +++ b/include/linux/mfd/asic3.h | |||
@@ -265,44 +265,12 @@ struct asic3_platform_data { | |||
265 | #define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */ | 265 | #define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */ |
266 | 266 | ||
267 | /********************************************* | 267 | /********************************************* |
268 | * The Onewire interface registers | 268 | * The Onewire interface (DS1WM) is handled |
269 | * | 269 | * by the ds1wm driver. |
270 | * OWM_CMD | ||
271 | * OWM_DAT | ||
272 | * OWM_INTR | ||
273 | * OWM_INTEN | ||
274 | * OWM_CLKDIV | ||
275 | * | 270 | * |
276 | *********************************************/ | 271 | *********************************************/ |
277 | 272 | ||
278 | #define ASIC3_OWM_Base 0xC00 | 273 | #define ASIC3_OWM_BASE 0xC00 |
279 | |||
280 | #define ASIC3_OWM_CMD 0x00 | ||
281 | #define ASIC3_OWM_DAT 0x04 | ||
282 | #define ASIC3_OWM_INTR 0x08 | ||
283 | #define ASIC3_OWM_INTEN 0x0C | ||
284 | #define ASIC3_OWM_CLKDIV 0x10 | ||
285 | |||
286 | #define ASIC3_OWM_CMD_ONEWR (1 << 0) | ||
287 | #define ASIC3_OWM_CMD_SRA (1 << 1) | ||
288 | #define ASIC3_OWM_CMD_DQO (1 << 2) | ||
289 | #define ASIC3_OWM_CMD_DQI (1 << 3) | ||
290 | |||
291 | #define ASIC3_OWM_INTR_PD (1 << 0) | ||
292 | #define ASIC3_OWM_INTR_PDR (1 << 1) | ||
293 | #define ASIC3_OWM_INTR_TBE (1 << 2) | ||
294 | #define ASIC3_OWM_INTR_TEMP (1 << 3) | ||
295 | #define ASIC3_OWM_INTR_RBF (1 << 4) | ||
296 | |||
297 | #define ASIC3_OWM_INTEN_EPD (1 << 0) | ||
298 | #define ASIC3_OWM_INTEN_IAS (1 << 1) | ||
299 | #define ASIC3_OWM_INTEN_ETBE (1 << 2) | ||
300 | #define ASIC3_OWM_INTEN_ETMT (1 << 3) | ||
301 | #define ASIC3_OWM_INTEN_ERBF (1 << 4) | ||
302 | |||
303 | #define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */ | ||
304 | #define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */ | ||
305 | |||
306 | 274 | ||
307 | /***************************************************************************** | 275 | /***************************************************************************** |
308 | * The SD configuration registers are at a completely different location | 276 | * The SD configuration registers are at a completely different location |