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authorRafał Miłecki <zajec5@gmail.com>2011-05-09 12:56:46 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-05-10 15:54:54 -0400
commit8369ae33b705222aa05ab53c7d6b4458f4ed161b (patch)
treece5d592a63134f1283473bc900bf59489b92d8eb
parent306fe9384f06d31219778cece2d3c646146e7bb6 (diff)
bcma: add Broadcom specific AMBA bus driver
Broadcom has released cards based on a new AMBA-based bus type. From a programming point of view, this new bus type differs from AMBA and does not use AMBA common registers. It also differs enough from SSB. We decided that a new bus driver is needed to keep the code clean. In its current form, the driver detects devices present on the bus and registers them in the system. It allows registering BCMA drivers for specified bus devices and provides them basic operations. The bus driver itself includes two important bus managing drivers: ChipCommon core driver and PCI(c) core driver. They are early used to allow correct initialization. Currently code is limited to supporting buses on PCI(e) devices, however the driver is designed to be used also on other hosts. The host abstraction layer is implemented and already used for PCI(e). Support for PCI(e) hosts is working and seems to be stable (access to 80211 core was tested successfully on a few devices). We can still optimize it by using some fixed windows, but this can be done later without affecting any external code. Windows are just ranges in MMIO used for accessing cores on the bus. Cc: Greg KH <greg@kroah.com> Cc: Michael Büsch <mb@bu3sch.de> Cc: Larry Finger <Larry.Finger@lwfinger.net> Cc: George Kashperko <george@znau.edu.ua> Cc: Arend van Spriel <arend@broadcom.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King <rmk@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Andy Botting <andy@andybotting.com> Cc: linuxdriverproject <devel@linuxdriverproject.org> Cc: linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--Documentation/ABI/testing/sysfs-bus-bcma31
-rw-r--r--MAINTAINERS7
-rw-r--r--drivers/Kconfig2
-rw-r--r--drivers/Makefile1
-rw-r--r--drivers/bcma/Kconfig33
-rw-r--r--drivers/bcma/Makefile7
-rw-r--r--drivers/bcma/README19
-rw-r--r--drivers/bcma/TODO3
-rw-r--r--drivers/bcma/bcma_private.h28
-rw-r--r--drivers/bcma/core.c51
-rw-r--r--drivers/bcma/driver_chipcommon.c87
-rw-r--r--drivers/bcma/driver_chipcommon_pmu.c134
-rw-r--r--drivers/bcma/driver_pci.c163
-rw-r--r--drivers/bcma/host_pci.c196
-rw-r--r--drivers/bcma/main.c247
-rw-r--r--drivers/bcma/scan.c360
-rw-r--r--drivers/bcma/scan.h56
-rw-r--r--include/linux/bcma/bcma.h224
-rw-r--r--include/linux/bcma/bcma_driver_chipcommon.h297
-rw-r--r--include/linux/bcma/bcma_driver_pci.h89
-rw-r--r--include/linux/bcma/bcma_regs.h34
-rw-r--r--include/linux/mod_devicetable.h17
-rw-r--r--scripts/mod/file2alias.c22
23 files changed, 2108 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-bcma b/Documentation/ABI/testing/sysfs-bus-bcma
new file mode 100644
index 000000000000..06b62badddd1
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-bcma
@@ -0,0 +1,31 @@
1What: /sys/bus/bcma/devices/.../manuf
2Date: May 2011
3KernelVersion: 2.6.40
4Contact: Rafał Miłecki <zajec5@gmail.com>
5Description:
6 Each BCMA core has it's manufacturer id. See
7 include/linux/bcma/bcma.h for possible values.
8
9What: /sys/bus/bcma/devices/.../id
10Date: May 2011
11KernelVersion: 2.6.40
12Contact: Rafał Miłecki <zajec5@gmail.com>
13Description:
14 There are a few types of BCMA cores, they can be identified by
15 id field.
16
17What: /sys/bus/bcma/devices/.../rev
18Date: May 2011
19KernelVersion: 2.6.40
20Contact: Rafał Miłecki <zajec5@gmail.com>
21Description:
22 BCMA cores of the same type can still slightly differ depending
23 on their revision. Use it for detailed programming.
24
25What: /sys/bus/bcma/devices/.../class
26Date: May 2011
27KernelVersion: 2.6.40
28Contact: Rafał Miłecki <zajec5@gmail.com>
29Description:
30 Each BCMA core is identified by few fields, including class it
31 belongs to. See include/linux/bcma/bcma.h for possible values.
diff --git a/MAINTAINERS b/MAINTAINERS
index 9f9104987a73..df5585819a62 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5810,6 +5810,13 @@ S: Maintained
5810F: drivers/ssb/ 5810F: drivers/ssb/
5811F: include/linux/ssb/ 5811F: include/linux/ssb/
5812 5812
5813BROADCOM SPECIFIC AMBA DRIVER (BCMA)
5814M: Rafał Miłecki <zajec5@gmail.com>
5815L: linux-wireless@vger.kernel.org
5816S: Maintained
5817F: drivers/bcma/
5818F: include/linux/bcma/
5819
5813SONY VAIO CONTROL DEVICE DRIVER 5820SONY VAIO CONTROL DEVICE DRIVER
5814M: Mattia Dongili <malattia@linux.it> 5821M: Mattia Dongili <malattia@linux.it>
5815L: platform-driver-x86@vger.kernel.org 5822L: platform-driver-x86@vger.kernel.org
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 177c7d156933..aca706751469 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -68,6 +68,8 @@ source "drivers/watchdog/Kconfig"
68 68
69source "drivers/ssb/Kconfig" 69source "drivers/ssb/Kconfig"
70 70
71source "drivers/bcma/Kconfig"
72
71source "drivers/mfd/Kconfig" 73source "drivers/mfd/Kconfig"
72 74
73source "drivers/regulator/Kconfig" 75source "drivers/regulator/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 3f135b6fb014..a29527f4ded6 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_HID) += hid/
110obj-$(CONFIG_PPC_PS3) += ps3/ 110obj-$(CONFIG_PPC_PS3) += ps3/
111obj-$(CONFIG_OF) += of/ 111obj-$(CONFIG_OF) += of/
112obj-$(CONFIG_SSB) += ssb/ 112obj-$(CONFIG_SSB) += ssb/
113obj-$(CONFIG_BCMA) += bcma/
113obj-$(CONFIG_VHOST_NET) += vhost/ 114obj-$(CONFIG_VHOST_NET) += vhost/
114obj-$(CONFIG_VLYNQ) += vlynq/ 115obj-$(CONFIG_VLYNQ) += vlynq/
115obj-$(CONFIG_STAGING) += staging/ 116obj-$(CONFIG_STAGING) += staging/
diff --git a/drivers/bcma/Kconfig b/drivers/bcma/Kconfig
new file mode 100644
index 000000000000..353781b5b78b
--- /dev/null
+++ b/drivers/bcma/Kconfig
@@ -0,0 +1,33 @@
1config BCMA_POSSIBLE
2 bool
3 depends on HAS_IOMEM && HAS_DMA
4 default y
5
6menu "Broadcom specific AMBA"
7 depends on BCMA_POSSIBLE
8
9config BCMA
10 tristate "BCMA support"
11 depends on BCMA_POSSIBLE
12 help
13 Bus driver for Broadcom specific Advanced Microcontroller Bus
14 Architecture.
15
16config BCMA_HOST_PCI_POSSIBLE
17 bool
18 depends on BCMA && PCI = y
19 default y
20
21config BCMA_HOST_PCI
22 bool "Support for BCMA on PCI-host bus"
23 depends on BCMA_HOST_PCI_POSSIBLE
24
25config BCMA_DEBUG
26 bool "BCMA debugging"
27 depends on BCMA
28 help
29 This turns on additional debugging messages.
30
31 If unsure, say N
32
33endmenu
diff --git a/drivers/bcma/Makefile b/drivers/bcma/Makefile
new file mode 100644
index 000000000000..0d56245bcb79
--- /dev/null
+++ b/drivers/bcma/Makefile
@@ -0,0 +1,7 @@
1bcma-y += main.o scan.o core.o
2bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
3bcma-y += driver_pci.o
4bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
5obj-$(CONFIG_BCMA) += bcma.o
6
7ccflags-$(CONFIG_BCMA_DEBUG) := -DDEBUG
diff --git a/drivers/bcma/README b/drivers/bcma/README
new file mode 100644
index 000000000000..f7e7ce46c603
--- /dev/null
+++ b/drivers/bcma/README
@@ -0,0 +1,19 @@
1Broadcom introduced new bus as replacement for older SSB. It is based on AMBA,
2however from programming point of view there is nothing AMBA specific we use.
3
4Standard AMBA drivers are platform specific, have hardcoded addresses and use
5AMBA standard fields like CID and PID.
6
7In case of Broadcom's cards every device consists of:
81) Broadcom specific AMBA device. It is put on AMBA bus, but can not be treated
9 as standard AMBA device. Reading it's CID or PID can cause machine lockup.
102) AMBA standard devices called ports or wrappers. They have CIDs (AMBA_CID)
11 and PIDs (0x103BB369), but we do not use that info for anything. One of that
12 devices is used for managing Broadcom specific core.
13
14Addresses of AMBA devices are not hardcoded in driver and have to be read from
15EPROM.
16
17In this situation we decided to introduce separated bus. It can contain up to
1816 devices identified by Broadcom specific fields: manufacturer, id, revision
19and class.
diff --git a/drivers/bcma/TODO b/drivers/bcma/TODO
new file mode 100644
index 000000000000..da7aa99fe81c
--- /dev/null
+++ b/drivers/bcma/TODO
@@ -0,0 +1,3 @@
1- Interrupts
2- Defines for PCI core driver
3- Create kernel Documentation (use info from README)
diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h
new file mode 100644
index 000000000000..2f72e9c585fd
--- /dev/null
+++ b/drivers/bcma/bcma_private.h
@@ -0,0 +1,28 @@
1#ifndef LINUX_BCMA_PRIVATE_H_
2#define LINUX_BCMA_PRIVATE_H_
3
4#ifndef pr_fmt
5#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
6#endif
7
8#include <linux/bcma/bcma.h>
9#include <linux/delay.h>
10
11#define BCMA_CORE_SIZE 0x1000
12
13struct bcma_bus;
14
15/* main.c */
16extern int bcma_bus_register(struct bcma_bus *bus);
17extern void bcma_bus_unregister(struct bcma_bus *bus);
18
19/* scan.c */
20int bcma_bus_scan(struct bcma_bus *bus);
21
22#ifdef CONFIG_BCMA_HOST_PCI
23/* host_pci.c */
24extern int __init bcma_host_pci_init(void);
25extern void __exit bcma_host_pci_exit(void);
26#endif /* CONFIG_BCMA_HOST_PCI */
27
28#endif
diff --git a/drivers/bcma/core.c b/drivers/bcma/core.c
new file mode 100644
index 000000000000..ced379f7b371
--- /dev/null
+++ b/drivers/bcma/core.c
@@ -0,0 +1,51 @@
1/*
2 * Broadcom specific AMBA
3 * Core ops
4 *
5 * Licensed under the GNU/GPL. See COPYING for details.
6 */
7
8#include "bcma_private.h"
9#include <linux/bcma/bcma.h>
10
11bool bcma_core_is_enabled(struct bcma_device *core)
12{
13 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
14 != BCMA_IOCTL_CLK)
15 return false;
16 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
17 return false;
18 return true;
19}
20EXPORT_SYMBOL_GPL(bcma_core_is_enabled);
21
22static void bcma_core_disable(struct bcma_device *core, u32 flags)
23{
24 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
25 return;
26
27 bcma_awrite32(core, BCMA_IOCTL, flags);
28 bcma_aread32(core, BCMA_IOCTL);
29 udelay(10);
30
31 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
32 udelay(1);
33}
34
35int bcma_core_enable(struct bcma_device *core, u32 flags)
36{
37 bcma_core_disable(core, flags);
38
39 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC | flags));
40 bcma_aread32(core, BCMA_IOCTL);
41
42 bcma_awrite32(core, BCMA_RESET_CTL, 0);
43 udelay(1);
44
45 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
46 bcma_aread32(core, BCMA_IOCTL);
47 udelay(1);
48
49 return 0;
50}
51EXPORT_SYMBOL_GPL(bcma_core_enable);
diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c
new file mode 100644
index 000000000000..caf596091d4d
--- /dev/null
+++ b/drivers/bcma/driver_chipcommon.c
@@ -0,0 +1,87 @@
1/*
2 * Broadcom specific AMBA
3 * ChipCommon core driver
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "bcma_private.h"
12#include <linux/bcma/bcma.h>
13
14static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
15 u32 mask, u32 value)
16{
17 value &= mask;
18 value |= bcma_cc_read32(cc, offset) & ~mask;
19 bcma_cc_write32(cc, offset, value);
20
21 return value;
22}
23
24void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
25{
26 if (cc->core->id.rev >= 11)
27 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
28 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
29 if (cc->core->id.rev >= 35)
30 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
31
32 bcma_cc_write32(cc, 0x58, 0);
33 bcma_cc_write32(cc, 0x5C, 0);
34
35 if (cc->capabilities & BCMA_CC_CAP_PMU)
36 bcma_pmu_init(cc);
37 if (cc->capabilities & BCMA_CC_CAP_PCTL)
38 pr_err("Power control not implemented!\n");
39}
40
41/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
42void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
43{
44 /* instant NMI */
45 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
46}
47
48void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
49{
50 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
51}
52
53u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
54{
55 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
56}
57
58u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
59{
60 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
61}
62
63u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
64{
65 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
66}
67
68u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
69{
70 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
71}
72
73u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
74{
75 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
76}
77EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
78
79u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
80{
81 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
82}
83
84u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
85{
86 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
87}
diff --git a/drivers/bcma/driver_chipcommon_pmu.c b/drivers/bcma/driver_chipcommon_pmu.c
new file mode 100644
index 000000000000..f44177a644c7
--- /dev/null
+++ b/drivers/bcma/driver_chipcommon_pmu.c
@@ -0,0 +1,134 @@
1/*
2 * Broadcom specific AMBA
3 * ChipCommon Power Management Unit driver
4 *
5 * Copyright 2009, Michael Buesch <mb@bu3sch.de>
6 * Copyright 2007, Broadcom Corporation
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "bcma_private.h"
12#include <linux/bcma/bcma.h>
13
14static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
15 u32 offset, u32 mask, u32 set)
16{
17 u32 value;
18
19 bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
20 bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
21 bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
22 value = bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
23 value &= mask;
24 value |= set;
25 bcma_cc_write32(cc, BCMA_CC_CHIPCTL_DATA, value);
26 bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
27}
28
29static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
30{
31 struct bcma_bus *bus = cc->core->bus;
32
33 switch (bus->chipinfo.id) {
34 case 0x4313:
35 case 0x4331:
36 case 43224:
37 case 43225:
38 break;
39 default:
40 pr_err("PLL init unknown for device 0x%04X\n",
41 bus->chipinfo.id);
42 }
43}
44
45static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
46{
47 struct bcma_bus *bus = cc->core->bus;
48 u32 min_msk = 0, max_msk = 0;
49
50 switch (bus->chipinfo.id) {
51 case 0x4313:
52 min_msk = 0x200D;
53 max_msk = 0xFFFF;
54 break;
55 case 43224:
56 break;
57 default:
58 pr_err("PMU resource config unknown for device 0x%04X\n",
59 bus->chipinfo.id);
60 }
61
62 /* Set the resource masks. */
63 if (min_msk)
64 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
65 if (max_msk)
66 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
67}
68
69void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
70{
71 struct bcma_bus *bus = cc->core->bus;
72
73 switch (bus->chipinfo.id) {
74 case 0x4313:
75 case 0x4331:
76 case 43224:
77 break;
78 default:
79 pr_err("PMU switch/regulators init unknown for device "
80 "0x%04X\n", bus->chipinfo.id);
81 }
82}
83
84void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
85{
86 struct bcma_bus *bus = cc->core->bus;
87
88 switch (bus->chipinfo.id) {
89 case 0x4313:
90 bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
91 break;
92 case 0x4331:
93 pr_err("Enabling Ext PA lines not implemented\n");
94 break;
95 case 43224:
96 if (bus->chipinfo.rev == 0) {
97 pr_err("Workarounds for 43224 rev 0 not fully "
98 "implemented\n");
99 bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
100 } else {
101 bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
102 }
103 break;
104 default:
105 pr_err("Workarounds unknown for device 0x%04X\n",
106 bus->chipinfo.id);
107 }
108}
109
110void bcma_pmu_init(struct bcma_drv_cc *cc)
111{
112 u32 pmucap;
113
114 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
115 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
116
117 pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
118 pmucap);
119
120 if (cc->pmu.rev == 1)
121 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
122 ~BCMA_CC_PMU_CTL_NOILPONW);
123 else
124 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
125 BCMA_CC_PMU_CTL_NOILPONW);
126
127 if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
128 pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
129
130 bcma_pmu_pll_init(cc);
131 bcma_pmu_resources_init(cc);
132 bcma_pmu_swreg_init(cc);
133 bcma_pmu_workarounds(cc);
134}
diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c
new file mode 100644
index 000000000000..b98b8359bef5
--- /dev/null
+++ b/drivers/bcma/driver_pci.c
@@ -0,0 +1,163 @@
1/*
2 * Broadcom specific AMBA
3 * PCI Core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "bcma_private.h"
12#include <linux/bcma/bcma.h>
13
14/**************************************************
15 * R/W ops.
16 **************************************************/
17
18static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
19{
20 pcicore_write32(pc, 0x130, address);
21 pcicore_read32(pc, 0x130);
22 return pcicore_read32(pc, 0x134);
23}
24
25#if 0
26static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
27{
28 pcicore_write32(pc, 0x130, address);
29 pcicore_read32(pc, 0x130);
30 pcicore_write32(pc, 0x134, data);
31}
32#endif
33
34static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
35{
36 const u16 mdio_control = 0x128;
37 const u16 mdio_data = 0x12C;
38 u32 v;
39 int i;
40
41 v = (1 << 30); /* Start of Transaction */
42 v |= (1 << 28); /* Write Transaction */
43 v |= (1 << 17); /* Turnaround */
44 v |= (0x1F << 18);
45 v |= (phy << 4);
46 pcicore_write32(pc, mdio_data, v);
47
48 udelay(10);
49 for (i = 0; i < 200; i++) {
50 v = pcicore_read32(pc, mdio_control);
51 if (v & 0x100 /* Trans complete */)
52 break;
53 msleep(1);
54 }
55}
56
57static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
58{
59 const u16 mdio_control = 0x128;
60 const u16 mdio_data = 0x12C;
61 int max_retries = 10;
62 u16 ret = 0;
63 u32 v;
64 int i;
65
66 v = 0x80; /* Enable Preamble Sequence */
67 v |= 0x2; /* MDIO Clock Divisor */
68 pcicore_write32(pc, mdio_control, v);
69
70 if (pc->core->id.rev >= 10) {
71 max_retries = 200;
72 bcma_pcie_mdio_set_phy(pc, device);
73 }
74
75 v = (1 << 30); /* Start of Transaction */
76 v |= (1 << 29); /* Read Transaction */
77 v |= (1 << 17); /* Turnaround */
78 if (pc->core->id.rev < 10)
79 v |= (u32)device << 22;
80 v |= (u32)address << 18;
81 pcicore_write32(pc, mdio_data, v);
82 /* Wait for the device to complete the transaction */
83 udelay(10);
84 for (i = 0; i < 200; i++) {
85 v = pcicore_read32(pc, mdio_control);
86 if (v & 0x100 /* Trans complete */) {
87 udelay(10);
88 ret = pcicore_read32(pc, mdio_data);
89 break;
90 }
91 msleep(1);
92 }
93 pcicore_write32(pc, mdio_control, 0);
94 return ret;
95}
96
97static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
98 u8 address, u16 data)
99{
100 const u16 mdio_control = 0x128;
101 const u16 mdio_data = 0x12C;
102 int max_retries = 10;
103 u32 v;
104 int i;
105
106 v = 0x80; /* Enable Preamble Sequence */
107 v |= 0x2; /* MDIO Clock Divisor */
108 pcicore_write32(pc, mdio_control, v);
109
110 if (pc->core->id.rev >= 10) {
111 max_retries = 200;
112 bcma_pcie_mdio_set_phy(pc, device);
113 }
114
115 v = (1 << 30); /* Start of Transaction */
116 v |= (1 << 28); /* Write Transaction */
117 v |= (1 << 17); /* Turnaround */
118 if (pc->core->id.rev < 10)
119 v |= (u32)device << 22;
120 v |= (u32)address << 18;
121 v |= data;
122 pcicore_write32(pc, mdio_data, v);
123 /* Wait for the device to complete the transaction */
124 udelay(10);
125 for (i = 0; i < max_retries; i++) {
126 v = pcicore_read32(pc, mdio_control);
127 if (v & 0x100 /* Trans complete */)
128 break;
129 msleep(1);
130 }
131 pcicore_write32(pc, mdio_control, 0);
132}
133
134/**************************************************
135 * Workarounds.
136 **************************************************/
137
138static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
139{
140 return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
141}
142
143static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
144{
145 const u8 serdes_pll_device = 0x1D;
146 const u8 serdes_rx_device = 0x1F;
147 u16 tmp;
148
149 bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
150 bcma_pcicore_polarity_workaround(pc));
151 tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
152 if (tmp & 0x4000)
153 bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
154}
155
156/**************************************************
157 * Init.
158 **************************************************/
159
160void bcma_core_pci_init(struct bcma_drv_pci *pc)
161{
162 bcma_pcicore_serdes_workaround(pc);
163}
diff --git a/drivers/bcma/host_pci.c b/drivers/bcma/host_pci.c
new file mode 100644
index 000000000000..99dd36e8500b
--- /dev/null
+++ b/drivers/bcma/host_pci.c
@@ -0,0 +1,196 @@
1/*
2 * Broadcom specific AMBA
3 * PCI Host
4 *
5 * Licensed under the GNU/GPL. See COPYING for details.
6 */
7
8#include "bcma_private.h"
9#include <linux/bcma/bcma.h>
10#include <linux/pci.h>
11
12static void bcma_host_pci_switch_core(struct bcma_device *core)
13{
14 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
15 core->addr);
16 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
17 core->wrap);
18 core->bus->mapped_core = core;
19 pr_debug("Switched to core: 0x%X\n", core->id.id);
20}
21
22static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
23{
24 if (core->bus->mapped_core != core)
25 bcma_host_pci_switch_core(core);
26 return ioread8(core->bus->mmio + offset);
27}
28
29static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
30{
31 if (core->bus->mapped_core != core)
32 bcma_host_pci_switch_core(core);
33 return ioread16(core->bus->mmio + offset);
34}
35
36static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
37{
38 if (core->bus->mapped_core != core)
39 bcma_host_pci_switch_core(core);
40 return ioread32(core->bus->mmio + offset);
41}
42
43static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
44 u8 value)
45{
46 if (core->bus->mapped_core != core)
47 bcma_host_pci_switch_core(core);
48 iowrite8(value, core->bus->mmio + offset);
49}
50
51static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
52 u16 value)
53{
54 if (core->bus->mapped_core != core)
55 bcma_host_pci_switch_core(core);
56 iowrite16(value, core->bus->mmio + offset);
57}
58
59static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
60 u32 value)
61{
62 if (core->bus->mapped_core != core)
63 bcma_host_pci_switch_core(core);
64 iowrite32(value, core->bus->mmio + offset);
65}
66
67static u32 bcma_host_pci_aread32(struct bcma_device *core, u16 offset)
68{
69 if (core->bus->mapped_core != core)
70 bcma_host_pci_switch_core(core);
71 return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
72}
73
74static void bcma_host_pci_awrite32(struct bcma_device *core, u16 offset,
75 u32 value)
76{
77 if (core->bus->mapped_core != core)
78 bcma_host_pci_switch_core(core);
79 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
80}
81
82const struct bcma_host_ops bcma_host_pci_ops = {
83 .read8 = bcma_host_pci_read8,
84 .read16 = bcma_host_pci_read16,
85 .read32 = bcma_host_pci_read32,
86 .write8 = bcma_host_pci_write8,
87 .write16 = bcma_host_pci_write16,
88 .write32 = bcma_host_pci_write32,
89 .aread32 = bcma_host_pci_aread32,
90 .awrite32 = bcma_host_pci_awrite32,
91};
92
93static int bcma_host_pci_probe(struct pci_dev *dev,
94 const struct pci_device_id *id)
95{
96 struct bcma_bus *bus;
97 int err = -ENOMEM;
98 const char *name;
99 u32 val;
100
101 /* Alloc */
102 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
103 if (!bus)
104 goto out;
105
106 /* Basic PCI configuration */
107 err = pci_enable_device(dev);
108 if (err)
109 goto err_kfree_bus;
110
111 name = dev_name(&dev->dev);
112 if (dev->driver && dev->driver->name)
113 name = dev->driver->name;
114 err = pci_request_regions(dev, name);
115 if (err)
116 goto err_pci_disable;
117 pci_set_master(dev);
118
119 /* Disable the RETRY_TIMEOUT register (0x41) to keep
120 * PCI Tx retries from interfering with C3 CPU state */
121 pci_read_config_dword(dev, 0x40, &val);
122 if ((val & 0x0000ff00) != 0)
123 pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
124
125 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
126 if (!pci_is_pcie(dev))
127 pr_err("PCI card detected, report problems.\n");
128
129 /* Map MMIO */
130 err = -ENOMEM;
131 bus->mmio = pci_iomap(dev, 0, ~0UL);
132 if (!bus->mmio)
133 goto err_pci_release_regions;
134
135 /* Host specific */
136 bus->host_pci = dev;
137 bus->hosttype = BCMA_HOSTTYPE_PCI;
138 bus->ops = &bcma_host_pci_ops;
139
140 /* Register */
141 err = bcma_bus_register(bus);
142 if (err)
143 goto err_pci_unmap_mmio;
144
145 pci_set_drvdata(dev, bus);
146
147out:
148 return err;
149
150err_pci_unmap_mmio:
151 pci_iounmap(dev, bus->mmio);
152err_pci_release_regions:
153 pci_release_regions(dev);
154err_pci_disable:
155 pci_disable_device(dev);
156err_kfree_bus:
157 kfree(bus);
158 return err;
159}
160
161static void bcma_host_pci_remove(struct pci_dev *dev)
162{
163 struct bcma_bus *bus = pci_get_drvdata(dev);
164
165 bcma_bus_unregister(bus);
166 pci_iounmap(dev, bus->mmio);
167 pci_release_regions(dev);
168 pci_disable_device(dev);
169 kfree(bus);
170 pci_set_drvdata(dev, NULL);
171}
172
173static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
174 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
175 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
176 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
177 { 0, },
178};
179MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
180
181static struct pci_driver bcma_pci_bridge_driver = {
182 .name = "bcma-pci-bridge",
183 .id_table = bcma_pci_bridge_tbl,
184 .probe = bcma_host_pci_probe,
185 .remove = bcma_host_pci_remove,
186};
187
188int __init bcma_host_pci_init(void)
189{
190 return pci_register_driver(&bcma_pci_bridge_driver);
191}
192
193void __exit bcma_host_pci_exit(void)
194{
195 pci_unregister_driver(&bcma_pci_bridge_driver);
196}
diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c
new file mode 100644
index 000000000000..be52344ed19d
--- /dev/null
+++ b/drivers/bcma/main.c
@@ -0,0 +1,247 @@
1/*
2 * Broadcom specific AMBA
3 * Bus subsystem
4 *
5 * Licensed under the GNU/GPL. See COPYING for details.
6 */
7
8#include "bcma_private.h"
9#include <linux/bcma/bcma.h>
10
11MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
12MODULE_LICENSE("GPL");
13
14static int bcma_bus_match(struct device *dev, struct device_driver *drv);
15static int bcma_device_probe(struct device *dev);
16static int bcma_device_remove(struct device *dev);
17
18static ssize_t manuf_show(struct device *dev, struct device_attribute *attr, char *buf)
19{
20 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
21 return sprintf(buf, "0x%03X\n", core->id.manuf);
22}
23static ssize_t id_show(struct device *dev, struct device_attribute *attr, char *buf)
24{
25 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
26 return sprintf(buf, "0x%03X\n", core->id.id);
27}
28static ssize_t rev_show(struct device *dev, struct device_attribute *attr, char *buf)
29{
30 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
31 return sprintf(buf, "0x%02X\n", core->id.rev);
32}
33static ssize_t class_show(struct device *dev, struct device_attribute *attr, char *buf)
34{
35 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
36 return sprintf(buf, "0x%X\n", core->id.class);
37}
38static struct device_attribute bcma_device_attrs[] = {
39 __ATTR_RO(manuf),
40 __ATTR_RO(id),
41 __ATTR_RO(rev),
42 __ATTR_RO(class),
43 __ATTR_NULL,
44};
45
46static struct bus_type bcma_bus_type = {
47 .name = "bcma",
48 .match = bcma_bus_match,
49 .probe = bcma_device_probe,
50 .remove = bcma_device_remove,
51 .dev_attrs = bcma_device_attrs,
52};
53
54static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
55{
56 struct bcma_device *core;
57
58 list_for_each_entry(core, &bus->cores, list) {
59 if (core->id.id == coreid)
60 return core;
61 }
62 return NULL;
63}
64
65static void bcma_release_core_dev(struct device *dev)
66{
67 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
68 kfree(core);
69}
70
71static int bcma_register_cores(struct bcma_bus *bus)
72{
73 struct bcma_device *core;
74 int err, dev_id = 0;
75
76 list_for_each_entry(core, &bus->cores, list) {
77 /* We support that cores ourself */
78 switch (core->id.id) {
79 case BCMA_CORE_CHIPCOMMON:
80 case BCMA_CORE_PCI:
81 case BCMA_CORE_PCIE:
82 continue;
83 }
84
85 core->dev.release = bcma_release_core_dev;
86 core->dev.bus = &bcma_bus_type;
87 dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
88
89 switch (bus->hosttype) {
90 case BCMA_HOSTTYPE_PCI:
91 core->dev.parent = &bus->host_pci->dev;
92 break;
93 case BCMA_HOSTTYPE_NONE:
94 case BCMA_HOSTTYPE_SDIO:
95 break;
96 }
97
98 err = device_register(&core->dev);
99 if (err) {
100 pr_err("Could not register dev for core 0x%03X\n",
101 core->id.id);
102 continue;
103 }
104 core->dev_registered = true;
105 dev_id++;
106 }
107
108 return 0;
109}
110
111static void bcma_unregister_cores(struct bcma_bus *bus)
112{
113 struct bcma_device *core;
114
115 list_for_each_entry(core, &bus->cores, list) {
116 if (core->dev_registered)
117 device_unregister(&core->dev);
118 }
119}
120
121int bcma_bus_register(struct bcma_bus *bus)
122{
123 int err;
124 struct bcma_device *core;
125
126 /* Scan for devices (cores) */
127 err = bcma_bus_scan(bus);
128 if (err) {
129 pr_err("Failed to scan: %d\n", err);
130 return -1;
131 }
132
133 /* Init CC core */
134 core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
135 if (core) {
136 bus->drv_cc.core = core;
137 bcma_core_chipcommon_init(&bus->drv_cc);
138 }
139
140 /* Init PCIE core */
141 core = bcma_find_core(bus, BCMA_CORE_PCIE);
142 if (core) {
143 bus->drv_pci.core = core;
144 bcma_core_pci_init(&bus->drv_pci);
145 }
146
147 /* Register found cores */
148 bcma_register_cores(bus);
149
150 pr_info("Bus registered\n");
151
152 return 0;
153}
154EXPORT_SYMBOL_GPL(bcma_bus_register);
155
156void bcma_bus_unregister(struct bcma_bus *bus)
157{
158 bcma_unregister_cores(bus);
159}
160EXPORT_SYMBOL_GPL(bcma_bus_unregister);
161
162int __bcma_driver_register(struct bcma_driver *drv, struct module *owner)
163{
164 drv->drv.name = drv->name;
165 drv->drv.bus = &bcma_bus_type;
166 drv->drv.owner = owner;
167
168 return driver_register(&drv->drv);
169}
170EXPORT_SYMBOL_GPL(__bcma_driver_register);
171
172void bcma_driver_unregister(struct bcma_driver *drv)
173{
174 driver_unregister(&drv->drv);
175}
176EXPORT_SYMBOL_GPL(bcma_driver_unregister);
177
178static int bcma_bus_match(struct device *dev, struct device_driver *drv)
179{
180 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
181 struct bcma_driver *adrv = container_of(drv, struct bcma_driver, drv);
182 const struct bcma_device_id *cid = &core->id;
183 const struct bcma_device_id *did;
184
185 for (did = adrv->id_table; did->manuf || did->id || did->rev; did++) {
186 if ((did->manuf == cid->manuf || did->manuf == BCMA_ANY_MANUF) &&
187 (did->id == cid->id || did->id == BCMA_ANY_ID) &&
188 (did->rev == cid->rev || did->rev == BCMA_ANY_REV) &&
189 (did->class == cid->class || did->class == BCMA_ANY_CLASS))
190 return 1;
191 }
192 return 0;
193}
194
195static int bcma_device_probe(struct device *dev)
196{
197 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
198 struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
199 drv);
200 int err = 0;
201
202 if (adrv->probe)
203 err = adrv->probe(core);
204
205 return err;
206}
207
208static int bcma_device_remove(struct device *dev)
209{
210 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
211 struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
212 drv);
213
214 if (adrv->remove)
215 adrv->remove(core);
216
217 return 0;
218}
219
220static int __init bcma_modinit(void)
221{
222 int err;
223
224 err = bus_register(&bcma_bus_type);
225 if (err)
226 return err;
227
228#ifdef CONFIG_BCMA_HOST_PCI
229 err = bcma_host_pci_init();
230 if (err) {
231 pr_err("PCI host initialization failed\n");
232 err = 0;
233 }
234#endif
235
236 return err;
237}
238fs_initcall(bcma_modinit);
239
240static void __exit bcma_modexit(void)
241{
242#ifdef CONFIG_BCMA_HOST_PCI
243 bcma_host_pci_exit();
244#endif
245 bus_unregister(&bcma_bus_type);
246}
247module_exit(bcma_modexit)
diff --git a/drivers/bcma/scan.c b/drivers/bcma/scan.c
new file mode 100644
index 000000000000..40d7dcce8933
--- /dev/null
+++ b/drivers/bcma/scan.c
@@ -0,0 +1,360 @@
1/*
2 * Broadcom specific AMBA
3 * Bus scanning
4 *
5 * Licensed under the GNU/GPL. See COPYING for details.
6 */
7
8#include "scan.h"
9#include "bcma_private.h"
10
11#include <linux/bcma/bcma.h>
12#include <linux/bcma/bcma_regs.h>
13#include <linux/pci.h>
14#include <linux/io.h>
15#include <linux/dma-mapping.h>
16#include <linux/slab.h>
17
18struct bcma_device_id_name {
19 u16 id;
20 const char *name;
21};
22struct bcma_device_id_name bcma_device_names[] = {
23 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
24 { BCMA_CORE_INVALID, "Invalid" },
25 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
26 { BCMA_CORE_ILINE20, "ILine 20" },
27 { BCMA_CORE_SRAM, "SRAM" },
28 { BCMA_CORE_SDRAM, "SDRAM" },
29 { BCMA_CORE_PCI, "PCI" },
30 { BCMA_CORE_MIPS, "MIPS" },
31 { BCMA_CORE_ETHERNET, "Fast Ethernet" },
32 { BCMA_CORE_V90, "V90" },
33 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
34 { BCMA_CORE_ADSL, "ADSL" },
35 { BCMA_CORE_ILINE100, "ILine 100" },
36 { BCMA_CORE_IPSEC, "IPSEC" },
37 { BCMA_CORE_UTOPIA, "UTOPIA" },
38 { BCMA_CORE_PCMCIA, "PCMCIA" },
39 { BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
40 { BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
41 { BCMA_CORE_OFDM, "OFDM" },
42 { BCMA_CORE_EXTIF, "EXTIF" },
43 { BCMA_CORE_80211, "IEEE 802.11" },
44 { BCMA_CORE_PHY_A, "PHY A" },
45 { BCMA_CORE_PHY_B, "PHY B" },
46 { BCMA_CORE_PHY_G, "PHY G" },
47 { BCMA_CORE_MIPS_3302, "MIPS 3302" },
48 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
49 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
50 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
51 { BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
52 { BCMA_CORE_SDIO_HOST, "SDIO Host" },
53 { BCMA_CORE_ROBOSWITCH, "Roboswitch" },
54 { BCMA_CORE_PARA_ATA, "PATA" },
55 { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
56 { BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
57 { BCMA_CORE_PCIE, "PCIe" },
58 { BCMA_CORE_PHY_N, "PHY N" },
59 { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
60 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
61 { BCMA_CORE_ARM_1176, "ARM 1176" },
62 { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
63 { BCMA_CORE_PHY_LP, "PHY LP" },
64 { BCMA_CORE_PMU, "PMU" },
65 { BCMA_CORE_PHY_SSN, "PHY SSN" },
66 { BCMA_CORE_SDIO_DEV, "SDIO Device" },
67 { BCMA_CORE_ARM_CM3, "ARM CM3" },
68 { BCMA_CORE_PHY_HT, "PHY HT" },
69 { BCMA_CORE_MIPS_74K, "MIPS 74K" },
70 { BCMA_CORE_MAC_GBIT, "GBit MAC" },
71 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
72 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
73 { BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
74 { BCMA_CORE_SHARED_COMMON, "Common Shared" },
75 { BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
76 { BCMA_CORE_SPI_HOST, "SPI Host" },
77 { BCMA_CORE_I2S, "I2S" },
78 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
79 { BCMA_CORE_SHIM, "SHIM" },
80 { BCMA_CORE_DEFAULT, "Default" },
81};
82const char *bcma_device_name(struct bcma_device_id *id)
83{
84 int i;
85
86 if (id->manuf == BCMA_MANUF_BCM) {
87 for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
88 if (bcma_device_names[i].id == id->id)
89 return bcma_device_names[i].name;
90 }
91 }
92 return "UNKNOWN";
93}
94
95static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
96 u16 offset)
97{
98 return readl(bus->mmio + offset);
99}
100
101static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
102{
103 if (bus->hosttype == BCMA_HOSTTYPE_PCI)
104 pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
105 addr);
106}
107
108static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
109{
110 u32 ent = readl(*eromptr);
111 (*eromptr)++;
112 return ent;
113}
114
115static void bcma_erom_push_ent(u32 **eromptr)
116{
117 (*eromptr)--;
118}
119
120static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
121{
122 u32 ent = bcma_erom_get_ent(bus, eromptr);
123 if (!(ent & SCAN_ER_VALID))
124 return -ENOENT;
125 if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
126 return -ENOENT;
127 return ent;
128}
129
130static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
131{
132 u32 ent = bcma_erom_get_ent(bus, eromptr);
133 bcma_erom_push_ent(eromptr);
134 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
135}
136
137static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
138{
139 u32 ent = bcma_erom_get_ent(bus, eromptr);
140 bcma_erom_push_ent(eromptr);
141 return (((ent & SCAN_ER_VALID)) &&
142 ((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
143 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
144}
145
146static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
147{
148 u32 ent;
149 while (1) {
150 ent = bcma_erom_get_ent(bus, eromptr);
151 if ((ent & SCAN_ER_VALID) &&
152 ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
153 break;
154 if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
155 break;
156 }
157 bcma_erom_push_ent(eromptr);
158}
159
160static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
161{
162 u32 ent = bcma_erom_get_ent(bus, eromptr);
163 if (!(ent & SCAN_ER_VALID))
164 return -ENOENT;
165 if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
166 return -ENOENT;
167 return ent;
168}
169
170static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
171 u32 type, u8 port)
172{
173 u32 addrl, addrh, sizel, sizeh = 0;
174 u32 size;
175
176 u32 ent = bcma_erom_get_ent(bus, eromptr);
177 if ((!(ent & SCAN_ER_VALID)) ||
178 ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
179 ((ent & SCAN_ADDR_TYPE) != type) ||
180 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
181 bcma_erom_push_ent(eromptr);
182 return -EINVAL;
183 }
184
185 addrl = ent & SCAN_ADDR_ADDR;
186 if (ent & SCAN_ADDR_AG32)
187 addrh = bcma_erom_get_ent(bus, eromptr);
188 else
189 addrh = 0;
190
191 if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
192 size = bcma_erom_get_ent(bus, eromptr);
193 sizel = size & SCAN_SIZE_SZ;
194 if (size & SCAN_SIZE_SG32)
195 sizeh = bcma_erom_get_ent(bus, eromptr);
196 } else
197 sizel = SCAN_ADDR_SZ_BASE <<
198 ((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);
199
200 return addrl;
201}
202
203int bcma_bus_scan(struct bcma_bus *bus)
204{
205 u32 erombase;
206 u32 __iomem *eromptr, *eromend;
207
208 s32 cia, cib;
209 u8 ports[2], wrappers[2];
210
211 s32 tmp;
212 u8 i, j;
213
214 int err;
215
216 INIT_LIST_HEAD(&bus->cores);
217 bus->nr_cores = 0;
218
219 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
220
221 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
222 bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
223 bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
224 bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
225
226 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
227 eromptr = bus->mmio;
228 eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
229
230 bcma_scan_switch_core(bus, erombase);
231
232 while (eromptr < eromend) {
233 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
234 if (!core)
235 return -ENOMEM;
236 INIT_LIST_HEAD(&core->list);
237 core->bus = bus;
238
239 /* get CIs */
240 cia = bcma_erom_get_ci(bus, &eromptr);
241 if (cia < 0) {
242 bcma_erom_push_ent(&eromptr);
243 if (bcma_erom_is_end(bus, &eromptr))
244 break;
245 err= -EILSEQ;
246 goto out;
247 }
248 cib = bcma_erom_get_ci(bus, &eromptr);
249 if (cib < 0) {
250 err= -EILSEQ;
251 goto out;
252 }
253
254 /* parse CIs */
255 core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
256 core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
257 core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
258 ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
259 ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
260 wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
261 wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
262 core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
263
264 if (((core->id.manuf == BCMA_MANUF_ARM) &&
265 (core->id.id == 0xFFF)) ||
266 (ports[1] == 0)) {
267 bcma_erom_skip_component(bus, &eromptr);
268 continue;
269 }
270
271 /* check if component is a core at all */
272 if (wrappers[0] + wrappers[1] == 0) {
273 /* we could save addrl of the router
274 if (cid == BCMA_CORE_OOB_ROUTER)
275 */
276 bcma_erom_skip_component(bus, &eromptr);
277 continue;
278 }
279
280 if (bcma_erom_is_bridge(bus, &eromptr)) {
281 bcma_erom_skip_component(bus, &eromptr);
282 continue;
283 }
284
285 /* get & parse master ports */
286 for (i = 0; i < ports[0]; i++) {
287 u32 mst_port_d = bcma_erom_get_mst_port(bus, &eromptr);
288 if (mst_port_d < 0) {
289 err= -EILSEQ;
290 goto out;
291 }
292 }
293
294 /* get & parse slave ports */
295 for (i = 0; i < ports[1]; i++) {
296 for (j = 0; ; j++) {
297 tmp = bcma_erom_get_addr_desc(bus, &eromptr,
298 SCAN_ADDR_TYPE_SLAVE, i);
299 if (tmp < 0) {
300 /* no more entries for port _i_ */
301 /* pr_debug("erom: slave port %d "
302 * "has %d descriptors\n", i, j); */
303 break;
304 } else {
305 if (i == 0 && j == 0)
306 core->addr = tmp;
307 }
308 }
309 }
310
311 /* get & parse master wrappers */
312 for (i = 0; i < wrappers[0]; i++) {
313 for (j = 0; ; j++) {
314 tmp = bcma_erom_get_addr_desc(bus, &eromptr,
315 SCAN_ADDR_TYPE_MWRAP, i);
316 if (tmp < 0) {
317 /* no more entries for port _i_ */
318 /* pr_debug("erom: master wrapper %d "
319 * "has %d descriptors\n", i, j); */
320 break;
321 } else {
322 if (i == 0 && j == 0)
323 core->wrap = tmp;
324 }
325 }
326 }
327
328 /* get & parse slave wrappers */
329 for (i = 0; i < wrappers[1]; i++) {
330 u8 hack = (ports[1] == 1) ? 0 : 1;
331 for (j = 0; ; j++) {
332 tmp = bcma_erom_get_addr_desc(bus, &eromptr,
333 SCAN_ADDR_TYPE_SWRAP, i + hack);
334 if (tmp < 0) {
335 /* no more entries for port _i_ */
336 /* pr_debug("erom: master wrapper %d "
337 * has %d descriptors\n", i, j); */
338 break;
339 } else {
340 if (wrappers[0] == 0 && !i && !j)
341 core->wrap = tmp;
342 }
343 }
344 }
345
346 pr_info("Core %d found: %s "
347 "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
348 bus->nr_cores, bcma_device_name(&core->id),
349 core->id.manuf, core->id.id, core->id.rev,
350 core->id.class);
351
352 core->core_index = bus->nr_cores++;
353 list_add(&core->list, &bus->cores);
354 continue;
355out:
356 return err;
357 }
358
359 return 0;
360}
diff --git a/drivers/bcma/scan.h b/drivers/bcma/scan.h
new file mode 100644
index 000000000000..113e6a66884c
--- /dev/null
+++ b/drivers/bcma/scan.h
@@ -0,0 +1,56 @@
1#ifndef BCMA_SCAN_H_
2#define BCMA_SCAN_H_
3
4#define BCMA_ADDR_BASE 0x18000000
5#define BCMA_WRAP_BASE 0x18100000
6
7#define SCAN_ER_VALID 0x00000001
8#define SCAN_ER_TAGX 0x00000006 /* we have to ignore 0x8 bit when checking tag for SCAN_ER_TAG_ADDR */
9#define SCAN_ER_TAG 0x0000000E
10#define SCAN_ER_TAG_CI 0x00000000
11#define SCAN_ER_TAG_MP 0x00000002
12#define SCAN_ER_TAG_ADDR 0x00000004
13#define SCAN_ER_TAG_END 0x0000000E
14#define SCAN_ER_BAD 0xFFFFFFFF
15
16#define SCAN_CIA_CLASS 0x000000F0
17#define SCAN_CIA_CLASS_SHIFT 4
18#define SCAN_CIA_ID 0x000FFF00
19#define SCAN_CIA_ID_SHIFT 8
20#define SCAN_CIA_MANUF 0xFFF00000
21#define SCAN_CIA_MANUF_SHIFT 20
22
23#define SCAN_CIB_NMP 0x000001F0
24#define SCAN_CIB_NMP_SHIFT 4
25#define SCAN_CIB_NSP 0x00003E00
26#define SCAN_CIB_NSP_SHIFT 9
27#define SCAN_CIB_NMW 0x0007C000
28#define SCAN_CIB_NMW_SHIFT 14
29#define SCAN_CIB_NSW 0x00F80000
30#define SCAN_CIB_NSW_SHIFT 17
31#define SCAN_CIB_REV 0xFF000000
32#define SCAN_CIB_REV_SHIFT 24
33
34#define SCAN_ADDR_AG32 0x00000008
35#define SCAN_ADDR_SZ 0x00000030
36#define SCAN_ADDR_SZ_SHIFT 4
37#define SCAN_ADDR_SZ_4K 0x00000000
38#define SCAN_ADDR_SZ_8K 0x00000010
39#define SCAN_ADDR_SZ_16K 0x00000020
40#define SCAN_ADDR_SZ_SZD 0x00000030
41#define SCAN_ADDR_TYPE 0x000000C0
42#define SCAN_ADDR_TYPE_SLAVE 0x00000000
43#define SCAN_ADDR_TYPE_BRIDGE 0x00000040
44#define SCAN_ADDR_TYPE_SWRAP 0x00000080
45#define SCAN_ADDR_TYPE_MWRAP 0x000000C0
46#define SCAN_ADDR_PORT 0x00000F00
47#define SCAN_ADDR_PORT_SHIFT 8
48#define SCAN_ADDR_ADDR 0xFFFFF000
49
50#define SCAN_ADDR_SZ_BASE 0x00001000 /* 4KB */
51
52#define SCAN_SIZE_SZ_ALIGN 0x00000FFF
53#define SCAN_SIZE_SZ 0xFFFFF000
54#define SCAN_SIZE_SG32 0x00000008
55
56#endif /* BCMA_SCAN_H_ */
diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
new file mode 100644
index 000000000000..08763e4e848f
--- /dev/null
+++ b/include/linux/bcma/bcma.h
@@ -0,0 +1,224 @@
1#ifndef LINUX_BCMA_H_
2#define LINUX_BCMA_H_
3
4#include <linux/pci.h>
5#include <linux/mod_devicetable.h>
6
7#include <linux/bcma/bcma_driver_chipcommon.h>
8#include <linux/bcma/bcma_driver_pci.h>
9
10#include "bcma_regs.h"
11
12struct bcma_device;
13struct bcma_bus;
14
15enum bcma_hosttype {
16 BCMA_HOSTTYPE_NONE,
17 BCMA_HOSTTYPE_PCI,
18 BCMA_HOSTTYPE_SDIO,
19};
20
21struct bcma_chipinfo {
22 u16 id;
23 u8 rev;
24 u8 pkg;
25};
26
27struct bcma_host_ops {
28 u8 (*read8)(struct bcma_device *core, u16 offset);
29 u16 (*read16)(struct bcma_device *core, u16 offset);
30 u32 (*read32)(struct bcma_device *core, u16 offset);
31 void (*write8)(struct bcma_device *core, u16 offset, u8 value);
32 void (*write16)(struct bcma_device *core, u16 offset, u16 value);
33 void (*write32)(struct bcma_device *core, u16 offset, u32 value);
34 /* Agent ops */
35 u32 (*aread32)(struct bcma_device *core, u16 offset);
36 void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
37};
38
39/* Core manufacturers */
40#define BCMA_MANUF_ARM 0x43B
41#define BCMA_MANUF_MIPS 0x4A7
42#define BCMA_MANUF_BCM 0x4BF
43
44/* Core class values. */
45#define BCMA_CL_SIM 0x0
46#define BCMA_CL_EROM 0x1
47#define BCMA_CL_CORESIGHT 0x9
48#define BCMA_CL_VERIF 0xB
49#define BCMA_CL_OPTIMO 0xD
50#define BCMA_CL_GEN 0xE
51#define BCMA_CL_PRIMECELL 0xF
52
53/* Core-ID values. */
54#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
55#define BCMA_CORE_INVALID 0x700
56#define BCMA_CORE_CHIPCOMMON 0x800
57#define BCMA_CORE_ILINE20 0x801
58#define BCMA_CORE_SRAM 0x802
59#define BCMA_CORE_SDRAM 0x803
60#define BCMA_CORE_PCI 0x804
61#define BCMA_CORE_MIPS 0x805
62#define BCMA_CORE_ETHERNET 0x806
63#define BCMA_CORE_V90 0x807
64#define BCMA_CORE_USB11_HOSTDEV 0x808
65#define BCMA_CORE_ADSL 0x809
66#define BCMA_CORE_ILINE100 0x80A
67#define BCMA_CORE_IPSEC 0x80B
68#define BCMA_CORE_UTOPIA 0x80C
69#define BCMA_CORE_PCMCIA 0x80D
70#define BCMA_CORE_INTERNAL_MEM 0x80E
71#define BCMA_CORE_MEMC_SDRAM 0x80F
72#define BCMA_CORE_OFDM 0x810
73#define BCMA_CORE_EXTIF 0x811
74#define BCMA_CORE_80211 0x812
75#define BCMA_CORE_PHY_A 0x813
76#define BCMA_CORE_PHY_B 0x814
77#define BCMA_CORE_PHY_G 0x815
78#define BCMA_CORE_MIPS_3302 0x816
79#define BCMA_CORE_USB11_HOST 0x817
80#define BCMA_CORE_USB11_DEV 0x818
81#define BCMA_CORE_USB20_HOST 0x819
82#define BCMA_CORE_USB20_DEV 0x81A
83#define BCMA_CORE_SDIO_HOST 0x81B
84#define BCMA_CORE_ROBOSWITCH 0x81C
85#define BCMA_CORE_PARA_ATA 0x81D
86#define BCMA_CORE_SATA_XORDMA 0x81E
87#define BCMA_CORE_ETHERNET_GBIT 0x81F
88#define BCMA_CORE_PCIE 0x820
89#define BCMA_CORE_PHY_N 0x821
90#define BCMA_CORE_SRAM_CTL 0x822
91#define BCMA_CORE_MINI_MACPHY 0x823
92#define BCMA_CORE_ARM_1176 0x824
93#define BCMA_CORE_ARM_7TDMI 0x825
94#define BCMA_CORE_PHY_LP 0x826
95#define BCMA_CORE_PMU 0x827
96#define BCMA_CORE_PHY_SSN 0x828
97#define BCMA_CORE_SDIO_DEV 0x829
98#define BCMA_CORE_ARM_CM3 0x82A
99#define BCMA_CORE_PHY_HT 0x82B
100#define BCMA_CORE_MIPS_74K 0x82C
101#define BCMA_CORE_MAC_GBIT 0x82D
102#define BCMA_CORE_DDR12_MEM_CTL 0x82E
103#define BCMA_CORE_PCIE_RC 0x82F /* PCIe Root Complex */
104#define BCMA_CORE_OCP_OCP_BRIDGE 0x830
105#define BCMA_CORE_SHARED_COMMON 0x831
106#define BCMA_CORE_OCP_AHB_BRIDGE 0x832
107#define BCMA_CORE_SPI_HOST 0x833
108#define BCMA_CORE_I2S 0x834
109#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
110#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
111#define BCMA_CORE_DEFAULT 0xFFF
112
113#define BCMA_MAX_NR_CORES 16
114
115struct bcma_device {
116 struct bcma_bus *bus;
117 struct bcma_device_id id;
118
119 struct device dev;
120 bool dev_registered;
121
122 u8 core_index;
123
124 u32 addr;
125 u32 wrap;
126
127 void *drvdata;
128 struct list_head list;
129};
130
131static inline void *bcma_get_drvdata(struct bcma_device *core)
132{
133 return core->drvdata;
134}
135static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
136{
137 core->drvdata = drvdata;
138}
139
140struct bcma_driver {
141 const char *name;
142 const struct bcma_device_id *id_table;
143
144 int (*probe)(struct bcma_device *dev);
145 void (*remove)(struct bcma_device *dev);
146 int (*suspend)(struct bcma_device *dev, pm_message_t state);
147 int (*resume)(struct bcma_device *dev);
148 void (*shutdown)(struct bcma_device *dev);
149
150 struct device_driver drv;
151};
152extern
153int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
154static inline int bcma_driver_register(struct bcma_driver *drv)
155{
156 return __bcma_driver_register(drv, THIS_MODULE);
157}
158extern void bcma_driver_unregister(struct bcma_driver *drv);
159
160struct bcma_bus {
161 /* The MMIO area. */
162 void __iomem *mmio;
163
164 const struct bcma_host_ops *ops;
165
166 enum bcma_hosttype hosttype;
167 union {
168 /* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
169 struct pci_dev *host_pci;
170 /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
171 struct sdio_func *host_sdio;
172 };
173
174 struct bcma_chipinfo chipinfo;
175
176 struct bcma_device *mapped_core;
177 struct list_head cores;
178 u8 nr_cores;
179
180 struct bcma_drv_cc drv_cc;
181 struct bcma_drv_pci drv_pci;
182};
183
184extern inline u32 bcma_read8(struct bcma_device *core, u16 offset)
185{
186 return core->bus->ops->read8(core, offset);
187}
188extern inline u32 bcma_read16(struct bcma_device *core, u16 offset)
189{
190 return core->bus->ops->read16(core, offset);
191}
192extern inline u32 bcma_read32(struct bcma_device *core, u16 offset)
193{
194 return core->bus->ops->read32(core, offset);
195}
196extern inline
197void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
198{
199 core->bus->ops->write8(core, offset, value);
200}
201extern inline
202void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
203{
204 core->bus->ops->write16(core, offset, value);
205}
206extern inline
207void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
208{
209 core->bus->ops->write32(core, offset, value);
210}
211extern inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
212{
213 return core->bus->ops->aread32(core, offset);
214}
215extern inline
216void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
217{
218 core->bus->ops->awrite32(core, offset, value);
219}
220
221extern bool bcma_core_is_enabled(struct bcma_device *core);
222extern int bcma_core_enable(struct bcma_device *core, u32 flags);
223
224#endif /* LINUX_BCMA_H_ */
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
new file mode 100644
index 000000000000..4f8fd6a4c1e6
--- /dev/null
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -0,0 +1,297 @@
1#ifndef LINUX_BCMA_DRIVER_CC_H_
2#define LINUX_BCMA_DRIVER_CC_H_
3
4/** ChipCommon core registers. **/
5#define BCMA_CC_ID 0x0000
6#define BCMA_CC_ID_ID 0x0000FFFF
7#define BCMA_CC_ID_ID_SHIFT 0
8#define BCMA_CC_ID_REV 0x000F0000
9#define BCMA_CC_ID_REV_SHIFT 16
10#define BCMA_CC_ID_PKG 0x00F00000
11#define BCMA_CC_ID_PKG_SHIFT 20
12#define BCMA_CC_ID_NRCORES 0x0F000000
13#define BCMA_CC_ID_NRCORES_SHIFT 24
14#define BCMA_CC_ID_TYPE 0xF0000000
15#define BCMA_CC_ID_TYPE_SHIFT 28
16#define BCMA_CC_CAP 0x0004 /* Capabilities */
17#define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
18#define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
19#define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
20#define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
21#define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
22#define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
23#define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
24#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
25#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
26#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
27#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
28#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
29#define BCMA_PLLTYPE_NONE 0x00000000
30#define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
31#define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
32#define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
33#define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
34#define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
35#define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
36#define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
37#define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
38#define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
39#define BCMA_CC_CAP_OTPS_SHIFT 19
40#define BCMA_CC_CAP_OTPS_BASE 5
41#define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
42#define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
43#define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
44#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
45#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
46#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
47#define BCMA_CC_CORECTL 0x0008
48#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
49#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
50#define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
51#define BCMA_CC_BIST 0x000C
52#define BCMA_CC_OTPS 0x0010 /* OTP status */
53#define BCMA_CC_OTPS_PROGFAIL 0x80000000
54#define BCMA_CC_OTPS_PROTECT 0x00000007
55#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
56#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
57#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
58#define BCMA_CC_OTPC 0x0014 /* OTP control */
59#define BCMA_CC_OTPC_RECWAIT 0xFF000000
60#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
61#define BCMA_CC_OTPC_PRW_SHIFT 8
62#define BCMA_CC_OTPC_MAXFAIL 0x00000038
63#define BCMA_CC_OTPC_VSEL 0x00000006
64#define BCMA_CC_OTPC_SELVL 0x00000001
65#define BCMA_CC_OTPP 0x0018 /* OTP prog */
66#define BCMA_CC_OTPP_COL 0x000000FF
67#define BCMA_CC_OTPP_ROW 0x0000FF00
68#define BCMA_CC_OTPP_ROW_SHIFT 8
69#define BCMA_CC_OTPP_READERR 0x10000000
70#define BCMA_CC_OTPP_VALUE 0x20000000
71#define BCMA_CC_OTPP_READ 0x40000000
72#define BCMA_CC_OTPP_START 0x80000000
73#define BCMA_CC_OTPP_BUSY 0x80000000
74#define BCMA_CC_IRQSTAT 0x0020
75#define BCMA_CC_IRQMASK 0x0024
76#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
77#define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
78#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
79#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
80#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
81#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
82#define BCMA_CC_JCMD_START 0x80000000
83#define BCMA_CC_JCMD_BUSY 0x80000000
84#define BCMA_CC_JCMD_PAUSE 0x40000000
85#define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
86#define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
87#define BCMA_CC_JCMD0_ACC_DR 0x00001000
88#define BCMA_CC_JCMD0_ACC_IR 0x00002000
89#define BCMA_CC_JCMD0_ACC_RESET 0x00003000
90#define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
91#define BCMA_CC_JCMD0_ACC_PDR 0x00005000
92#define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
93#define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
94#define BCMA_CC_JCMD_ACC_IRDR 0x00000000
95#define BCMA_CC_JCMD_ACC_DR 0x00010000
96#define BCMA_CC_JCMD_ACC_IR 0x00020000
97#define BCMA_CC_JCMD_ACC_RESET 0x00030000
98#define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
99#define BCMA_CC_JCMD_ACC_PDR 0x00050000
100#define BCMA_CC_JCMD_IRW_MASK 0x00001F00
101#define BCMA_CC_JCMD_IRW_SHIFT 8
102#define BCMA_CC_JCMD_DRW_MASK 0x0000003F
103#define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
104#define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
105#define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
106#define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
107#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
108#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
109#define BCMA_CC_FLASHCTL 0x0040
110#define BCMA_CC_FLASHCTL_START 0x80000000
111#define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
112#define BCMA_CC_FLASHADDR 0x0044
113#define BCMA_CC_FLASHDATA 0x0048
114#define BCMA_CC_BCAST_ADDR 0x0050
115#define BCMA_CC_BCAST_DATA 0x0054
116#define BCMA_CC_GPIOIN 0x0060
117#define BCMA_CC_GPIOOUT 0x0064
118#define BCMA_CC_GPIOOUTEN 0x0068
119#define BCMA_CC_GPIOCTL 0x006C
120#define BCMA_CC_GPIOPOL 0x0070
121#define BCMA_CC_GPIOIRQ 0x0074
122#define BCMA_CC_WATCHDOG 0x0080
123#define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
124#define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
125#define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
126#define BCMA_CC_CLOCK_N 0x0090
127#define BCMA_CC_CLOCK_SB 0x0094
128#define BCMA_CC_CLOCK_PCI 0x0098
129#define BCMA_CC_CLOCK_M2 0x009C
130#define BCMA_CC_CLOCK_MIPS 0x00A0
131#define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
132#define BCMA_CC_CLKDIV_SFLASH 0x0F000000
133#define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
134#define BCMA_CC_CLKDIV_OTP 0x000F0000
135#define BCMA_CC_CLKDIV_OTP_SHIFT 16
136#define BCMA_CC_CLKDIV_JTAG 0x00000F00
137#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
138#define BCMA_CC_CLKDIV_UART 0x000000FF
139#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
140#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
141#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
142#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
143#define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
144#define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
145#define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
146#define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
147#define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
148#define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
149#define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
150#define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
151#define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
152#define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
153#define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
154#define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
155#define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
156#define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
157#define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
158#define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
159#define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
160#define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
161#define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
162#define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
163#define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
164#define BCMA_CC_EROM 0x00FC
165#define BCMA_CC_PCMCIA_CFG 0x0100
166#define BCMA_CC_PCMCIA_MEMWAIT 0x0104
167#define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
168#define BCMA_CC_PCMCIA_IOWAIT 0x010C
169#define BCMA_CC_IDE_CFG 0x0110
170#define BCMA_CC_IDE_MEMWAIT 0x0114
171#define BCMA_CC_IDE_ATTRWAIT 0x0118
172#define BCMA_CC_IDE_IOWAIT 0x011C
173#define BCMA_CC_PROG_CFG 0x0120
174#define BCMA_CC_PROG_WAITCNT 0x0124
175#define BCMA_CC_FLASH_CFG 0x0128
176#define BCMA_CC_FLASH_WAITCNT 0x012C
177#define BCMA_CC_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
178#define BCMA_CC_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
179#define BCMA_CC_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
180#define BCMA_CC_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
181#define BCMA_CC_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
182#define BCMA_CC_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
183#define BCMA_CC_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
184#define BCMA_CC_CLKCTLST_HAVEHT 0x00010000 /* HT available */
185#define BCMA_CC_CLKCTLST_HAVEALP 0x00020000 /* APL available */
186#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
187#define BCMA_CC_UART0_DATA 0x0300
188#define BCMA_CC_UART0_IMR 0x0304
189#define BCMA_CC_UART0_FCR 0x0308
190#define BCMA_CC_UART0_LCR 0x030C
191#define BCMA_CC_UART0_MCR 0x0310
192#define BCMA_CC_UART0_LSR 0x0314
193#define BCMA_CC_UART0_MSR 0x0318
194#define BCMA_CC_UART0_SCRATCH 0x031C
195#define BCMA_CC_UART1_DATA 0x0400
196#define BCMA_CC_UART1_IMR 0x0404
197#define BCMA_CC_UART1_FCR 0x0408
198#define BCMA_CC_UART1_LCR 0x040C
199#define BCMA_CC_UART1_MCR 0x0410
200#define BCMA_CC_UART1_LSR 0x0414
201#define BCMA_CC_UART1_MSR 0x0418
202#define BCMA_CC_UART1_SCRATCH 0x041C
203/* PMU registers (rev >= 20) */
204#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
205#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
206#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
207#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
208#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
209#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
210#define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
211#define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
212#define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
213#define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
214#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
215#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
216#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
217#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
218#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
219#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
220#define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
221#define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
222#define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
223#define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
224#define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
225#define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
226#define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
227#define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
228#define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
229#define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
230#define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
231#define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
232#define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
233#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
234#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
235#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
236#define BCMA_CC_CHIPCTL_ADDR 0x0650
237#define BCMA_CC_CHIPCTL_DATA 0x0654
238#define BCMA_CC_REGCTL_ADDR 0x0658
239#define BCMA_CC_REGCTL_DATA 0x065C
240#define BCMA_CC_PLLCTL_ADDR 0x0660
241#define BCMA_CC_PLLCTL_DATA 0x0664
242
243/* Data for the PMU, if available.
244 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
245 */
246struct bcma_chipcommon_pmu {
247 u8 rev; /* PMU revision */
248 u32 crystalfreq; /* The active crystal frequency (in kHz) */
249};
250
251struct bcma_drv_cc {
252 struct bcma_device *core;
253 u32 status;
254 u32 capabilities;
255 u32 capabilities_ext;
256 /* Fast Powerup Delay constant */
257 u16 fast_pwrup_delay;
258 struct bcma_chipcommon_pmu pmu;
259};
260
261/* Register access */
262#define bcma_cc_read32(cc, offset) \
263 bcma_read32((cc)->core, offset)
264#define bcma_cc_write32(cc, offset, val) \
265 bcma_write32((cc)->core, offset, val)
266
267#define bcma_cc_mask32(cc, offset, mask) \
268 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
269#define bcma_cc_set32(cc, offset, set) \
270 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
271#define bcma_cc_maskset32(cc, offset, mask, set) \
272 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
273
274extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
275
276extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
277extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
278
279extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
280 u32 ticks);
281
282void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
283
284u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
285
286/* Chipcommon GPIO pin access. */
287u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
288u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
289u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
290u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
291u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
292u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
293
294/* PMU support */
295extern void bcma_pmu_init(struct bcma_drv_cc *cc);
296
297#endif /* LINUX_BCMA_DRIVER_CC_H_ */
diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h
new file mode 100644
index 000000000000..b7e191cf00ec
--- /dev/null
+++ b/include/linux/bcma/bcma_driver_pci.h
@@ -0,0 +1,89 @@
1#ifndef LINUX_BCMA_DRIVER_PCI_H_
2#define LINUX_BCMA_DRIVER_PCI_H_
3
4#include <linux/types.h>
5
6struct pci_dev;
7
8/** PCI core registers. **/
9#define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */
10#define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
11#define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
12#define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
13#define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
14#define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */
15#define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
16#define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
17#define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
18#define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
19#define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
20#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
21#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
22#define BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */
23#define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */
24#define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */
25#define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
26#define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
27#define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */
28#define BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */
29#define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */
30#define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */
31#define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */
32#define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */
33#define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */
34#define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */
35#define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
36#define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
37#define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
38#define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
39#define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
40#define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
41#define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
42#define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
43#define BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
44#define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF
45#define BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
46#define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */
47#define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */
48#define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */
49#define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */
50#define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
51#define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000
52#define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
53#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
54#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
55#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
56#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
57#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
58#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
59#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
60#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
61
62/* SBtoPCIx */
63#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
64#define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001
65#define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002
66#define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003
67#define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
68#define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */
69#define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
70#define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
71#define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */
72#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
73#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
74
75/* PCIcore specific boardflags */
76#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
77
78struct bcma_drv_pci {
79 struct bcma_device *core;
80 u8 setup_done:1;
81};
82
83/* Register access */
84#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
85#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
86
87extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
88
89#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
diff --git a/include/linux/bcma/bcma_regs.h b/include/linux/bcma/bcma_regs.h
new file mode 100644
index 000000000000..f82d88a960ce
--- /dev/null
+++ b/include/linux/bcma/bcma_regs.h
@@ -0,0 +1,34 @@
1#ifndef LINUX_BCMA_REGS_H_
2#define LINUX_BCMA_REGS_H_
3
4/* Agent registers (common for every core) */
5#define BCMA_IOCTL 0x0408
6#define BCMA_IOCTL_CLK 0x0001
7#define BCMA_IOCTL_FGC 0x0002
8#define BCMA_IOCTL_CORE_BITS 0x3FFC
9#define BCMA_IOCTL_PME_EN 0x4000
10#define BCMA_IOCTL_BIST_EN 0x8000
11#define BCMA_RESET_CTL 0x0800
12#define BCMA_RESET_CTL_RESET 0x0001
13
14/* BCMA PCI config space registers. */
15#define BCMA_PCI_PMCSR 0x44
16#define BCMA_PCI_PE 0x100
17#define BCMA_PCI_BAR0_WIN 0x80 /* Backplane address space 0 */
18#define BCMA_PCI_BAR1_WIN 0x84 /* Backplane address space 1 */
19#define BCMA_PCI_SPROMCTL 0x88 /* SPROM control */
20#define BCMA_PCI_SPROMCTL_WE 0x10 /* SPROM write enable */
21#define BCMA_PCI_BAR1_CONTROL 0x8c /* Address space 1 burst control */
22#define BCMA_PCI_IRQS 0x90 /* PCI interrupts */
23#define BCMA_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */
24#define BCMA_PCI_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */
25#define BCMA_PCI_BAR0_WIN2 0xAC
26#define BCMA_PCI_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */
27#define BCMA_PCI_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */
28#define BCMA_PCI_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */
29#define BCMA_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
30#define BCMA_PCI_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
31#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
32#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
33
34#endif /* LINUX_BCMA_REGS_H_ */
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 48c007dae476..ae28e93fd072 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -382,6 +382,23 @@ struct ssb_device_id {
382#define SSB_ANY_ID 0xFFFF 382#define SSB_ANY_ID 0xFFFF
383#define SSB_ANY_REV 0xFF 383#define SSB_ANY_REV 0xFF
384 384
385/* Broadcom's specific AMBA core, see drivers/bcma/ */
386struct bcma_device_id {
387 __u16 manuf;
388 __u16 id;
389 __u8 rev;
390 __u8 class;
391};
392#define BCMA_CORE(_manuf, _id, _rev, _class) \
393 { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
394#define BCMA_CORETABLE_END \
395 { 0, },
396
397#define BCMA_ANY_MANUF 0xFFFF
398#define BCMA_ANY_ID 0xFFFF
399#define BCMA_ANY_REV 0xFF
400#define BCMA_ANY_CLASS 0xFF
401
385struct virtio_device_id { 402struct virtio_device_id {
386 __u32 device; 403 __u32 device;
387 __u32 vendor; 404 __u32 vendor;
diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index 88f3f07205f8..e26e2fb462d4 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -702,6 +702,24 @@ static int do_ssb_entry(const char *filename,
702 return 1; 702 return 1;
703} 703}
704 704
705/* Looks like: bcma:mNidNrevNclN. */
706static int do_bcma_entry(const char *filename,
707 struct bcma_device_id *id, char *alias)
708{
709 id->manuf = TO_NATIVE(id->manuf);
710 id->id = TO_NATIVE(id->id);
711 id->rev = TO_NATIVE(id->rev);
712 id->class = TO_NATIVE(id->class);
713
714 strcpy(alias, "bcma:");
715 ADD(alias, "m", id->manuf != BCMA_ANY_MANUF, id->manuf);
716 ADD(alias, "id", id->id != BCMA_ANY_ID, id->id);
717 ADD(alias, "rev", id->rev != BCMA_ANY_REV, id->rev);
718 ADD(alias, "cl", id->class != BCMA_ANY_CLASS, id->class);
719 add_wildcard(alias);
720 return 1;
721}
722
705/* Looks like: virtio:dNvN */ 723/* Looks like: virtio:dNvN */
706static int do_virtio_entry(const char *filename, struct virtio_device_id *id, 724static int do_virtio_entry(const char *filename, struct virtio_device_id *id,
707 char *alias) 725 char *alias)
@@ -968,6 +986,10 @@ void handle_moddevtable(struct module *mod, struct elf_info *info,
968 do_table(symval, sym->st_size, 986 do_table(symval, sym->st_size,
969 sizeof(struct ssb_device_id), "ssb", 987 sizeof(struct ssb_device_id), "ssb",
970 do_ssb_entry, mod); 988 do_ssb_entry, mod);
989 else if (sym_is(symname, "__mod_bcma_device_table"))
990 do_table(symval, sym->st_size,
991 sizeof(struct bcma_device_id), "bcma",
992 do_bcma_entry, mod);
971 else if (sym_is(symname, "__mod_virtio_device_table")) 993 else if (sym_is(symname, "__mod_virtio_device_table"))
972 do_table(symval, sym->st_size, 994 do_table(symval, sym->st_size,
973 sizeof(struct virtio_device_id), "virtio", 995 sizeof(struct virtio_device_id), "virtio",
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 06:59:25 -0500