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authorRalf Baechle <ralf@linux-mips.org>2008-07-16 11:12:25 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-20 09:38:18 -0400
commit73b4390fb23456964201abda79f1210fe337d01a (patch)
treebc613dfa0a3926bd889025cebbc28ae034b8c854
parent36a0a3cd45b49ceff78ac28efef1cbeec413d8c2 (diff)
[MIPS] Routerboard 532: Support for base system
Signed-off-by: Phil Sutter <n0-1@freewrt.org> Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/Kconfig20
-rw-r--r--arch/mips/Makefile7
-rw-r--r--arch/mips/configs/rb532_defconfig1314
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-rc32434.c69
-rw-r--r--arch/mips/pci/ops-rc32434.c207
-rw-r--r--arch/mips/pci/pci-rc32434.c221
-rw-r--r--arch/mips/rb532/Makefile7
-rw-r--r--arch/mips/rb532/devices.c331
-rw-r--r--arch/mips/rb532/gpio.c220
-rw-r--r--arch/mips/rb532/irq.c209
-rw-r--r--arch/mips/rb532/prom.c158
-rw-r--r--arch/mips/rb532/serial.c53
-rw-r--r--arch/mips/rb532/setup.c79
-rw-r--r--arch/mips/rb532/time.c67
-rw-r--r--include/asm-mips/bootinfo.h6
-rw-r--r--include/asm-mips/mach-rc32434/cpu-feature-overrides.h81
-rw-r--r--include/asm-mips/mach-rc32434/ddr.h141
-rw-r--r--include/asm-mips/mach-rc32434/dma.h103
-rw-r--r--include/asm-mips/mach-rc32434/dma_v.h52
-rw-r--r--include/asm-mips/mach-rc32434/eth.h220
-rw-r--r--include/asm-mips/mach-rc32434/gpio.h126
-rw-r--r--include/asm-mips/mach-rc32434/integ.h59
-rw-r--r--include/asm-mips/mach-rc32434/irq.h8
-rw-r--r--include/asm-mips/mach-rc32434/pci.h481
-rw-r--r--include/asm-mips/mach-rc32434/prom.h44
-rw-r--r--include/asm-mips/mach-rc32434/rb.h81
-rw-r--r--include/asm-mips/mach-rc32434/rc32434.h61
-rw-r--r--include/asm-mips/mach-rc32434/timer.h65
-rw-r--r--include/asm-mips/mach-rc32434/war.h25
30 files changed, 4515 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 30edc395dce7..b9c754f4070c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -558,6 +558,24 @@ config MACH_TX39XX
558config MACH_TX49XX 558config MACH_TX49XX
559 bool "Toshiba TX49 series based machines" 559 bool "Toshiba TX49 series based machines"
560 560
561config MIKROTIK_RB532
562 bool "Mikrotik RB532 boards"
563 select CEVT_R4K
564 select CSRC_R4K
565 select DMA_NONCOHERENT
566 select GENERIC_HARDIRQS_NO__DO_IRQ
567 select HW_HAS_PCI
568 select IRQ_CPU
569 select SYS_HAS_CPU_MIPS32_R1
570 select SYS_SUPPORTS_32BIT_KERNEL
571 select SYS_SUPPORTS_LITTLE_ENDIAN
572 select SWAP_IO_SPACE
573 select BOOT_RAW
574 select GENERIC_GPIO
575 help
576 Support the Mikrotik(tm) RouterBoard 532 series,
577 based on the IDT RC32434 SoC.
578
561config WR_PPMC 579config WR_PPMC
562 bool "Wind River PPMC board" 580 bool "Wind River PPMC board"
563 select CEVT_R4K 581 select CEVT_R4K
@@ -899,7 +917,7 @@ config BOOT_ELF32
899 917
900config MIPS_L1_CACHE_SHIFT 918config MIPS_L1_CACHE_SHIFT
901 int 919 int
902 default "4" if MACH_DECSTATION 920 default "4" if MACH_DECSTATION || MIKROTIK_RB532
903 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM 921 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
904 default "4" if PMC_MSP4200_EVAL 922 default "4" if PMC_MSP4200_EVAL
905 default "5" 923 default "5"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 356453322b49..9aab51caf16a 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -560,6 +560,13 @@ load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000
560core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ 560core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/
561 561
562# 562#
563# Routerboard 532 board
564#
565core-$(CONFIG_MIKROTIK_RB532) += arch/mips/rb532/
566cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434
567load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
568
569#
563# Toshiba RBTX4927 board or 570# Toshiba RBTX4927 board or
564# Toshiba RBTX4937 board 571# Toshiba RBTX4937 board
565# 572#
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
new file mode 100644
index 000000000000..f28dc32974e5
--- /dev/null
+++ b/arch/mips/configs/rb532_defconfig
@@ -0,0 +1,1314 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25
4# Mon Apr 28 12:24:17 2008
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set
19# CONFIG_MIPS_ATLAS is not set
20# CONFIG_MIPS_MALTA is not set
21# CONFIG_MIPS_SEAD is not set
22# CONFIG_MIPS_SIM is not set
23# CONFIG_MARKEINS is not set
24# CONFIG_MACH_VR41XX is not set
25# CONFIG_PNX8550_JBS is not set
26# CONFIG_PNX8550_STB810 is not set
27# CONFIG_PMC_MSP is not set
28# CONFIG_PMC_YOSEMITE is not set
29# CONFIG_SGI_IP22 is not set
30# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP28 is not set
32# CONFIG_SGI_IP32 is not set
33# CONFIG_SIBYTE_CRHINE is not set
34# CONFIG_SIBYTE_CARMEL is not set
35# CONFIG_SIBYTE_CRHONE is not set
36# CONFIG_SIBYTE_RHONE is not set
37# CONFIG_SIBYTE_SWARM is not set
38# CONFIG_SIBYTE_LITTLESUR is not set
39# CONFIG_SIBYTE_SENTOSA is not set
40# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set
42# CONFIG_TOSHIBA_JMR3927 is not set
43CONFIG_MIKROTIK_RB532=y
44# CONFIG_TOSHIBA_RBTX4927 is not set
45# CONFIG_TOSHIBA_RBTX4938 is not set
46# CONFIG_WR_PPMC is not set
47CONFIG_RWSEM_GENERIC_SPINLOCK=y
48# CONFIG_ARCH_HAS_ILOG2_U32 is not set
49# CONFIG_ARCH_HAS_ILOG2_U64 is not set
50CONFIG_ARCH_SUPPORTS_OPROFILE=y
51CONFIG_GENERIC_FIND_NEXT_BIT=y
52CONFIG_GENERIC_HWEIGHT=y
53CONFIG_GENERIC_CALIBRATE_DELAY=y
54CONFIG_GENERIC_CLOCKEVENTS=y
55CONFIG_GENERIC_TIME=y
56CONFIG_GENERIC_CMOS_UPDATE=y
57CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
58CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
59CONFIG_BOOT_RAW=y
60CONFIG_CEVT_R4K=y
61CONFIG_CSRC_R4K=y
62CONFIG_DMA_NONCOHERENT=y
63CONFIG_DMA_NEED_PCI_MAP_STATE=y
64# CONFIG_HOTPLUG_CPU is not set
65# CONFIG_NO_IOPORT is not set
66CONFIG_GENERIC_GPIO=y
67# CONFIG_CPU_BIG_ENDIAN is not set
68CONFIG_CPU_LITTLE_ENDIAN=y
69CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
70CONFIG_IRQ_CPU=y
71CONFIG_SWAP_IO_SPACE=y
72CONFIG_MIPS_L1_CACHE_SHIFT=4
73
74#
75# CPU selection
76#
77# CONFIG_CPU_LOONGSON2 is not set
78CONFIG_CPU_MIPS32_R1=y
79# CONFIG_CPU_MIPS32_R2 is not set
80# CONFIG_CPU_MIPS64_R1 is not set
81# CONFIG_CPU_MIPS64_R2 is not set
82# CONFIG_CPU_R3000 is not set
83# CONFIG_CPU_TX39XX is not set
84# CONFIG_CPU_VR41XX is not set
85# CONFIG_CPU_R4300 is not set
86# CONFIG_CPU_R4X00 is not set
87# CONFIG_CPU_TX49XX is not set
88# CONFIG_CPU_R5000 is not set
89# CONFIG_CPU_R5432 is not set
90# CONFIG_CPU_R6000 is not set
91# CONFIG_CPU_NEVADA is not set
92# CONFIG_CPU_R8000 is not set
93# CONFIG_CPU_R10000 is not set
94# CONFIG_CPU_RM7000 is not set
95# CONFIG_CPU_RM9000 is not set
96# CONFIG_CPU_SB1 is not set
97CONFIG_SYS_HAS_CPU_MIPS32_R1=y
98CONFIG_CPU_MIPS32=y
99CONFIG_CPU_MIPSR1=y
100CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
101CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
102
103#
104# Kernel type
105#
106CONFIG_32BIT=y
107# CONFIG_64BIT is not set
108CONFIG_PAGE_SIZE_4KB=y
109# CONFIG_PAGE_SIZE_8KB is not set
110# CONFIG_PAGE_SIZE_16KB is not set
111# CONFIG_PAGE_SIZE_64KB is not set
112CONFIG_CPU_HAS_PREFETCH=y
113CONFIG_MIPS_MT_DISABLED=y
114# CONFIG_MIPS_MT_SMP is not set
115# CONFIG_MIPS_MT_SMTC is not set
116CONFIG_CPU_HAS_LLSC=y
117CONFIG_CPU_HAS_SYNC=y
118CONFIG_GENERIC_HARDIRQS=y
119CONFIG_GENERIC_IRQ_PROBE=y
120CONFIG_CPU_SUPPORTS_HIGHMEM=y
121CONFIG_ARCH_FLATMEM_ENABLE=y
122CONFIG_ARCH_POPULATES_NODE_MAP=y
123CONFIG_SELECT_MEMORY_MODEL=y
124CONFIG_FLATMEM_MANUAL=y
125# CONFIG_DISCONTIGMEM_MANUAL is not set
126# CONFIG_SPARSEMEM_MANUAL is not set
127CONFIG_FLATMEM=y
128CONFIG_FLAT_NODE_MEM_MAP=y
129# CONFIG_SPARSEMEM_STATIC is not set
130# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
131CONFIG_SPLIT_PTLOCK_CPUS=4
132# CONFIG_RESOURCES_64BIT is not set
133CONFIG_ZONE_DMA_FLAG=0
134CONFIG_VIRT_TO_BUS=y
135CONFIG_TICK_ONESHOT=y
136CONFIG_NO_HZ=y
137CONFIG_HIGH_RES_TIMERS=y
138CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
139# CONFIG_HZ_48 is not set
140CONFIG_HZ_100=y
141# CONFIG_HZ_128 is not set
142# CONFIG_HZ_250 is not set
143# CONFIG_HZ_256 is not set
144# CONFIG_HZ_1000 is not set
145# CONFIG_HZ_1024 is not set
146CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
147CONFIG_HZ=100
148CONFIG_PREEMPT_NONE=y
149# CONFIG_PREEMPT_VOLUNTARY is not set
150# CONFIG_PREEMPT is not set
151# CONFIG_KEXEC is not set
152# CONFIG_SECCOMP is not set
153CONFIG_LOCKDEP_SUPPORT=y
154CONFIG_STACKTRACE_SUPPORT=y
155CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
156
157#
158# General setup
159#
160CONFIG_EXPERIMENTAL=y
161CONFIG_BROKEN_ON_SMP=y
162CONFIG_INIT_ENV_ARG_LIMIT=32
163CONFIG_LOCALVERSION=""
164# CONFIG_LOCALVERSION_AUTO is not set
165CONFIG_SWAP=y
166CONFIG_SYSVIPC=y
167CONFIG_SYSVIPC_SYSCTL=y
168# CONFIG_POSIX_MQUEUE is not set
169CONFIG_BSD_PROCESS_ACCT=y
170# CONFIG_BSD_PROCESS_ACCT_V3 is not set
171# CONFIG_TASKSTATS is not set
172# CONFIG_AUDIT is not set
173CONFIG_IKCONFIG=y
174CONFIG_IKCONFIG_PROC=y
175CONFIG_LOG_BUF_SHIFT=14
176# CONFIG_CGROUPS is not set
177CONFIG_GROUP_SCHED=y
178CONFIG_FAIR_GROUP_SCHED=y
179# CONFIG_RT_GROUP_SCHED is not set
180CONFIG_USER_SCHED=y
181# CONFIG_CGROUP_SCHED is not set
182CONFIG_SYSFS_DEPRECATED=y
183CONFIG_SYSFS_DEPRECATED_V2=y
184# CONFIG_RELAY is not set
185# CONFIG_NAMESPACES is not set
186CONFIG_BLK_DEV_INITRD=y
187CONFIG_INITRAMFS_SOURCE=""
188CONFIG_CC_OPTIMIZE_FOR_SIZE=y
189CONFIG_SYSCTL=y
190CONFIG_EMBEDDED=y
191CONFIG_SYSCTL_SYSCALL=y
192# CONFIG_KALLSYMS is not set
193CONFIG_HOTPLUG=y
194CONFIG_PRINTK=y
195CONFIG_BUG=y
196# CONFIG_ELF_CORE is not set
197CONFIG_COMPAT_BRK=y
198CONFIG_BASE_FULL=y
199CONFIG_FUTEX=y
200CONFIG_ANON_INODES=y
201CONFIG_EPOLL=y
202CONFIG_SIGNALFD=y
203CONFIG_TIMERFD=y
204CONFIG_EVENTFD=y
205CONFIG_SHMEM=y
206# CONFIG_VM_EVENT_COUNTERS is not set
207CONFIG_SLAB=y
208# CONFIG_SLUB is not set
209# CONFIG_SLOB is not set
210# CONFIG_PROFILING is not set
211# CONFIG_MARKERS is not set
212CONFIG_HAVE_OPROFILE=y
213# CONFIG_HAVE_KPROBES is not set
214# CONFIG_HAVE_KRETPROBES is not set
215CONFIG_PROC_PAGE_MONITOR=y
216CONFIG_SLABINFO=y
217CONFIG_RT_MUTEXES=y
218# CONFIG_TINY_SHMEM is not set
219CONFIG_BASE_SMALL=0
220CONFIG_MODULES=y
221CONFIG_MODULE_UNLOAD=y
222# CONFIG_MODULE_FORCE_UNLOAD is not set
223# CONFIG_MODVERSIONS is not set
224# CONFIG_MODULE_SRCVERSION_ALL is not set
225# CONFIG_KMOD is not set
226CONFIG_BLOCK=y
227# CONFIG_LBD is not set
228# CONFIG_BLK_DEV_IO_TRACE is not set
229# CONFIG_LSF is not set
230# CONFIG_BLK_DEV_BSG is not set
231
232#
233# IO Schedulers
234#
235CONFIG_IOSCHED_NOOP=y
236# CONFIG_IOSCHED_AS is not set
237CONFIG_IOSCHED_DEADLINE=y
238# CONFIG_IOSCHED_CFQ is not set
239# CONFIG_DEFAULT_AS is not set
240CONFIG_DEFAULT_DEADLINE=y
241# CONFIG_DEFAULT_CFQ is not set
242# CONFIG_DEFAULT_NOOP is not set
243CONFIG_DEFAULT_IOSCHED="deadline"
244CONFIG_CLASSIC_RCU=y
245
246#
247# Bus options (PCI, PCMCIA, EISA, ISA, TC)
248#
249CONFIG_HW_HAS_PCI=y
250CONFIG_PCI=y
251CONFIG_PCI_DOMAINS=y
252# CONFIG_ARCH_SUPPORTS_MSI is not set
253CONFIG_PCI_LEGACY=y
254CONFIG_MMU=y
255# CONFIG_PCCARD is not set
256# CONFIG_HOTPLUG_PCI is not set
257
258#
259# Executable file formats
260#
261CONFIG_BINFMT_ELF=y
262# CONFIG_BINFMT_MISC is not set
263CONFIG_TRAD_SIGNALS=y
264
265#
266# Power management options
267#
268CONFIG_ARCH_SUSPEND_POSSIBLE=y
269# CONFIG_PM is not set
270
271#
272# Networking
273#
274CONFIG_NET=y
275
276#
277# Networking options
278#
279CONFIG_PACKET=y
280CONFIG_PACKET_MMAP=y
281CONFIG_UNIX=y
282# CONFIG_NET_KEY is not set
283CONFIG_INET=y
284CONFIG_IP_MULTICAST=y
285CONFIG_IP_ADVANCED_ROUTER=y
286CONFIG_ASK_IP_FIB_HASH=y
287# CONFIG_IP_FIB_TRIE is not set
288CONFIG_IP_FIB_HASH=y
289CONFIG_IP_MULTIPLE_TABLES=y
290CONFIG_IP_ROUTE_MULTIPATH=y
291CONFIG_IP_ROUTE_VERBOSE=y
292# CONFIG_IP_PNP is not set
293# CONFIG_NET_IPIP is not set
294# CONFIG_NET_IPGRE is not set
295# CONFIG_IP_MROUTE is not set
296CONFIG_ARPD=y
297CONFIG_SYN_COOKIES=y
298# CONFIG_INET_AH is not set
299# CONFIG_INET_ESP is not set
300# CONFIG_INET_IPCOMP is not set
301# CONFIG_INET_XFRM_TUNNEL is not set
302# CONFIG_INET_TUNNEL is not set
303# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
304# CONFIG_INET_XFRM_MODE_TUNNEL is not set
305# CONFIG_INET_XFRM_MODE_BEET is not set
306# CONFIG_INET_LRO is not set
307CONFIG_INET_DIAG=m
308CONFIG_INET_TCP_DIAG=m
309CONFIG_TCP_CONG_ADVANCED=y
310CONFIG_TCP_CONG_BIC=m
311CONFIG_TCP_CONG_CUBIC=m
312CONFIG_TCP_CONG_WESTWOOD=m
313CONFIG_TCP_CONG_HTCP=m
314CONFIG_TCP_CONG_HSTCP=m
315CONFIG_TCP_CONG_HYBLA=m
316CONFIG_TCP_CONG_VEGAS=y
317CONFIG_TCP_CONG_SCALABLE=m
318CONFIG_TCP_CONG_LP=m
319CONFIG_TCP_CONG_VENO=m
320CONFIG_TCP_CONG_YEAH=m
321CONFIG_TCP_CONG_ILLINOIS=m
322# CONFIG_DEFAULT_BIC is not set
323# CONFIG_DEFAULT_CUBIC is not set
324# CONFIG_DEFAULT_HTCP is not set
325CONFIG_DEFAULT_VEGAS=y
326# CONFIG_DEFAULT_WESTWOOD is not set
327# CONFIG_DEFAULT_RENO is not set
328CONFIG_DEFAULT_TCP_CONG="vegas"
329# CONFIG_TCP_MD5SIG is not set
330# CONFIG_IP_VS is not set
331# CONFIG_IPV6 is not set
332# CONFIG_NETWORK_SECMARK is not set
333CONFIG_NETFILTER=y
334# CONFIG_NETFILTER_DEBUG is not set
335CONFIG_NETFILTER_ADVANCED=y
336# CONFIG_BRIDGE_NETFILTER is not set
337
338#
339# Core Netfilter Configuration
340#
341# CONFIG_NETFILTER_NETLINK_QUEUE is not set
342# CONFIG_NETFILTER_NETLINK_LOG is not set
343CONFIG_NF_CONNTRACK=y
344CONFIG_NF_CT_ACCT=y
345CONFIG_NF_CONNTRACK_MARK=y
346# CONFIG_NF_CONNTRACK_EVENTS is not set
347# CONFIG_NF_CT_PROTO_DCCP is not set
348# CONFIG_NF_CT_PROTO_SCTP is not set
349# CONFIG_NF_CT_PROTO_UDPLITE is not set
350# CONFIG_NF_CONNTRACK_AMANDA is not set
351CONFIG_NF_CONNTRACK_FTP=m
352# CONFIG_NF_CONNTRACK_H323 is not set
353CONFIG_NF_CONNTRACK_IRC=m
354# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
355# CONFIG_NF_CONNTRACK_PPTP is not set
356# CONFIG_NF_CONNTRACK_SANE is not set
357# CONFIG_NF_CONNTRACK_SIP is not set
358CONFIG_NF_CONNTRACK_TFTP=m
359# CONFIG_NF_CT_NETLINK is not set
360CONFIG_NETFILTER_XTABLES=y
361# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
362# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
363# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
364# CONFIG_NETFILTER_XT_TARGET_MARK is not set
365CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
366CONFIG_NETFILTER_XT_TARGET_NFLOG=m
367# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
368# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
369CONFIG_NETFILTER_XT_TARGET_TRACE=m
370# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
371# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
372CONFIG_NETFILTER_XT_MATCH_COMMENT=m
373# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
374CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
375# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
376# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
377CONFIG_NETFILTER_XT_MATCH_DCCP=m
378# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
379# CONFIG_NETFILTER_XT_MATCH_ESP is not set
380# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
381# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
382# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
383CONFIG_NETFILTER_XT_MATCH_LIMIT=y
384# CONFIG_NETFILTER_XT_MATCH_MAC is not set
385# CONFIG_NETFILTER_XT_MATCH_MARK is not set
386# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
387CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
388# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
389# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
390# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
391CONFIG_NETFILTER_XT_MATCH_REALM=m
392CONFIG_NETFILTER_XT_MATCH_SCTP=m
393CONFIG_NETFILTER_XT_MATCH_STATE=y
394# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
395# CONFIG_NETFILTER_XT_MATCH_STRING is not set
396# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
397# CONFIG_NETFILTER_XT_MATCH_TIME is not set
398CONFIG_NETFILTER_XT_MATCH_U32=m
399CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
400
401#
402# IP: Netfilter Configuration
403#
404CONFIG_NF_CONNTRACK_IPV4=y
405CONFIG_NF_CONNTRACK_PROC_COMPAT=y
406# CONFIG_IP_NF_QUEUE is not set
407CONFIG_IP_NF_IPTABLES=y
408# CONFIG_IP_NF_MATCH_RECENT is not set
409# CONFIG_IP_NF_MATCH_ECN is not set
410# CONFIG_IP_NF_MATCH_AH is not set
411# CONFIG_IP_NF_MATCH_TTL is not set
412CONFIG_IP_NF_MATCH_ADDRTYPE=m
413CONFIG_IP_NF_FILTER=y
414CONFIG_IP_NF_TARGET_REJECT=y
415# CONFIG_IP_NF_TARGET_LOG is not set
416# CONFIG_IP_NF_TARGET_ULOG is not set
417CONFIG_NF_NAT=y
418CONFIG_NF_NAT_NEEDED=y
419CONFIG_IP_NF_TARGET_MASQUERADE=y
420# CONFIG_IP_NF_TARGET_REDIRECT is not set
421# CONFIG_IP_NF_TARGET_NETMAP is not set
422# CONFIG_NF_NAT_SNMP_BASIC is not set
423CONFIG_NF_NAT_FTP=m
424CONFIG_NF_NAT_IRC=m
425CONFIG_NF_NAT_TFTP=m
426# CONFIG_NF_NAT_AMANDA is not set
427# CONFIG_NF_NAT_PPTP is not set
428# CONFIG_NF_NAT_H323 is not set
429# CONFIG_NF_NAT_SIP is not set
430CONFIG_IP_NF_MANGLE=y
431# CONFIG_IP_NF_TARGET_ECN is not set
432# CONFIG_IP_NF_TARGET_TTL is not set
433# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
434CONFIG_IP_NF_RAW=m
435# CONFIG_IP_NF_ARPTABLES is not set
436# CONFIG_IP_DCCP is not set
437# CONFIG_IP_SCTP is not set
438# CONFIG_TIPC is not set
439# CONFIG_ATM is not set
440CONFIG_BRIDGE=y
441CONFIG_VLAN_8021Q=y
442# CONFIG_DECNET is not set
443CONFIG_LLC=y
444CONFIG_LLC2=m
445# CONFIG_IPX is not set
446# CONFIG_ATALK is not set
447# CONFIG_X25 is not set
448# CONFIG_LAPB is not set
449# CONFIG_ECONET is not set
450# CONFIG_WAN_ROUTER is not set
451CONFIG_NET_SCHED=y
452
453#
454# Queueing/Scheduling
455#
456CONFIG_NET_SCH_CBQ=m
457# CONFIG_NET_SCH_HTB is not set
458# CONFIG_NET_SCH_HFSC is not set
459CONFIG_NET_SCH_PRIO=m
460CONFIG_NET_SCH_RR=m
461# CONFIG_NET_SCH_RED is not set
462# CONFIG_NET_SCH_SFQ is not set
463# CONFIG_NET_SCH_TEQL is not set
464# CONFIG_NET_SCH_TBF is not set
465# CONFIG_NET_SCH_GRED is not set
466# CONFIG_NET_SCH_DSMARK is not set
467CONFIG_NET_SCH_NETEM=m
468# CONFIG_NET_SCH_INGRESS is not set
469
470#
471# Classification
472#
473CONFIG_NET_CLS=y
474CONFIG_NET_CLS_BASIC=m
475CONFIG_NET_CLS_TCINDEX=m
476CONFIG_NET_CLS_ROUTE4=m
477CONFIG_NET_CLS_ROUTE=y
478CONFIG_NET_CLS_FW=m
479CONFIG_NET_CLS_U32=m
480CONFIG_CLS_U32_PERF=y
481CONFIG_CLS_U32_MARK=y
482CONFIG_NET_CLS_RSVP=m
483CONFIG_NET_CLS_RSVP6=m
484# CONFIG_NET_CLS_FLOW is not set
485CONFIG_NET_EMATCH=y
486CONFIG_NET_EMATCH_STACK=32
487CONFIG_NET_EMATCH_CMP=m
488CONFIG_NET_EMATCH_NBYTE=m
489CONFIG_NET_EMATCH_U32=m
490CONFIG_NET_EMATCH_META=m
491CONFIG_NET_EMATCH_TEXT=m
492CONFIG_NET_CLS_ACT=y
493CONFIG_NET_ACT_POLICE=y
494CONFIG_NET_ACT_GACT=m
495CONFIG_GACT_PROB=y
496CONFIG_NET_ACT_MIRRED=m
497CONFIG_NET_ACT_IPT=m
498# CONFIG_NET_ACT_NAT is not set
499CONFIG_NET_ACT_PEDIT=m
500# CONFIG_NET_ACT_SIMP is not set
501CONFIG_NET_CLS_IND=y
502CONFIG_NET_SCH_FIFO=y
503
504#
505# Network testing
506#
507# CONFIG_NET_PKTGEN is not set
508CONFIG_HAMRADIO=y
509
510#
511# Packet Radio protocols
512#
513# CONFIG_AX25 is not set
514# CONFIG_CAN is not set
515# CONFIG_IRDA is not set
516# CONFIG_BT is not set
517# CONFIG_AF_RXRPC is not set
518CONFIG_FIB_RULES=y
519
520#
521# Wireless
522#
523# CONFIG_CFG80211 is not set
524CONFIG_WIRELESS_EXT=y
525# CONFIG_MAC80211 is not set
526# CONFIG_IEEE80211 is not set
527# CONFIG_RFKILL is not set
528# CONFIG_NET_9P is not set
529
530#
531# Device Drivers
532#
533
534#
535# Generic Driver Options
536#
537CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
538CONFIG_STANDALONE=y
539CONFIG_PREVENT_FIRMWARE_BUILD=y
540CONFIG_FW_LOADER=y
541# CONFIG_SYS_HYPERVISOR is not set
542# CONFIG_CONNECTOR is not set
543CONFIG_MTD=y
544# CONFIG_MTD_DEBUG is not set
545# CONFIG_MTD_CONCAT is not set
546CONFIG_MTD_PARTITIONS=y
547# CONFIG_MTD_REDBOOT_PARTS is not set
548# CONFIG_MTD_CMDLINE_PARTS is not set
549# CONFIG_MTD_AR7_PARTS is not set
550
551#
552# User Modules And Translation Layers
553#
554CONFIG_MTD_CHAR=y
555CONFIG_MTD_BLKDEVS=y
556CONFIG_MTD_BLOCK=y
557# CONFIG_FTL is not set
558# CONFIG_NFTL is not set
559# CONFIG_INFTL is not set
560# CONFIG_RFD_FTL is not set
561# CONFIG_SSFDC is not set
562# CONFIG_MTD_OOPS is not set
563
564#
565# RAM/ROM/Flash chip drivers
566#
567# CONFIG_MTD_CFI is not set
568# CONFIG_MTD_JEDECPROBE is not set
569CONFIG_MTD_MAP_BANK_WIDTH_1=y
570CONFIG_MTD_MAP_BANK_WIDTH_2=y
571CONFIG_MTD_MAP_BANK_WIDTH_4=y
572# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
573# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
574# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
575CONFIG_MTD_CFI_I1=y
576CONFIG_MTD_CFI_I2=y
577# CONFIG_MTD_CFI_I4 is not set
578# CONFIG_MTD_CFI_I8 is not set
579# CONFIG_MTD_RAM is not set
580# CONFIG_MTD_ROM is not set
581# CONFIG_MTD_ABSENT is not set
582
583#
584# Mapping drivers for chip access
585#
586# CONFIG_MTD_COMPLEX_MAPPINGS is not set
587# CONFIG_MTD_INTEL_VR_NOR is not set
588# CONFIG_MTD_PLATRAM is not set
589
590#
591# Self-contained MTD device drivers
592#
593# CONFIG_MTD_PMC551 is not set
594# CONFIG_MTD_SLRAM is not set
595# CONFIG_MTD_PHRAM is not set
596# CONFIG_MTD_MTDRAM is not set
597CONFIG_MTD_BLOCK2MTD=y
598
599#
600# Disk-On-Chip Device Drivers
601#
602# CONFIG_MTD_DOC2000 is not set
603# CONFIG_MTD_DOC2001 is not set
604# CONFIG_MTD_DOC2001PLUS is not set
605CONFIG_MTD_NAND=y
606CONFIG_MTD_NAND_VERIFY_WRITE=y
607# CONFIG_MTD_NAND_ECC_SMC is not set
608# CONFIG_MTD_NAND_MUSEUM_IDS is not set
609CONFIG_MTD_NAND_IDS=y
610# CONFIG_MTD_NAND_DISKONCHIP is not set
611# CONFIG_MTD_NAND_CAFE is not set
612# CONFIG_MTD_NAND_NANDSIM is not set
613CONFIG_MTD_NAND_PLATFORM=y
614# CONFIG_MTD_ONENAND is not set
615
616#
617# UBI - Unsorted block images
618#
619# CONFIG_MTD_UBI is not set
620# CONFIG_PARPORT is not set
621CONFIG_BLK_DEV=y
622# CONFIG_BLK_CPQ_DA is not set
623# CONFIG_BLK_CPQ_CISS_DA is not set
624# CONFIG_BLK_DEV_DAC960 is not set
625# CONFIG_BLK_DEV_UMEM is not set
626# CONFIG_BLK_DEV_COW_COMMON is not set
627# CONFIG_BLK_DEV_LOOP is not set
628# CONFIG_BLK_DEV_NBD is not set
629# CONFIG_BLK_DEV_SX8 is not set
630# CONFIG_BLK_DEV_RAM is not set
631# CONFIG_CDROM_PKTCDVD is not set
632# CONFIG_ATA_OVER_ETH is not set
633CONFIG_MISC_DEVICES=y
634# CONFIG_PHANTOM is not set
635# CONFIG_EEPROM_93CX6 is not set
636# CONFIG_SGI_IOC4 is not set
637# CONFIG_TIFM_CORE is not set
638# CONFIG_ENCLOSURE_SERVICES is not set
639CONFIG_HAVE_IDE=y
640# CONFIG_IDE is not set
641
642#
643# SCSI device support
644#
645# CONFIG_RAID_ATTRS is not set
646CONFIG_SCSI=y
647CONFIG_SCSI_DMA=y
648# CONFIG_SCSI_TGT is not set
649# CONFIG_SCSI_NETLINK is not set
650CONFIG_SCSI_PROC_FS=y
651
652#
653# SCSI support type (disk, tape, CD-ROM)
654#
655# CONFIG_BLK_DEV_SD is not set
656# CONFIG_CHR_DEV_ST is not set
657# CONFIG_CHR_DEV_OSST is not set
658# CONFIG_BLK_DEV_SR is not set
659# CONFIG_CHR_DEV_SG is not set
660# CONFIG_CHR_DEV_SCH is not set
661
662#
663# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
664#
665# CONFIG_SCSI_MULTI_LUN is not set
666# CONFIG_SCSI_CONSTANTS is not set
667# CONFIG_SCSI_LOGGING is not set
668# CONFIG_SCSI_SCAN_ASYNC is not set
669CONFIG_SCSI_WAIT_SCAN=m
670
671#
672# SCSI Transports
673#
674# CONFIG_SCSI_SPI_ATTRS is not set
675# CONFIG_SCSI_FC_ATTRS is not set
676# CONFIG_SCSI_ISCSI_ATTRS is not set
677# CONFIG_SCSI_SAS_LIBSAS is not set
678# CONFIG_SCSI_SRP_ATTRS is not set
679CONFIG_SCSI_LOWLEVEL=y
680# CONFIG_ISCSI_TCP is not set
681# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
682# CONFIG_SCSI_3W_9XXX is not set
683# CONFIG_SCSI_ACARD is not set
684# CONFIG_SCSI_AACRAID is not set
685# CONFIG_SCSI_AIC7XXX is not set
686# CONFIG_SCSI_AIC7XXX_OLD is not set
687# CONFIG_SCSI_AIC79XX is not set
688# CONFIG_SCSI_AIC94XX is not set
689# CONFIG_SCSI_DPT_I2O is not set
690# CONFIG_SCSI_ADVANSYS is not set
691# CONFIG_SCSI_ARCMSR is not set
692# CONFIG_MEGARAID_NEWGEN is not set
693# CONFIG_MEGARAID_LEGACY is not set
694# CONFIG_MEGARAID_SAS is not set
695# CONFIG_SCSI_HPTIOP is not set
696# CONFIG_SCSI_DMX3191D is not set
697# CONFIG_SCSI_FUTURE_DOMAIN is not set
698# CONFIG_SCSI_IPS is not set
699# CONFIG_SCSI_INITIO is not set
700# CONFIG_SCSI_INIA100 is not set
701# CONFIG_SCSI_MVSAS is not set
702# CONFIG_SCSI_STEX is not set
703# CONFIG_SCSI_SYM53C8XX_2 is not set
704# CONFIG_SCSI_IPR is not set
705# CONFIG_SCSI_QLOGIC_1280 is not set
706# CONFIG_SCSI_QLA_FC is not set
707# CONFIG_SCSI_QLA_ISCSI is not set
708# CONFIG_SCSI_LPFC is not set
709# CONFIG_SCSI_DC395x is not set
710# CONFIG_SCSI_DC390T is not set
711# CONFIG_SCSI_NSP32 is not set
712# CONFIG_SCSI_DEBUG is not set
713# CONFIG_SCSI_SRP is not set
714CONFIG_ATA=y
715# CONFIG_ATA_NONSTANDARD is not set
716# CONFIG_SATA_PMP is not set
717# CONFIG_SATA_AHCI is not set
718# CONFIG_SATA_SIL24 is not set
719CONFIG_ATA_SFF=y
720# CONFIG_SATA_SVW is not set
721# CONFIG_ATA_PIIX is not set
722# CONFIG_SATA_MV is not set
723# CONFIG_SATA_NV is not set
724# CONFIG_PDC_ADMA is not set
725# CONFIG_SATA_QSTOR is not set
726# CONFIG_SATA_PROMISE is not set
727# CONFIG_SATA_SX4 is not set
728# CONFIG_SATA_SIL is not set
729# CONFIG_SATA_SIS is not set
730# CONFIG_SATA_ULI is not set
731# CONFIG_SATA_VIA is not set
732# CONFIG_SATA_VITESSE is not set
733# CONFIG_SATA_INIC162X is not set
734# CONFIG_PATA_ALI is not set
735# CONFIG_PATA_AMD is not set
736# CONFIG_PATA_ARTOP is not set
737# CONFIG_PATA_ATIIXP is not set
738# CONFIG_PATA_CMD640_PCI is not set
739# CONFIG_PATA_CMD64X is not set
740# CONFIG_PATA_CS5520 is not set
741# CONFIG_PATA_CS5530 is not set
742# CONFIG_PATA_CYPRESS is not set
743# CONFIG_PATA_EFAR is not set
744# CONFIG_ATA_GENERIC is not set
745# CONFIG_PATA_HPT366 is not set
746# CONFIG_PATA_HPT37X is not set
747# CONFIG_PATA_HPT3X2N is not set
748# CONFIG_PATA_HPT3X3 is not set
749# CONFIG_PATA_IT821X is not set
750# CONFIG_PATA_IT8213 is not set
751# CONFIG_PATA_JMICRON is not set
752# CONFIG_PATA_TRIFLEX is not set
753# CONFIG_PATA_MARVELL is not set
754# CONFIG_PATA_MPIIX is not set
755# CONFIG_PATA_OLDPIIX is not set
756# CONFIG_PATA_NETCELL is not set
757# CONFIG_PATA_NINJA32 is not set
758# CONFIG_PATA_NS87410 is not set
759# CONFIG_PATA_NS87415 is not set
760# CONFIG_PATA_OPTI is not set
761# CONFIG_PATA_OPTIDMA is not set
762# CONFIG_PATA_PDC_OLD is not set
763# CONFIG_PATA_RADISYS is not set
764CONFIG_PATA_RB532=y
765# CONFIG_PATA_RZ1000 is not set
766# CONFIG_PATA_SC1200 is not set
767# CONFIG_PATA_SERVERWORKS is not set
768# CONFIG_PATA_PDC2027X is not set
769# CONFIG_PATA_SIL680 is not set
770# CONFIG_PATA_SIS is not set
771# CONFIG_PATA_VIA is not set
772# CONFIG_PATA_WINBOND is not set
773# CONFIG_PATA_PLATFORM is not set
774# CONFIG_MD is not set
775# CONFIG_FUSION is not set
776
777#
778# IEEE 1394 (FireWire) support
779#
780# CONFIG_FIREWIRE is not set
781# CONFIG_IEEE1394 is not set
782# CONFIG_I2O is not set
783CONFIG_NETDEVICES=y
784# CONFIG_NETDEVICES_MULTIQUEUE is not set
785CONFIG_IFB=m
786# CONFIG_DUMMY is not set
787# CONFIG_BONDING is not set
788# CONFIG_MACVLAN is not set
789# CONFIG_EQUALIZER is not set
790# CONFIG_TUN is not set
791# CONFIG_VETH is not set
792# CONFIG_ARCNET is not set
793# CONFIG_PHYLIB is not set
794CONFIG_NET_ETHERNET=y
795CONFIG_MII=y
796# CONFIG_AX88796 is not set
797CONFIG_KORINA=y
798# CONFIG_HAPPYMEAL is not set
799# CONFIG_SUNGEM is not set
800# CONFIG_CASSINI is not set
801# CONFIG_NET_VENDOR_3COM is not set
802# CONFIG_DM9000 is not set
803# CONFIG_NET_TULIP is not set
804# CONFIG_HP100 is not set
805# CONFIG_IBM_NEW_EMAC_ZMII is not set
806# CONFIG_IBM_NEW_EMAC_RGMII is not set
807# CONFIG_IBM_NEW_EMAC_TAH is not set
808# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
809CONFIG_NET_PCI=y
810# CONFIG_PCNET32 is not set
811# CONFIG_AMD8111_ETH is not set
812# CONFIG_ADAPTEC_STARFIRE is not set
813# CONFIG_B44 is not set
814# CONFIG_FORCEDETH is not set
815# CONFIG_TC35815 is not set
816# CONFIG_EEPRO100 is not set
817# CONFIG_E100 is not set
818# CONFIG_FEALNX is not set
819# CONFIG_NATSEMI is not set
820# CONFIG_NE2K_PCI is not set
821# CONFIG_8139CP is not set
822# CONFIG_8139TOO is not set
823# CONFIG_R6040 is not set
824# CONFIG_SIS900 is not set
825# CONFIG_EPIC100 is not set
826# CONFIG_SUNDANCE is not set
827# CONFIG_TLAN is not set
828CONFIG_VIA_RHINE=y
829# CONFIG_VIA_RHINE_MMIO is not set
830CONFIG_VIA_RHINE_NAPI=y
831# CONFIG_SC92031 is not set
832# CONFIG_NETDEV_1000 is not set
833# CONFIG_NETDEV_10000 is not set
834# CONFIG_TR is not set
835
836#
837# Wireless LAN
838#
839# CONFIG_WLAN_PRE80211 is not set
840CONFIG_WLAN_80211=y
841# CONFIG_IPW2100 is not set
842# CONFIG_IPW2200 is not set
843# CONFIG_LIBERTAS is not set
844# CONFIG_HERMES is not set
845CONFIG_ATMEL=m
846# CONFIG_PCI_ATMEL is not set
847# CONFIG_PRISM54 is not set
848# CONFIG_IWLWIFI_LEDS is not set
849# CONFIG_HOSTAP is not set
850# CONFIG_WAN is not set
851# CONFIG_FDDI is not set
852# CONFIG_HIPPI is not set
853CONFIG_PPP=m
854CONFIG_PPP_MULTILINK=y
855CONFIG_PPP_FILTER=y
856CONFIG_PPP_ASYNC=m
857# CONFIG_PPP_SYNC_TTY is not set
858CONFIG_PPP_DEFLATE=m
859CONFIG_PPP_BSDCOMP=m
860# CONFIG_PPP_MPPE is not set
861CONFIG_PPPOE=m
862CONFIG_PPPOL2TP=m
863# CONFIG_SLIP is not set
864CONFIG_SLHC=m
865# CONFIG_NET_FC is not set
866# CONFIG_NETCONSOLE is not set
867# CONFIG_NETPOLL is not set
868# CONFIG_NET_POLL_CONTROLLER is not set
869# CONFIG_ISDN is not set
870# CONFIG_PHONE is not set
871
872#
873# Input device support
874#
875CONFIG_INPUT=y
876# CONFIG_INPUT_FF_MEMLESS is not set
877# CONFIG_INPUT_POLLDEV is not set
878
879#
880# Userland interfaces
881#
882# CONFIG_INPUT_MOUSEDEV is not set
883# CONFIG_INPUT_JOYDEV is not set
884# CONFIG_INPUT_EVDEV is not set
885# CONFIG_INPUT_EVBUG is not set
886
887#
888# Input Device Drivers
889#
890CONFIG_INPUT_KEYBOARD=y
891# CONFIG_KEYBOARD_ATKBD is not set
892# CONFIG_KEYBOARD_SUNKBD is not set
893# CONFIG_KEYBOARD_LKKBD is not set
894# CONFIG_KEYBOARD_XTKBD is not set
895# CONFIG_KEYBOARD_NEWTON is not set
896# CONFIG_KEYBOARD_STOWAWAY is not set
897# CONFIG_KEYBOARD_GPIO is not set
898# CONFIG_INPUT_MOUSE is not set
899# CONFIG_INPUT_JOYSTICK is not set
900# CONFIG_INPUT_TABLET is not set
901# CONFIG_INPUT_TOUCHSCREEN is not set
902# CONFIG_INPUT_MISC is not set
903
904#
905# Hardware I/O ports
906#
907# CONFIG_SERIO is not set
908# CONFIG_GAMEPORT is not set
909
910#
911# Character devices
912#
913# CONFIG_VT is not set
914# CONFIG_SERIAL_NONSTANDARD is not set
915# CONFIG_NOZOMI is not set
916
917#
918# Serial drivers
919#
920CONFIG_SERIAL_8250=y
921CONFIG_SERIAL_8250_CONSOLE=y
922# CONFIG_SERIAL_8250_PCI is not set
923CONFIG_SERIAL_8250_NR_UARTS=2
924CONFIG_SERIAL_8250_RUNTIME_UARTS=2
925# CONFIG_SERIAL_8250_EXTENDED is not set
926
927#
928# Non-8250 serial port support
929#
930CONFIG_SERIAL_CORE=y
931CONFIG_SERIAL_CORE_CONSOLE=y
932# CONFIG_SERIAL_JSM is not set
933CONFIG_UNIX98_PTYS=y
934# CONFIG_LEGACY_PTYS is not set
935# CONFIG_IPMI_HANDLER is not set
936CONFIG_HW_RANDOM=y
937# CONFIG_RTC is not set
938# CONFIG_R3964 is not set
939# CONFIG_APPLICOM is not set
940# CONFIG_RAW_DRIVER is not set
941# CONFIG_TCG_TPM is not set
942CONFIG_DEVPORT=y
943# CONFIG_I2C is not set
944
945#
946# SPI support
947#
948# CONFIG_SPI is not set
949# CONFIG_SPI_MASTER is not set
950# CONFIG_W1 is not set
951# CONFIG_POWER_SUPPLY is not set
952# CONFIG_HWMON is not set
953# CONFIG_THERMAL is not set
954CONFIG_WATCHDOG=y
955# CONFIG_WATCHDOG_NOWAYOUT is not set
956
957#
958# Watchdog Device Drivers
959#
960# CONFIG_SOFT_WATCHDOG is not set
961
962#
963# PCI-based Watchdog Cards
964#
965# CONFIG_PCIPCWATCHDOG is not set
966# CONFIG_WDTPCI is not set
967
968#
969# Sonics Silicon Backplane
970#
971CONFIG_SSB_POSSIBLE=y
972# CONFIG_SSB is not set
973
974#
975# Multifunction device drivers
976#
977# CONFIG_MFD_SM501 is not set
978# CONFIG_HTC_PASIC3 is not set
979
980#
981# Multimedia devices
982#
983CONFIG_VIDEO_DEV=m
984CONFIG_VIDEO_V4L2_COMMON=m
985CONFIG_VIDEO_ALLOW_V4L1=y
986CONFIG_VIDEO_V4L1_COMPAT=y
987CONFIG_VIDEO_V4L2=m
988CONFIG_VIDEO_V4L1=m
989CONFIG_VIDEO_CAPTURE_DRIVERS=y
990# CONFIG_VIDEO_ADV_DEBUG is not set
991# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
992
993#
994# Encoders/decoders and other helper chips
995#
996
997#
998# Audio decoders
999#
1000
1001#
1002# Video decoders
1003#
1004
1005#
1006# Video and audio decoders
1007#
1008
1009#
1010# MPEG video encoders
1011#
1012# CONFIG_VIDEO_CX2341X is not set
1013
1014#
1015# Video encoders
1016#
1017
1018#
1019# Video improvement chips
1020#
1021# CONFIG_VIDEO_VIVI is not set
1022# CONFIG_VIDEO_CPIA is not set
1023# CONFIG_VIDEO_STRADIS is not set
1024# CONFIG_SOC_CAMERA is not set
1025# CONFIG_RADIO_ADAPTERS is not set
1026# CONFIG_DVB_CORE is not set
1027# CONFIG_DAB is not set
1028
1029#
1030# Graphics support
1031#
1032# CONFIG_DRM is not set
1033# CONFIG_VGASTATE is not set
1034# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1035# CONFIG_FB is not set
1036# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1037
1038#
1039# Display device support
1040#
1041# CONFIG_DISPLAY_SUPPORT is not set
1042
1043#
1044# Sound
1045#
1046# CONFIG_SOUND is not set
1047CONFIG_HID_SUPPORT=y
1048# CONFIG_HID is not set
1049CONFIG_USB_SUPPORT=y
1050CONFIG_USB_ARCH_HAS_HCD=y
1051CONFIG_USB_ARCH_HAS_OHCI=y
1052CONFIG_USB_ARCH_HAS_EHCI=y
1053# CONFIG_USB is not set
1054# CONFIG_USB_OTG_WHITELIST is not set
1055# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1056
1057#
1058# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1059#
1060# CONFIG_USB_GADGET is not set
1061# CONFIG_MMC is not set
1062# CONFIG_MEMSTICK is not set
1063CONFIG_NEW_LEDS=y
1064CONFIG_LEDS_CLASS=y
1065
1066#
1067# LED drivers
1068#
1069# CONFIG_LEDS_GPIO is not set
1070
1071#
1072# LED Triggers
1073#
1074CONFIG_LEDS_TRIGGERS=y
1075CONFIG_LEDS_TRIGGER_TIMER=y
1076CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1077# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1078# CONFIG_INFINIBAND is not set
1079CONFIG_RTC_LIB=y
1080# CONFIG_RTC_CLASS is not set
1081# CONFIG_UIO is not set
1082
1083#
1084# File systems
1085#
1086CONFIG_EXT2_FS=y
1087# CONFIG_EXT2_FS_XATTR is not set
1088# CONFIG_EXT2_FS_XIP is not set
1089# CONFIG_EXT3_FS is not set
1090# CONFIG_EXT4DEV_FS is not set
1091# CONFIG_REISERFS_FS is not set
1092# CONFIG_JFS_FS is not set
1093# CONFIG_FS_POSIX_ACL is not set
1094# CONFIG_XFS_FS is not set
1095# CONFIG_OCFS2_FS is not set
1096# CONFIG_DNOTIFY is not set
1097# CONFIG_INOTIFY is not set
1098# CONFIG_QUOTA is not set
1099# CONFIG_AUTOFS_FS is not set
1100# CONFIG_AUTOFS4_FS is not set
1101# CONFIG_FUSE_FS is not set
1102
1103#
1104# CD-ROM/DVD Filesystems
1105#
1106# CONFIG_ISO9660_FS is not set
1107# CONFIG_UDF_FS is not set
1108
1109#
1110# DOS/FAT/NT Filesystems
1111#
1112# CONFIG_MSDOS_FS is not set
1113# CONFIG_VFAT_FS is not set
1114# CONFIG_NTFS_FS is not set
1115
1116#
1117# Pseudo filesystems
1118#
1119CONFIG_PROC_FS=y
1120CONFIG_PROC_KCORE=y
1121CONFIG_PROC_SYSCTL=y
1122CONFIG_SYSFS=y
1123CONFIG_TMPFS=y
1124# CONFIG_TMPFS_POSIX_ACL is not set
1125# CONFIG_HUGETLB_PAGE is not set
1126CONFIG_CONFIGFS_FS=y
1127
1128#
1129# Miscellaneous filesystems
1130#
1131# CONFIG_ADFS_FS is not set
1132# CONFIG_AFFS_FS is not set
1133# CONFIG_HFS_FS is not set
1134# CONFIG_HFSPLUS_FS is not set
1135# CONFIG_BEFS_FS is not set
1136# CONFIG_BFS_FS is not set
1137# CONFIG_EFS_FS is not set
1138CONFIG_JFFS2_FS=y
1139CONFIG_JFFS2_FS_DEBUG=0
1140CONFIG_JFFS2_FS_WRITEBUFFER=y
1141# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1142CONFIG_JFFS2_SUMMARY=y
1143# CONFIG_JFFS2_FS_XATTR is not set
1144CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1145CONFIG_JFFS2_ZLIB=y
1146# CONFIG_JFFS2_LZO is not set
1147CONFIG_JFFS2_RTIME=y
1148# CONFIG_JFFS2_RUBIN is not set
1149# CONFIG_JFFS2_CMODE_NONE is not set
1150CONFIG_JFFS2_CMODE_PRIORITY=y
1151# CONFIG_JFFS2_CMODE_SIZE is not set
1152# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
1153# CONFIG_CRAMFS is not set
1154# CONFIG_VXFS_FS is not set
1155# CONFIG_MINIX_FS is not set
1156# CONFIG_HPFS_FS is not set
1157# CONFIG_QNX4FS_FS is not set
1158# CONFIG_ROMFS_FS is not set
1159# CONFIG_SYSV_FS is not set
1160# CONFIG_UFS_FS is not set
1161CONFIG_NETWORK_FILESYSTEMS=y
1162# CONFIG_NFS_FS is not set
1163# CONFIG_NFSD is not set
1164# CONFIG_SMB_FS is not set
1165# CONFIG_CIFS is not set
1166# CONFIG_NCP_FS is not set
1167# CONFIG_CODA_FS is not set
1168# CONFIG_AFS_FS is not set
1169
1170#
1171# Partition Types
1172#
1173CONFIG_PARTITION_ADVANCED=y
1174# CONFIG_ACORN_PARTITION is not set
1175# CONFIG_OSF_PARTITION is not set
1176# CONFIG_AMIGA_PARTITION is not set
1177# CONFIG_ATARI_PARTITION is not set
1178CONFIG_MAC_PARTITION=y
1179CONFIG_MSDOS_PARTITION=y
1180CONFIG_BSD_DISKLABEL=y
1181# CONFIG_MINIX_SUBPARTITION is not set
1182# CONFIG_SOLARIS_X86_PARTITION is not set
1183# CONFIG_UNIXWARE_DISKLABEL is not set
1184# CONFIG_LDM_PARTITION is not set
1185# CONFIG_SGI_PARTITION is not set
1186# CONFIG_ULTRIX_PARTITION is not set
1187# CONFIG_SUN_PARTITION is not set
1188# CONFIG_KARMA_PARTITION is not set
1189# CONFIG_EFI_PARTITION is not set
1190# CONFIG_SYSV68_PARTITION is not set
1191# CONFIG_NLS is not set
1192# CONFIG_DLM is not set
1193
1194#
1195# Kernel hacking
1196#
1197CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1198# CONFIG_PRINTK_TIME is not set
1199CONFIG_ENABLE_WARN_DEPRECATED=y
1200# CONFIG_ENABLE_MUST_CHECK is not set
1201CONFIG_FRAME_WARN=1024
1202# CONFIG_MAGIC_SYSRQ is not set
1203# CONFIG_UNUSED_SYMBOLS is not set
1204# CONFIG_DEBUG_FS is not set
1205# CONFIG_HEADERS_CHECK is not set
1206# CONFIG_DEBUG_KERNEL is not set
1207# CONFIG_SAMPLES is not set
1208CONFIG_CMDLINE=""
1209
1210#
1211# Security options
1212#
1213# CONFIG_KEYS is not set
1214# CONFIG_SECURITY is not set
1215# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1216CONFIG_CRYPTO=y
1217
1218#
1219# Crypto core or helper
1220#
1221CONFIG_CRYPTO_ALGAPI=m
1222CONFIG_CRYPTO_AEAD=m
1223CONFIG_CRYPTO_BLKCIPHER=m
1224# CONFIG_CRYPTO_MANAGER is not set
1225# CONFIG_CRYPTO_GF128MUL is not set
1226# CONFIG_CRYPTO_NULL is not set
1227# CONFIG_CRYPTO_CRYPTD is not set
1228# CONFIG_CRYPTO_AUTHENC is not set
1229CONFIG_CRYPTO_TEST=m
1230
1231#
1232# Authenticated Encryption with Associated Data
1233#
1234# CONFIG_CRYPTO_CCM is not set
1235# CONFIG_CRYPTO_GCM is not set
1236# CONFIG_CRYPTO_SEQIV is not set
1237
1238#
1239# Block modes
1240#
1241# CONFIG_CRYPTO_CBC is not set
1242# CONFIG_CRYPTO_CTR is not set
1243# CONFIG_CRYPTO_CTS is not set
1244# CONFIG_CRYPTO_ECB is not set
1245# CONFIG_CRYPTO_LRW is not set
1246# CONFIG_CRYPTO_PCBC is not set
1247# CONFIG_CRYPTO_XTS is not set
1248
1249#
1250# Hash modes
1251#
1252# CONFIG_CRYPTO_HMAC is not set
1253# CONFIG_CRYPTO_XCBC is not set
1254
1255#
1256# Digest
1257#
1258# CONFIG_CRYPTO_CRC32C is not set
1259# CONFIG_CRYPTO_MD4 is not set
1260# CONFIG_CRYPTO_MD5 is not set
1261# CONFIG_CRYPTO_MICHAEL_MIC is not set
1262# CONFIG_CRYPTO_SHA1 is not set
1263# CONFIG_CRYPTO_SHA256 is not set
1264# CONFIG_CRYPTO_SHA512 is not set
1265# CONFIG_CRYPTO_TGR192 is not set
1266# CONFIG_CRYPTO_WP512 is not set
1267
1268#
1269# Ciphers
1270#
1271# CONFIG_CRYPTO_AES is not set
1272# CONFIG_CRYPTO_ANUBIS is not set
1273# CONFIG_CRYPTO_ARC4 is not set
1274# CONFIG_CRYPTO_BLOWFISH is not set
1275# CONFIG_CRYPTO_CAMELLIA is not set
1276# CONFIG_CRYPTO_CAST5 is not set
1277# CONFIG_CRYPTO_CAST6 is not set
1278# CONFIG_CRYPTO_DES is not set
1279# CONFIG_CRYPTO_FCRYPT is not set
1280# CONFIG_CRYPTO_KHAZAD is not set
1281# CONFIG_CRYPTO_SALSA20 is not set
1282# CONFIG_CRYPTO_SEED is not set
1283# CONFIG_CRYPTO_SERPENT is not set
1284# CONFIG_CRYPTO_TEA is not set
1285# CONFIG_CRYPTO_TWOFISH is not set
1286
1287#
1288# Compression
1289#
1290# CONFIG_CRYPTO_DEFLATE is not set
1291# CONFIG_CRYPTO_LZO is not set
1292# CONFIG_CRYPTO_HW is not set
1293
1294#
1295# Library routines
1296#
1297CONFIG_BITREVERSE=y
1298# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1299CONFIG_CRC_CCITT=m
1300CONFIG_CRC16=m
1301# CONFIG_CRC_ITU_T is not set
1302CONFIG_CRC32=y
1303# CONFIG_CRC7 is not set
1304CONFIG_LIBCRC32C=m
1305CONFIG_ZLIB_INFLATE=y
1306CONFIG_ZLIB_DEFLATE=y
1307CONFIG_TEXTSEARCH=y
1308CONFIG_TEXTSEARCH_KMP=m
1309CONFIG_TEXTSEARCH_BM=m
1310CONFIG_TEXTSEARCH_FSM=m
1311CONFIG_PLIST=y
1312CONFIG_HAS_IOMEM=y
1313CONFIG_HAS_IOPORT=y
1314CONFIG_HAS_DMA=y
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 57e34cafa497..15e01aec37fd 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
49obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 49obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
50obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 50obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
51obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 51obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
52obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
new file mode 100644
index 000000000000..75b90dcb7a09
--- /dev/null
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -0,0 +1,69 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * stevel@mvista.com or source@mvista.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/types.h>
28#include <linux/pci.h>
29#include <linux/kernel.h>
30#include <linux/init.h>
31
32#include <asm/mach-rc32434/rc32434.h>
33
34static int __devinitdata irq_map[2][12] = {
35 {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
36 {0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3}
37};
38
39int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
40{
41 int irq = 0;
42
43 if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12)
44 irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
45
46 return irq + GROUP4_IRQ_BASE + 4;
47}
48
49static void rc32434_pci_early_fixup(struct pci_dev *dev)
50{
51 if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
52 /* disable prefetched memory range */
53 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
54 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
55
56 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
57 }
58}
59
60/*
61 * The fixup applies to both the IDT and VIA devices present on the board
62 */
63DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, rc32434_pci_early_fixup);
64
65/* Do platform specific device initialization at pci_enable_device() time */
66int pcibios_plat_dev_init(struct pci_dev *dev)
67{
68 return 0;
69}
diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c
new file mode 100644
index 000000000000..d1f8fa210ca1
--- /dev/null
+++ b/arch/mips/pci/ops-rc32434.c
@@ -0,0 +1,207 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * pci_ops for IDT EB434 board
4 *
5 * Copyright 2004 IDT Inc. (rischelp@idt.com)
6 * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28#include <linux/delay.h>
29#include <linux/init.h>
30#include <linux/io.h>
31#include <linux/pci.h>
32#include <linux/types.h>
33
34#include <asm/cpu.h>
35#include <asm/mach-rc32434/rc32434.h>
36#include <asm/mach-rc32434/pci.h>
37
38#define PCI_ACCESS_READ 0
39#define PCI_ACCESS_WRITE 1
40
41
42#define PCI_CFG_SET(bus, slot, func, off) \
43 (rc32434_pci->pcicfga = (0x80000000 | \
44 ((bus) << 16) | ((slot)<<11) | \
45 ((func)<<8) | (off)))
46
47static inline int config_access(unsigned char access_type,
48 struct pci_bus *bus, unsigned int devfn,
49 unsigned char where, u32 *data)
50{
51 unsigned int slot = PCI_SLOT(devfn);
52 u8 func = PCI_FUNC(devfn);
53
54 /* Setup address */
55 PCI_CFG_SET(bus->number, slot, func, where);
56 rc32434_sync();
57
58 if (access_type == PCI_ACCESS_WRITE)
59 rc32434_pci->pcicfgd = *data;
60 else
61 *data = rc32434_pci->pcicfgd;
62
63 rc32434_sync();
64
65 return 0;
66}
67
68
69/*
70 * We can't address 8 and 16 bit words directly. Instead we have to
71 * read/write a 32bit word and mask/modify the data we actually want.
72 */
73static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
74 int where, u8 *val)
75{
76 u32 data;
77 int ret;
78
79 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
80 *val = (data >> ((where & 3) << 3)) & 0xff;
81 return ret;
82}
83
84static int read_config_word(struct pci_bus *bus, unsigned int devfn,
85 int where, u16 *val)
86{
87 u32 data;
88 int ret;
89
90 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
91 *val = (data >> ((where & 3) << 3)) & 0xffff;
92 return ret;
93}
94
95static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
96 int where, u32 *val)
97{
98 int ret;
99 int delay = 1;
100
101 /*
102 * Don't scan too far, else there will be errors with plugged in
103 * daughterboard (rb564).
104 */
105 if (bus->number == 0 && PCI_SLOT(devfn) > 21)
106 return 0;
107
108retry:
109 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
110
111 /*
112 * Certain devices react delayed at device scan time, this
113 * gives them time to settle
114 */
115 if (where == PCI_VENDOR_ID) {
116 if (ret == 0xffffffff || ret == 0x00000000 ||
117 ret == 0x0000ffff || ret == 0xffff0000) {
118 if (delay > 4)
119 return 0;
120 delay *= 2;
121 msleep(delay);
122 goto retry;
123 }
124 }
125
126 return ret;
127}
128
129static int
130write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
131 u8 val)
132{
133 u32 data = 0;
134
135 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
136 return -1;
137
138 data = (data & ~(0xff << ((where & 3) << 3))) |
139 (val << ((where & 3) << 3));
140
141 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
142 return -1;
143
144 return PCIBIOS_SUCCESSFUL;
145}
146
147
148static int
149write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
150 u16 val)
151{
152 u32 data = 0;
153
154 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
155 return -1;
156
157 data = (data & ~(0xffff << ((where & 3) << 3))) |
158 (val << ((where & 3) << 3));
159
160 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
161 return -1;
162
163
164 return PCIBIOS_SUCCESSFUL;
165}
166
167
168static int
169write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
170 u32 val)
171{
172 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
173 return -1;
174
175 return PCIBIOS_SUCCESSFUL;
176}
177
178static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
179 int where, int size, u32 *val)
180{
181 switch (size) {
182 case 1:
183 return read_config_byte(bus, devfn, where, (u8 *) val);
184 case 2:
185 return read_config_word(bus, devfn, where, (u16 *) val);
186 default:
187 return read_config_dword(bus, devfn, where, val);
188 }
189}
190
191static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
192 int where, int size, u32 val)
193{
194 switch (size) {
195 case 1:
196 return write_config_byte(bus, devfn, where, (u8) val);
197 case 2:
198 return write_config_word(bus, devfn, where, (u16) val);
199 default:
200 return write_config_dword(bus, devfn, where, val);
201 }
202}
203
204struct pci_ops rc32434_pci_ops = {
205 .read = pci_config_read,
206 .write = pci_config_write,
207};
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
new file mode 100644
index 000000000000..1c2821e2f494
--- /dev/null
+++ b/arch/mips/pci/pci-rc32434.c
@@ -0,0 +1,221 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * PCI initialization for IDT EB434 board
4 *
5 * Copyright 2004 IDT Inc. (rischelp@idt.com)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/types.h>
29#include <linux/pci.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32
33#include <asm/mach-rc32434/rc32434.h>
34#include <asm/mach-rc32434/pci.h>
35
36#define PCI_ACCESS_READ 0
37#define PCI_ACCESS_WRITE 1
38
39/* define an unsigned array for the PCI registers */
40static unsigned int korina_cnfg_regs[25] = {
41 KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
42 KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
43 KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
44 KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
45 KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
46 KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
47};
48static struct resource rc32434_res_pci_mem1;
49static struct resource rc32434_res_pci_mem2;
50
51static struct resource rc32434_res_pci_mem1 = {
52 .name = "PCI MEM1",
53 .start = 0x50000000,
54 .end = 0x5FFFFFFF,
55 .flags = IORESOURCE_MEM,
56 .parent = &rc32434_res_pci_mem1,
57 .sibling = NULL,
58 .child = &rc32434_res_pci_mem2
59};
60
61static struct resource rc32434_res_pci_mem2 = {
62 .name = "PCI Mem2",
63 .start = 0x60000000,
64 .end = 0x6FFFFFFF,
65 .flags = IORESOURCE_MEM,
66 .parent = &rc32434_res_pci_mem1,
67 .sibling = NULL,
68 .child = NULL
69};
70
71static struct resource rc32434_res_pci_io1 = {
72 .name = "PCI I/O1",
73 .start = 0x18800000,
74 .end = 0x188FFFFF,
75 .flags = IORESOURCE_IO,
76};
77
78extern struct pci_ops rc32434_pci_ops;
79
80#define PCI_MEM1_START PCI_ADDR_START
81#define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1)
82#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
83#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1)
84#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
85#define PCI_IO1_END \
86 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
87#define PCI_IO2_START \
88 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
89#define PCI_IO2_END \
90 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
91
92struct pci_controller rc32434_controller2;
93
94struct pci_controller rc32434_controller = {
95 .pci_ops = &rc32434_pci_ops,
96 .mem_resource = &rc32434_res_pci_mem1,
97 .io_resource = &rc32434_res_pci_io1,
98 .mem_offset = 0,
99 .io_offset = 0,
100
101};
102
103#ifdef __MIPSEB__
104#define PCI_ENDIAN_FLAG PCILBAC_sb_m
105#else
106#define PCI_ENDIAN_FLAG 0
107#endif
108
109static int __init rc32434_pcibridge_init(void)
110{
111 unsigned int pcicvalue, pcicdata = 0;
112 unsigned int dummyread, pcicntlval;
113 int loopCount;
114 unsigned int pci_config_addr;
115
116 pcicvalue = rc32434_pci->pcic;
117 pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN;
118 if (!((pcicvalue == PCIM_H_EA) ||
119 (pcicvalue == PCIM_H_IA_FIX) ||
120 (pcicvalue == PCIM_H_IA_RR))) {
121 pr_err(KERN_ERR "PCI init error!!!\n");
122 /* Not in Host Mode, return ERROR */
123 return -1;
124 }
125 /* Enables the Idle Grant mode, Arbiter Parking */
126 pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN);
127 rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */
128 /* Zero out the PCI status & PCI Status Mask */
129 for (;;) {
130 pcicdata = rc32434_pci->pcis;
131 if (!(pcicdata & PCI_STAT_RIP))
132 break;
133 }
134
135 rc32434_pci->pcis = 0;
136 rc32434_pci->pcism = 0xFFFFFFFF;
137 /* Zero out the PCI decoupled registers */
138 rc32434_pci->pcidac = 0; /*
139 * disable PCI decoupled accesses at
140 * initialization
141 */
142 rc32434_pci->pcidas = 0; /* clear the status */
143 rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */
144 /* Mask PCI Messaging Interrupts */
145 rc32434_pci_msg->pciiic = 0;
146 rc32434_pci_msg->pciiim = 0xFFFFFFFF;
147 rc32434_pci_msg->pciioic = 0;
148 rc32434_pci_msg->pciioim = 0;
149
150
151 /* Setup PCILB0 as Memory Window */
152 rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START);
153
154 /* setup the PCI map address as same as the local address */
155
156 rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START);
157
158
159 /* Setup PCILBA1 as MEM */
160 rc32434_pci->pcilba[0].control =
161 (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
162 dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */
163 rc32434_pci->pcilba[1].address = 0x60000000;
164 rc32434_pci->pcilba[1].mapping = 0x60000000;
165
166 /* setup PCILBA2 as IO Window */
167 rc32434_pci->pcilba[1].control =
168 (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
169 dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */
170 rc32434_pci->pcilba[2].address = 0x18C00000;
171 rc32434_pci->pcilba[2].mapping = 0x18FFFFFF;
172
173 /* setup PCILBA2 as IO Window */
174 rc32434_pci->pcilba[2].control =
175 (((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
176 dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */
177
178 /* Setup PCILBA3 as IO Window */
179 rc32434_pci->pcilba[3].address = 0x18800000;
180 rc32434_pci->pcilba[3].mapping = 0x18800000;
181 rc32434_pci->pcilba[3].control =
182 ((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) |
183 PCI_ENDIAN_FLAG);
184 dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */
185
186 pci_config_addr = (unsigned int) (0x80000004);
187 for (loopCount = 0; loopCount < 24; loopCount++) {
188 rc32434_pci->pcicfga = pci_config_addr;
189 dummyread = rc32434_pci->pcicfga;
190 rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount];
191 dummyread = rc32434_pci->pcicfgd;
192 pci_config_addr += 4;
193 }
194 rc32434_pci->pcitc =
195 (unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) |
196 ((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT);
197
198 pcicntlval = rc32434_pci->pcic;
199 pcicntlval &= ~PCI_CTL_TNR;
200 rc32434_pci->pcic = pcicntlval;
201 pcicntlval = rc32434_pci->pcic;
202
203 return 0;
204}
205
206static int __init rc32434_pci_init(void)
207{
208 pr_info("PCI: Initializing PCI\n");
209
210 ioport_resource.start = rc32434_res_pci_io1.start;
211 ioport_resource.end = rc32434_res_pci_io1.end;
212
213 rc32434_pcibridge_init();
214
215 register_pci_controller(&rc32434_controller);
216 rc32434_sync();
217
218 return 0;
219}
220
221arch_initcall(rc32434_pci_init);
diff --git a/arch/mips/rb532/Makefile b/arch/mips/rb532/Makefile
new file mode 100644
index 000000000000..8f0b6b6a1625
--- /dev/null
+++ b/arch/mips/rb532/Makefile
@@ -0,0 +1,7 @@
1#
2# Makefile for the RB532 board specific parts of the kernel
3#
4
5obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
new file mode 100644
index 000000000000..44fb0a62877f
--- /dev/null
+++ b/arch/mips/rb532/devices.c
@@ -0,0 +1,331 @@
1/*
2 * RouterBoard 500 Platform devices
3 *
4 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/ctype.h>
20#include <linux/string.h>
21#include <linux/platform_device.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/partitions.h>
25#include <linux/gpio_keys.h>
26#include <linux/input.h>
27
28#include <asm/bootinfo.h>
29
30#include <asm/mach-rc32434/rc32434.h>
31#include <asm/mach-rc32434/dma.h>
32#include <asm/mach-rc32434/dma_v.h>
33#include <asm/mach-rc32434/eth.h>
34#include <asm/mach-rc32434/rb.h>
35#include <asm/mach-rc32434/integ.h>
36#include <asm/mach-rc32434/gpio.h>
37
38#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
39#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
40#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
41#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
42
43#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
44#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
45
46/* NAND definitions */
47#define GPIO_RDY (1 << 0x08)
48#define GPIO_WPX (1 << 0x09)
49#define GPIO_ALE (1 << 0x0a)
50#define GPIO_CLE (1 << 0x0b)
51
52extern char *board_type;
53
54static struct resource korina_dev0_res[] = {
55 {
56 .name = "korina_regs",
57 .start = ETH0_BASE_ADDR,
58 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
59 .flags = IORESOURCE_MEM,
60 }, {
61 .name = "korina_rx",
62 .start = ETH0_DMA_RX_IRQ,
63 .end = ETH0_DMA_RX_IRQ,
64 .flags = IORESOURCE_IRQ
65 }, {
66 .name = "korina_tx",
67 .start = ETH0_DMA_TX_IRQ,
68 .end = ETH0_DMA_TX_IRQ,
69 .flags = IORESOURCE_IRQ
70 }, {
71 .name = "korina_ovr",
72 .start = ETH0_RX_OVR_IRQ,
73 .end = ETH0_RX_OVR_IRQ,
74 .flags = IORESOURCE_IRQ
75 }, {
76 .name = "korina_und",
77 .start = ETH0_TX_UND_IRQ,
78 .end = ETH0_TX_UND_IRQ,
79 .flags = IORESOURCE_IRQ
80 }, {
81 .name = "korina_dma_rx",
82 .start = ETH0_RX_DMA_ADDR,
83 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
84 .flags = IORESOURCE_MEM,
85 }, {
86 .name = "korina_dma_tx",
87 .start = ETH0_TX_DMA_ADDR,
88 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
89 .flags = IORESOURCE_MEM,
90 }
91};
92
93static struct korina_device korina_dev0_data = {
94 .name = "korina0",
95 .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
96};
97
98static struct platform_device korina_dev0 = {
99 .id = 0,
100 .name = "korina",
101 .dev.platform_data = &korina_dev0_data,
102 .resource = korina_dev0_res,
103 .num_resources = ARRAY_SIZE(korina_dev0_res),
104};
105
106#define CF_GPIO_NUM 13
107
108static struct resource cf_slot0_res[] = {
109 {
110 .name = "cf_membase",
111 .flags = IORESOURCE_MEM
112 }, {
113 .name = "cf_irq",
114 .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
115 .end = (8 + 4 * 32 + CF_GPIO_NUM),
116 .flags = IORESOURCE_IRQ
117 }
118};
119
120static struct cf_device cf_slot0_data = {
121 .gpio_pin = 13
122};
123
124static struct platform_device cf_slot0 = {
125 .id = 0,
126 .name = "pata-rb532-cf",
127 .dev.platform_data = &cf_slot0_data,
128 .resource = cf_slot0_res,
129 .num_resources = ARRAY_SIZE(cf_slot0_res),
130};
131
132/* Resources and device for NAND */
133static int rb532_dev_ready(struct mtd_info *mtd)
134{
135 return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
136}
137
138static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
139{
140 struct nand_chip *chip = mtd->priv;
141 unsigned char orbits, nandbits;
142
143 if (ctrl & NAND_CTRL_CHANGE) {
144 orbits = (ctrl & NAND_CLE) << 1;
145 orbits |= (ctrl & NAND_ALE) >> 1;
146
147 nandbits = (~ctrl & NAND_CLE) << 1;
148 nandbits |= (~ctrl & NAND_ALE) >> 1;
149
150 set_latch_u5(orbits, nandbits);
151 }
152 if (cmd != NAND_CMD_NONE)
153 writeb(cmd, chip->IO_ADDR_W);
154}
155
156static struct resource nand_slot0_res[] = {
157 [0] = {
158 .name = "nand_membase",
159 .flags = IORESOURCE_MEM
160 }
161};
162
163static struct platform_nand_data rb532_nand_data = {
164 .ctrl.dev_ready = rb532_dev_ready,
165 .ctrl.cmd_ctrl = rb532_cmd_ctrl,
166};
167
168static struct platform_device nand_slot0 = {
169 .name = "gen_nand",
170 .id = -1,
171 .resource = nand_slot0_res,
172 .num_resources = ARRAY_SIZE(nand_slot0_res),
173 .dev.platform_data = &rb532_nand_data,
174};
175
176static struct mtd_partition rb532_partition_info[] = {
177 {
178 .name = "Routerboard NAND boot",
179 .offset = 0,
180 .size = 4 * 1024 * 1024,
181 }, {
182 .name = "rootfs",
183 .offset = MTDPART_OFS_NXTBLK,
184 .size = MTDPART_SIZ_FULL,
185 }
186};
187
188static struct platform_device rb532_led = {
189 .name = "rb532-led",
190 .id = 0,
191};
192
193static struct gpio_keys_button rb532_gpio_btn[] = {
194 {
195 .gpio = 1,
196 .code = BTN_0,
197 .desc = "S1",
198 .active_low = 1,
199 }
200};
201
202static struct gpio_keys_platform_data rb532_gpio_btn_data = {
203 .buttons = rb532_gpio_btn,
204 .nbuttons = ARRAY_SIZE(rb532_gpio_btn),
205};
206
207static struct platform_device rb532_button = {
208 .name = "gpio-keys",
209 .id = -1,
210 .dev = {
211 .platform_data = &rb532_gpio_btn_data,
212 }
213};
214
215static struct resource rb532_wdt_res[] = {
216 {
217 .name = "rb532_wdt_res",
218 .start = INTEG0_BASE_ADDR,
219 .end = INTEG0_BASE_ADDR + sizeof(struct integ),
220 .flags = IORESOURCE_MEM,
221 }
222};
223
224static struct platform_device rb532_wdt = {
225 .name = "rc32434_wdt",
226 .id = -1,
227 .resource = rb532_wdt_res,
228 .num_resources = ARRAY_SIZE(rb532_wdt_res),
229};
230
231static struct platform_device *rb532_devs[] = {
232 &korina_dev0,
233 &nand_slot0,
234 &cf_slot0,
235 &rb532_led,
236 &rb532_button,
237 &rb532_wdt
238};
239
240static void __init parse_mac_addr(char *macstr)
241{
242 int i, j;
243 unsigned char result, value;
244
245 for (i = 0; i < 6; i++) {
246 result = 0;
247
248 if (i != 5 && *(macstr + 2) != ':')
249 return;
250
251 for (j = 0; j < 2; j++) {
252 if (isxdigit(*macstr)
253 && (value =
254 isdigit(*macstr) ? *macstr -
255 '0' : toupper(*macstr) - 'A' + 10) < 16) {
256 result = result * 16 + value;
257 macstr++;
258 } else
259 return;
260 }
261
262 macstr++;
263 korina_dev0_data.mac[i] = result;
264 }
265}
266
267
268/* DEVICE CONTROLLER 1 */
269#define CFG_DC_DEV1 ((void *)0xb8010010)
270#define CFG_DC_DEV2 ((void *)0xb8010020)
271#define CFG_DC_DEVBASE 0x0
272#define CFG_DC_DEVMASK 0x4
273#define CFG_DC_DEVC 0x8
274#define CFG_DC_DEVTC 0xC
275
276/* NAND definitions */
277#define NAND_CHIP_DELAY 25
278
279static void __init rb532_nand_setup(void)
280{
281 switch (mips_machtype) {
282 case MACH_MIKROTIK_RB532A:
283 set_latch_u5(LO_FOFF | LO_CEX,
284 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
285 break;
286 default:
287 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
288 LO_ULED | LO_ALE | LO_CLE);
289 break;
290 }
291
292 /* Setup NAND specific settings */
293 rb532_nand_data.chip.nr_chips = 1;
294 rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
295 rb532_nand_data.chip.partitions = rb532_partition_info;
296 rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
297 rb532_nand_data.chip.options = NAND_NO_AUTOINCR;
298}
299
300
301static int __init plat_setup_devices(void)
302{
303 /* Look for the CF card reader */
304 if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
305 rb532_devs[1] = NULL;
306 else {
307 cf_slot0_res[0].start =
308 readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
309 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
310 }
311
312 /* Read the NAND resources from the device controller */
313 nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
314 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
315
316 /* Initialise the NAND device */
317 rb532_nand_setup();
318
319 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
320}
321
322static int __init setup_kmac(char *s)
323{
324 printk(KERN_INFO "korina mac = %s\n", s);
325 parse_mac_addr(s);
326 return 0;
327}
328
329__setup("kmac=", setup_kmac);
330
331arch_initcall(plat_setup_devices);
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
new file mode 100644
index 000000000000..b2fe82dba0a5
--- /dev/null
+++ b/arch/mips/rb532/gpio.c
@@ -0,0 +1,220 @@
1/*
2 * Miscellaneous functions for IDT EB434 board
3 *
4 * Copyright 2004 IDT Inc. (rischelp@idt.com)
5 * Copyright 2006 Phil Sutter <n0-1@freewrt.org>
6 * Copyright 2007 Florian Fainelli <florian@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/kernel.h>
30#include <linux/gpio.h>
31#include <linux/init.h>
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/spinlock.h>
35#include <linux/io.h>
36#include <linux/platform_device.h>
37
38#include <asm/addrspace.h>
39
40#include <asm/mach-rc32434/rb.h>
41
42struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
43EXPORT_SYMBOL(rb532_gpio_reg0);
44
45struct mpmc_device dev3;
46
47static struct resource rb532_gpio_reg0_res[] = {
48 {
49 .name = "gpio_reg0",
50 .start = (u32)(IDT434_REG_BASE + GPIOBASE),
51 .end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)),
52 .flags = IORESOURCE_MEM,
53 }
54};
55
56static struct resource rb532_dev3_ctl_res[] = {
57 {
58 .name = "dev3_ctl",
59 .start = (u32)(IDT434_REG_BASE + DEV3BASE),
60 .end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)),
61 .flags = IORESOURCE_MEM,
62 }
63};
64
65void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
66{
67 unsigned flags, data;
68 unsigned i = 0;
69
70 spin_lock_irqsave(&dev3.lock, flags);
71
72 data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs);
73 for (i = 0; i != len; ++i) {
74 if (val & (1 << i))
75 data |= (1 << (i + bit));
76 else
77 data &= ~(1 << (i + bit));
78 }
79 writel(data, (IDT434_REG_BASE + reg_offs));
80
81 spin_unlock_irqrestore(&dev3.lock, flags);
82}
83EXPORT_SYMBOL(set_434_reg);
84
85unsigned get_434_reg(unsigned reg_offs)
86{
87 return readl(IDT434_REG_BASE + reg_offs);
88}
89EXPORT_SYMBOL(get_434_reg);
90
91void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
92{
93 unsigned flags;
94
95 spin_lock_irqsave(&dev3.lock, flags);
96
97 dev3.state = (dev3.state | or_mask) & ~nand_mask;
98 writel(dev3.state, &dev3.base);
99
100 spin_unlock_irqrestore(&dev3.lock, flags);
101}
102EXPORT_SYMBOL(set_latch_u5);
103
104unsigned char get_latch_u5(void)
105{
106 return dev3.state;
107}
108EXPORT_SYMBOL(get_latch_u5);
109
110int rb532_gpio_get_value(unsigned gpio)
111{
112 return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
113}
114EXPORT_SYMBOL(rb532_gpio_get_value);
115
116void rb532_gpio_set_value(unsigned gpio, int value)
117{
118 unsigned tmp;
119
120 tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
121 if (value)
122 tmp |= 1 << gpio;
123
124 writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
125}
126EXPORT_SYMBOL(rb532_gpio_set_value);
127
128int rb532_gpio_direction_input(unsigned gpio)
129{
130 writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
131 (void *)&rb532_gpio_reg0->gpiocfg);
132
133 return 0;
134}
135EXPORT_SYMBOL(rb532_gpio_direction_input);
136
137int rb532_gpio_direction_output(unsigned gpio, int value)
138{
139 gpio_set_value(gpio, value);
140 writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
141 (void *)&rb532_gpio_reg0->gpiocfg);
142
143 return 0;
144}
145EXPORT_SYMBOL(rb532_gpio_direction_output);
146
147void rb532_gpio_set_int_level(unsigned gpio, int value)
148{
149 unsigned tmp;
150
151 tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
152 if (value)
153 tmp |= 1 << gpio;
154 writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
155}
156EXPORT_SYMBOL(rb532_gpio_set_int_level);
157
158int rb532_gpio_get_int_level(unsigned gpio)
159{
160 return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
161}
162EXPORT_SYMBOL(rb532_gpio_get_int_level);
163
164void rb532_gpio_set_int_status(unsigned gpio, int value)
165{
166 unsigned tmp;
167
168 tmp = readl(&rb532_gpio_reg0->gpioistat);
169 if (value)
170 tmp |= 1 << gpio;
171 writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
172}
173EXPORT_SYMBOL(rb532_gpio_set_int_status);
174
175int rb532_gpio_get_int_status(unsigned gpio)
176{
177 return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
178}
179EXPORT_SYMBOL(rb532_gpio_get_int_status);
180
181void rb532_gpio_set_func(unsigned gpio, int value)
182{
183 unsigned tmp;
184
185 tmp = readl(&rb532_gpio_reg0->gpiofunc);
186 if (value)
187 tmp |= 1 << gpio;
188 writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
189}
190EXPORT_SYMBOL(rb532_gpio_set_func);
191
192int rb532_gpio_get_func(unsigned gpio)
193{
194 return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
195}
196EXPORT_SYMBOL(rb532_gpio_get_func);
197
198int __init rb532_gpio_init(void)
199{
200 rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
201 rb532_gpio_reg0_res[0].end -
202 rb532_gpio_reg0_res[0].start);
203
204 if (!rb532_gpio_reg0) {
205 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
206 return -ENXIO;
207 }
208
209 dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
210 rb532_dev3_ctl_res[0].end -
211 rb532_dev3_ctl_res[0].start);
212
213 if (!dev3.base) {
214 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
215 return -ENXIO;
216 }
217
218 return 0;
219}
220arch_initcall(rb532_gpio_init);
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
new file mode 100644
index 000000000000..c0d0f950caf2
--- /dev/null
+++ b/arch/mips/rb532/irq.c
@@ -0,0 +1,209 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2002 MontaVista Software Inc.
23 * Author: MontaVista Software, Inc.
24 * stevel@mvista.com or source@mvista.com
25 */
26
27#include <linux/bitops.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/io.h>
31#include <linux/kernel_stat.h>
32#include <linux/module.h>
33#include <linux/signal.h>
34#include <linux/sched.h>
35#include <linux/types.h>
36#include <linux/interrupt.h>
37#include <linux/ioport.h>
38#include <linux/timex.h>
39#include <linux/slab.h>
40#include <linux/random.h>
41#include <linux/delay.h>
42
43#include <asm/bootinfo.h>
44#include <asm/time.h>
45#include <asm/mipsregs.h>
46#include <asm/system.h>
47
48#include <asm/mach-rc32434/rc32434.h>
49
50struct intr_group {
51 u32 mask; /* mask of valid bits in pending/mask registers */
52 volatile u32 *base_addr;
53};
54
55#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
56
57#if (NR_IRQS < RC32434_NR_IRQS)
58#error Too little irqs defined. Did you override <asm/irq.h> ?
59#endif
60
61static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
62 {
63 .mask = 0x0000efff,
64 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
65 {
66 .mask = 0x00001fff,
67 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
68 {
69 .mask = 0x00000007,
70 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
71 {
72 .mask = 0x0003ffff,
73 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
74 {
75 .mask = 0xffffffff,
76 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
77};
78
79#define READ_PEND(base) (*(base))
80#define READ_MASK(base) (*(base + 2))
81#define WRITE_MASK(base, val) (*(base + 2) = (val))
82
83static inline int irq_to_group(unsigned int irq_nr)
84{
85 return (irq_nr - GROUP0_IRQ_BASE) >> 5;
86}
87
88static inline int group_to_ip(unsigned int group)
89{
90 return group + 2;
91}
92
93static inline void enable_local_irq(unsigned int ip)
94{
95 int ipnum = 0x100 << ip;
96
97 set_c0_status(ipnum);
98}
99
100static inline void disable_local_irq(unsigned int ip)
101{
102 int ipnum = 0x100 << ip;
103
104 clear_c0_status(ipnum);
105}
106
107static inline void ack_local_irq(unsigned int ip)
108{
109 int ipnum = 0x100 << ip;
110
111 clear_c0_cause(ipnum);
112}
113
114static void rb532_enable_irq(unsigned int irq_nr)
115{
116 int ip = irq_nr - GROUP0_IRQ_BASE;
117 unsigned int group, intr_bit;
118 volatile unsigned int *addr;
119
120 if (ip < 0)
121 enable_local_irq(irq_nr);
122 else {
123 group = ip >> 5;
124
125 ip &= (1 << 5) - 1;
126 intr_bit = 1 << ip;
127
128 enable_local_irq(group_to_ip(group));
129
130 addr = intr_group[group].base_addr;
131 WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
132 }
133}
134
135static void rb532_disable_irq(unsigned int irq_nr)
136{
137 int ip = irq_nr - GROUP0_IRQ_BASE;
138 unsigned int group, intr_bit, mask;
139 volatile unsigned int *addr;
140
141 if (ip < 0) {
142 disable_local_irq(irq_nr);
143 } else {
144 group = ip >> 5;
145
146 ip &= (1 << 5) - 1;
147 intr_bit = 1 << ip;
148 addr = intr_group[group].base_addr;
149 mask = READ_MASK(addr);
150 mask |= intr_bit;
151 WRITE_MASK(addr, mask);
152
153 /*
154 * if there are no more interrupts enabled in this
155 * group, disable corresponding IP
156 */
157 if (mask == intr_group[group].mask)
158 disable_local_irq(group_to_ip(group));
159 }
160}
161
162static void rb532_mask_and_ack_irq(unsigned int irq_nr)
163{
164 rb532_disable_irq(irq_nr);
165 ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
166}
167
168static struct irq_chip rc32434_irq_type = {
169 .name = "RB532",
170 .ack = rb532_disable_irq,
171 .mask = rb532_disable_irq,
172 .mask_ack = rb532_mask_and_ack_irq,
173 .unmask = rb532_enable_irq,
174};
175
176void __init arch_init_irq(void)
177{
178 int i;
179
180 pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
181
182 for (i = 0; i < RC32434_NR_IRQS; i++)
183 set_irq_chip_and_handler(i, &rc32434_irq_type,
184 handle_level_irq);
185}
186
187/* Main Interrupt dispatcher */
188asmlinkage void plat_irq_dispatch(void)
189{
190 unsigned int ip, pend, group;
191 volatile unsigned int *addr;
192 unsigned int cp0_cause = read_c0_cause() & read_c0_status();
193
194 if (cp0_cause & CAUSEF_IP7) {
195 do_IRQ(7);
196 } else {
197 ip = (cp0_cause & 0x7c00);
198 if (ip) {
199 group = 21 + (fls(ip) - 32);
200
201 addr = intr_group[group].base_addr;
202
203 pend = READ_PEND(addr);
204 pend &= ~READ_MASK(addr); /* only unmasked interrupts */
205 pend = 39 + (fls(pend) - 32);
206 do_IRQ((group << 5) + pend);
207 }
208 }
209}
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
new file mode 100644
index 000000000000..1bc0af8febf4
--- /dev/null
+++ b/arch/mips/rb532/prom.c
@@ -0,0 +1,158 @@
1/*
2 * RouterBoard 500 specific prom routines
3 *
4 * Copyright (C) 2003, Peter Sadik <peter.sadik@idt.com>
5 * Copyright (C) 2005-2006, P.Christeas <p_christ@hol.gr>
6 * Copyright (C) 2007, Gabor Juhos <juhosg@openwrt.org>
7 * Felix Fietkau <nbd@openwrt.org>
8 * Florian Fainelli <florian@openwrt.org>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the
22 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
23 * Boston, MA 02110-1301, USA.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/mm.h>
29#include <linux/module.h>
30#include <linux/string.h>
31#include <linux/console.h>
32#include <linux/bootmem.h>
33#include <linux/ioport.h>
34#include <linux/blkdev.h>
35
36#include <asm/bootinfo.h>
37#include <asm/mach-rc32434/ddr.h>
38#include <asm/mach-rc32434/prom.h>
39
40extern void __init setup_serial_port(void);
41
42unsigned int idt_cpu_freq = 132000000;
43EXPORT_SYMBOL(idt_cpu_freq);
44unsigned int gpio_bootup_state;
45EXPORT_SYMBOL(gpio_bootup_state);
46
47static struct resource ddr_reg[] = {
48 {
49 .name = "ddr-reg",
50 .start = DDR0_PHYS_ADDR,
51 .end = DDR0_PHYS_ADDR + sizeof(struct ddr_ram),
52 .flags = IORESOURCE_MEM,
53 }
54};
55
56void __init prom_free_prom_memory(void)
57{
58 /* No prom memory to free */
59}
60
61static inline int match_tag(char *arg, const char *tag)
62{
63 return strncmp(arg, tag, strlen(tag)) == 0;
64}
65
66static inline unsigned long tag2ul(char *arg, const char *tag)
67{
68 char *num;
69
70 num = arg + strlen(tag);
71 return simple_strtoul(num, 0, 10);
72}
73
74void __init prom_setup_cmdline(void)
75{
76 char cmd_line[CL_SIZE];
77 char *cp, *board;
78 int prom_argc;
79 char **prom_argv, **prom_envp;
80 int i;
81
82 prom_argc = fw_arg0;
83 prom_argv = (char **) fw_arg1;
84 prom_envp = (char **) fw_arg2;
85
86 cp = cmd_line;
87 /* Note: it is common that parameters start
88 * at argv[1] and not argv[0],
89 * however, our elf loader starts at [0] */
90 for (i = 0; i < prom_argc; i++) {
91 if (match_tag(prom_argv[i], FREQ_TAG)) {
92 idt_cpu_freq = tag2ul(prom_argv[i], FREQ_TAG);
93 continue;
94 }
95#ifdef IGNORE_CMDLINE_MEM
96 /* parses out the "mem=xx" arg */
97 if (match_tag(prom_argv[i], MEM_TAG))
98 continue;
99#endif
100 if (i > 0)
101 *(cp++) = ' ';
102 if (match_tag(prom_argv[i], BOARD_TAG)) {
103 board = prom_argv[i] + strlen(BOARD_TAG);
104
105 if (match_tag(board, BOARD_RB532A))
106 mips_machtype = MACH_MIKROTIK_RB532A;
107 else
108 mips_machtype = MACH_MIKROTIK_RB532;
109 }
110
111 if (match_tag(prom_argv[i], GPIO_TAG))
112 gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
113
114 strcpy(cp, prom_argv[i]);
115 cp += strlen(prom_argv[i]);
116 }
117 *(cp++) = ' ';
118
119 i = strlen(arcs_cmdline);
120 if (i > 0) {
121 *(cp++) = ' ';
122 strcpy(cp, arcs_cmdline);
123 cp += strlen(arcs_cmdline);
124 }
125 if (gpio_bootup_state & 0x02)
126 strcpy(cp, GPIO_INIT_NOBUTTON);
127 else
128 strcpy(cp, GPIO_INIT_BUTTON);
129
130 cmd_line[CL_SIZE-1] = '\0';
131
132 strcpy(arcs_cmdline, cmd_line);
133}
134
135void __init prom_init(void)
136{
137 struct ddr_ram __iomem *ddr;
138 phys_t memsize;
139 phys_t ddrbase;
140
141 ddr = ioremap_nocache(ddr_reg[0].start,
142 ddr_reg[0].end - ddr_reg[0].start);
143
144 if (!ddr) {
145 printk(KERN_ERR "Unable to remap DDR register\n");
146 return;
147 }
148
149 ddrbase = (phys_t)&ddr->ddrbase;
150 memsize = (phys_t)&ddr->ddrmask;
151 memsize = 0 - memsize;
152
153 prom_setup_cmdline();
154
155 /* give all RAM to boot allocator,
156 * except for the first 0x400 and the last 0x200 bytes */
157 add_memory_region(ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
158}
diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
new file mode 100644
index 000000000000..1a05b5ddee09
--- /dev/null
+++ b/arch/mips/rb532/serial.c
@@ -0,0 +1,53 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Serial port initialisation.
4 *
5 * Copyright 2004 IDT Inc. (rischelp@idt.com)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/tty.h>
30#include <linux/serial_core.h>
31#include <linux/serial_8250.h>
32
33#include <asm/serial.h>
34#include <asm/mach-rc32434/rc32434.h>
35
36extern unsigned int idt_cpu_freq;
37
38static struct uart_port rb532_uart = {
39 .type = PORT_16550A,
40 .line = 0,
41 .irq = RC32434_UART0_IRQ,
42 .iotype = UPIO_MEM,
43 .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE),
44 .regshift = 2
45};
46
47int __init setup_serial_port(void)
48{
49 rb532_uart.uartclk = idt_cpu_freq;
50
51 return early_serial_setup(&rb532_uart);
52}
53arch_initcall(setup_serial_port);
diff --git a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c
new file mode 100644
index 000000000000..7aafa95ac20b
--- /dev/null
+++ b/arch/mips/rb532/setup.c
@@ -0,0 +1,79 @@
1/*
2 * setup.c - boot time setup code
3 */
4
5#include <linux/init.h>
6
7#include <asm/bootinfo.h>
8#include <asm/reboot.h>
9#include <asm/time.h>
10#include <linux/ioport.h>
11
12#include <asm/mach-rc32434/rc32434.h>
13#include <asm/mach-rc32434/pci.h>
14
15struct pci_reg __iomem *pci_reg;
16EXPORT_SYMBOL(pci_reg);
17
18static struct resource pci0_res[] = {
19 {
20 .name = "pci_reg0",
21 .start = PCI0_BASE_ADDR,
22 .end = PCI0_BASE_ADDR + sizeof(struct pci_reg),
23 .flags = IORESOURCE_MEM,
24 }
25};
26
27static void rb_machine_restart(char *command)
28{
29 /* just jump to the reset vector */
30 writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST));
31 ((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
32}
33
34static void rb_machine_halt(void)
35{
36 for (;;)
37 continue;
38}
39
40void __init plat_mem_setup(void)
41{
42 u32 val;
43
44 _machine_restart = rb_machine_restart;
45 _machine_halt = rb_machine_halt;
46 pm_power_off = rb_machine_halt;
47
48 set_io_port_base(KSEG1);
49
50 pci_reg = ioremap_nocache(pci0_res[0].start,
51 pci0_res[0].end - pci0_res[0].start);
52 if (!pci_reg) {
53 printk(KERN_ERR "Could not remap PCI registers\n");
54 return;
55 }
56
57 val = __raw_readl(&pci_reg->pcic);
58 val &= 0xFFFFFF7;
59 __raw_writel(val, (void *)&pci_reg->pcic);
60
61#ifdef CONFIG_PCI
62 /* Enable PCI interrupts in EPLD Mask register */
63 *epld_mask = 0x0;
64 *(epld_mask + 1) = 0x0;
65#endif
66 write_c0_wired(0);
67}
68
69const char *get_system_type(void)
70{
71 switch (mips_machtype) {
72 case MACH_MIKROTIK_RB532A:
73 return "Mikrotik RB532A";
74 break;
75 default:
76 return "Mikrotik RB532";
77 break;
78 }
79}
diff --git a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c
new file mode 100644
index 000000000000..db74edf8cefb
--- /dev/null
+++ b/arch/mips/rb532/time.c
@@ -0,0 +1,67 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
20
21#include <linux/init.h>
22#include <linux/kernel_stat.h>
23#include <linux/ptrace.h>
24#include <linux/sched.h>
25#include <linux/spinlock.h>
26#include <linux/mc146818rtc.h>
27#include <linux/irq.h>
28#include <linux/timex.h>
29
30#include <asm/mipsregs.h>
31#include <asm/debug.h>
32#include <asm/time.h>
33#include <asm/mach-rc32434/rc32434.h>
34
35extern unsigned int idt_cpu_freq;
36
37/*
38 * Figure out the r4k offset, the amount to increment the compare
39 * register for each time tick. There is no RTC available.
40 *
41 * The RC32434 counts at half the CPU *core* speed.
42 */
43static unsigned long __init cal_r4koff(void)
44{
45 mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
46
47 return mips_hpt_frequency / HZ;
48}
49
50void __init plat_time_init(void)
51{
52 unsigned int est_freq, flags;
53 unsigned long r4k_offset;
54
55 local_irq_save(flags);
56
57 printk(KERN_INFO "calculating r4koff... ");
58 r4k_offset = cal_r4koff();
59 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
60
61 est_freq = 2 * r4k_offset * HZ;
62 est_freq += 5000; /* round */
63 est_freq -= est_freq % 10000;
64 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
65 (est_freq % 1000000) * 100 / 1000000);
66 local_irq_restore(flags);
67}
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index d39e143b4a3c..610fe3af7a03 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -51,6 +51,12 @@
51#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ 51#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
52#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ 52#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
53 53
54/*
55 * Valid machtype for group Mikrotik
56 */
57#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
58#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
59
54#define CL_SIZE COMMAND_LINE_SIZE 60#define CL_SIZE COMMAND_LINE_SIZE
55 61
56extern char *system_type; 62extern char *system_type;
diff --git a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f3bc7efa2608
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
@@ -0,0 +1,81 @@
1/*
2 * IDT RC32434 specific CPU feature overrides
3 *
4 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
5 *
6 * This file was derived from: include/asm-mips/cpu-features.h
7 * Copyright (C) 2003, 2004 Ralf Baechle
8 * Copyright (C) 2004 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the
22 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
23 * Boston, MA 02110-1301, USA.
24 */
25#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
26#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
27
28/*
29 * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
30 */
31#define cpu_has_tlb 1
32#define cpu_has_4kex 1
33#define cpu_has_3k_cache 0
34#define cpu_has_4k_cache 1
35#define cpu_has_tx39_cache 0
36#define cpu_has_sb1_cache 0
37#define cpu_has_fpu 0
38#define cpu_has_32fpr 0
39#define cpu_has_counter 1
40#define cpu_has_watch 1
41#define cpu_has_divec 1
42#define cpu_has_vce 0
43#define cpu_has_cache_cdex_p 0
44#define cpu_has_cache_cdex_s 0
45#define cpu_has_prefetch 1
46#define cpu_has_mcheck 1
47#define cpu_has_ejtag 1
48#define cpu_has_llsc 1
49
50#define cpu_has_mips16 0
51#define cpu_has_mdmx 0
52#define cpu_has_mips3d 0
53#define cpu_has_smartmips 0
54
55#define cpu_has_vtag_icache 0
56/* #define cpu_has_dc_aliases ? */
57/* #define cpu_has_ic_fills_f_dc ? */
58/* #define cpu_has_pindexed_dcache ? */
59
60/* #define cpu_icache_snoops_remote_store ? */
61
62#define cpu_has_mips32r1 1
63#define cpu_has_mips32r2 0
64#define cpu_has_mips64r1 0
65#define cpu_has_mips64r2 0
66
67#define cpu_has_dsp 0
68#define cpu_has_mipsmt 0
69
70/* #define cpu_has_nofpuex ? */
71#define cpu_has_64bits 0
72#define cpu_has_64bit_zero_reg 0
73#define cpu_has_64bit_gp_regs 0
74#define cpu_has_64bit_addresses 0
75
76#define cpu_has_inclusive_pcaches 0
77
78#define cpu_dcache_line_size() 16
79#define cpu_icache_line_size() 16
80
81#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rc32434/ddr.h b/include/asm-mips/mach-rc32434/ddr.h
new file mode 100644
index 000000000000..291e2cf9dde0
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/ddr.h
@@ -0,0 +1,141 @@
1/*
2 * Definitions for the DDR registers
3 *
4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef _ASM_RC32434_DDR_H_
30#define _ASM_RC32434_DDR_H_
31
32#include <asm/mach-rc32434/rb.h>
33
34/* DDR register structure */
35struct ddr_ram {
36 u32 ddrbase;
37 u32 ddrmask;
38 u32 res1;
39 u32 res2;
40 u32 ddrc;
41 u32 ddrabase;
42 u32 ddramask;
43 u32 ddramap;
44 u32 ddrcust;
45 u32 ddrrdc;
46 u32 ddrspare;
47};
48
49#define DDR0_PHYS_ADDR 0x18018000
50
51/* DDR banks masks */
52#define DDR_MASK 0xffff0000
53#define DDR0_BASE_MSK DDR_MASK
54#define DDR1_BASE_MSK DDR_MASK
55
56/* DDR bank0 registers */
57#define RC32434_DDR0_ATA_BIT 5
58#define RC32434_DDR0_ATA_MSK 0x000000E0
59#define RC32434_DDR0_DBW_BIT 8
60#define RC32434_DDR0_DBW_MSK 0x00000100
61#define RC32434_DDR0_WR_BIT 9
62#define RC32434_DDR0_WR_MSK 0x00000600
63#define RC32434_DDR0_PS_BIT 11
64#define RC32434_DDR0_PS_MSK 0x00001800
65#define RC32434_DDR0_DTYPE_BIT 13
66#define RC32434_DDR0_DTYPE_MSK 0x0000e000
67#define RC32434_DDR0_RFC_BIT 16
68#define RC32434_DDR0_RFC_MSK 0x000f0000
69#define RC32434_DDR0_RP_BIT 20
70#define RC32434_DDR0_RP_MSK 0x00300000
71#define RC32434_DDR0_AP_BIT 22
72#define RC32434_DDR0_AP_MSK 0x00400000
73#define RC32434_DDR0_RCD_BIT 23
74#define RC32434_DDR0_RCD_MSK 0x01800000
75#define RC32434_DDR0_CL_BIT 25
76#define RC32434_DDR0_CL_MSK 0x06000000
77#define RC32434_DDR0_DBM_BIT 27
78#define RC32434_DDR0_DBM_MSK 0x08000000
79#define RC32434_DDR0_SDS_BIT 28
80#define RC32434_DDR0_SDS_MSK 0x10000000
81#define RC32434_DDR0_ATP_BIT 29
82#define RC32434_DDR0_ATP_MSK 0x60000000
83#define RC32434_DDR0_RE_BIT 31
84#define RC32434_DDR0_RE_MSK 0x80000000
85
86/* DDR bank C registers */
87#define RC32434_DDRC_MSK(x) BIT_TO_MASK(x)
88#define RC32434_DDRC_CES_BIT 0
89#define RC32434_DDRC_ACE_BIT 1
90
91/* Custom DDR bank registers */
92#define RC32434_DCST_MSK(x) BIT_TO_MASK(x)
93#define RC32434_DCST_CS_BIT 0
94#define RC32434_DCST_CS_MSK 0x00000003
95#define RC32434_DCST_WE_BIT 2
96#define RC32434_DCST_RAS_BIT 3
97#define RC32434_DCST_CAS_BIT 4
98#define RC32434_DSCT_CKE_BIT 5
99#define RC32434_DSCT_BA_BIT 6
100#define RC32434_DSCT_BA_MSK 0x000000c0
101
102/* DDR QSC registers */
103#define RC32434_QSC_DM_BIT 0
104#define RC32434_QSC_DM_MSK 0x00000003
105#define RC32434_QSC_DQSBS_BIT 2
106#define RC32434_QSC_DQSBS_MSK 0x000000fc
107#define RC32434_QSC_DB_BIT 8
108#define RC32434_QSC_DB_MSK 0x00000100
109#define RC32434_QSC_DBSP_BIT 9
110#define RC32434_QSC_DBSP_MSK 0x01fffe00
111#define RC32434_QSC_BDP_BIT 25
112#define RC32434_QSC_BDP_MSK 0x7e000000
113
114/* DDR LLC registers */
115#define RC32434_LLC_EAO_BIT 0
116#define RC32434_LLC_EAO_MSK 0x00000001
117#define RC32434_LLC_EO_BIT 1
118#define RC32434_LLC_EO_MSK 0x0000003e
119#define RC32434_LLC_FS_BIT 6
120#define RC32434_LLC_FS_MSK 0x000000c0
121#define RC32434_LLC_AS_BIT 8
122#define RC32434_LLC_AS_MSK 0x00000700
123#define RC32434_LLC_SP_BIT 11
124#define RC32434_LLC_SP_MSK 0x001ff800
125
126/* DDR LLFC registers */
127#define RC32434_LLFC_MSK(x) BIT_TO_MASK(x)
128#define RC32434_LLFC_MEN_BIT 0
129#define RC32434_LLFC_EAN_BIT 1
130#define RC32434_LLFC_FF_BIT 2
131
132/* DDR DLLTA registers */
133#define RC32434_DLLTA_ADDR_BIT 2
134#define RC32434_DLLTA_ADDR_MSK 0xfffffffc
135
136/* DDR DLLED registers */
137#define RC32434_DLLED_MSK(x) BIT_TO_MASK(x)
138#define RC32434_DLLED_DBE_BIT 0
139#define RC32434_DLLED_DTE_BIT 1
140
141#endif /* _ASM_RC32434_DDR_H_ */
diff --git a/include/asm-mips/mach-rc32434/dma.h b/include/asm-mips/mach-rc32434/dma.h
new file mode 100644
index 000000000000..5f898b5873f7
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/dma.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * DMA register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 */
10
11#ifndef __ASM_RC32434_DMA_H
12#define __ASM_RC32434_DMA_H
13
14#include <asm/mach-rc32434/rb.h>
15
16#define DMA0_BASE_ADDR 0x18040000
17
18/*
19 * DMA descriptor (in physical memory).
20 */
21
22struct dma_desc {
23 u32 control; /* Control. use DMAD_* */
24 u32 ca; /* Current Address. */
25 u32 devcs; /* Device control and status. */
26 u32 link; /* Next descriptor in chain. */
27};
28
29#define DMA_DESC_SIZ sizeof(struct dma_desc)
30#define DMA_DESC_COUNT_BIT 0
31#define DMA_DESC_COUNT_MSK 0x0003ffff
32#define DMA_DESC_DS_BIT 20
33#define DMA_DESC_DS_MSK 0x00300000
34
35#define DMA_DESC_DEV_CMD_BIT 22
36#define DMA_DESC_DEV_CMD_MSK 0x01c00000
37
38/* DMA command sizes */
39#define DMA_DESC_DEV_CMD_BYTE 0
40#define DMA_DESC_DEV_CMD_HLF_WD 1
41#define DMA_DESC_DEV_CMD_WORD 2
42#define DMA_DESC_DEV_CMD_2WORDS 3
43#define DMA_DESC_DEV_CMD_4WORDS 4
44#define DMA_DESC_DEV_CMD_6WORDS 5
45#define DMA_DESC_DEV_CMD_8WORDS 6
46#define DMA_DESC_DEV_CMD_16WORDS 7
47
48/* DMA descriptors interrupts */
49#define DMA_DESC_COF (1 << 25) /* Chain on finished */
50#define DMA_DESC_COD (1 << 26) /* Chain on done */
51#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */
52#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */
53#define DMA_DESC_TERM (1 << 29) /* Terminated */
54#define DMA_DESC_DONE (1 << 30) /* Done */
55#define DMA_DESC_FINI (1 << 31) /* Finished */
56
57/*
58 * DMA register (within Internal Register Map).
59 */
60
61struct dma_reg {
62 u32 dmac; /* Control. */
63 u32 dmas; /* Status. */
64 u32 dmasm; /* Mask. */
65 u32 dmadptr; /* Descriptor pointer. */
66 u32 dmandptr; /* Next descriptor pointer. */
67};
68
69/* DMA channels specific registers */
70#define DMA_CHAN_RUN_BIT (1 << 0)
71#define DMA_CHAN_DONE_BIT (1 << 1)
72#define DMA_CHAN_MODE_BIT (1 << 2)
73#define DMA_CHAN_MODE_MSK 0x0000000c
74#define DMA_CHAN_MODE_AUTO 0
75#define DMA_CHAN_MODE_BURST 1
76#define DMA_CHAN_MODE_XFRT 2
77#define DMA_CHAN_MODE_RSVD 3
78#define DMA_CHAN_ACT_BIT (1 << 4)
79
80/* DMA status registers */
81#define DMA_STAT_FINI (1 << 0)
82#define DMA_STAT_DONE (1 << 1)
83#define DMA_STAT_CHAIN (1 << 2)
84#define DMA_STAT_ERR (1 << 3)
85#define DMA_STAT_HALT (1 << 4)
86
87/*
88 * DMA channel definitions
89 */
90
91#define DMA_CHAN_ETH_RCV 0
92#define DMA_CHAN_ETH_XMT 1
93#define DMA_CHAN_MEM_TO_FIFO 2
94#define DMA_CHAN_FIFO_TO_MEM 3
95#define DMA_CHAN_PCI_TO_MEM 4
96#define DMA_CHAN_MEM_TO_PCI 5
97#define DMA_CHAN_COUNT 6
98
99struct dma_channel {
100 struct dma_reg ch[DMA_CHAN_COUNT];
101};
102
103#endif /* __ASM_RC32434_DMA_H */
diff --git a/include/asm-mips/mach-rc32434/dma_v.h b/include/asm-mips/mach-rc32434/dma_v.h
new file mode 100644
index 000000000000..173a9f9146cd
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/dma_v.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * DMA register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 */
10
11#ifndef _ASM_RC32434_DMA_V_H_
12#define _ASM_RC32434_DMA_V_H_
13
14#include <asm/mach-rc32434/dma.h>
15#include <asm/mach-rc32434/rc32434.h>
16
17#define DMA_CHAN_OFFSET 0x14
18#define IS_DMA_USED(X) (((X) & \
19 (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
20 != 0)
21#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK)
22
23#define DMA_HALT_TIMEOUT 500
24
25static inline int rc32434_halt_dma(struct dma_reg *ch)
26{
27 int timeout = 1;
28 if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
29 __raw_writel(0, &ch->dmac);
30 for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
31 if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
32 __raw_writel(0, &ch->dmas);
33 break;
34 }
35 }
36 }
37
38 return timeout ? 0 : 1;
39}
40
41static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
42{
43 __raw_writel(0, &ch->dmandptr);
44 __raw_writel(dma_addr, &ch->dmadptr);
45}
46
47static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
48{
49 __raw_writel(dma_addr, &ch->dmandptr);
50}
51
52#endif /* _ASM_RC32434_DMA_V_H_ */
diff --git a/include/asm-mips/mach-rc32434/eth.h b/include/asm-mips/mach-rc32434/eth.h
new file mode 100644
index 000000000000..a25cbc56173d
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/eth.h
@@ -0,0 +1,220 @@
1/*
2 * Definitions for the Ethernet registers
3 *
4 * Copyright 2002 Allend Stichter <allen.stichter@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef __ASM_RC32434_ETH_H
30#define __ASM_RC32434_ETH_H
31
32
33#define ETH0_BASE_ADDR 0x18060000
34
35struct eth_regs {
36 u32 ethintfc;
37 u32 ethfifott;
38 u32 etharc;
39 u32 ethhash0;
40 u32 ethhash1;
41 u32 ethu0[4]; /* Reserved. */
42 u32 ethpfs;
43 u32 ethmcp;
44 u32 eth_u1[10]; /* Reserved. */
45 u32 ethspare;
46 u32 eth_u2[42]; /* Reserved. */
47 u32 ethsal0;
48 u32 ethsah0;
49 u32 ethsal1;
50 u32 ethsah1;
51 u32 ethsal2;
52 u32 ethsah2;
53 u32 ethsal3;
54 u32 ethsah3;
55 u32 ethrbc;
56 u32 ethrpc;
57 u32 ethrupc;
58 u32 ethrfc;
59 u32 ethtbc;
60 u32 ethgpf;
61 u32 eth_u9[50]; /* Reserved. */
62 u32 ethmac1;
63 u32 ethmac2;
64 u32 ethipgt;
65 u32 ethipgr;
66 u32 ethclrt;
67 u32 ethmaxf;
68 u32 eth_u10; /* Reserved. */
69 u32 ethmtest;
70 u32 miimcfg;
71 u32 miimcmd;
72 u32 miimaddr;
73 u32 miimwtd;
74 u32 miimrdd;
75 u32 miimind;
76 u32 eth_u11; /* Reserved. */
77 u32 eth_u12; /* Reserved. */
78 u32 ethcfsa0;
79 u32 ethcfsa1;
80 u32 ethcfsa2;
81};
82
83/* Ethernet interrupt registers */
84#define ETH_INT_FC_EN (1 << 0)
85#define ETH_INT_FC_ITS (1 << 1)
86#define ETH_INT_FC_RIP (1 << 2)
87#define ETH_INT_FC_JAM (1 << 3)
88#define ETH_INT_FC_OVR (1 << 4)
89#define ETH_INT_FC_UND (1 << 5)
90#define ETH_INT_FC_IOC 0x000000c0
91
92/* Ethernet FIFO registers */
93#define ETH_FIFI_TT_TTH_BIT 0
94#define ETH_FIFO_TT_TTH 0x0000007f
95
96/* Ethernet ARC/multicast registers */
97#define ETH_ARC_PRO (1 << 0)
98#define ETH_ARC_AM (1 << 1)
99#define ETH_ARC_AFM (1 << 2)
100#define ETH_ARC_AB (1 << 3)
101
102/* Ethernet SAL registers */
103#define ETH_SAL_BYTE_5 0x000000ff
104#define ETH_SAL_BYTE_4 0x0000ff00
105#define ETH_SAL_BYTE_3 0x00ff0000
106#define ETH_SAL_BYTE_2 0xff000000
107
108/* Ethernet SAH registers */
109#define ETH_SAH_BYTE1 0x000000ff
110#define ETH_SAH_BYTE0 0x0000ff00
111
112/* Ethernet GPF register */
113#define ETH_GPF_PTV 0x0000ffff
114
115/* Ethernet PFG register */
116#define ETH_PFS_PFD (1 << 0)
117
118/* Ethernet CFSA[0-3] registers */
119#define ETH_CFSA0_CFSA4 0x000000ff
120#define ETH_CFSA0_CFSA5 0x0000ff00
121#define ETH_CFSA1_CFSA2 0x000000ff
122#define ETH_CFSA1_CFSA3 0x0000ff00
123#define ETH_CFSA1_CFSA0 0x000000ff
124#define ETH_CFSA1_CFSA1 0x0000ff00
125
126/* Ethernet MAC1 registers */
127#define ETH_MAC1_RE (1 << 0)
128#define ETH_MAC1_PAF (1 << 1)
129#define ETH_MAC1_RFC (1 << 2)
130#define ETH_MAC1_TFC (1 << 3)
131#define ETH_MAC1_LB (1 << 4)
132#define ETH_MAC1_MR (1 << 31)
133
134/* Ethernet MAC2 registers */
135#define ETH_MAC2_FD (1 << 0)
136#define ETH_MAC2_FLC (1 << 1)
137#define ETH_MAC2_HFE (1 << 2)
138#define ETH_MAC2_DC (1 << 3)
139#define ETH_MAC2_CEN (1 << 4)
140#define ETH_MAC2_PE (1 << 5)
141#define ETH_MAC2_VPE (1 << 6)
142#define ETH_MAC2_APE (1 << 7)
143#define ETH_MAC2_PPE (1 << 8)
144#define ETH_MAC2_LPE (1 << 9)
145#define ETH_MAC2_NB (1 << 12)
146#define ETH_MAC2_BP (1 << 13)
147#define ETH_MAC2_ED (1 << 14)
148
149/* Ethernet IPGT register */
150#define ETH_IPGT 0x0000007f
151
152/* Ethernet IPGR registers */
153#define ETH_IPGR_IPGR2 0x0000007f
154#define ETH_IPGR_IPGR1 0x00007f00
155
156/* Ethernet CLRT registers */
157#define ETH_CLRT_MAX_RET 0x0000000f
158#define ETH_CLRT_COL_WIN 0x00003f00
159
160/* Ethernet MAXF register */
161#define ETH_MAXF 0x0000ffff
162
163/* Ethernet test registers */
164#define ETH_TEST_REG (1 << 2)
165#define ETH_MCP_DIV 0x000000ff
166
167/* MII registers */
168#define ETH_MII_CFG_RSVD 0x0000000c
169#define ETH_MII_CMD_RD (1 << 0)
170#define ETH_MII_CMD_SCN (1 << 1)
171#define ETH_MII_REG_ADDR 0x0000001f
172#define ETH_MII_PHY_ADDR 0x00001f00
173#define ETH_MII_WTD_DATA 0x0000ffff
174#define ETH_MII_RDD_DATA 0x0000ffff
175#define ETH_MII_IND_BSY (1 << 0)
176#define ETH_MII_IND_SCN (1 << 1)
177#define ETH_MII_IND_NV (1 << 2)
178
179/*
180 * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
181 */
182
183#define ETH_RX_FD (1 << 0)
184#define ETH_RX_LD (1 << 1)
185#define ETH_RX_ROK (1 << 2)
186#define ETH_RX_FM (1 << 3)
187#define ETH_RX_MP (1 << 4)
188#define ETH_RX_BP (1 << 5)
189#define ETH_RX_VLT (1 << 6)
190#define ETH_RX_CF (1 << 7)
191#define ETH_RX_OVR (1 << 8)
192#define ETH_RX_CRC (1 << 9)
193#define ETH_RX_CV (1 << 10)
194#define ETH_RX_DB (1 << 11)
195#define ETH_RX_LE (1 << 12)
196#define ETH_RX_LOR (1 << 13)
197#define ETH_RX_CES (1 << 14)
198#define ETH_RX_LEN_BIT 16
199#define ETH_RX_LEN 0xffff0000
200
201#define ETH_TX_FD (1 << 0)
202#define ETH_TX_LD (1 << 1)
203#define ETH_TX_OEN (1 << 2)
204#define ETH_TX_PEN (1 << 3)
205#define ETH_TX_CEN (1 << 4)
206#define ETH_TX_HEN (1 << 5)
207#define ETH_TX_TOK (1 << 6)
208#define ETH_TX_MP (1 << 7)
209#define ETH_TX_BP (1 << 8)
210#define ETH_TX_UND (1 << 9)
211#define ETH_TX_OF (1 << 10)
212#define ETH_TX_ED (1 << 11)
213#define ETH_TX_EC (1 << 12)
214#define ETH_TX_LC (1 << 13)
215#define ETH_TX_TD (1 << 14)
216#define ETH_TX_CRC (1 << 15)
217#define ETH_TX_LE (1 << 16)
218#define ETH_TX_CC 0x001E0000
219
220#endif /* __ASM_RC32434_ETH_H */
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
new file mode 100644
index 000000000000..f946f5f45bbb
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/gpio.h
@@ -0,0 +1,126 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * GPIO register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
10 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
11 */
12
13#ifndef _RC32434_GPIO_H_
14#define _RC32434_GPIO_H_
15
16#include <linux/types.h>
17
18struct rb532_gpio_reg {
19 u32 gpiofunc; /* GPIO Function Register
20 * gpiofunc[x]==0 bit = gpio
21 * func[x]==1 bit = altfunc
22 */
23 u32 gpiocfg; /* GPIO Configuration Register
24 * gpiocfg[x]==0 bit = input
25 * gpiocfg[x]==1 bit = output
26 */
27 u32 gpiod; /* GPIO Data Register
28 * gpiod[x] read/write gpio pinX status
29 */
30 u32 gpioilevel; /* GPIO Interrupt Status Register
31 * interrupt level (see gpioistat)
32 */
33 u32 gpioistat; /* Gpio Interrupt Status Register
34 * istat[x] = (gpiod[x] == level[x])
35 * cleared in ISR (STICKY bits)
36 */
37 u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
38};
39
40/* UART GPIO signals */
41#define RC32434_UART0_SOUT (1 << 0)
42#define RC32434_UART0_SIN (1 << 1)
43#define RC32434_UART0_RTS (1 << 2)
44#define RC32434_UART0_CTS (1 << 3)
45
46/* M & P bus GPIO signals */
47#define RC32434_MP_BIT_22 (1 << 4)
48#define RC32434_MP_BIT_23 (1 << 5)
49#define RC32434_MP_BIT_24 (1 << 6)
50#define RC32434_MP_BIT_25 (1 << 7)
51
52/* CPU GPIO signals */
53#define RC32434_CPU_GPIO (1 << 8)
54
55/* Reserved GPIO signals */
56#define RC32434_AF_SPARE_6 (1 << 9)
57#define RC32434_AF_SPARE_4 (1 << 10)
58#define RC32434_AF_SPARE_3 (1 << 11)
59#define RC32434_AF_SPARE_2 (1 << 12)
60
61/* PCI messaging unit */
62#define RC32434_PCI_MSU_GPIO (1 << 13)
63
64
65extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
66extern unsigned get_434_reg(unsigned reg_offs);
67extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
68extern unsigned char get_latch_u5(void);
69
70extern int rb532_gpio_get_value(unsigned gpio);
71extern void rb532_gpio_set_value(unsigned gpio, int value);
72extern int rb532_gpio_direction_input(unsigned gpio);
73extern int rb532_gpio_direction_output(unsigned gpio, int value);
74extern void rb532_gpio_set_int_level(unsigned gpio, int value);
75extern int rb532_gpio_get_int_level(unsigned gpio);
76extern void rb532_gpio_set_int_status(unsigned gpio, int value);
77extern int rb532_gpio_get_int_status(unsigned gpio);
78
79
80/* Wrappers for the arch-neutral GPIO API */
81
82static inline int gpio_request(unsigned gpio, const char *label)
83{
84 /* Not yet implemented */
85 return 0;
86}
87
88static inline void gpio_free(unsigned gpio)
89{
90 /* Not yet implemented */
91}
92
93static inline int gpio_direction_input(unsigned gpio)
94{
95 return rb532_gpio_direction_input(gpio);
96}
97
98static inline int gpio_direction_output(unsigned gpio, int value)
99{
100 return rb532_gpio_direction_output(gpio, value);
101}
102
103static inline int gpio_get_value(unsigned gpio)
104{
105 return rb532_gpio_get_value(gpio);
106}
107
108static inline void gpio_set_value(unsigned gpio, int value)
109{
110 rb532_gpio_set_value(gpio, value);
111}
112
113static inline int gpio_to_irq(unsigned gpio)
114{
115 return gpio;
116}
117
118static inline int irq_to_gpio(unsigned irq)
119{
120 return irq;
121}
122
123/* For cansleep */
124#include <asm-generic/gpio.h>
125
126#endif /* _RC32434_GPIO_H_ */
diff --git a/include/asm-mips/mach-rc32434/integ.h b/include/asm-mips/mach-rc32434/integ.h
new file mode 100644
index 000000000000..fa65bc3d8807
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/integ.h
@@ -0,0 +1,59 @@
1/*
2 * Definitions for the Watchdog registers
3 *
4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef __RC32434_INTEG_H__
30#define __RC32434_INTEG_H__
31
32#include <asm/mach-rc32434/rb.h>
33
34#define INTEG0_BASE_ADDR 0x18030030
35
36struct integ {
37 u32 errcs; /* sticky use ERRCS_ */
38 u32 wtcount; /* Watchdog timer count reg. */
39 u32 wtcompare; /* Watchdog timer timeout value. */
40 u32 wtc; /* Watchdog timer control. use WTC_ */
41};
42
43/* Error counters */
44#define RC32434_ERR_WTO 0
45#define RC32434_ERR_WNE 1
46#define RC32434_ERR_UCW 2
47#define RC32434_ERR_UCR 3
48#define RC32434_ERR_UPW 4
49#define RC32434_ERR_UPR 5
50#define RC32434_ERR_UDW 6
51#define RC32434_ERR_UDR 7
52#define RC32434_ERR_SAE 8
53#define RC32434_ERR_WRE 9
54
55/* Watchdog control bits */
56#define RC32434_WTC_EN 0
57#define RC32434_WTC_TO 1
58
59#endif /* __RC32434_INTEG_H__ */
diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
new file mode 100644
index 000000000000..cb9e4725f5dc
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/irq.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_RC32434_IRQ_H
2#define __ASM_RC32434_IRQ_H
3
4#define NR_IRQS 256
5
6#include <asm/mach-generic/irq.h>
7
8#endif /* __ASM_RC32434_IRQ_H */
diff --git a/include/asm-mips/mach-rc32434/pci.h b/include/asm-mips/mach-rc32434/pci.h
new file mode 100644
index 000000000000..410638f2af74
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/pci.h
@@ -0,0 +1,481 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2004 IDT Inc. (rischelp@idt.com)
23 *
24 * Initial Release
25 */
26
27#ifndef _ASM_RC32434_PCI_H_
28#define _ASM_RC32434_PCI_H_
29
30#define epld_mask ((volatile unsigned char *)0xB900000d)
31
32#define PCI0_BASE_ADDR 0x18080000
33#define PCI_LBA_COUNT 4
34
35struct pci_map {
36 u32 address; /* Address. */
37 u32 control; /* Control. */
38 u32 mapping; /* mapping. */
39};
40
41struct pci_reg {
42 u32 pcic;
43 u32 pcis;
44 u32 pcism;
45 u32 pcicfga;
46 u32 pcicfgd;
47 volatile struct pci_map pcilba[PCI_LBA_COUNT];
48 u32 pcidac;
49 u32 pcidas;
50 u32 pcidasm;
51 u32 pcidad;
52 u32 pcidma8c;
53 u32 pcidma9c;
54 u32 pcitc;
55};
56
57#define PCI_MSU_COUNT 2
58
59struct pci_msu {
60 u32 pciim[PCI_MSU_COUNT];
61 u32 pciom[PCI_MSU_COUNT];
62 u32 pciid;
63 u32 pciiic;
64 u32 pciiim;
65 u32 pciiod;
66 u32 pciioic;
67 u32 pciioim;
68};
69
70/*
71 * PCI Control Register
72 */
73
74#define PCI_CTL_EN (1 << 0)
75#define PCI_CTL_TNR (1 << 1)
76#define PCI_CTL_SCE (1 << 2)
77#define PCI_CTL_IEN (1 << 3)
78#define PCI_CTL_AAA (1 << 4)
79#define PCI_CTL_EAP (1 << 5)
80#define PCI_CTL_PCIM_BIT 6
81#define PCI_CTL_PCIM 0x000001c0
82
83#define PCI_CTL_PCIM_DIS 0
84#define PCI_CTL_PCIM_TNR 1 /* Satellite - target not ready */
85#define PCI_CTL_PCIM_SUS 2 /* Satellite - suspended CPU. */
86#define PCI_CTL_PCIM_EXT 3 /* Host - external arbiter. */
87#define PCI_CTL PCIM_PRIO 4 /* Host - fixed priority arb. */
88#define PCI_CTL_PCIM_RR 5 /* Host - round robin priority. */
89#define PCI_CTL_PCIM_RSVD6 6
90#define PCI_CTL_PCIM_RSVD7 7
91
92#define PCI_CTL_IGM (1 << 9)
93
94/*
95 * PCI Status Register
96 */
97
98#define PCI_STAT_EED (1 << 0)
99#define PCI_STAT_WR (1 << 1)
100#define PCI_STAT_NMI (1 << 2)
101#define PCI_STAT_II (1 << 3)
102#define PCI_STAT_CWE (1 << 4)
103#define PCI_STAT_CRE (1 << 5)
104#define PCI_STAT_MDPE (1 << 6)
105#define PCI_STAT_STA (1 << 7)
106#define PCI_STAT_RTA (1 << 8)
107#define PCI_STAT_RMA (1 << 9)
108#define PCI_STAT_SSE (1 << 10)
109#define PCI_STAT_OSE (1 << 11)
110#define PCI_STAT_PE (1 << 12)
111#define PCI_STAT_TAE (1 << 13)
112#define PCI_STAT_RLE (1 << 14)
113#define PCI_STAT_BME (1 << 15)
114#define PCI_STAT_PRD (1 << 16)
115#define PCI_STAT_RIP (1 << 17)
116
117/*
118 * PCI Status Mask Register
119 */
120
121#define PCI_STATM_EED PCI_STAT_EED
122#define PCI_STATM_WR PCI_STAT_WR
123#define PCI_STATM_NMI PCI_STAT_NMI
124#define PCI_STATM_II PCI_STAT_II
125#define PCI_STATM_CWE PCI_STAT_CWE
126#define PCI_STATM_CRE PCI_STAT_CRE
127#define PCI_STATM_MDPE PCI_STAT_MDPE
128#define PCI_STATM_STA PCI_STAT_STA
129#define PCI_STATM_RTA PCI_STAT_RTA
130#define PCI_STATM_RMA PCI_STAT_RMA
131#define PCI_STATM_SSE PCI_STAT_SSE
132#define PCI_STATM_OSE PCI_STAT_OSE
133#define PCI_STATM_PE PCI_STAT_PE
134#define PCI_STATM_TAE PCI_STAT_TAE
135#define PCI_STATM_RLE PCI_STAT_RLE
136#define PCI_STATM_BME PCI_STAT_BME
137#define PCI_STATM_PRD PCI_STAT_PRD
138#define PCI_STATM_RIP PCI_STAT_RIP
139
140/*
141 * PCI Configuration Address Register
142 */
143#define PCI_CFGA_REG_BIT 2
144#define PCI_CFGA_REG 0x000000fc
145#define PCI_CFGA_REG_ID (0x00 >> 2) /* use PCFGID */
146#define PCI_CFGA_REG_04 (0x04 >> 2) /* use PCFG04_ */
147#define PCI_CFGA_REG_08 (0x08 >> 2) /* use PCFG08_ */
148#define PCI_CFGA_REG_0C (0x0C >> 2) /* use PCFG0C_ */
149#define PCI_CFGA_REG_PBA0 (0x10 >> 2) /* use PCIPBA_ */
150#define PCI_CFGA_REG_PBA1 (0x14 >> 2) /* use PCIPBA_ */
151#define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */
152#define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */
153#define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */
154#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */
155#define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */
156#define PCI_CFGA_REG_PBA0M (0x48 >> 2)
157#define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */
158#define PCI_CFGA_REG_PBA1M (0x50 >> 2)
159#define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */
160#define PCI_CFGA_REG_PBA2M (0x58 >> 2)
161#define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */
162#define PCI_CFGA_REG_PBA3M (0x60 >> 2)
163#define PCI_CFGA_REG_PMGT (0x64 >> 2)
164#define PCI_CFGA_FUNC_BIT 8
165#define PCI_CFGA_FUNC 0x00000700
166#define PCI_CFGA_DEV_BIT 11
167#define PCI_CFGA_DEV 0x0000f800
168#define PCI_CFGA_DEV_INTERN 0
169#define PCI_CFGA_BUS_BIT 16
170#define PCI CFGA_BUS 0x00ff0000
171#define PCI_CFGA_BUS_TYPE0 0
172#define PCI_CFGA_EN (1 << 31)
173
174/* PCI CFG04 commands */
175#define PCI_CFG04_CMD_IO_ENA (1 << 0)
176#define PCI_CFG04_CMD_MEM_ENA (1 << 1)
177#define PCI_CFG04_CMD_BM_ENA (1 << 2)
178#define PCI_CFG04_CMD_MW_INV (1 << 4)
179#define PCI_CFG04_CMD_PAR_ENA (1 << 6)
180#define PCI_CFG04_CMD_SER_ENA (1 << 8)
181#define PCI_CFG04_CMD_FAST_ENA (1 << 9)
182
183/* PCI CFG04 status fields */
184#define PCI_CFG04_STAT_BIT 16
185#define PCI_CFG04_STAT 0xffff0000
186#define PCI_CFG04_STAT_66_MHZ (1 << 21)
187#define PCI_CFG04_STAT_FBB (1 << 23)
188#define PCI_CFG04_STAT_MDPE (1 << 24)
189#define PCI_CFG04_STAT_DST (1 << 25)
190#define PCI_CFG04_STAT_STA (1 << 27)
191#define PCI_CFG04_STAT_RTA (1 << 28)
192#define PCI_CFG04_STAT_RMA (1 << 29)
193#define PCI_CFG04_STAT_SSE (1 << 30)
194#define PCI_CFG04_STAT_PE (1 << 31)
195
196#define PCI_PBA_MSI (1 << 0)
197#define PCI_PBA_P (1 << 2)
198
199/* PCI PBAC registers */
200#define PCI_PBAC_MSI (1 << 0)
201#define PCI_PBAC_P (1 << 1)
202#define PCI_PBAC_SIZE_BIT 2
203#define PCI_PBAC_SIZE 0x0000007c
204#define PCI_PBAC_SB (1 << 7)
205#define PCI_PBAC_PP (1 << 8)
206#define PCI_PBAC_MR_BIT 9
207#define PCI_PBAC_MR 0x00000600
208#define PCI_PBAC_MR_RD 0
209#define PCI_PBAC_MR_RD_LINE 1
210#define PCI_PBAC_MR_RD_MULT 2
211#define PCI_PBAC_MRL (1 << 11)
212#define PCI_PBAC_MRM (1 << 12)
213#define PCI_PBAC_TRP (1 << 13)
214
215#define PCI_CFG40_TRDY_TIM 0x000000ff
216#define PCI_CFG40_RET_LIM 0x0000ff00
217
218/*
219 * PCI Local Base Address [0|1|2|3] Register
220 */
221
222#define PCI_LBA_BADDR_BIT 0
223#define PCI_LBA_BADDR 0xffffff00
224
225/*
226 * PCI Local Base Address Control Register
227 */
228
229#define PCI_LBAC_MSI (1 << 0)
230#define PCI_LBAC_MSI_MEM 0
231#define PCI_LBAC_MSI_IO 1
232#define PCI_LBAC_SIZE_BIT 2
233#define PCI_LBAC_SIZE 0x0000007c
234#define PCI_LBAC_SB (1 << 7)
235#define PCI_LBAC_RT (1 << 8)
236#define PCI_LBAC_RT_NO_PREF 0
237#define PCI_LBAC_RT_PREF 1
238
239/*
240 * PCI Local Base Address [0|1|2|3] Mapping Register
241 */
242#define PCI_LBAM_MADDR_BIT 8
243#define PCI_LBAM_MADDR 0xffffff00
244
245/*
246 * PCI Decoupled Access Control Register
247 */
248#define PCI_DAC_DEN (1 << 0)
249
250/*
251 * PCI Decoupled Access Status Register
252 */
253#define PCI_DAS_D (1 << 0)
254#define PCI_DAS_B (1 << 1)
255#define PCI_DAS_E (1 << 2)
256#define PCI_DAS_OFE (1 << 3)
257#define PCI_DAS_OFF (1 << 4)
258#define PCI_DAS_IFE (1 << 5)
259#define PCI_DAS_IFF (1 << 6)
260
261/*
262 * PCI DMA Channel 8 Configuration Register
263 */
264#define PCI_DMA8C_MBS_BIT 0
265#define PCI_DMA8C_MBS 0x00000fff /* Maximum Burst Size. */
266#define PCI_DMA8C_OUR (1 << 12)
267
268/*
269 * PCI DMA Channel 9 Configuration Register
270 */
271#define PCI_DMA9C_MBS_BIT 0 /* Maximum Burst Size. */
272#define PCI_DMA9C_MBS 0x00000fff
273
274/*
275 * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
276 */
277
278#define PCI_DMAD_PT_BIT 22 /* in DEVCMD field (descriptor) */
279#define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */
280/* These are for reads (DMA channel 8) */
281#define PCI_DMAD_DEVCMD_MR 0 /* memory read */
282#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */
283#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */
284#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */
285/* These are for writes (DMA channel 9) */
286#define PCI_DMAD_DEVCMD_MW 0 /* memory write */
287#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */
288#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */
289
290/* Swap byte field applies to both DMA channel 8 and 9 */
291#define PCI_DMAD_SB (1 << 24) /* swap byte field */
292
293
294/*
295 * PCI Target Control Register
296 */
297
298#define PCI_TC_RTIMER_BIT 0
299#define PCI_TC_RTIMER 0x000000ff
300#define PCI_TC_DTIMER_BIT 8
301#define PCI_TC_DTIMER 0x0000ff00
302#define PCI_TC_RDR (1 << 18)
303#define PCI_TC_DDT (1 << 19)
304
305/*
306 * PCI messaging unit [applies to both inbound and outbound registers ]
307 */
308#define PCI_MSU_M0 (1 << 0)
309#define PCI_MSU_M1 (1 << 1)
310#define PCI_MSU_DB (1 << 2)
311
312#define PCI_MSG_ADDR 0xB8088010
313#define PCI0_ADDR 0xB8080000
314#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
315#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
316
317#define PCIM_SHFT 0x6
318#define PCIM_BIT_LEN 0x7
319#define PCIM_H_EA 0x3
320#define PCIM_H_IA_FIX 0x4
321#define PCIM_H_IA_RR 0x5
322#if 0
323#define PCI_ADDR_START 0x13000000
324#endif
325
326#define PCI_ADDR_START 0x50000000
327
328#define CPUTOPCI_MEM_WIN 0x02000000
329#define CPUTOPCI_IO_WIN 0x00100000
330#define PCILBA_SIZE_SHFT 2
331#define PCILBA_SIZE_MASK 0x1F
332#define SIZE_256MB 0x1C
333#define SIZE_128MB 0x1B
334#define SIZE_64MB 0x1A
335#define SIZE_32MB 0x19
336#define SIZE_16MB 0x18
337#define SIZE_4MB 0x16
338#define SIZE_2MB 0x15
339#define SIZE_1MB 0x14
340#define KORINA_CONFIG0_ADDR 0x80000000
341#define KORINA_CONFIG1_ADDR 0x80000004
342#define KORINA_CONFIG2_ADDR 0x80000008
343#define KORINA_CONFIG3_ADDR 0x8000000C
344#define KORINA_CONFIG4_ADDR 0x80000010
345#define KORINA_CONFIG5_ADDR 0x80000014
346#define KORINA_CONFIG6_ADDR 0x80000018
347#define KORINA_CONFIG7_ADDR 0x8000001C
348#define KORINA_CONFIG8_ADDR 0x80000020
349#define KORINA_CONFIG9_ADDR 0x80000024
350#define KORINA_CONFIG10_ADDR 0x80000028
351#define KORINA_CONFIG11_ADDR 0x8000002C
352#define KORINA_CONFIG12_ADDR 0x80000030
353#define KORINA_CONFIG13_ADDR 0x80000034
354#define KORINA_CONFIG14_ADDR 0x80000038
355#define KORINA_CONFIG15_ADDR 0x8000003C
356#define KORINA_CONFIG16_ADDR 0x80000040
357#define KORINA_CONFIG17_ADDR 0x80000044
358#define KORINA_CONFIG18_ADDR 0x80000048
359#define KORINA_CONFIG19_ADDR 0x8000004C
360#define KORINA_CONFIG20_ADDR 0x80000050
361#define KORINA_CONFIG21_ADDR 0x80000054
362#define KORINA_CONFIG22_ADDR 0x80000058
363#define KORINA_CONFIG23_ADDR 0x8000005C
364#define KORINA_CONFIG24_ADDR 0x80000060
365#define KORINA_CONFIG25_ADDR 0x80000064
366#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \
367 PCI_CFG04_CMD_MEM_ENA | \
368 PCI_CFG04_CMD_BM_ENA | \
369 PCI_CFG04_CMD_MW_INV | \
370 PCI_CFG04_CMD_PAR_ENA | \
371 PCI_CFG04_CMD_SER_ENA)
372
373#define KORINA_STAT (PCI_CFG04_STAT_MDPE | \
374 PCI_CFG04_STAT_STA | \
375 PCI_CFG04_STAT_RTA | \
376 PCI_CFG04_STAT_RMA | \
377 PCI_CFG04_STAT_SSE | \
378 PCI_CFG04_STAT_PE)
379
380#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
381
382#define KORINA_REVID 0
383#define KORINA_CLASS_CODE 0
384#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
385 KORINA_REVID)
386
387#define KORINA_CACHE_LINE_SIZE 4
388#define KORINA_MASTER_LAT 0x3c
389#define KORINA_HEADER_TYPE 0
390#define KORINA_BIST 0
391
392#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
393 (KORINA_HEADER_TYPE<<16) | \
394 (KORINA_MASTER_LAT<<8) | \
395 KORINA_CACHE_LINE_SIZE)
396
397#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
398#define KORINA_BAR1 0x18800001 /* 1 MB IO */
399#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
400 internal Registers */
401#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
402
403#define KORINA_CNFG4 KORINA_BAR0
404#define KORINA_CNFG5 KORINA_BAR1
405#define KORINA_CNFG6 KORINA_BAR2
406#define KORINA_CNFG7 KORINA_BAR3
407
408#define KORINA_SUBSYS_VENDOR_ID 0x011d
409#define KORINA_SUBSYSTEM_ID 0x0214
410#define KORINA_CNFG8 0
411#define KORINA_CNFG9 0
412#define KORINA_CNFG10 0
413#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
414 KORINA_SUBSYSTEM_ID)
415#define KORINA_INT_LINE 1
416#define KORINA_INT_PIN 1
417#define KORINA_MIN_GNT 8
418#define KORINA_MAX_LAT 0x38
419#define KORINA_CNFG12 0
420#define KORINA_CNFG13 0
421#define KORINA_CNFG14 0
422#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
423 (KORINA_MIN_GNT<<16) | \
424 (KORINA_INT_PIN<<8) | \
425 KORINA_INT_LINE)
426#define KORINA_RETRY_LIMIT 0x80
427#define KORINA_TRDY_LIMIT 0x80
428#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
429 KORINA_TRDY_LIMIT)
430#define PCI_PBAxC_R 0x0
431#define PCI_PBAxC_RL 0x1
432#define PCI_PBAxC_RM 0x2
433#define SIZE_SHFT 2
434
435#if defined(__MIPSEB__)
436#define KORINA_PBA0C (PCI_PBAC_MRL | PCI_PBAC_SB | \
437 ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
438 PCI_PBAC_PP | \
439 (SIZE_128MB<<SIZE_SHFT) | \
440 PCI_PBAC_P)
441#else
442#define KORINA_PBA0C (PCI_PBAC_MRL | \
443 ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
444 PCI_PBAC_PP | \
445 (SIZE_128MB<<SIZE_SHFT) | \
446 PCI_PBAC_P)
447#endif
448#define KORINA_CNFG17 KORINA_PBA0C
449#define KORINA_PBA0M 0x0
450#define KORINA_CNFG18 KORINA_PBA0M
451
452#if defined(__MIPSEB__)
453#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
454 PCI_PBAC_MSI)
455#else
456#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
457 PCI_PBAC_MSI)
458#endif
459#define KORINA_CNFG19 KORINA_PBA1C
460#define KORINA_PBA1M 0x0
461#define KORINA_CNFG20 KORINA_PBA1M
462
463#if defined(__MIPSEB__)
464#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
465 PCI_PBAC_MSI)
466#else
467#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
468 PCI_PBAC_MSI)
469#endif
470#define KORINA_CNFG21 KORINA_PBA2C
471#define KORINA_PBA2M 0x18000000
472#define KORINA_CNFG22 KORINA_PBA2M
473#define KORINA_PBA3C 0
474#define KORINA_CNFG23 KORINA_PBA3C
475#define KORINA_PBA3M 0
476#define KORINA_CNFG24 KORINA_PBA3M
477
478#define PCITC_DTIMER_VAL 8
479#define PCITC_RTIMER_VAL 0x10
480
481#endif /* __ASM_RC32434_PCI_H */
diff --git a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h
new file mode 100644
index 000000000000..1d66ddcda89a
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/prom.h
@@ -0,0 +1,44 @@
1/*
2 * Definitions for the PROM
3 *
4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8))
30
31#define GPIO_INIT_NOBUTTON ""
32#define GPIO_INIT_BUTTON " 2"
33
34#define SR_NMI 0x00180000
35#define SERIAL_SPEED_ENTRY 0x00000001
36
37#define FREQ_TAG "HZ="
38#define GPIO_TAG "gpio="
39#define KMAC_TAG "kmac="
40#define MEM_TAG "mem="
41#define BOARD_TAG "board="
42
43#define BOARD_RB532 "500"
44#define BOARD_RB532A "500r5"
diff --git a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h
new file mode 100644
index 000000000000..e0a76e3ffea8
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/rb.h
@@ -0,0 +1,81 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * Copyright (C) 2004 IDT Inc.
13 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
14 */
15#ifndef __ASM_RC32434_RB_H
16#define __ASM_RC32434_RB_H
17
18#include <linux/genhd.h>
19
20#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
21#define DEV0BASE 0x010000
22#define DEV0MASK 0x010004
23#define DEV0C 0x010008
24#define DEV0T 0x01000C
25#define DEV1BASE 0x010010
26#define DEV1MASK 0x010014
27#define DEV1C 0x010018
28#define DEV1TC 0x01001C
29#define DEV2BASE 0x010020
30#define DEV2MASK 0x010024
31#define DEV2C 0x010028
32#define DEV2TC 0x01002C
33#define DEV3BASE 0x010030
34#define DEV3MASK 0x010034
35#define DEV3C 0x010038
36#define DEV3TC 0x01003C
37#define BTCS 0x010040
38#define BTCOMPARE 0x010044
39#define GPIOBASE 0x050000
40#define GPIOCFG 0x050004
41#define GPIOD 0x050008
42#define GPIOILEVEL 0x05000C
43#define GPIOISTAT 0x050010
44#define GPIONMIEN 0x050014
45#define IMASK6 0x038038
46#define LO_WPX (1 << 0)
47#define LO_ALE (1 << 1)
48#define LO_CLE (1 << 2)
49#define LO_CEX (1 << 3)
50#define LO_FOFF (1 << 5)
51#define LO_SPICS (1 << 6)
52#define LO_ULED (1 << 7)
53
54#define BIT_TO_MASK(x) (1 << x)
55
56struct dev_reg {
57 u32 base;
58 u32 mask;
59 u32 ctl;
60 u32 timing;
61};
62
63struct korina_device {
64 char *name;
65 unsigned char mac[6];
66 struct net_device *dev;
67};
68
69struct cf_device {
70 int gpio_pin;
71 void *dev;
72 struct gendisk *gd;
73};
74
75struct mpmc_device {
76 unsigned char state;
77 spinlock_t lock;
78 void __iomem *base;
79};
80
81#endif /* __ASM_RC32434_RB_H */
diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h
new file mode 100644
index 000000000000..c4a02145104e
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/rc32434.h
@@ -0,0 +1,61 @@
1/*
2 * Definitions for IDT RC323434 CPU.
3 */
4
5#ifndef _ASM_RC32434_RC32434_H_
6#define _ASM_RC32434_RC32434_H_
7
8#include <linux/delay.h>
9#include <linux/io.h>
10
11#define RC32434_REG_BASE 0x18000000
12#define RC32434_RST (1 << 15)
13
14#define IDT_CLOCK_MULT 2
15#define MIPS_CPU_TIMER_IRQ 7
16
17/* Interrupt Controller */
18#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
19#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
20#define IC_GROUP_OFFSET 0x0C
21
22#define NUM_INTR_GROUPS 5
23
24/* 16550 UARTs */
25#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
26 /* GRP3 IRQ numbers start here */
27#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
28 /* GRP4 IRQ numbers start here */
29#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
30 /* GRP5 IRQ numbers start here */
31#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
32#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
33
34
35#ifdef __MIPSEB__
36#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
37#else
38#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
39#endif
40
41#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0)
42
43/* cpu pipeline flush */
44static inline void rc32434_sync(void)
45{
46 __asm__ volatile ("sync");
47}
48
49static inline void rc32434_sync_udelay(int us)
50{
51 __asm__ volatile ("sync");
52 udelay(us);
53}
54
55static inline void rc32434_sync_delay(int ms)
56{
57 __asm__ volatile ("sync");
58 mdelay(ms);
59}
60
61#endif /* _ASM_RC32434_RC32434_H_ */
diff --git a/include/asm-mips/mach-rc32434/timer.h b/include/asm-mips/mach-rc32434/timer.h
new file mode 100644
index 000000000000..e49b1d57a017
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/timer.h
@@ -0,0 +1,65 @@
1/*
2 * Definitions for timer registers
3 *
4 * Copyright 2004 Philip Rischel <rischelp@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef __ASM_RC32434_TIMER_H
30#define __ASM_RC32434_TIMER_H
31
32#include <asm/mach-rc32434/rb.h>
33
34#define TIMER0_BASE_ADDR 0x18028000
35#define TIMER_COUNT 3
36
37struct timer_counter {
38 u32 count;
39 u32 compare;
40 u32 ctc; /*use CTC_ */
41};
42
43struct timer {
44 struct timer_counter tim[TIMER_COUNT];
45 u32 rcount; /* use RCOUNT_ */
46 u32 rcompare; /* use RCOMPARE_ */
47 u32 rtc; /* use RTC_ */
48};
49
50#define RC32434_CTC_EN_BIT 0
51#define RC32434_CTC_TO_BIT 1
52
53/* Real time clock registers */
54#define RC32434_RTC_MSK(x) BIT_TO_MASK(x)
55#define RC32434_RTC_CE_BIT 0
56#define RC32434_RTC_TO_BIT 1
57#define RC32434_RTC_RQE_BIT 2
58
59/* Counter registers */
60#define RC32434_RCOUNT_BIT 0
61#define RC32434_RCOUNT_MSK 0x0000ffff
62#define RC32434_RCOMP_BIT 0
63#define RC32434_RCOMP_MSK 0x0000ffff
64
65#endif /* __ASM_RC32434_TIMER_H */
diff --git a/include/asm-mips/mach-rc32434/war.h b/include/asm-mips/mach-rc32434/war.h
new file mode 100644
index 000000000000..3ddf187e98a6
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
9#define __ASM_MIPS_MACH_MIPS_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 22:45:24 -0500