crypto: padlock - Enable on x86_64

Almost everything stays the same, we need just to use the extended registers
on the bit variant.

Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

2 files changed, 14 insertions, 1 deletions

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 01afd758072f..39eedd431413 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -12,7 +12,7 @@ if CRYPTO_HW
 
 config CRYPTO_DEV_PADLOCK
         tristate "Support for VIA PadLock ACE"
-        depends on X86_32 && !UML
+        depends on !UML
         select CRYPTO_ALGAPI
         help
           Some VIA processors come with an integrated crypto engine
diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c
index 856b3cc25583..87f92c39b5f0 100644
--- a/drivers/crypto/padlock-aes.c
+++ b/drivers/crypto/padlock-aes.c
@@ -154,7 +154,11 @@ static inline void padlock_reset_key(struct cword *cword)
         int cpu = raw_smp_processor_id();
 
         if (cword != per_cpu(last_cword, cpu))
+#ifndef CONFIG_X86_64
                 asm volatile ("pushfl; popfl");
+#else
+                asm volatile ("pushfq; popfq");
+#endif
 }
 
 static inline void padlock_store_cword(struct cword *cword)
@@ -208,10 +212,19 @@ static inline void padlock_xcrypt_ecb(const u8 *input, u8 *output, void *key,
 
         asm volatile ("test $1, %%cl;"
                       "je 1f;"
+#ifndef CONFIG_X86_64
                       "lea -1(%%ecx), %%eax;"
                       "mov $1, %%ecx;"
+#else
+                      "lea -1(%%rcx), %%rax;"
+                      "mov $1, %%rcx;"
+#endif
                       ".byte 0xf3,0x0f,0xa7,0xc8;"      /* rep xcryptecb */
+#ifndef CONFIG_X86_64
                       "mov %%eax, %%ecx;"
+#else
+                      "mov %%rax, %%rcx;"
+#endif
                       "1:"
                       ".byte 0xf3,0x0f,0xa7,0xc8"       /* rep xcryptecb */
                       : "+S"(input), "+D"(output)