diff options
author | Manish Lachwani <mlachwani@mvista.com> | 2006-10-05 19:30:44 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2006-10-30 16:41:28 -0500 |
commit | 9448b8f6a014f46450ef65d81c0be2ca5a81c867 (patch) | |
tree | fc1b5ece555ed23b3918151df58608ac0abbc05c | |
parent | f0ec69e52989986e861a352099803cbb77ca53ba (diff) |
[MIPS] Make SB1 cache flushes not to use on_each_cpu
This fixes the
start_kernel(): bug: interrupts were enabled early
messages.
Signed-off-by: Manish Lachwani <mlachwani@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/mm/c-sb1.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index f2941b4c9f33..ea49a775bf28 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c | |||
@@ -49,6 +49,15 @@ static unsigned short dcache_sets; | |||
49 | static unsigned int icache_range_cutoff; | 49 | static unsigned int icache_range_cutoff; |
50 | static unsigned int dcache_range_cutoff; | 50 | static unsigned int dcache_range_cutoff; |
51 | 51 | ||
52 | static inline void sb1_on_each_cpu(void (*func) (void *info), void *info, | ||
53 | int retry, int wait) | ||
54 | { | ||
55 | preempt_disable(); | ||
56 | smp_call_function(func, info, retry, wait); | ||
57 | func(info); | ||
58 | preempt_enable(); | ||
59 | } | ||
60 | |||
52 | /* | 61 | /* |
53 | * The dcache is fully coherent to the system, with one | 62 | * The dcache is fully coherent to the system, with one |
54 | * big caveat: the instruction stream. In other words, | 63 | * big caveat: the instruction stream. In other words, |
@@ -226,7 +235,7 @@ static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, | |||
226 | args.vma = vma; | 235 | args.vma = vma; |
227 | args.addr = addr; | 236 | args.addr = addr; |
228 | args.pfn = pfn; | 237 | args.pfn = pfn; |
229 | on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1); | 238 | sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1); |
230 | } | 239 | } |
231 | #else | 240 | #else |
232 | void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) | 241 | void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) |
@@ -249,7 +258,7 @@ void sb1___flush_cache_all_ipi(void *ignored) | |||
249 | 258 | ||
250 | static void sb1___flush_cache_all(void) | 259 | static void sb1___flush_cache_all(void) |
251 | { | 260 | { |
252 | on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1); | 261 | sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1); |
253 | } | 262 | } |
254 | #else | 263 | #else |
255 | void sb1___flush_cache_all(void) | 264 | void sb1___flush_cache_all(void) |
@@ -299,7 +308,7 @@ void sb1_flush_icache_range(unsigned long start, unsigned long end) | |||
299 | 308 | ||
300 | args.start = start; | 309 | args.start = start; |
301 | args.end = end; | 310 | args.end = end; |
302 | on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1); | 311 | sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1); |
303 | } | 312 | } |
304 | #else | 313 | #else |
305 | void sb1_flush_icache_range(unsigned long start, unsigned long end) | 314 | void sb1_flush_icache_range(unsigned long start, unsigned long end) |
@@ -326,7 +335,7 @@ static void sb1_flush_cache_sigtramp_ipi(void *info) | |||
326 | 335 | ||
327 | static void sb1_flush_cache_sigtramp(unsigned long addr) | 336 | static void sb1_flush_cache_sigtramp(unsigned long addr) |
328 | { | 337 | { |
329 | on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1); | 338 | sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1); |
330 | } | 339 | } |
331 | #else | 340 | #else |
332 | void sb1_flush_cache_sigtramp(unsigned long addr) | 341 | void sb1_flush_cache_sigtramp(unsigned long addr) |