x86, mce: unify Intel thermal init, prepare

Prepare for unification, make two intel_init_thermal equal.

[ Impact: cleanup ]

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>

2 files changed, 40 insertions, 39 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
index cef3ee30744b..b85d0c107c84 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
@@ -34,21 +34,22 @@ asmlinkage void smp_thermal_interrupt(void)
         irq_exit();
 }
 
+static inline void intel_set_thermal_handler(void) { }
+
 static void intel_init_thermal(struct cpuinfo_x86 *c)
 {
-        u32 l, h;
-        int tm2 = 0;
         unsigned int cpu = smp_processor_id();
+        int tm2 = 0;
+        u32 l, h;
 
-        if (!cpu_has(c, X86_FEATURE_ACPI))
-                return;
-
-        if (!cpu_has(c, X86_FEATURE_ACC))
+        /* Thermal monitoring depends on ACPI and clock modulation*/
+        if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
                 return;
 
-        /* first check if TM1 is already enabled by the BIOS, in which
-         * case there might be some SMM goo which handles it, so we can't even
-         * put a handler since it might be delivered via SMI already.
+        /*
+         * First check if its enabled already, in which case there might
+         * be some SMM goo which handles it, so we can't even put a handler
+         * since it might be delivered via SMI already:
          */
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
         h = apic_read(APIC_LVTTHMR);
@@ -61,31 +62,35 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
         if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
                 tm2 = 1;
 
+        /* Check whether a vector already exists */
         if (h & APIC_VECTOR_MASK) {
                 printk(KERN_DEBUG
-                       "CPU%d: Thermal LVT vector (%#x) already "
-                       "installed\n", cpu, (h & APIC_VECTOR_MASK));
+                       "CPU%d: Thermal LVT vector (%#x) already installed\n",
+                       cpu, (h & APIC_VECTOR_MASK));
                 return;
         }
 
-        h = THERMAL_APIC_VECTOR;
-        h |= (APIC_DM_FIXED | APIC_LVT_MASKED);
+        /* We'll mask the thermal vector in the lapic till we're ready: */
+        h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
         apic_write(APIC_LVTTHMR, h);
 
         rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
         wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
 
+        intel_set_thermal_handler();
+
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
         wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
 
+        /* Unmask the thermal vector: */
         l = apic_read(APIC_LVTTHMR);
         apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
+
         printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
-                cpu, tm2 ? "TM2" : "TM1");
+               cpu, tm2 ? "TM2" : "TM1");
 
         /* enable thermal throttle processing */
         atomic_set(&therm_throt_en, 1);
-        return;
 }
 
 /*
diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c
index cb344aba479c..f70753a443bb 100644
--- a/arch/x86/kernel/cpu/mcheck/p4.c
+++ b/arch/x86/kernel/cpu/mcheck/p4.c
@@ -66,19 +66,21 @@ void smp_thermal_interrupt(struct pt_regs *regs)
         irq_exit();
 }
 
+static void intel_set_thermal_handler(void)
+{
+        vendor_thermal_interrupt = intel_thermal_interrupt;
+}
+
 /* P4/Xeon Thermal regulation detect and init: */
 static void intel_init_thermal(struct cpuinfo_x86 *c)
 {
         unsigned int cpu = smp_processor_id();
+        int tm2 = 0;
         u32 l, h;
 
-        /* Thermal monitoring: */
-        if (!cpu_has(c, X86_FEATURE_ACPI))
-                return; /* -ENODEV */
-
-        /* Clock modulation: */
-        if (!cpu_has(c, X86_FEATURE_ACC))
-                return; /* -ENODEV */
+        /* Thermal monitoring depends on ACPI and clock modulation*/
+        if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
+                return;
 
         /*
          * First check if its enabled already, in which case there might
@@ -90,35 +92,28 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
         if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
                 printk(KERN_DEBUG
                        "CPU%d: Thermal monitoring handled by SMI\n", cpu);
-
-                return; /* -EBUSY */
+                return;
         }
 
-        /* Check whether a vector already exists, temporarily masked? */
+        if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
+                tm2 = 1;
+
+        /* Check whether a vector already exists */
         if (h & APIC_VECTOR_MASK) {
                 printk(KERN_DEBUG
                        "CPU%d: Thermal LVT vector (%#x) already installed\n",
                        cpu, (h & APIC_VECTOR_MASK));
-
-                return; /* -EBUSY */
+                return;
         }
 
-        /*
-         * The temperature transition interrupt handler setup:
-         */
-
-        /* Our delivery vector: */
-        h = THERMAL_APIC_VECTOR;
-
         /* We'll mask the thermal vector in the lapic till we're ready: */
-        h |= APIC_DM_FIXED | APIC_LVT_MASKED;
+        h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
         apic_write(APIC_LVTTHMR, h);
 
         rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
-        wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
+        wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
 
-        /* Ok, we're good to go... */
-        vendor_thermal_interrupt = intel_thermal_interrupt;
+        intel_set_thermal_handler();
 
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
         wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
@@ -127,7 +122,8 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
         l = apic_read(APIC_LVTTHMR);
         apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
 
-        printk(KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
+        printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
+               cpu, tm2 ? "TM2" : "TM1");
 
         /* enable thermal throttle processing */
         atomic_set(&therm_throt_en, 1);