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authorZachary Amsden <zach@vmware.com>2005-09-03 18:56:37 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:06:11 -0400
commit245067d1674d451855692fcd4647daf9fd47f82d (patch)
tree9e82ee9ce5c1899e0da06622716dffda02e94b15
parent4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa (diff)
[PATCH] i386: cleanup serialize msr
i386 arch cleanup. Introduce the serialize macro to serialize processor state. Why the microcode update needs it I am not quite sure, since wrmsr() is already a serializing instruction, but it is a microcode update, so I will keep the semantic the same, since this could be a timing workaround. As far as I can tell, this has always been there since the original microcode update source. Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--arch/i386/kernel/microcode.c7
-rw-r--r--include/asm-i386/processor.h5
-rw-r--r--include/asm-x86_64/processor.h5
3 files changed, 15 insertions, 2 deletions
diff --git a/arch/i386/kernel/microcode.c b/arch/i386/kernel/microcode.c
index a77c612aad00..165f13158c60 100644
--- a/arch/i386/kernel/microcode.c
+++ b/arch/i386/kernel/microcode.c
@@ -164,7 +164,8 @@ static void collect_cpu_info (void *unused)
164 } 164 }
165 165
166 wrmsr(MSR_IA32_UCODE_REV, 0, 0); 166 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
167 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); 167 /* see notes above for revision 1.07. Apparent chip bug */
168 serialize_cpu();
168 /* get the current revision from MSR 0x8B */ 169 /* get the current revision from MSR 0x8B */
169 rdmsr(MSR_IA32_UCODE_REV, val[0], uci->rev); 170 rdmsr(MSR_IA32_UCODE_REV, val[0], uci->rev);
170 pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n", 171 pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
@@ -377,7 +378,9 @@ static void do_update_one (void * unused)
377 (unsigned long) uci->mc->bits >> 16 >> 16); 378 (unsigned long) uci->mc->bits >> 16 >> 16);
378 wrmsr(MSR_IA32_UCODE_REV, 0, 0); 379 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
379 380
380 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); 381 /* see notes above for revision 1.07. Apparent chip bug */
382 serialize_cpu();
383
381 /* get the current revision from MSR 0x8B */ 384 /* get the current revision from MSR 0x8B */
382 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); 385 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
383 386
diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h
index 7e17d3b4f65a..a0489b222702 100644
--- a/include/asm-i386/processor.h
+++ b/include/asm-i386/processor.h
@@ -277,6 +277,11 @@ static inline void clear_in_cr4 (unsigned long mask)
277 outb((data), 0x23); \ 277 outb((data), 0x23); \
278} while (0) 278} while (0)
279 279
280static inline void serialize_cpu(void)
281{
282 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
283}
284
280static inline void __monitor(const void *eax, unsigned long ecx, 285static inline void __monitor(const void *eax, unsigned long ecx,
281 unsigned long edx) 286 unsigned long edx)
282{ 287{
diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h
index 85549e656eeb..194160f6a43f 100644
--- a/include/asm-x86_64/processor.h
+++ b/include/asm-x86_64/processor.h
@@ -437,6 +437,11 @@ static inline void prefetchw(void *x)
437 outb((data), 0x23); \ 437 outb((data), 0x23); \
438} while (0) 438} while (0)
439 439
440static inline void serialize_cpu(void)
441{
442 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
443}
444
440static inline void __monitor(const void *eax, unsigned long ecx, 445static inline void __monitor(const void *eax, unsigned long ecx,
441 unsigned long edx) 446 unsigned long edx)
442{ 447{