diff options
author | Bruno Randolf <br1@einfach.org> | 2010-06-07 00:11:35 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2010-06-08 09:31:21 -0400 |
commit | 20fbed21e934355ee00850f6dead22be3147893f (patch) | |
tree | af00747418f8fa4383c6485804180ade94ff1454 | |
parent | 0ca74027ac709f99aae1805e593c95843dd18234 (diff) |
ath5k: no need to save/restore the default antenna
Since ath5k_hw_set_antenna_mode() always writes the default antenna register
and is called at the end of reset, there is no need to separately save and
restore the default antenna.
Signed-off-by: Bruno Randolf <br1@einfach.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/ath/ath5k/reset.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c index d561f7cb56cb..498aa28ea9e6 100644 --- a/drivers/net/wireless/ath/ath5k/reset.c +++ b/drivers/net/wireless/ath/ath5k/reset.c | |||
@@ -877,12 +877,11 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, | |||
877 | struct ieee80211_channel *channel, bool change_channel) | 877 | struct ieee80211_channel *channel, bool change_channel) |
878 | { | 878 | { |
879 | struct ath_common *common = ath5k_hw_common(ah); | 879 | struct ath_common *common = ath5k_hw_common(ah); |
880 | u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo; | 880 | u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo; |
881 | u32 phy_tst1; | 881 | u32 phy_tst1; |
882 | u8 mode, freq, ee_mode; | 882 | u8 mode, freq, ee_mode; |
883 | int i, ret; | 883 | int i, ret; |
884 | 884 | ||
885 | s_ant = 0; | ||
886 | ee_mode = 0; | 885 | ee_mode = 0; |
887 | staid1_flags = 0; | 886 | staid1_flags = 0; |
888 | tsf_up = 0; | 887 | tsf_up = 0; |
@@ -979,9 +978,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, | |||
979 | } | 978 | } |
980 | } | 979 | } |
981 | 980 | ||
982 | /* Save default antenna */ | ||
983 | s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); | ||
984 | |||
985 | if (ah->ah_version == AR5K_AR5212) { | 981 | if (ah->ah_version == AR5K_AR5212) { |
986 | /* Restore normal 32/40MHz clock operation | 982 | /* Restore normal 32/40MHz clock operation |
987 | * to avoid register access delay on certain | 983 | * to avoid register access delay on certain |
@@ -1141,8 +1137,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, | |||
1141 | ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32); | 1137 | ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32); |
1142 | } | 1138 | } |
1143 | } | 1139 | } |
1144 | |||
1145 | ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA); | ||
1146 | } | 1140 | } |
1147 | 1141 | ||
1148 | /* Ledstate */ | 1142 | /* Ledstate */ |