diff options
author | Thiemo Seufer <ths@networkno.de> | 2005-09-09 15:45:41 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:32:17 -0400 |
commit | 02fe2c9ce3159f62339f30dfe62aeb6e4aa75d6e (patch) | |
tree | 8d330ba1629926b2bf0404d58921b15a873f3d17 | |
parent | f5b4d9563b3dc43d3b5df2422baecd2d4b77750a (diff) |
Minor code cleanup.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/mm/c-r4k.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 15a60c7e1a70..586baf29fe88 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
@@ -197,12 +197,12 @@ static inline void r4k_blast_icache_page_indexed_setup(void) | |||
197 | if (ic_lsize == 16) | 197 | if (ic_lsize == 16) |
198 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; | 198 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
199 | else if (ic_lsize == 32) { | 199 | else if (ic_lsize == 32) { |
200 | if (TX49XX_ICACHE_INDEX_INV_WAR) | 200 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
201 | r4k_blast_icache_page_indexed = | ||
202 | tx49_blast_icache32_page_indexed; | ||
203 | else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | ||
204 | r4k_blast_icache_page_indexed = | 201 | r4k_blast_icache_page_indexed = |
205 | blast_icache32_r4600_v1_page_indexed; | 202 | blast_icache32_r4600_v1_page_indexed; |
203 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | ||
204 | r4k_blast_icache_page_indexed = | ||
205 | tx49_blast_icache32_page_indexed; | ||
206 | else | 206 | else |
207 | r4k_blast_icache_page_indexed = | 207 | r4k_blast_icache_page_indexed = |
208 | blast_icache32_page_indexed; | 208 | blast_icache32_page_indexed; |
@@ -470,9 +470,9 @@ struct flush_icache_range_args { | |||
470 | static inline void local_r4k_flush_icache_range(void *args) | 470 | static inline void local_r4k_flush_icache_range(void *args) |
471 | { | 471 | { |
472 | struct flush_icache_range_args *fir_args = args; | 472 | struct flush_icache_range_args *fir_args = args; |
473 | unsigned long dc_lsize = current_cpu_data.dcache.linesz; | 473 | unsigned long dc_lsize = cpu_dcache_line_size(); |
474 | unsigned long ic_lsize = current_cpu_data.icache.linesz; | 474 | unsigned long ic_lsize = cpu_icache_line_size(); |
475 | unsigned long sc_lsize = current_cpu_data.scache.linesz; | 475 | unsigned long sc_lsize = cpu_scache_line_size(); |
476 | unsigned long start = fir_args->start; | 476 | unsigned long start = fir_args->start; |
477 | unsigned long end = fir_args->end; | 477 | unsigned long end = fir_args->end; |
478 | unsigned long addr, aend; | 478 | unsigned long addr, aend; |
@@ -501,7 +501,7 @@ static inline void local_r4k_flush_icache_range(void *args) | |||
501 | aend = (end - 1) & ~(sc_lsize - 1); | 501 | aend = (end - 1) & ~(sc_lsize - 1); |
502 | 502 | ||
503 | while (1) { | 503 | while (1) { |
504 | /* Hit_Writeback_Inv_D */ | 504 | /* Hit_Writeback_Inv_SD */ |
505 | protected_writeback_scache_line(addr); | 505 | protected_writeback_scache_line(addr); |
506 | if (addr == aend) | 506 | if (addr == aend) |
507 | break; | 507 | break; |
@@ -624,7 +624,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |||
624 | BUG_ON(size == 0); | 624 | BUG_ON(size == 0); |
625 | 625 | ||
626 | if (cpu_has_subset_pcaches) { | 626 | if (cpu_has_subset_pcaches) { |
627 | unsigned long sc_lsize = current_cpu_data.scache.linesz; | 627 | unsigned long sc_lsize = cpu_scache_line_size(); |
628 | 628 | ||
629 | if (size >= scache_size) { | 629 | if (size >= scache_size) { |
630 | r4k_blast_scache(); | 630 | r4k_blast_scache(); |
@@ -650,7 +650,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |||
650 | if (size >= dcache_size) { | 650 | if (size >= dcache_size) { |
651 | r4k_blast_dcache(); | 651 | r4k_blast_dcache(); |
652 | } else { | 652 | } else { |
653 | unsigned long dc_lsize = current_cpu_data.dcache.linesz; | 653 | unsigned long dc_lsize = cpu_dcache_line_size(); |
654 | 654 | ||
655 | R4600_HIT_CACHEOP_WAR_IMPL; | 655 | R4600_HIT_CACHEOP_WAR_IMPL; |
656 | a = addr & ~(dc_lsize - 1); | 656 | a = addr & ~(dc_lsize - 1); |
@@ -674,7 +674,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |||
674 | BUG_ON(size == 0); | 674 | BUG_ON(size == 0); |
675 | 675 | ||
676 | if (cpu_has_subset_pcaches) { | 676 | if (cpu_has_subset_pcaches) { |
677 | unsigned long sc_lsize = current_cpu_data.scache.linesz; | 677 | unsigned long sc_lsize = cpu_scache_line_size(); |
678 | 678 | ||
679 | if (size >= scache_size) { | 679 | if (size >= scache_size) { |
680 | r4k_blast_scache(); | 680 | r4k_blast_scache(); |
@@ -695,7 +695,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |||
695 | if (size >= dcache_size) { | 695 | if (size >= dcache_size) { |
696 | r4k_blast_dcache(); | 696 | r4k_blast_dcache(); |
697 | } else { | 697 | } else { |
698 | unsigned long dc_lsize = current_cpu_data.dcache.linesz; | 698 | unsigned long dc_lsize = cpu_dcache_line_size(); |
699 | 699 | ||
700 | R4600_HIT_CACHEOP_WAR_IMPL; | 700 | R4600_HIT_CACHEOP_WAR_IMPL; |
701 | a = addr & ~(dc_lsize - 1); | 701 | a = addr & ~(dc_lsize - 1); |
@@ -719,9 +719,9 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |||
719 | */ | 719 | */ |
720 | static void local_r4k_flush_cache_sigtramp(void * arg) | 720 | static void local_r4k_flush_cache_sigtramp(void * arg) |
721 | { | 721 | { |
722 | unsigned long ic_lsize = current_cpu_data.icache.linesz; | 722 | unsigned long ic_lsize = cpu_icache_line_size(); |
723 | unsigned long dc_lsize = current_cpu_data.dcache.linesz; | 723 | unsigned long dc_lsize = cpu_dcache_line_size(); |
724 | unsigned long sc_lsize = current_cpu_data.scache.linesz; | 724 | unsigned long sc_lsize = cpu_scache_line_size(); |
725 | unsigned long addr = (unsigned long) arg; | 725 | unsigned long addr = (unsigned long) arg; |
726 | 726 | ||
727 | R4600_HIT_CACHEOP_WAR_IMPL; | 727 | R4600_HIT_CACHEOP_WAR_IMPL; |